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wr2rf-vme
Commits
4fe6e8ed
Commit
4fe6e8ed
authored
Jun 29, 2020
by
Tristan Gingold
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wr2rf_vme_p0: rename lb1b/lb2b ports.
parent
48df77a3
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2 changed files
with
16 additions
and
16 deletions
+16
-16
wr2rf_vme_p0.vhd
hdl/rtl/wr2rf_vme_p0.vhd
+8
-8
wr2rf_vme.vhd
hdl/top/wr2rf_vme.vhd
+8
-8
No files found.
hdl/rtl/wr2rf_vme_p0.vhd
View file @
4fe6e8ed
...
...
@@ -36,14 +36,14 @@ entity wr2rf_vme_p0 is
vme_p0_h1_bsb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_c40_o
:
out
std_logic
;
vme_p0_h1_lb
1
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_
lb2
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_lbb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_
hb
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_tc_o
:
out
std_logic
;
vme_p0_h2_bsb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_c40_o
:
out
std_logic
;
vme_p0_h2_lb
1
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_
lb2
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_lbb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_
hb
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_tc_o
:
out
std_logic
;
vme_p0_oen_o
:
out
std_logic
);
...
...
@@ -84,14 +84,14 @@ begin
vme_p0_oen_o
<=
h1_lfsr32_r
(
31
);
vme_p0_h1_bsb_o
<=
h1_lfsr32_r
(
7
downto
0
);
vme_p0_h1_lb
1
b_o
<=
h1_lfsr32_r
(
15
downto
8
);
vme_p0_h1_
lb2
b_o
<=
h1_lfsr32_r
(
23
downto
16
);
vme_p0_h1_lbb_o
<=
h1_lfsr32_r
(
15
downto
8
);
vme_p0_h1_
hb
b_o
<=
h1_lfsr32_r
(
23
downto
16
);
vme_p0_h1_tc_o
<=
rf1_clk_bufg_i
;
vme_p0_h1_c40_o
<=
rf1_clk_bufg_i
;
vme_p0_h2_bsb_o
<=
h2_lfsr32_r
(
7
downto
0
);
vme_p0_h2_lb
1
b_o
<=
h2_lfsr32_r
(
15
downto
8
);
vme_p0_h2_
lb2
b_o
<=
h2_lfsr32_r
(
23
downto
16
);
vme_p0_h2_lbb_o
<=
h2_lfsr32_r
(
15
downto
8
);
vme_p0_h2_
hb
b_o
<=
h2_lfsr32_r
(
23
downto
16
);
vme_p0_h2_tc_o
<=
rf2_clk_bufg_i
;
vme_p0_h2_c40_o
<=
rf2_clk_bufg_i
;
...
...
hdl/top/wr2rf_vme.vhd
View file @
4fe6e8ed
...
...
@@ -215,13 +215,13 @@ entity wr2rf_vme is
-- vme p0
vme_p0_h1_bsb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_c40_o
:
out
std_logic
;
vme_p0_h1_lb
1
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_
lb2
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_lbb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_
hb
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h1_tc_o
:
out
std_logic
;
vme_p0_h2_bsb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_c40_o
:
out
std_logic
;
vme_p0_h2_lb
1
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_
lb2
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_lbb_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_
hb
b_o
:
out
std_logic_vector
(
7
downto
0
);
vme_p0_h2_tc_o
:
out
std_logic
;
vme_p0_oen_o
:
out
std_logic
;
...
...
@@ -862,13 +862,13 @@ begin
rf2_clk_bufg_i
=>
rf2_clk_bufg
,
vme_p0_h1_bsb_o
=>
vme_p0_h1_bsb_o
,
vme_p0_h1_c40_o
=>
vme_p0_h1_c40_o
,
vme_p0_h1_lb
1b_o
=>
vme_p0_h1_lb1
b_o
,
vme_p0_h1_
lb2b_o
=>
vme_p0_h1_lb2
b_o
,
vme_p0_h1_lb
b_o
=>
vme_p0_h1_lb
b_o
,
vme_p0_h1_
hbb_o
=>
vme_p0_h1_hb
b_o
,
vme_p0_h1_tc_o
=>
vme_p0_h1_tc_o
,
vme_p0_h2_bsb_o
=>
vme_p0_h2_bsb_o
,
vme_p0_h2_c40_o
=>
vme_p0_h2_c40_o
,
vme_p0_h2_lb
1b_o
=>
vme_p0_h2_lb1
b_o
,
vme_p0_h2_
lb2b_o
=>
vme_p0_h2_lb2
b_o
,
vme_p0_h2_lb
b_o
=>
vme_p0_h2_lb
b_o
,
vme_p0_h2_
hbb_o
=>
vme_p0_h2_hb
b_o
,
vme_p0_h2_tc_o
=>
vme_p0_h2_tc_o
,
vme_p0_oen_o
=>
vme_p0_oen_o
);
...
...
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