Commit 40e6f0b1 authored by Tristan Gingold's avatar Tristan Gingold

vtuCore: add comments.

parent c538661b
......@@ -439,20 +439,31 @@ entity vtuDataShifter is
g_DisableDoubleSync : std_logic := '1'
-- Avoid pulses between two words
);
port (CoarseZero : out std_logic;
port (
Clk : in std_logic;
-- Data output, provided 1 clock cycle after DataIn.
-- The first bit to generate is the MSB.
DataOut : out std_logic_vector(7 downto 0);
OutputEnabled : out std_logic;
Clk : in std_logic;
Delay : in std_logic_vector(N - 1 downto 0 );
-- Input data. The first bit is the MSB. This is handled as a pulse.
DataIn : in std_logic_vector(7 downto 0);
-- Delay to be applied to DataIn. The 3 LSB is the fine delay (1/8 of CLK),
-- the other bits are the coarse delay (CLK)
Delay : in std_logic_vector(N - 1 downto 0);
-- True if the coarse part of Delay is 0 (which is incorrect).
CoarseZero : out std_logic;
-- Data output, provided 1 clock cycle after DataIn.
-- The first bit to generate is the MSB.
DataOut : out std_logic_vector(7 downto 0);
-- Set when the output is generated (1 pulse after the delay)
OutputEnabled : out std_logic;
-- Input data. The first bit is the MSB.
DataIn : in std_logic_vector(7 downto 0);
-- Must be set to operate.
Enabled : in std_logic;
Enabled : in std_logic;
SyncPulse : out std_logic);
-- Set when a pulse has been detected on DataIn
SyncPulse : out std_logic);
end vtuDataShifter;
......
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