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wr2rf-vme
Commit 3fe0ae97 authored by John Gill's avatar John Gill
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Updated version to v0.13 and double buffered reading the incoming rfframe timestamps for atomicity.

parent 29d46cfd
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hdl/rtl/registers/trigunit_regs.vhd
View file @ 3fe0ae97
-- Do not edit. Generated on Mon Sep 06 15:26:43 2021 by jgill
-- Do not edit. Generated on Tue Sep 07 11:28:03 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 3fe0ae97
......@@ -639,6 +639,17 @@ memory-map:
description: Timestamp when the last frame was received from RFFrameTransceiver
width: 32
access: ro
- reg:
name: rfframe_ts
description: Update the RF frame timestamps for readout
width: 16
access: rw
children:
- field:
name: update
range: 0
x-hdl:
type: autoclear
- reg:
name: nco_reset_tai
description: Timestamp TAI for the last RFframe received that asserted nco_reset
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 3fe0ae97
-- Do not edit. Generated on Mon Sep 06 15:26:44 2021 by jgill
-- Do not edit. Generated on Tue Sep 07 11:28:03 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rfnco_regs.vhd
View file @ 3fe0ae97
-- Do not edit. Generated on Mon Sep 06 15:26:45 2021 by jgill
-- Do not edit. Generated on Tue Sep 07 11:28:04 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i RFNCO.cheby --gen-hdl
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 3fe0ae97
-- Do not edit. Generated on Mon Sep 06 15:26:44 2021 by jgill
-- Do not edit. Generated on Tue Sep 07 11:28:03 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 3fe0ae97
-- Do not edit. Generated on Mon Sep 06 15:26:46 2021 by jgill
-- Do not edit. Generated on Tue Sep 07 11:28:05 2021 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......@@ -266,6 +266,9 @@ entity wr2rf_vme_regs is
-- Timestamp when the last frame was received from RFFrameTransceiver
init_wrs_rxframe_rftimestamp_i : in std_logic_vector(31 downto 0);
-- Update the RF frame timestamps for readout
init_wrs_rxframe_rfframe_ts_update_o : out std_logic;
-- Timestamp TAI for the last RFframe received that asserted nco_reset
init_wrs_rxframe_nco_reset_tai_val_i : in std_logic_vector(39 downto 0);
......@@ -626,6 +629,9 @@ architecture syn of wr2rf_vme_regs is
signal init_svec_mup_fmc2_led_reg : std_logic_vector(1 downto 0);
signal init_svec_mup_fmc2_wreq : std_logic;
signal init_svec_mup_fmc2_wack : std_logic;
signal init_wrs_rxframe_rfframe_ts_update_reg : std_logic;
signal init_wrs_rxframe_rfframe_ts_wreq : std_logic;
signal init_wrs_rxframe_rfframe_ts_wack : std_logic;
signal init_wrc_page0_reg : std_logic_vector(31 downto 0);
signal init_wrc_page0_wreq : std_logic_vector(1 downto 0);
signal init_wrc_page0_wack : std_logic_vector(1 downto 0);
......@@ -1691,6 +1697,24 @@ begin
-- Register init_wrs_rxframe_rftimestamp
-- Register init_wrs_rxframe_rfframe_ts
init_wrs_rxframe_rfframe_ts_update_o <= init_wrs_rxframe_rfframe_ts_update_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
init_wrs_rxframe_rfframe_ts_update_reg <= '0';
init_wrs_rxframe_rfframe_ts_wack <= '0';
else
if init_wrs_rxframe_rfframe_ts_wreq = '1' then
init_wrs_rxframe_rfframe_ts_update_reg <= wr_dat_d0(0);
else
init_wrs_rxframe_rfframe_ts_update_reg <= '0';
end if;
init_wrs_rxframe_rfframe_ts_wack <= init_wrs_rxframe_rfframe_ts_wreq;
end if;
end if;
end process;
-- Register init_wrs_rxframe_nco_reset_tai
-- Register init_wrs_rxframe_nco_reset_cycles
......@@ -2593,7 +2617,7 @@ begin
end process;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, init_hwinfo_echo_wack, init_fw_update_wack, init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack, init_mmcm_shift_wack, init_tmg_wack, init_lemo_rf1_t1_start_wack, init_lemo_rf1_t2_start_wack, init_lemo_rf2_t1_start_wack, init_lemo_rf2_t2_start_wack, init_lemo_rf1_t1_stop_wack, init_lemo_rf1_t2_stop_wack, init_lemo_rf2_t1_stop_wack, init_lemo_rf2_t2_stop_wack, init_tmgio1_wack, init_tmgio2_wack, init_tmgio3_wack, init_tmgio4_wack, init_tmgclk1_wack, init_tmgclk2_wack, init_lemo_wack, init_lemo_ext_wack, init_softstart_wack, init_softstop_wack, init_lemo_pulse_wack, init_pin_ctrl_wack, init_pll_ctrl_wack, init_dds_ctrl_wack, init_dds_ioupdate_wack, init_ocxo_ctrl_wack, init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack, init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack, init_nco_update_wack, init_nco_loc_or_wrs_wack, init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack, init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack, init_wrc_page0_wack, init_wrc_page1_wack, init_txframe_ftw_h1_main_wack, init_txframe_ftw_h1_prog_wack, init_txframe_ftw_h1_on_wack, init_txframe_dftw_h1_slip1_wack, init_txframe_dftw_h1_slip2_wack, init_txframe_setpoint1_wack, init_txframe_setpoint2_wack, init_txframe_setpoint3_wack, init_txframe_setpoint4_wack, init_txframe_setpoint5_wack, init_txframe_setpoint6_wack, init_txframe_setpoint7_wack, init_txframe_setpoint8_wack, init_txframe_noise_wack, init_txframe_control_wack, init_pll_spi_wack, init_rf_spi_wack, init_rf_wack, init_framerxtx_wack, init_wrpc_wack, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_rf1_rfnco_wack, ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_phase_wack, ctrl_rf2_iqdac_phase_wack, ctrl_rf1_iqdac_phase_update_wack, ctrl_rf2_iqdac_phase_update_wack, ctrl_rf1_iqdac_igain_arm_wack, ctrl_rf1_iqdac_qgain_arm_wack, ctrl_rf2_iqdac_igain_arm_wack, ctrl_rf2_iqdac_qgain_arm_wack, ctrl_rf1_iqdac_ctrl_wack, ctrl_rf2_iqdac_ctrl_wack, ctrl_iqdac_ram_addr_wack, ctrl_iqdac_ram_data_wack, ctrl_iqdac_ram_write_wack, ctrl_iqdac_ram_play_wack, ctrl_rf1_dds_ftw_valid_wack, ctrl_rf1_dds_ftw_wack, ctrl_rf2_dds_ftw_valid_wack, ctrl_rf2_dds_ftw_wack, ctrl_nco_reset_ctrl_wack) begin
process (wr_adr_d0, wr_req_d0, init_hwinfo_echo_wack, init_fw_update_wack, init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack, init_mmcm_shift_wack, init_tmg_wack, init_lemo_rf1_t1_start_wack, init_lemo_rf1_t2_start_wack, init_lemo_rf2_t1_start_wack, init_lemo_rf2_t2_start_wack, init_lemo_rf1_t1_stop_wack, init_lemo_rf1_t2_stop_wack, init_lemo_rf2_t1_stop_wack, init_lemo_rf2_t2_stop_wack, init_tmgio1_wack, init_tmgio2_wack, init_tmgio3_wack, init_tmgio4_wack, init_tmgclk1_wack, init_tmgclk2_wack, init_lemo_wack, init_lemo_ext_wack, init_softstart_wack, init_softstop_wack, init_lemo_pulse_wack, init_pin_ctrl_wack, init_pll_ctrl_wack, init_dds_ctrl_wack, init_dds_ioupdate_wack, init_ocxo_ctrl_wack, init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack, init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack, init_nco_update_wack, init_nco_loc_or_wrs_wack, init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack, init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack, init_wrs_rxframe_rfframe_ts_wack, init_wrc_page0_wack, init_wrc_page1_wack, init_txframe_ftw_h1_main_wack, init_txframe_ftw_h1_prog_wack, init_txframe_ftw_h1_on_wack, init_txframe_dftw_h1_slip1_wack, init_txframe_dftw_h1_slip2_wack, init_txframe_setpoint1_wack, init_txframe_setpoint2_wack, init_txframe_setpoint3_wack, init_txframe_setpoint4_wack, init_txframe_setpoint5_wack, init_txframe_setpoint6_wack, init_txframe_setpoint7_wack, init_txframe_setpoint8_wack, init_txframe_noise_wack, init_txframe_control_wack, init_pll_spi_wack, init_rf_spi_wack, init_rf_wack, init_framerxtx_wack, init_wrpc_wack, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_rf1_rfnco_wack, ctrl_rf2_rfnco_wack, ctrl_rf1_iqdac_phase_wack, ctrl_rf2_iqdac_phase_wack, ctrl_rf1_iqdac_phase_update_wack, ctrl_rf2_iqdac_phase_update_wack, ctrl_rf1_iqdac_igain_arm_wack, ctrl_rf1_iqdac_qgain_arm_wack, ctrl_rf2_iqdac_igain_arm_wack, ctrl_rf2_iqdac_qgain_arm_wack, ctrl_rf1_iqdac_ctrl_wack, ctrl_rf2_iqdac_ctrl_wack, ctrl_iqdac_ram_addr_wack, ctrl_iqdac_ram_data_wack, ctrl_iqdac_ram_write_wack, ctrl_iqdac_ram_play_wack, ctrl_rf1_dds_ftw_valid_wack, ctrl_rf1_dds_ftw_wack, ctrl_rf2_dds_ftw_valid_wack, ctrl_rf2_dds_ftw_wack, ctrl_nco_reset_ctrl_wack) begin
init_hwinfo_echo_wreq <= (others => '0');
init_fw_update_we <= '0';
init_reconfigure_wreq <= '0';
......@@ -2638,6 +2662,7 @@ begin
init_svec_mup_rftrig_wreq <= '0';
init_svec_mup_fmc1_wreq <= '0';
init_svec_mup_fmc2_wreq <= '0';
init_wrs_rxframe_rfframe_ts_wreq <= '0';
init_wrc_page0_wreq <= (others => '0');
init_wrc_page1_wreq <= (others => '0');
init_txframe_ftw_h1_main_wreq <= (others => '0');
......@@ -3099,6 +3124,15 @@ begin
wr_ack_int <= wr_req_d0;
end case;
when "011" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_rfframe_ts
init_wrs_rxframe_rfframe_ts_wreq <= wr_req_d0;
wr_ack_int <= init_wrs_rxframe_rfframe_ts_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "100" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_nco_reset_tai
......@@ -3115,7 +3149,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "100" =>
when "101" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_nco_reset_cycles
......@@ -3126,7 +3160,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "101" =>
when "110" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_tai
......@@ -3143,7 +3177,7 @@ begin
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "110" =>
when "111" =>
case wr_adr_d0(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_cycles
......@@ -4250,6 +4284,16 @@ begin
rd_ack_d0 <= rd_req_int;
end case;
when "011" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_rfframe_ts
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= '0';
rd_dat_d0(15 downto 1) <= (others => '0');
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "100" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_nco_reset_tai
......@@ -4271,7 +4315,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "100" =>
when "101" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_nco_reset_cycles
......@@ -4285,7 +4329,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "101" =>
when "110" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_tai
......@@ -4307,7 +4351,7 @@ begin
when others =>
rd_ack_d0 <= rd_req_int;
end case;
when "110" =>
when "111" =>
case adr_int(2 downto 1) is
when "00" =>
-- Reg init_wrs_rxframe_cycles
......
hdl/rtl/wr2rf_regs_core.vhd
View file @ 3fe0ae97
......@@ -175,6 +175,7 @@ entity wr2rf_regs_core is
wrs_frame_last_txwrtimestamp_i : in std_logic_vector (31 downto 0);
wrs_frame_last_rftimestamp_i : in std_logic_vector (31 downto 0);
wrs_frame_counter_i : in std_logic_vector (15 downto 0);
rfframe_ts_update_o : out std_logic;
rfframe_nco_reset_tai_i : in std_logic_vector(39 downto 0);
rfframe_nco_reset_cycles_i : in std_logic_vector(27 downto 0);
rfframe_tai_i : in std_logic_vector(39 downto 0);
......@@ -349,8 +350,8 @@ begin
init_hwinfo_ident_jtagRemoteDisable_i => '1',
init_hwinfo_ident_extendedID_i => "0000000",
init_hwinfo_ident_cardID_i => x"56",
init_hwinfo_firmwareVersion_i => x"0000_12_00",
init_hwinfo_memMapVersion_i => x"0000_12_00",
init_hwinfo_firmwareVersion_i => x"0000_13_00",
init_hwinfo_memMapVersion_i => x"0000_13_00",
init_hwinfo_echo_echo_o => open,
init_fw_update_i => wb_fw_update_in,
......@@ -454,6 +455,7 @@ begin
init_wrs_rxframe_txwrtimestamp_i => wrs_frame_last_txwrtimestamp_i,
init_wrs_rxframe_rftimestamp_i => wrs_frame_last_rftimestamp_i,
init_wrs_rxframe_counter_i => wrs_frame_counter_i,
init_wrs_rxframe_rfframe_ts_update_o => rfframe_ts_update_o,
init_wrs_rxframe_nco_reset_tai_val_i => rfframe_nco_reset_tai_i,
init_wrs_rxframe_nco_reset_cycles_val_i => rfframe_nco_reset_cycles_i,
init_wrs_rxframe_tai_val_i => rfframe_tai_i,
......
hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 3fe0ae97
......@@ -603,10 +603,15 @@ architecture rtl of wr2rf_vme is
signal wrs_frame_rftimestamp_r : std_logic_vector(31 downto 0);
signal wrs_rx_reset_nco_pulse : std_logic;
signal rfframe_ts_update : std_logic;
signal rfframe_nco_reset_tai_r : std_logic_vector(39 downto 0);
signal rfframe_nco_reset_cycles_r : std_logic_vector(27 downto 0);
signal rfframe_tai_r : std_logic_vector(39 downto 0);
signal rfframe_cycles_r : std_logic_vector(27 downto 0);
signal rfframe_nco_reset_tai_h : std_logic_vector(39 downto 0);
signal rfframe_nco_reset_cycles_h : std_logic_vector(27 downto 0);
signal rfframe_tai_h : std_logic_vector(39 downto 0);
signal rfframe_cycles_h : std_logic_vector(27 downto 0);
signal rfframe_nco_reset_tai : std_logic_vector(39 downto 0);
signal rfframe_nco_reset_cycles : std_logic_vector(27 downto 0);
signal rfframe_tai : std_logic_vector(39 downto 0);
......@@ -1052,6 +1057,10 @@ begin
rfframe_nco_reset_cycles_r <= (others => '0');
rfframe_tai_r <= (others => '0');
rfframe_cycles_r <= (others => '0');
rfframe_nco_reset_tai_h <= (others => '0');
rfframe_nco_reset_cycles_h <= (others => '0');
rfframe_tai_h <= (others => '0');
rfframe_cycles_h <= (others => '0');
else
wrs_frame_counter_r <= wrs_frame_counter;
wrs_frame_rxwrtimestamp_r <= wrs_frame_rxwrtimestamp;
......@@ -1061,6 +1070,12 @@ begin
rfframe_nco_reset_cycles_r <= rfframe_nco_reset_cycles;
rfframe_tai_r <= rfframe_tai;
rfframe_cycles_r <= rfframe_cycles;
if rfframe_ts_update = '1' then
rfframe_nco_reset_tai_h <= rfframe_nco_reset_tai_r;
rfframe_nco_reset_cycles_h <= rfframe_nco_reset_cycles_r;
rfframe_tai_h <= rfframe_tai_r;
rfframe_cycles_h <= rfframe_cycles_r;
end if;
end if;
end if;
end process;
......@@ -1600,10 +1615,11 @@ begin
wrs_frame_last_txwrtimestamp_i => wrs_frame_txwrtimestamp_r,
wrs_frame_last_rftimestamp_i => wrs_frame_rftimestamp_r,
wrs_frame_counter_i => std_logic_vector(wrs_frame_counter_r),
rfframe_nco_reset_tai_i => rfframe_nco_reset_tai,
rfframe_nco_reset_cycles_i => rfframe_nco_reset_cycles,
rfframe_tai_i => rfframe_tai,
rfframe_cycles_i => rfframe_cycles,
rfframe_ts_update_o => rfframe_ts_update,
rfframe_nco_reset_tai_i => rfframe_nco_reset_tai_h,
rfframe_nco_reset_cycles_i => rfframe_nco_reset_cycles_h,
rfframe_tai_i => rfframe_tai_h,
rfframe_cycles_i => rfframe_cycles_h,
txframe_payload_o => wrs_tx_RFmFramePayloads,
......
software/include/wr2rf_init_regs.h
View file @ 3fe0ae97
#ifndef __CHEBY__WR2RF_INIT_REGS__H__
#define __CHEBY__WR2RF_INIT_REGS__H__
#include "oc_spi16_regs.h"
#include "hwInfo.h"
#include "wr2rf_init_rf_regs.h"
#include "hwInfo.h"
#include "oc_spi16_regs.h"
#define WR2RF_INIT_REGS_SIZE 16384 /* 0x4000 = 16KB */
/* RF indentification */
......@@ -274,54 +274,78 @@
#define WR2RF_INIT_REGS_SVEC_MUP_FMC2_LED_SHIFT 10
/* Last rx frame from WR */
#define WR2RF_INIT_REGS_WRS_RXFRAME 0x1e0UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_SIZE 32 /* 0x20 */
#define WR2RF_INIT_REGS_WRS_RXFRAME 0x200UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_SIZE 64 /* 0x40 */
/* Last FTW received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW 0x1e0UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW 0x200UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW_VALUE_MASK 0xffffffffffffULL
#define WR2RF_INIT_REGS_WRS_RXFRAME_FTW_VALUE_SHIFT 0
/* Last Control received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_CTRL 0x1e8UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_CTRL 0x208UL
/* Number of RFFrameTransceiver frames received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_COUNTER 0x1eaUL
#define WR2RF_INIT_REGS_WRS_RXFRAME_COUNTER 0x20aUL
/* Timestamp when the last frame was received from wr streamers */
#define WR2RF_INIT_REGS_WRS_RXFRAME_RXWRTIMESTAMP 0x1ecUL
#define WR2RF_INIT_REGS_WRS_RXFRAME_RXWRTIMESTAMP 0x20cUL
/* Timestamp when the last frame was transmitted from wr streamers */
#define WR2RF_INIT_REGS_WRS_RXFRAME_TXWRTIMESTAMP 0x1f0UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_TXWRTIMESTAMP 0x210UL
/* Timestamp when the last frame was received from RFFrameTransceiver */
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFTIMESTAMP 0x1f4UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFTIMESTAMP 0x214UL
/* Update the RF frame timestamps for readout */
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFFRAME_TS 0x218UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_RFFRAME_TS_UPDATE 0x1UL
/* Timestamp TAI for the last RFframe received that asserted nco_reset */
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI 0x220UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI_VAL_MASK 0xffffffffffULL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_TAI_VAL_SHIFT 0
/* Timestamp TAI for the last RFframe received that asserted nco_reset */
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES 0x228UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES_VAL_MASK 0xfffffffUL
#define WR2RF_INIT_REGS_WRS_RXFRAME_NCO_RESET_CYCLES_VAL_SHIFT 0
/* Timestamp TAI for the last RFframe received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_TAI 0x230UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_TAI_VAL_MASK 0xffffffffffULL
#define WR2RF_INIT_REGS_WRS_RXFRAME_TAI_VAL_SHIFT 0
/* Timestamp TAI for the last RFframe received */
#define WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES 0x238UL
#define WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES_VAL_MASK 0xfffffffUL
#define WR2RF_INIT_REGS_WRS_RXFRAME_CYCLES_VAL_SHIFT 0
/* WR status and time */
#define WR2RF_INIT_REGS_WRC 0x200UL
#define WR2RF_INIT_REGS_WRC 0x240UL
#define WR2RF_INIT_REGS_WRC_SIZE 32 /* 0x20 */
/* Absolute time (in sec) */
#define WR2RF_INIT_REGS_WRC_TAI 0x200UL
#define WR2RF_INIT_REGS_WRC_TAI 0x240UL
#define WR2RF_INIT_REGS_WRC_TAI_VALUE_MASK 0xffffffffffULL
#define WR2RF_INIT_REGS_WRC_TAI_VALUE_SHIFT 0
/* Number of cycles */
#define WR2RF_INIT_REGS_WRC_CYCLES 0x208UL
#define WR2RF_INIT_REGS_WRC_CYCLES 0x248UL
#define WR2RF_INIT_REGS_WRC_CYCLES_VALUE_MASK 0xfffffffUL
#define WR2RF_INIT_REGS_WRC_CYCLES_VALUE_SHIFT 0
/* WR status */
#define WR2RF_INIT_REGS_WRC_STATUS 0x20cUL
#define WR2RF_INIT_REGS_WRC_STATUS 0x24cUL
#define WR2RF_INIT_REGS_WRC_STATUS_LINKUP 0x1UL
#define WR2RF_INIT_REGS_WRC_STATUS_TIME_VALID 0x2UL
/* Page 0 offset */
#define WR2RF_INIT_REGS_WRC_PAGE0 0x210UL
#define WR2RF_INIT_REGS_WRC_PAGE0 0x250UL
#define WR2RF_INIT_REGS_WRC_PAGE0_PRESET 0x40000UL
/* Page 1 offset */
#define WR2RF_INIT_REGS_WRC_PAGE1 0x214UL
#define WR2RF_INIT_REGS_WRC_PAGE1 0x254UL
/* Frame to be sent over WR (for testing purposes) */
#define WR2RF_INIT_REGS_TXFRAME 0x280UL
......@@ -562,10 +586,10 @@ struct wr2rf_init_regs {
uint16_t fmc2;
} svec_mup;
/* padding to: 120 words */
uint32_t __padding_2[6];
/* padding to: 128 words */
uint32_t __padding_2[14];
/* [0x1e0]: BLOCK Last rx frame from WR */
/* [0x200]: BLOCK Last rx frame from WR */
struct wrs_rxframe {
/* [0x0]: REG (ro) Last FTW received */
uint64_t ftw;
......@@ -585,11 +609,32 @@ struct wr2rf_init_regs {
/* [0x14]: REG (ro) Timestamp when the last frame was received from RFFrameTransceiver */
uint32_t rftimestamp;
/* padding to: 5 words */
uint32_t __padding_0[2];
/* [0x18]: REG (rw) Update the RF frame timestamps for readout */
uint16_t rfframe_ts;
/* padding to: 32 words */
uint8_t __padding_0[6];
/* [0x20]: REG (ro) Timestamp TAI for the last RFframe received that asserted nco_reset */
uint64_t nco_reset_tai;
/* [0x28]: REG (ro) Timestamp TAI for the last RFframe received that asserted nco_reset */
uint32_t nco_reset_cycles;
/* padding to: 12 words */
uint32_t __padding_1[1];
/* [0x30]: REG (ro) Timestamp TAI for the last RFframe received */
uint64_t tai;
/* [0x38]: REG (ro) Timestamp TAI for the last RFframe received */
uint32_t cycles;
/* padding to: 14 words */
uint32_t __padding_2[1];
} wrs_rxframe;
/* [0x200]: BLOCK WR status and time */
/* [0x240]: BLOCK WR status and time */
struct wrc {
/* [0x0]: REG (ro) Absolute time (in sec) */
uint64_t tai;
......@@ -614,7 +659,7 @@ struct wr2rf_init_regs {
} wrc;
/* padding to: 160 words */
uint32_t __padding_3[24];
uint32_t __padding_3[8];
/* [0x280]: BLOCK Frame to be sent over WR (for testing purposes) */
struct txframe {
......
software/include/wr2rf_rftrigger_regs.h
View file @ 3fe0ae97
#ifndef __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#define __CHEBY__WR2RF_RFTRIGGER_REGS__H__
#include "vtudiag_regs.h"
#include "trigunit_regs.h"
#include "vtudiag_regs.h"
#define WR2RF_RFTRIGGER_REGS_SIZE 272 /* 0x110 */
/* None */
......
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