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wr2rf-vme
Commit 36d21fba authored by John Gill's avatar John Gill
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Clean wishbone signal namespace. Add pll_main_sync signal from pll_main_ctrl register.

parent 9522d47b
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hdl/rtl/registers/trigunit_regs.vhd
View file @ 36d21fba
-- Do not edit. Generated on Wed Nov 25 16:59:15 2020 by jgill
-- Do not edit. Generated on Thu Nov 26 11:18:22 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i trigunit_regs.cheby --gen-hdl trigunit_regs.vhd
......
hdl/rtl/registers/wr2rf_init_regs.cheby
View file @ 36d21fba
......@@ -115,6 +115,17 @@ memory-map:
name: locked
description: Set when locked
range: 1
- reg:
name: pll_ctrl
description: Ctrl lines to the main PLL (LTC6950)
access: rw
width: 16
children:
- field:
name: sync
description: Enables the sync line
comment: "LTC6950 sync is activated by a 0->1 transition"
range: 0
- reg:
name: dds_ctrl
description: dds (AD9910) control signals
......
hdl/rtl/registers/wr2rf_init_rf_regs.vhd
View file @ 36d21fba
-- Do not edit. Generated on Wed Nov 25 16:59:16 2020 by jgill
-- Do not edit. Generated on Thu Nov 26 11:18:23 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
......
hdl/rtl/registers/wr2rf_rftrigger_regs.vhd
View file @ 36d21fba
-- Do not edit. Generated on Wed Nov 25 16:59:16 2020 by jgill
-- Do not edit. Generated on Thu Nov 26 11:18:23 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_rftrigger_regs.cheby --gen-hdl wr2rf_rftrigger_regs.vhd
......
hdl/rtl/registers/wr2rf_vme_regs.vhd
View file @ 36d21fba
-- Do not edit. Generated on Wed Nov 25 16:59:17 2020 by jgill
-- Do not edit. Generated on Thu Nov 26 11:18:24 2020 by jgill
-- With Cheby 1.4.dev0 and these options:
-- -i wr2rf_vme_regs.cheby --gen-hdl wr2rf_vme_regs.vhd
......@@ -74,6 +74,10 @@ entity wr2rf_vme_regs is
-- Set when locked
init_pll_status_locked_i : in std_logic;
-- Ctrl lines to the main PLL (LTC6950)
-- LTC6950 sync is activated by a 0->1 transition
init_pll_ctrl_sync_o : out std_logic;
-- dds (AD9910) control signals
-- Full chip reset (master reset)
init_dds_ctrl_reset_o : out std_logic;
......@@ -240,6 +244,9 @@ architecture syn of wr2rf_vme_regs is
signal init_pin_ctrl_ext_ref_dir_reg : std_logic;
signal init_pin_ctrl_wreq : std_logic;
signal init_pin_ctrl_wack : std_logic;
signal init_pll_ctrl_sync_reg : std_logic;
signal init_pll_ctrl_wreq : std_logic;
signal init_pll_ctrl_wack : std_logic;
signal init_dds_ctrl_reset_reg : std_logic;
signal init_dds_ctrl_ioupdate_reg : std_logic;
signal init_dds_ctrl_profile_reg : std_logic_vector(2 downto 0);
......@@ -582,6 +589,22 @@ begin
-- Register init_pll_status
-- Register init_pll_ctrl
init_pll_ctrl_sync_o <= init_pll_ctrl_sync_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
init_pll_ctrl_sync_reg <= '0';
init_pll_ctrl_wack <= '0';
else
if init_pll_ctrl_wreq = '1' then
init_pll_ctrl_sync_reg <= wr_dat_d0(0);
end if;
init_pll_ctrl_wack <= init_pll_ctrl_wreq;
end if;
end if;
end process;
-- Register init_dds_ctrl
init_dds_ctrl_reset_o <= init_dds_ctrl_reset_reg;
init_dds_ctrl_ioupdate_o <= init_dds_ctrl_ioupdate_reg;
......@@ -1020,7 +1043,7 @@ begin
init_wrpc_o.dat(15 downto 0) <= wr_dat_d0;
-- Process for write requests.
process (wr_adr_d0, wr_req_d0, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_reg1_wack, ctrl_reg2_wack, init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack, init_mmcm_shift_wack, init_tmg_wack, init_pin_ctrl_wack, init_dds_ctrl_wack, init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack, init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack, init_nco_update_wack, init_nco_loc_or_wrs_wack, init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack, init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack, init_pll_spi_wack, init_rf_spi_wack, init_fw_update_wack, init_rf_wack, init_framerxtx_wack, init_wrpc_wack) begin
process (wr_adr_d0, wr_req_d0, ctrl_rf1_vtus_wack, ctrl_rf2_vtus_wack, ctrl_reg1_wack, ctrl_reg2_wack, init_clock_ctrl_wack, init_wrcore_ctrl_wack, init_iodelay_ctrl_wack, init_mmcm_shift_wack, init_tmg_wack, init_pin_ctrl_wack, init_pll_ctrl_wack, init_dds_ctrl_wack, init_nco_azimuthal_wack, init_nco_cabledelay_wack, init_nco_hb_wack, init_nco_h1_ftw_wack, init_nco_h1_prog_wack, init_nco_ctrl_wack, init_nco_update_wack, init_nco_loc_or_wrs_wack, init_svec_mup_ctrl_wack, init_svec_mup_rftrig_wack, init_svec_mup_fmc1_wack, init_svec_mup_fmc2_wack, init_pll_spi_wack, init_rf_spi_wack, init_fw_update_wack, init_rf_wack, init_framerxtx_wack, init_wrpc_wack) begin
ctrl_rf1_vtus_we <= '0';
ctrl_rf2_vtus_we <= '0';
ctrl_reg1_wreq <= '0';
......@@ -1031,6 +1054,7 @@ begin
init_mmcm_shift_wreq <= '0';
init_tmg_wreq <= '0';
init_pin_ctrl_wreq <= '0';
init_pll_ctrl_wreq <= '0';
init_dds_ctrl_wreq <= '0';
init_nco_azimuthal_wreq <= (others => '0');
init_nco_cabledelay_wreq <= (others => '0');
......@@ -1112,10 +1136,14 @@ begin
-- Reg init_pll_status
wr_ack_int <= wr_req_d0;
when "01000" =>
-- Reg init_pll_ctrl
init_pll_ctrl_wreq <= wr_req_d0;
wr_ack_int <= init_pll_ctrl_wack;
when "01001" =>
-- Reg init_dds_ctrl
init_dds_ctrl_wreq <= wr_req_d0;
wr_ack_int <= init_dds_ctrl_wack;
when "01001" =>
when "01010" =>
-- Reg init_dds_status
wr_ack_int <= wr_req_d0;
when others =>
......@@ -1388,7 +1416,7 @@ begin
end process;
-- Process for read requests.
process (adr_int, rd_req_int, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_reg1_reg, ctrl_reg2_reg, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg, init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i, init_clock_status_shift_busy_i, init_tmg_io_term_reg, init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_pin_ctrl_ext_ref_dir_reg, init_pll_status_error_i, init_pll_status_locked_i, init_dds_ctrl_reset_reg, init_dds_ctrl_profile_reg, init_dds_status_sync_error_i, init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg, init_nco_hb_value_reg, init_nco_h1_ftw_value_reg, init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg, init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg, init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg, init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg, init_svec_mup_ctrl_bclk_rfclk_sel_reg, init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg, init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg, init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg, init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg, init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg, init_svec_mup_fmc2_led_reg, init_rxframe_ftw_value_i, init_rxframe_ctrl_i, init_rxframe_counter_i, init_wrc_tai_value_i, init_wrc_cycles_value_i, init_wrc_status_linkup_i, init_wrc_status_time_valid_i, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_fw_update_i.dat, init_fw_update_rack, init_rf_i.dat, init_rf_rack, init_framerxtx_i.dat, init_framerxtx_rack, init_wrpc_i.dat, init_wrpc_rack) begin
process (adr_int, rd_req_int, ctrl_rf1_vtus_i.dat, ctrl_rf1_vtus_rack, ctrl_rf2_vtus_i.dat, ctrl_rf2_vtus_rack, ctrl_reg1_reg, ctrl_reg2_reg, init_clock_ctrl_clk_sel_reg, init_clock_ctrl_mmcm_reset_reg, init_wrcore_ctrl_reset_n_reg, init_iodelay_ctrl_reset_reg, init_clock_status_mmcm_locked_i, init_clock_status_shift_busy_i, init_tmg_io_term_reg, init_tmg_io_oe_reg, init_tmg_clk_term_reg, init_tmg_clk_oe_reg, init_pin_ctrl_ext_ref_dir_reg, init_pll_status_error_i, init_pll_status_locked_i, init_pll_ctrl_sync_reg, init_dds_ctrl_reset_reg, init_dds_ctrl_profile_reg, init_dds_status_sync_error_i, init_nco_azimuthal_value_reg, init_nco_cabledelay_value_reg, init_nco_hb_value_reg, init_nco_h1_ftw_value_reg, init_nco_h1_prog_value_reg, init_nco_ctrl_reset_nco_reg, init_nco_ctrl_reset_slip_reg, init_nco_ctrl_reset_fsk_reg, init_nco_ctrl_rate_reg, init_nco_loc_or_wrs_params_sel_reg, init_svec_mup_ctrl_gpio_sel_reg, init_svec_mup_ctrl_led_sel_reg, init_svec_mup_ctrl_bclk_rfclk_sel_reg, init_svec_mup_ctrl_ila_sel_reg, init_svec_mup_rftrig_t1stop_reg, init_svec_mup_rftrig_t1start_reg, init_svec_mup_rftrig_t2stop_reg, init_svec_mup_rftrig_t2start_reg, init_svec_mup_fmc1_term_reg, init_svec_mup_fmc1_oe_n_reg, init_svec_mup_fmc1_led_reg, init_svec_mup_fmc2_term_reg, init_svec_mup_fmc2_oe_n_reg, init_svec_mup_fmc2_led_reg, init_rxframe_ftw_value_i, init_rxframe_ctrl_i, init_rxframe_counter_i, init_wrc_tai_value_i, init_wrc_cycles_value_i, init_wrc_status_linkup_i, init_wrc_status_time_valid_i, init_pll_spi_i.dat, init_pll_spi_rack, init_rf_spi_i.dat, init_rf_spi_rack, init_fw_update_i.dat, init_fw_update_rack, init_rf_i.dat, init_rf_rack, init_framerxtx_i.dat, init_framerxtx_rack, init_wrpc_i.dat, init_wrpc_rack) begin
-- By default ack read requests
rd_dat_d0 <= (others => 'X');
ctrl_rf1_vtus_re <= '0';
......@@ -1477,6 +1505,11 @@ begin
rd_dat_d0(1) <= init_pll_status_locked_i;
rd_dat_d0(15 downto 2) <= (others => '0');
when "01000" =>
-- Reg init_pll_ctrl
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= init_pll_ctrl_sync_reg;
rd_dat_d0(15 downto 1) <= (others => '0');
when "01001" =>
-- Reg init_dds_ctrl
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= init_dds_ctrl_reset_reg;
......@@ -1484,7 +1517,7 @@ begin
rd_dat_d0(3) <= '0';
rd_dat_d0(6 downto 4) <= init_dds_ctrl_profile_reg;
rd_dat_d0(15 downto 7) <= (others => '0');
when "01001" =>
when "01010" =>
-- Reg init_dds_status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= init_dds_status_sync_error_i;
......
hdl/rtl/wr2rf_dds.vhd
View file @ 36d21fba
......@@ -31,29 +31,25 @@ use unisim.vcomponents.all;
use work.wishbone_pkg.all;
entity wr2rf_dds is
generic (
g_use_fine_delay : boolean := false );
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_sys_n_i : in std_logic;
port (
clk_sys_i : in std_logic;
clk_ref_i : in std_logic;
rst_sys_n_i : in std_logic;
pps_csync_i : in std_logic;
rf_reset_nco_i : in std_logic;
pps_csync_i : in std_logic;
rf_reset_nco_i : in std_logic;
dds_sync_p_o : out std_logic;
dds_sync_n_o : out std_logic;
dds_sync_p_o : out std_logic;
dds_sync_n_o : out std_logic;
--clka_sync_p_o : out std_logic;
--clka_sync_n_o : out std_logic;
--clkb_sync_p_o : out std_logic;
--clkb_sync_n_o : out std_logic;
--dds_ioupdate_n_o : out std_logic;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out );
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
wb_slave_o : out t_wishbone_slave_out );
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of wr2rf_dds : entity is "yes";
attribute keep_hierarchy : STRING;
attribute keep_hierarchy of wr2rf_dds : entity is "yes";
end entity;
architecture rtl of wr2rf_dds is
......@@ -65,64 +61,55 @@ architecture rtl of wr2rf_dds is
begin
xwb_fine_pulse_gen_i : entity work.xwb_fine_pulse_gen
generic map
(
g_use_odelay => "111100",
g_num_channels => 4,
g_use_external_serdes_clock => false,
g_target_platform => "Kintex7" )
port map (
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
rst_sys_n_i => rst_sys_n_i,
pps_p_i => pps_csync_i,
clk_ser_ext_i => '0',
ext_trigger_p_i => rf_reset_nco_i,
pulse_o(0) => dds_sync_prebuf,
pulse_o(1) => clka_sync_prebuf,
pulse_o(2) => clkb_sync_prebuf,
pulse_o(3) => dds_ioupdate_prebuf,
slave_i => wb_slave_i,
slave_o => wb_slave_o );
dds_sync_i : obufds
generic map(
slew => "FAST" )
port map(
o => dds_sync_p_o,
ob => dds_sync_n_o,
i => dds_sync_prebuf );
--U_OBuf_CLKA_Sync : obufds
-- generic map(
-- IOSTANDARD => "LVDS_25",
-- SLEW => "FAST")
-- port map(
-- O => clka_sync_p_o,
-- OB => clka_sync_n_o,
-- I => clka_sync_prebuf);
--U_OBuf_CLKB_Sync : obufds
-- generic map(
-- IOSTANDARD => "LVDS_25",
-- SLEW => "FAST")
-- port map(
-- O => clkb_sync_p_o,
-- OB => clkb_sync_n_o,
-- I => clkb_sync_prebuf);
--U_OBuf_DDS0_IOUPDATE : OBUFDS
-- generic map(
-- IOSTANDARD => "LVDS_25",
-- SLEW => "FAST")
-- port map(
-- O => dds_ioupdate_p_o,
-- OB => dds_ioupdate_n_o,
-- I => dds_ioupdate_prebuf);
g_not_fine_delay : if (g_use_fine_delay = false) generate
begin
dds_sync_i : obufds
generic map(
slew => "FAST" )
port map(
o => dds_sync_p_o,
ob => dds_sync_n_o,
i => rf_reset_nco_i );
end generate;
g_fine_delay : if (g_use_fine_delay = true) generate
begin
xwb_fine_pulse_gen_i : entity work.xwb_fine_pulse_gen
generic map
(
g_use_odelay => "111100",
g_num_channels => 4,
g_use_external_serdes_clock => false,
g_target_platform => "Kintex7" )
port map (
clk_sys_i => clk_sys_i,
clk_ref_i => clk_ref_i,
rst_sys_n_i => rst_sys_n_i,
pps_p_i => pps_csync_i,
clk_ser_ext_i => '0',
ext_trigger_p_i => rf_reset_nco_i,
pulse_o(0) => dds_sync_prebuf,
pulse_o(1) => clka_sync_prebuf,
pulse_o(2) => clkb_sync_prebuf,
pulse_o(3) => dds_ioupdate_prebuf,
slave_i => wb_slave_i,
slave_o => wb_slave_o );
dds_sync_i : obufds
generic map(
slew => "FAST" )
port map(
o => dds_sync_p_o,
ob => dds_sync_n_o,
i => dds_sync_prebuf );
end generate;
end architecture;
hdl/rtl/wr2rf_regs_core.vhd
View file @ 36d21fba
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hdl/top/wr2rf_vme/wr2rf_vme.vhd
View file @ 36d21fba
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