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wr2rf-vme
Commit 0428923e authored by Tristan Gingold's avatar Tristan Gingold
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tb_vtu: simplify assertions.

parent b470113a
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Showing with 1 addition and 7 deletions
hdl/testbench/vtu/tb_vtu.vhd
View file @ 0428923e
......@@ -279,7 +279,7 @@ begin
assert val (TRIGUNIT_REGS_STATUS_MISSVALID_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_MISSREADY_OFFSET) = '0' severity error;
-- Should be 0 if close enough to the start pulse.
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_STARTREADY_OFFSET) = '0' severity note;
assert val (TRIGUNIT_REGS_STATUS_RUNNING_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGBVALUE_OFFSET) = '0' severity error;
assert val (TRIGUNIT_REGS_STATUS_WRONGHTVALUE_OFFSET) = '0' severity error;
......@@ -301,12 +301,6 @@ begin
-- Check online registers
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 6, val);
assert val = std_logic_vector(to_unsigned(wval, 16)) severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 4, val);
assert val = x"0000" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 2, val);
assert val = x"0000" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_WVALUEONLINE + 0, val);
assert val = x"0000" severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_HTVALUEONLINE + 6, val);
assert val = std_logic_vector(to_unsigned(hval, 16)) severity error;
read16_pl (clk_sys, wb_in, wb_out, ADDR_TRIGUNIT_REGS_BVALUEONLINE + 6, val);
......
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