create_project -force svec_wr2rf_vme ./
set_property part xc6slx150tfgg900-3 [current_project]
set_property target_language vhdl [current_project]
set_property top svec_wr2rf_vme [get_property srcset [current_run]]
set_property -name {steps.bitgen.args.More Options} -value {-g Binary:Yes} -objects [get_runs impl_1]
source files.tcl
update_compile_order -fileset sources_1
update_compile_order -fileset sim_1

#set_property steps.map.args.timing true [get_runs impl_1]
#set_property steps.map.args.logic_opt on [get_runs impl_1]
#set_property steps.map.args.ol high [get_runs impl_1]
#set_property steps.par.args.ol high [get_runs impl_1]


