action = "synthesis"
target = "xilinx"
board  = "svec"

syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"

syn_top = "svec_wr2rf_vme"
syn_project = "svec_wr2rf_vme.ppr"
syn_tool = "planahead"

files = ["svec_wr2rf_vme.ucf"]

modules = {'local': ['../../top/svec']}
           
