// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
// Date        : Thu May 11 09:02:12 2023
// Host        : cispace running 64-bit Ubuntu 22.04.2 LTS
// Command     : write_verilog RFNCO.v
// Design      : RFNCO_wrapper
// Purpose     : This is a Verilog netlist of the current design or from a specific cell of the design. The output is an
//               IEEE 1364-2001 compliant Verilog HDL file that contains netlist information obtained from the input
//               design files.
// Device      : xc7k160tfbg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CORE_GENERATION_INFO = "RFNCO,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=RFNCO,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=60,numReposBlks=56,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=2,numHdlrefBlks=35,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "RFNCO.hwdef" *) 
module RFNCO
   (AM_auto_on_o,
    AM_o,
    FTW_H1_on_muxed_o,
    FTW_H1_on_muxed_vld_o,
    aximm_i_araddr,
    aximm_i_arprot,
    aximm_i_arready,
    aximm_i_arvalid,
    aximm_i_awaddr,
    aximm_i_awprot,
    aximm_i_awready,
    aximm_i_awvalid,
    aximm_i_bready,
    aximm_i_bresp,
    aximm_i_bvalid,
    aximm_i_rdata,
    aximm_i_rready,
    aximm_i_rresp,
    aximm_i_rvalid,
    aximm_i_wdata,
    aximm_i_wready,
    aximm_i_wstrb,
    aximm_i_wvalid,
    clk_i,
    coef_o,
    coef_vld_o,
    cos_IF0_o,
    cos_IF1_o,
    ext_reset_enable_o,
    ext_reset_o,
    frev_main_o,
    frev_o,
    ftw_H1_o,
    ftw_H1_on_o,
    ftw_LO_0_i,
    ftw_LO_1_i,
    ftw_valid_o,
    interlock_o,
    offset_FSK_i_0,
    offset_i_0,
    phase_H1_comp_o,
    phase_H1_main_o,
    phase_H1_o,
    phase_H1_offset_o,
    phase_H1_prog_offset_o,
    phase_H1_slip_o,
    phase_IF0_o,
    phase_IF1_o,
    rst_i,
    sin_IF0_o,
    sin_IF1_o,
    sincos_vld_o,
    tw_H1_o,
    wr_rf_frame_bus_i_dftw_h1_slip0,
    wr_rf_frame_bus_i_dftw_h1_slip1,
    wr_rf_frame_bus_i_ftw_h1_main,
    wr_rf_frame_bus_i_ftw_h1_on,
    wr_rf_frame_bus_i_ftw_h1_prog,
    wr_rf_frame_bus_i_inputs_valid,
    wr_rf_frame_bus_i_rate,
    wr_rf_frame_bus_i_reset_fsk,
    wr_rf_frame_bus_i_reset_nco,
    wr_rf_frame_bus_i_reset_slip);
  output AM_auto_on_o;
  output AM_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.FTW_H1_ON_MUXED_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.FTW_H1_ON_MUXED_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]FTW_H1_on_muxed_o;
  output FTW_H1_on_muxed_vld_o;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i ARADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aximm_i, ADDR_WIDTH 12, ARUSER_WIDTH 0, AWUSER_WIDTH 0, BUSER_WIDTH 0, CLK_DOMAIN RFNCO_clk_i, DATA_WIDTH 32, FREQ_HZ 125000000, HAS_BRESP 1, HAS_BURST 0, HAS_CACHE 0, HAS_LOCK 0, HAS_PROT 1, HAS_QOS 0, HAS_REGION 0, HAS_RRESP 1, HAS_WSTRB 1, ID_WIDTH 0, MAX_BURST_LENGTH 1, NUM_READ_OUTSTANDING 1, NUM_READ_THREADS 1, NUM_WRITE_OUTSTANDING 1, NUM_WRITE_THREADS 1, PHASE 0.000, PROTOCOL AXI4LITE, READ_WRITE_MODE READ_WRITE, RUSER_BITS_PER_BYTE 0, RUSER_WIDTH 0, SUPPORTS_NARROW_BURST 0, WUSER_BITS_PER_BYTE 0, WUSER_WIDTH 0" *) input [11:0]aximm_i_araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i ARPROT" *) input [2:0]aximm_i_arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i ARREADY" *) output aximm_i_arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i ARVALID" *) input aximm_i_arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i AWADDR" *) input [11:0]aximm_i_awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i AWPROT" *) input [2:0]aximm_i_awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i AWREADY" *) output aximm_i_awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i AWVALID" *) input aximm_i_awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i BREADY" *) input aximm_i_bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i BRESP" *) output [1:0]aximm_i_bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i BVALID" *) output aximm_i_bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i RDATA" *) output [31:0]aximm_i_rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i RREADY" *) input aximm_i_rready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i RRESP" *) output [1:0]aximm_i_rresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i RVALID" *) output aximm_i_rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i WDATA" *) input [31:0]aximm_i_wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i WREADY" *) output aximm_i_wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i WSTRB" *) input [3:0]aximm_i_wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 aximm_i WVALID" *) input aximm_i_wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK.CLK_I CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK.CLK_I, ASSOCIATED_BUSIF aximm_i, ASSOCIATED_RESET rst_i, CLK_DOMAIN RFNCO_clk_i, FREQ_HZ 125000000, PHASE 0.000" *) input clk_i;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.COEF_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.COEF_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value -4294967258} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [31:0]coef_o;
  output coef_vld_o;
  output [24:0]cos_IF0_o;
  output [24:0]cos_IF1_o;
  output ext_reset_enable_o;
  output [0:0]ext_reset_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.FREV_MAIN_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.FREV_MAIN_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) output frev_main_o;
  output frev_o;
  output [47:0]ftw_H1_o;
  output [47:0]ftw_H1_on_o;
  input [47:0]ftw_LO_0_i;
  input [47:0]ftw_LO_1_i;
  output [0:0]ftw_valid_o;
  output interlock_o;
  input [47:0]offset_FSK_i_0;
  input [47:0]offset_i_0;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_H1_COMP_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_H1_COMP_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}" *) output [47:0]phase_H1_comp_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_H1_MAIN_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_H1_MAIN_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]phase_H1_main_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_H1_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_H1_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]phase_H1_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_H1_OFFSET_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_H1_OFFSET_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]phase_H1_offset_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_H1_PROG_OFFSET_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_H1_PROG_OFFSET_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]phase_H1_prog_offset_o;
  output [47:0]phase_H1_slip_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_IF0_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_IF0_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]phase_IF0_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.PHASE_IF1_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.PHASE_IF1_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]phase_IF1_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.RST_I RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.RST_I, POLARITY ACTIVE_HIGH" *) input rst_i;
  output [24:0]sin_IF0_o;
  output [24:0]sin_IF1_o;
  output [0:0]sincos_vld_o;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 DATA.TW_H1_O DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DATA.TW_H1_O, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value -4294967228} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [31:0]tw_H1_o;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i dFTW_H1_slip0" *) input [31:0]wr_rf_frame_bus_i_dftw_h1_slip0;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i dFTW_H1_slip1" *) input [31:0]wr_rf_frame_bus_i_dftw_h1_slip1;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i FTW_H1_main" *) input [47:0]wr_rf_frame_bus_i_ftw_h1_main;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i FTW_H1_on" *) input [47:0]wr_rf_frame_bus_i_ftw_h1_on;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i FTW_H1_prog" *) input [47:0]wr_rf_frame_bus_i_ftw_h1_prog;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i inputs_valid" *) input wr_rf_frame_bus_i_inputs_valid;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i rate" *) input [2:0]wr_rf_frame_bus_i_rate;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i reset_FSK" *) input wr_rf_frame_bus_i_reset_fsk;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i reset_NCO" *) input wr_rf_frame_bus_i_reset_nco;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_rf_frame_bus_i reset_slip" *) input wr_rf_frame_bus_i_reset_slip;

  wire AM_auto_on_o;
  wire AM_o;
  wire [47:0]B_1;
  wire [47:0]FTW_H1_on_muxed_o;
  wire FTW_H1_on_muxed_vld_o;
  wire [47:0]H1_mux1_C;
  wire [47:0]H1_mux_C;
  wire [47:0]H1_on_mux_C;
  wire [47:0]LO0_mux1_C;
  wire [31:0]RFNCO_Divider_HLS_0_COEF_V;
  wire RFNCO_Divider_HLS_0_COEF_V_ap_vld;
  wire RFNCO_HLS_0_outputs_AM;
  wire RFNCO_HLS_0_outputs_Phase_H1_V_ap_vld;
  wire RFNCO_HLS_0_outputs_frev;
  wire [15:0]RegCtrl_rfnco_0_ftw_h;
  wire [47:0]RegCtrl_rfnco_0_ftw_h1;
  wire [47:0]RegCtrl_rfnco_0_ftw_lo0;
  wire [47:0]RegCtrl_rfnco_0_ftw_lo1;
  wire [47:0]RegCtrl_rfnco_0_ftw_offsetH1;
  wire [47:0]RegCtrl_rfnco_0_ftw_on;
  wire [2:0]RegCtrl_rfnco_0_ftw_rate;
  wire [47:0]WRFrameBusSlave_0_slave_FTW_H1_main;
  wire [47:0]WRFrameBusSlave_0_slave_FTW_H1_on;
  wire [47:0]WRFrameBusSlave_0_slave_FTW_H1_prog;
  wire [31:0]WRFrameBusSlave_0_slave_dFTW_H1_slip0;
  wire [31:0]WRFrameBusSlave_0_slave_dFTW_H1_slip1;
  wire WRFrameBusSlave_0_slave_inputs_valid;
  wire [2:0]WRFrameBusSlave_0_slave_rate;
  wire ap_rst_1;
  wire [11:0]aximm_i_araddr;
  wire [2:0]aximm_i_arprot;
  wire aximm_i_arready;
  wire aximm_i_arvalid;
  wire [11:0]aximm_i_awaddr;
  wire [2:0]aximm_i_awprot;
  wire aximm_i_awready;
  wire aximm_i_awvalid;
  wire aximm_i_bready;
  wire [1:0]aximm_i_bresp;
  wire aximm_i_bvalid;
  wire [31:0]aximm_i_rdata;
  wire aximm_i_rready;
  wire [1:0]aximm_i_rresp;
  wire aximm_i_rvalid;
  wire [31:0]aximm_i_wdata;
  wire aximm_i_wready;
  wire [3:0]aximm_i_wstrb;
  wire aximm_i_wvalid;
  wire b_memory_map_control_enableFSK;
  wire b_memory_map_control_enableFreqDoubling_o;
  wire b_memory_map_control_enableSlip;
  wire b_memory_map_control_forceAM_o;
  wire b_memory_map_control_reset;
  wire b_memory_map_control_resetFSK;
  wire b_memory_map_control_resetSlip;
  wire b_memory_map_control_selDftwH1slip;
  wire b_memory_map_control_selFtwH1;
  wire b_memory_map_control_selFtwH1On;
  wire b_memory_map_control_selFtwLo0;
  wire b_memory_map_control_selFtwLo1;
  wire b_memory_map_control_selLoad_o;
  wire b_memory_map_control_selOffsetFskH1;
  wire b_memory_map_control_selOffsetH1;
  wire b_memory_map_control_selRate;
  wire b_memory_map_control_selWrDftwH1slip;
  wire b_memory_map_control_selWrFtwH1;
  wire b_memory_map_control_signIF0;
  wire b_memory_map_control_signIF1;
  wire b_memory_map_control_slipSign;
  wire b_memory_map_control_softLoad;
  wire [31:0]b_memory_map_delayComp;
  wire [31:0]b_memory_map_ftw_slip;
  wire [47:0]b_memory_map_inputs_offsetAM_reg_o;
  wire [47:0]b_memory_map_inputs_pulseLengthAM_reg_o;
  wire [47:0]b_mux_C;
  wire [24:0]b_slices_sin_IF0_o;
  wire [24:0]b_slices_sin_IF1_o;
  wire clk_i;
  wire cmp_RFNCO_Divider_HLS_ap_done;
  wire [47:0]cmp_RFNCO_Divider_HLS_offset_H1_comp_V;
  wire cmp_RFNCO_Divider_HLS_tw_H1_V_ap_vld;
  wire cmp_RFNCO_HLS_outputs_valid;
  wire cmp_WRFrameBusSlave_slave_reset_FSK;
  wire cmp_WRFrameBusSlave_slave_reset_NCO;
  wire cmp_WRFrameBusSlave_slave_reset_slip;
  wire [47:0]cmp_bit_shift_data_o;
  wire [31:0]cmp_concat_phase_in_dout;
  wire [31:0]cmp_concat_phase_in_dout1;
  wire cmp_dds_IF0_m_axis_data_tlast;
  wire [31:0]cmp_dftw_slip_mux_C;
  wire [47:0]cmp_ftw_slip_adder_ftw_H1_o;
  wire cmp_or_reset_FSK_Res;
  wire cmp_or_reset_slip_Res;
  wire cmp_or_softLoad_Res;
  wire [24:0]cmp_sign_invert0_signed_o;
  wire [24:0]cmp_sign_invert1_signed_o;
  wire [24:0]cmp_slice_phase_IF0_Dout;
  wire [24:0]cmp_slice_phase_IF1_Dout;
  wire [24:0]cmp_slice_sin_if_Dout;
  wire [24:0]cmp_slice_sin_if_Dout1;
  wire [6:0]cmp_zero_7b_dout;
  wire [31:0]coef_o;
  wire coef_vld_o;
  wire [24:0]cos_IF0_o;
  wire [24:0]cos_IF1_o;
  wire [63:0]dds_compiler_0_m_axis_data_tdata;
  wire [63:0]dds_compiler_0_m_axis_data_tdata1;
  wire ext_reset_enable_o;
  wire [0:0]ext_reset_o;
  wire frev_main_o;
  wire frev_o;
  wire [47:0]ftw_H1_o;
  wire [47:0]ftw_H1_on_o;
  wire [47:0]ftw_LO_0_i;
  wire [47:0]ftw_LO_1_i;
  wire [0:0]ftw_valid_o;
  wire [47:0]generic_mux_0_C;
  wire interlock_o;
  wire [47:0]memory_map_ftw_offsetFSK;
  wire [47:0]offset_FSK_i_0;
  wire [47:0]offset_i_0;
  wire [2:0]on_mux1_C;
  wire [47:0]phase_H1_comp_o;
  wire [47:0]phase_H1_main_o;
  wire [47:0]phase_H1_o;
  wire [47:0]phase_H1_offset_o;
  wire [47:0]phase_H1_prog_offset_o;
  wire [47:0]phase_H1_slip_o;
  wire [47:0]phase_IF0_o;
  wire [47:0]phase_IF1_o;
  wire [47:0]rate_mux1_C;
  wire rst_i;
  wire sel_1;
  wire [24:0]sin_IF0_o;
  wire [24:0]sin_IF1_o;
  wire [0:0]sincos_vld_o;
  wire [31:0]tw_H1_o;
  wire util_vector_logic_0_Res;
  wire valid_dout;
  wire [31:0]wr_rf_frame_bus_i_dftw_h1_slip0;
  wire [31:0]wr_rf_frame_bus_i_dftw_h1_slip1;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_main;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_on;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_prog;
  wire wr_rf_frame_bus_i_inputs_valid;
  wire [2:0]wr_rf_frame_bus_i_rate;
  wire wr_rf_frame_bus_i_reset_fsk;
  wire wr_rf_frame_bus_i_reset_nco;
  wire wr_rf_frame_bus_i_reset_slip;

  b_NCO_rst_imp_1APBVP b_NCO_rst
       (.NCO_rst_i(cmp_WRFrameBusSlave_slave_reset_NCO),
        .NCO_rst_o(util_vector_logic_0_Res),
        .control_reset(b_memory_map_control_reset),
        .ext_reset_enable_o(ext_reset_enable_o),
        .ext_reset_o(ext_reset_o),
        .master_reset_o(ap_rst_1),
        .rst_i(rst_i),
        .valid_i(WRFrameBusSlave_0_slave_inputs_valid));
  b_memory_map_imp_QHGYDM b_memory_map
       (.AM_auto_on_o(AM_auto_on_o),
        .aximm_i_araddr(aximm_i_araddr),
        .aximm_i_arprot(aximm_i_arprot),
        .aximm_i_arready(aximm_i_arready),
        .aximm_i_arvalid(aximm_i_arvalid),
        .aximm_i_awaddr(aximm_i_awaddr),
        .aximm_i_awprot(aximm_i_awprot),
        .aximm_i_awready(aximm_i_awready),
        .aximm_i_awvalid(aximm_i_awvalid),
        .aximm_i_bready(aximm_i_bready),
        .aximm_i_bresp(aximm_i_bresp),
        .aximm_i_bvalid(aximm_i_bvalid),
        .aximm_i_rdata(aximm_i_rdata),
        .aximm_i_rready(aximm_i_rready),
        .aximm_i_rresp(aximm_i_rresp),
        .aximm_i_rvalid(aximm_i_rvalid),
        .aximm_i_wdata(aximm_i_wdata),
        .aximm_i_wready(aximm_i_wready),
        .aximm_i_wstrb(aximm_i_wstrb),
        .aximm_i_wvalid(aximm_i_wvalid),
        .clk_i(clk_i),
        .coef_o(coef_o),
        .control_enableFSK(b_memory_map_control_enableFSK),
        .control_enableFreqDoubling_o(b_memory_map_control_enableFreqDoubling_o),
        .control_enableSlip(b_memory_map_control_enableSlip),
        .control_forceAM_o(b_memory_map_control_forceAM_o),
        .control_reset(b_memory_map_control_reset),
        .control_resetFSK(b_memory_map_control_resetFSK),
        .control_resetSlip(b_memory_map_control_resetSlip),
        .control_selDftwH1slip(b_memory_map_control_selDftwH1slip),
        .control_selFtwH1(b_memory_map_control_selFtwH1),
        .control_selFtwH1On(b_memory_map_control_selFtwH1On),
        .control_selFtwH1prog_o(sel_1),
        .control_selFtwLo0(b_memory_map_control_selFtwLo0),
        .control_selFtwLo1(b_memory_map_control_selFtwLo1),
        .control_selLoad(b_memory_map_control_selLoad_o),
        .control_selOffsetFskH1(b_memory_map_control_selOffsetFskH1),
        .control_selOffsetH1(b_memory_map_control_selOffsetH1),
        .control_selRate(b_memory_map_control_selRate),
        .control_selWrDftwH1slip(b_memory_map_control_selWrDftwH1slip),
        .control_selWrFtwH1(b_memory_map_control_selWrFtwH1),
        .control_signIF0(b_memory_map_control_signIF0),
        .control_signIF1(b_memory_map_control_signIF1),
        .control_slipSign(b_memory_map_control_slipSign),
        .control_softLoad(b_memory_map_control_softLoad),
        .delayComp(b_memory_map_delayComp),
        .ext_reset_enable_o(ext_reset_enable_o),
        .ext_reset_o(ext_reset_o),
        .ftw_h1(RegCtrl_rfnco_0_ftw_h1),
        .ftw_h1Prog(B_1),
        .ftw_lo0(RegCtrl_rfnco_0_ftw_lo0),
        .ftw_lo1(RegCtrl_rfnco_0_ftw_lo1),
        .ftw_on(RegCtrl_rfnco_0_ftw_on),
        .ftw_slip(b_memory_map_ftw_slip),
        .inputs_h(RegCtrl_rfnco_0_ftw_h),
        .inputs_offsetAM_o(b_memory_map_inputs_offsetAM_reg_o),
        .inputs_offsetFSK(memory_map_ftw_offsetFSK),
        .inputs_offsetH1(RegCtrl_rfnco_0_ftw_offsetH1),
        .inputs_pulseLengthAM_o(b_memory_map_inputs_pulseLengthAM_reg_o),
        .inputs_rate(RegCtrl_rfnco_0_ftw_rate),
        .interlock_o(interlock_o),
        .phase_H1_comp_o(phase_H1_comp_o),
        .phase_H1_main_o(phase_H1_main_o),
        .phase_H1_o(phase_H1_o),
        .phase_H1_slip_o(phase_H1_slip_o),
        .phase_IF0_o(phase_IF0_o),
        .phase_IF1_o(phase_IF1_o),
        .presentLatch_am(RFNCO_HLS_0_outputs_AM),
        .presentLatch_frev(RFNCO_HLS_0_outputs_frev),
        .presentLatch_load(cmp_or_softLoad_Res),
        .presentLatch_tw(cmp_RFNCO_Divider_HLS_tw_H1_V_ap_vld),
        .rst_i(rst_i),
        .status_coefVld(RFNCO_Divider_HLS_0_COEF_V_ap_vld),
        .status_phaseH1Vld(RFNCO_HLS_0_outputs_Phase_H1_V_ap_vld),
        .tw_H1_o(tw_H1_o));
  b_mux_imp_1CMX53U b_mux
       (.H1_mux_o(H1_mux_C),
        .H1_on_mux_o(H1_on_mux_C),
        .H1_prog_mux_o(b_mux_C),
        .LO0_mux_o(H1_mux1_C),
        .LO1_mux_o(LO0_mux1_C),
        .dftw_H1_slip0_i(WRFrameBusSlave_0_slave_dFTW_H1_slip0),
        .dftw_H1_slip1_i(WRFrameBusSlave_0_slave_dFTW_H1_slip1),
        .dftw_slip_mm(b_memory_map_ftw_slip),
        .dftw_slip_mux_o(cmp_dftw_slip_mux_C),
        .ftw_H1_main_i(WRFrameBusSlave_0_slave_FTW_H1_main),
        .ftw_H1_mm_i(RegCtrl_rfnco_0_ftw_h1),
        .ftw_H1_on_i(WRFrameBusSlave_0_slave_FTW_H1_on),
        .ftw_H1_on_mm_i(RegCtrl_rfnco_0_ftw_on),
        .ftw_H1_prog_i(WRFrameBusSlave_0_slave_FTW_H1_prog),
        .ftw_H1_prog_mm_i(B_1),
        .ftw_LO_0_i(ftw_LO_0_i),
        .ftw_LO_0_mm_i(RegCtrl_rfnco_0_ftw_lo0),
        .ftw_LO_1_i(ftw_LO_1_i),
        .ftw_LO_1_mm_i(RegCtrl_rfnco_0_ftw_lo1),
        .offset_FSK_i_0(offset_FSK_i_0),
        .offset_FSK_mm_i(memory_map_ftw_offsetFSK),
        .offset_FSK_mux_o(generic_mux_0_C),
        .offset_i_0(offset_i_0),
        .offset_mm_i(RegCtrl_rfnco_0_ftw_offsetH1),
        .offset_mux_o(rate_mux1_C),
        .rate_i(WRFrameBusSlave_0_slave_rate),
        .rate_mm_i(RegCtrl_rfnco_0_ftw_rate),
        .rate_mux_o(on_mux1_C),
        .sel_H1_mux(b_memory_map_control_selFtwH1),
        .sel_H1_on_mux(b_memory_map_control_selFtwH1On),
        .sel_H1_prog_mux(sel_1),
        .sel_LO0_mux(b_memory_map_control_selFtwLo0),
        .sel_LO1_mux(b_memory_map_control_selFtwLo1),
        .sel_dftw_slip_mux(b_memory_map_control_selDftwH1slip),
        .sel_offset_FSK_mux(b_memory_map_control_selOffsetFskH1),
        .sel_offset_mux(b_memory_map_control_selOffsetH1),
        .sel_rate_mux(b_memory_map_control_selRate),
        .sel_wr_dftw_slip_mux(b_memory_map_control_selWrDftwH1slip),
        .sel_wr_ftw_H1_mux(b_memory_map_control_selWrFtwH1));
  b_slices_imp_11H86KG b_slices
       (.\bbstub_outputs_phase_IF_0_V[47] (phase_IF0_o),
        .cos_IF0_o(cmp_slice_sin_if_Dout),
        .cos_IF1_o(cmp_slice_sin_if_Dout1),
        .phase_IF0_o(cmp_slice_phase_IF0_Dout),
        .phase_IF1_i(cmp_bit_shift_data_o),
        .phase_IF1_o(cmp_slice_phase_IF1_Dout),
        .sin_IF0_o(b_slices_sin_IF0_o),
        .sin_IF1_o(b_slices_sin_IF1_o),
        .sincos_IF0_i(dds_compiler_0_m_axis_data_tdata),
        .sincos_IF1_i(dds_compiler_0_m_axis_data_tdata1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlconstant_v1_1_5_xlconstant,Vivado 2018.2" *) 
  RFNCO_c_valid_0 c_valid
       (.dout(valid_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "RFNCO_Divider_HLS,Vivado 2018.2" *) 
  RFNCO_cmp_RFNCO_Divider_HLS_0 cmp_RFNCO_Divider_HLS
       (.COEF_V(RFNCO_Divider_HLS_0_COEF_V),
        .COEF_V_ap_vld(RFNCO_Divider_HLS_0_COEF_V_ap_vld),
        .ap_clk(clk_i),
        .ap_done(cmp_RFNCO_Divider_HLS_ap_done),
        .ap_rst(ap_rst_1),
        .ap_start(cmp_or_softLoad_Res),
        .inputs_delay_comp_V(b_memory_map_delayComp),
        .inputs_delay_comp_V_ap_vld(valid_dout),
        .inputs_enable_FSK(b_memory_map_control_enableFSK),
        .inputs_enable_FSK_ap_vld(valid_dout),
        .inputs_ftw_H1_V(cmp_ftw_slip_adder_ftw_H1_o),
        .inputs_ftw_H1_V_ap_vld(valid_dout),
        .inputs_ftw_H1_on_V(H1_on_mux_C),
        .inputs_ftw_H1_on_V_ap_vld(valid_dout),
        .inputs_offset_H1_V(rate_mux1_C),
        .inputs_offset_H1_V_ap_vld(valid_dout),
        .inputs_rate_V(on_mux1_C),
        .inputs_rate_V_ap_vld(valid_dout),
        .offset_H1_comp_V(cmp_RFNCO_Divider_HLS_offset_H1_comp_V),
        .phase_H1_comp_V(phase_H1_comp_o),
        .tw_H1_V(tw_H1_o),
        .tw_H1_V_ap_vld(cmp_RFNCO_Divider_HLS_tw_H1_V_ap_vld));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "RFNCO_HLS,Vivado 2018.2" *) 
  RFNCO_cmp_RFNCO_HLS_0 cmp_RFNCO_HLS
       (.ap_clk(clk_i),
        .ap_rst(ap_rst_1),
        .inputs_H_V(RegCtrl_rfnco_0_ftw_h),
        .inputs_H_V_ap_vld(valid_dout),
        .inputs_coef_V(RFNCO_Divider_HLS_0_COEF_V),
        .inputs_coef_V_ap_vld(valid_dout),
        .inputs_dftw_H1_slip_V(cmp_dftw_slip_mux_C),
        .inputs_dftw_H1_slip_V_ap_vld(valid_dout),
        .inputs_enable_FSK(b_memory_map_control_enableFSK),
        .inputs_enable_FSK_ap_vld(valid_dout),
        .inputs_enable_slip(b_memory_map_control_enableSlip),
        .inputs_enable_slip_ap_vld(valid_dout),
        .inputs_force_AM(b_memory_map_control_forceAM_o),
        .inputs_force_AM_ap_vld(valid_dout),
        .inputs_ftw_H1_V(H1_mux_C),
        .inputs_ftw_H1_V_ap_vld(valid_dout),
        .inputs_ftw_H1_on_V(H1_on_mux_C),
        .inputs_ftw_H1_on_V_ap_vld(valid_dout),
        .inputs_ftw_H1_prog_V(b_mux_C),
        .inputs_ftw_H1_prog_V_ap_vld(valid_dout),
        .inputs_ftw_LO_0_V(H1_mux1_C),
        .inputs_ftw_LO_0_V_ap_vld(valid_dout),
        .inputs_ftw_LO_1_V(LO0_mux1_C),
        .inputs_ftw_LO_1_V_ap_vld(valid_dout),
        .inputs_offset_AM_off_V(b_memory_map_inputs_pulseLengthAM_reg_o),
        .inputs_offset_AM_off_V_ap_vld(valid_dout),
        .inputs_offset_AM_on_V(b_memory_map_inputs_offsetAM_reg_o),
        .inputs_offset_AM_on_V_ap_vld(valid_dout),
        .inputs_offset_FSK_V(generic_mux_0_C),
        .inputs_offset_FSK_V_ap_vld(valid_dout),
        .inputs_offset_V(cmp_RFNCO_Divider_HLS_offset_H1_comp_V),
        .inputs_offset_V_ap_vld(valid_dout),
        .inputs_phase_H1_comp_V(phase_H1_comp_o),
        .inputs_phase_H1_comp_V_ap_vld(valid_dout),
        .inputs_rate_V(on_mux1_C),
        .inputs_rate_V_ap_vld(valid_dout),
        .inputs_reset_FSK(cmp_or_reset_FSK_Res),
        .inputs_reset_FSK_ap_vld(valid_dout),
        .inputs_reset_NCO(util_vector_logic_0_Res),
        .inputs_reset_NCO_ap_vld(valid_dout),
        .inputs_reset_slip(cmp_or_reset_slip_Res),
        .inputs_reset_slip_ap_vld(valid_dout),
        .inputs_slip_sign(b_memory_map_control_slipSign),
        .inputs_slip_sign_ap_vld(valid_dout),
        .inputs_valid(cmp_RFNCO_Divider_HLS_ap_done),
        .inputs_valid_ap_vld(valid_dout),
        .outputs_AM(RFNCO_HLS_0_outputs_AM),
        .outputs_AM_auto_on(AM_auto_on_o),
        .outputs_coef_muxed_V(coef_o),
        .outputs_coef_muxed_V_ap_vld(coef_vld_o),
        .outputs_frev(RFNCO_HLS_0_outputs_frev),
        .outputs_frev_main(frev_main_o),
        .outputs_ftw_H1_muxed_V(FTW_H1_on_muxed_o),
        .outputs_ftw_H1_muxed_V_ap_vld(FTW_H1_on_muxed_vld_o),
        .outputs_phase_H1_V(phase_H1_o),
        .outputs_phase_H1_V_ap_vld(RFNCO_HLS_0_outputs_Phase_H1_V_ap_vld),
        .outputs_phase_H1_main_V(phase_H1_main_o),
        .outputs_phase_H1_offset_V(phase_H1_offset_o),
        .outputs_phase_H1_prog_offset_V(phase_H1_prog_offset_o),
        .outputs_phase_H1_slip_V(phase_H1_slip_o),
        .outputs_phase_IF_0_V(phase_IF0_o),
        .outputs_phase_IF_1_V(phase_IF1_o),
        .outputs_valid(cmp_RFNCO_HLS_outputs_valid));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "RFNCO_veto,Vivado 2018.2" *) 
  RFNCO_cmp_RFNCO_veto_0 cmp_RFNCO_veto
       (.NCO_rst_i(util_vector_logic_0_Res),
        .interlock_o(interlock_o),
        .phase_valid_i(RFNCO_HLS_0_outputs_Phase_H1_V_ap_vld),
        .sel_H1_i(b_memory_map_control_selFtwH1),
        .sel_H1on_i(b_memory_map_control_selFtwH1On),
        .sel_load_i(b_memory_map_control_selLoad_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "WRFrameBusSlave,Vivado 2018.2" *) 
  RFNCO_cmp_WRFrameBusSlave_0 cmp_WRFrameBusSlave
       (.master_FTW_H1_main(wr_rf_frame_bus_i_ftw_h1_main),
        .master_FTW_H1_on(wr_rf_frame_bus_i_ftw_h1_on),
        .master_FTW_H1_prog(wr_rf_frame_bus_i_ftw_h1_prog),
        .master_dFTW_H1_slip0(wr_rf_frame_bus_i_dftw_h1_slip0),
        .master_dFTW_H1_slip1(wr_rf_frame_bus_i_dftw_h1_slip1),
        .master_inputs_valid(wr_rf_frame_bus_i_inputs_valid),
        .master_rate(wr_rf_frame_bus_i_rate),
        .master_reset_FSK(wr_rf_frame_bus_i_reset_fsk),
        .master_reset_NCO(wr_rf_frame_bus_i_reset_nco),
        .master_reset_slip(wr_rf_frame_bus_i_reset_slip),
        .slave_FTW_H1_main(WRFrameBusSlave_0_slave_FTW_H1_main),
        .slave_FTW_H1_on(WRFrameBusSlave_0_slave_FTW_H1_on),
        .slave_FTW_H1_prog(WRFrameBusSlave_0_slave_FTW_H1_prog),
        .slave_dFTW_H1_slip0(WRFrameBusSlave_0_slave_dFTW_H1_slip0),
        .slave_dFTW_H1_slip1(WRFrameBusSlave_0_slave_dFTW_H1_slip1),
        .slave_inputs_valid(WRFrameBusSlave_0_slave_inputs_valid),
        .slave_rate(WRFrameBusSlave_0_slave_rate),
        .slave_reset_FSK(cmp_WRFrameBusSlave_slave_reset_FSK),
        .slave_reset_NCO(cmp_WRFrameBusSlave_slave_reset_NCO),
        .slave_reset_slip(cmp_WRFrameBusSlave_slave_reset_slip));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "bit_shift,Vivado 2018.2" *) 
  RFNCO_cmp_bit_shift_0 cmp_bit_shift
       (.data_i(phase_IF1_o),
        .data_o(cmp_bit_shift_data_o),
        .enable_i(b_memory_map_control_enableFreqDoubling_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlconcat_v2_1_1_xlconcat,Vivado 2018.2" *) 
  RFNCO_cmp_concat_phase_IF0_0 cmp_concat_phase_IF0
       (.In0(cmp_slice_phase_IF0_Dout),
        .In1(cmp_zero_7b_dout),
        .dout(cmp_concat_phase_in_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlconcat_v2_1_1_xlconcat,Vivado 2018.2" *) 
  RFNCO_cmp_concat_phase_IF1_0 cmp_concat_phase_IF1
       (.In0(cmp_slice_phase_IF1_Dout),
        .In1(cmp_zero_7b_dout),
        .dout(cmp_concat_phase_in_dout1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "dds_compiler_v6_0_16,Vivado 2018.2" *) 
  RFNCO_cmp_dds_IF0_0 cmp_dds_IF0
       (.aclk(clk_i),
        .m_axis_data_tdata(dds_compiler_0_m_axis_data_tdata),
        .m_axis_data_tlast(cmp_dds_IF0_m_axis_data_tlast),
        .s_axis_phase_tdata(cmp_concat_phase_in_dout),
        .s_axis_phase_tlast(cmp_RFNCO_HLS_outputs_valid),
        .s_axis_phase_tvalid(valid_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "dds_compiler_v6_0_16,Vivado 2018.2" *) 
  RFNCO_cmp_dds_IF1_0 cmp_dds_IF1
       (.aclk(clk_i),
        .m_axis_data_tdata(dds_compiler_0_m_axis_data_tdata1),
        .s_axis_phase_tdata(cmp_concat_phase_in_dout1),
        .s_axis_phase_tvalid(valid_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_cos_IF0_0 cmp_ff_cos_IF0
       (.clk_i(clk_i),
        .data_i(cmp_slice_sin_if_Dout),
        .data_o(cos_IF0_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_cos_IF1_0 cmp_ff_cos_IF1
       (.clk_i(clk_i),
        .data_i(cmp_slice_sin_if_Dout1),
        .data_o(cos_IF1_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_ftw_H1_0 cmp_ff_ftw_H1
       (.clk_i(clk_i),
        .data_i(cmp_ftw_slip_adder_ftw_H1_o),
        .data_o(ftw_H1_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_ftw_H1_on_0 cmp_ff_ftw_H1_on
       (.clk_i(clk_i),
        .data_i(H1_on_mux_C),
        .data_o(ftw_H1_on_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_ftw_H1_vld_0 cmp_ff_ftw_H1_vld
       (.clk_i(clk_i),
        .data_i(cmp_or_softLoad_Res),
        .data_o(ftw_valid_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_sin_IF0_0 cmp_ff_sin_IF0
       (.clk_i(clk_i),
        .data_i(cmp_sign_invert0_signed_o),
        .data_o(sin_IF0_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_sin_IF1_0 cmp_ff_sin_IF1
       (.clk_i(clk_i),
        .data_i(cmp_sign_invert1_signed_o),
        .data_o(sin_IF1_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_sincos_vld_0 cmp_ff_sincos_vld
       (.clk_i(clk_i),
        .data_i(cmp_dds_IF0_m_axis_data_tlast),
        .data_o(sincos_vld_o),
        .enable_i(valid_dout),
        .rst_i(ap_rst_1));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "ftw_slip_adder,Vivado 2018.2" *) 
  RFNCO_cmp_ftw_slip_adder_0 cmp_ftw_slip_adder
       (.ftw_H1_i(H1_mux_C),
        .ftw_H1_o(cmp_ftw_slip_adder_ftw_H1_o),
        .ftw_slip_i(cmp_dftw_slip_mux_C),
        .slip_enable_i(b_memory_map_control_enableSlip),
        .slip_sign_i(b_memory_map_control_slipSign));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_mux_soflLoad_0 cmp_mux_soflLoad
       (.A(WRFrameBusSlave_0_slave_inputs_valid),
        .B(b_memory_map_control_softLoad),
        .C(cmp_or_softLoad_Res),
        .sel(b_memory_map_control_selLoad_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
  RFNCO_cmp_or_reset_FSK_0 cmp_or_reset_FSK
       (.Op1(cmp_WRFrameBusSlave_slave_reset_FSK),
        .Op2(b_memory_map_control_resetFSK),
        .Res(cmp_or_reset_FSK_Res));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
  RFNCO_cmp_or_reset_slip_0 cmp_or_reset_slip
       (.Op1(cmp_WRFrameBusSlave_slave_reset_slip),
        .Op2(b_memory_map_control_resetSlip),
        .Res(cmp_or_reset_slip_Res));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "sign_invert,Vivado 2018.2" *) 
  RFNCO_cmp_sign_invert0_0 cmp_sign_invert0
       (.invert_i(b_memory_map_control_signIF0),
        .signed_i(b_slices_sin_IF0_o),
        .signed_o(cmp_sign_invert0_signed_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "sign_invert,Vivado 2018.2" *) 
  RFNCO_cmp_sign_invert1_0 cmp_sign_invert1
       (.invert_i(b_memory_map_control_signIF1),
        .signed_i(b_slices_sin_IF1_o),
        .signed_o(cmp_sign_invert1_signed_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "vector_to_std,Vivado 2018.2" *) 
  RFNCO_cmp_vector_to_std_AM_0 cmp_vector_to_std_AM
       (.in_i(RFNCO_HLS_0_outputs_AM),
        .out_o(AM_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "vector_to_std,Vivado 2018.2" *) 
  RFNCO_cmp_vector_to_std_frev_0 cmp_vector_to_std_frev
       (.in_i(RFNCO_HLS_0_outputs_frev),
        .out_o(frev_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlconstant_v1_1_5_xlconstant,Vivado 2018.2" *) 
  RFNCO_cmp_zero_7b_0 cmp_zero_7b
       (.dout(cmp_zero_7b_dout));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_c_valid_0,xlconstant_v1_1_5_xlconstant,{}" *) (* CORE_GENERATION_INFO = "RFNCO_c_valid_0,xlconstant_v1_1_5_xlconstant,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlconstant_v1_1_5_xlconstant,Vivado 2018.2" *) 
module RFNCO_c_valid_0
   (.dout(\<const1> ));
  output \<const1> ;

  wire \<const1> ;

  VCC VCC
       (.P(\<const1> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_c_zeros_1b_0,xlconstant_v1_1_5_xlconstant,{}" *) (* CORE_GENERATION_INFO = "RFNCO_c_zeros_1b_0,xlconstant_v1_1_5_xlconstant,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=1,CONST_VAL=0x0}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlconstant_v1_1_5_xlconstant,Vivado 2018.2" *) 
module RFNCO_c_zeros_1b_0
   (.dout(\<const0> ));
  output \<const0> ;

  wire \<const0> ;

  GND GND
       (.G(\<const0> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_H1_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_H1_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_H1_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_H1_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_H1_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_H1_on_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_H1_on_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_H1_on_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_H1_on_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_H1_on_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_H1_prog_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_H1_prog_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_H1_prog_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_H1_prog_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_H1_prog_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_LO0_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_LO0_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_LO0_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_LO0_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_LO0_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_LO1_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_LO1_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_LO1_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_LO1_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_LO1_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_RFNCO_Divider_HLS_0,RFNCO_Divider_HLS,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_RFNCO_Divider_HLS_0,RFNCO_Divider_HLS,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=RFNCO_Divider_HLS,x_ipVersion=1.1,x_ipCoreRevision=2113025637,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "RFNCO_Divider_HLS,Vivado 2018.2" *) (* ip_definition_source = "HLS" *) 
module RFNCO_cmp_RFNCO_Divider_HLS_0
   (inputs_ftw_H1_on_V_ap_vld,
    inputs_ftw_H1_V_ap_vld,
    inputs_delay_comp_V_ap_vld,
    inputs_enable_FSK_ap_vld,
    inputs_rate_V_ap_vld,
    inputs_offset_H1_V_ap_vld,
    COEF_V_ap_vld,
    tw_H1_V_ap_vld,
    phase_H1_comp_V_ap_vld,
    offset_H1_comp_V_ap_vld,
    ap_clk,
    ap_rst,
    ap_start,
    ap_done,
    ap_idle,
    ap_ready,
    inputs_ftw_H1_on_V,
    inputs_ftw_H1_V,
    inputs_delay_comp_V,
    inputs_enable_FSK,
    inputs_rate_V,
    inputs_offset_H1_V,
    COEF_V,
    tw_H1_V,
    phase_H1_comp_V,
    offset_H1_comp_V);
  input inputs_ftw_H1_on_V_ap_vld;
  input inputs_ftw_H1_V_ap_vld;
  input inputs_delay_comp_V_ap_vld;
  input inputs_enable_FSK_ap_vld;
  input inputs_rate_V_ap_vld;
  input inputs_offset_H1_V_ap_vld;
  output COEF_V_ap_vld;
  output tw_H1_V_ap_vld;
  output phase_H1_comp_V_ap_vld;
  output offset_H1_comp_V_ap_vld;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_RESET ap_rst, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input ap_clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst, POLARITY ACTIVE_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input ap_rst;
  (* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl start" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_ctrl, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {start {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} done {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} idle {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} ready {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input ap_start;
  (* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl done" *) output ap_done;
  (* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl idle" *) output ap_idle;
  (* X_INTERFACE_INFO = "xilinx.com:interface:acc_handshake:1.0 ap_ctrl ready" *) output ap_ready;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_H1_on_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_H1_on_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_H1_on_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_H1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_H1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_H1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_delay_comp_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_delay_comp_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 18} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}" *) input [31:0]inputs_delay_comp_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_enable_FSK DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_enable_FSK, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_enable_FSK;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_rate_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_rate_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 3} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [2:0]inputs_rate_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_offset_H1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_offset_H1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_offset_H1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 COEF_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME COEF_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value -4294967258} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [31:0]COEF_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 tw_H1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME tw_H1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value -4294967228} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [31:0]tw_H1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 phase_H1_comp_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME phase_H1_comp_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}" *) output [47:0]phase_H1_comp_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 offset_H1_comp_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME offset_H1_comp_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]offset_H1_comp_V;

  wire [31:0]COEF_V;
  wire COEF_V_ap_vld;
  wire ap_clk;
  wire ap_done;
  wire ap_idle;
  wire ap_ready;
  wire ap_rst;
  wire ap_start;
  wire [31:0]inputs_delay_comp_V;
  wire inputs_delay_comp_V_ap_vld;
  wire [0:0]inputs_enable_FSK;
  wire inputs_enable_FSK_ap_vld;
  wire [47:0]inputs_ftw_H1_V;
  wire inputs_ftw_H1_V_ap_vld;
  wire [47:0]inputs_ftw_H1_on_V;
  wire inputs_ftw_H1_on_V_ap_vld;
  wire [47:0]inputs_offset_H1_V;
  wire inputs_offset_H1_V_ap_vld;
  wire [2:0]inputs_rate_V;
  wire inputs_rate_V_ap_vld;
  wire [47:0]offset_H1_comp_V;
  wire offset_H1_comp_V_ap_vld;
  wire [47:0]phase_H1_comp_V;
  wire phase_H1_comp_V_ap_vld;
  wire [31:0]tw_H1_V;
  wire tw_H1_V_ap_vld;

  (* core_generation_info = "RFNCO_Divider_HLS,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7k160tfbg676-2,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.908000,HLS_SYN_LAT=77,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=13,HLS_SYN_FF=1319,HLS_SYN_LUT=1248,HLS_VERSION=2018_2}" *) 
  RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLS U0
       (.COEF_V(COEF_V),
        .COEF_V_ap_vld(COEF_V_ap_vld),
        .ap_clk(ap_clk),
        .ap_done(ap_done),
        .ap_idle(ap_idle),
        .ap_ready(ap_ready),
        .ap_rst(ap_rst),
        .ap_start(ap_start),
        .inputs_delay_comp_V(inputs_delay_comp_V),
        .inputs_delay_comp_V_ap_vld(inputs_delay_comp_V_ap_vld),
        .inputs_enable_FSK(inputs_enable_FSK),
        .inputs_enable_FSK_ap_vld(inputs_enable_FSK_ap_vld),
        .inputs_ftw_H1_V(inputs_ftw_H1_V),
        .inputs_ftw_H1_V_ap_vld(inputs_ftw_H1_V_ap_vld),
        .inputs_ftw_H1_on_V(inputs_ftw_H1_on_V),
        .inputs_ftw_H1_on_V_ap_vld(inputs_ftw_H1_on_V_ap_vld),
        .inputs_offset_H1_V(inputs_offset_H1_V),
        .inputs_offset_H1_V_ap_vld(inputs_offset_H1_V_ap_vld),
        .inputs_rate_V(inputs_rate_V),
        .inputs_rate_V_ap_vld(inputs_rate_V_ap_vld),
        .offset_H1_comp_V(offset_H1_comp_V),
        .offset_H1_comp_V_ap_vld(offset_H1_comp_V_ap_vld),
        .phase_H1_comp_V(phase_H1_comp_V),
        .phase_H1_comp_V_ap_vld(phase_H1_comp_V_ap_vld),
        .tw_H1_V(tw_H1_V),
        .tw_H1_V_ap_vld(tw_H1_V_ap_vld));
endmodule

(* CORE_GENERATION_INFO = "RFNCO_Divider_HLS,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=1,HLS_INPUT_PART=xc7k160tfbg676-2,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=6.908000,HLS_SYN_LAT=77,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=13,HLS_SYN_FF=1319,HLS_SYN_LUT=1248,HLS_VERSION=2018_2}" *) (* ORIG_REF_NAME = "RFNCO_Divider_HLS" *) 
module RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLS
   (ap_clk,
    ap_rst,
    ap_start,
    ap_done,
    ap_idle,
    ap_ready,
    inputs_ftw_H1_on_V,
    inputs_ftw_H1_on_V_ap_vld,
    inputs_ftw_H1_V,
    inputs_ftw_H1_V_ap_vld,
    inputs_delay_comp_V,
    inputs_delay_comp_V_ap_vld,
    inputs_enable_FSK,
    inputs_enable_FSK_ap_vld,
    inputs_rate_V,
    inputs_rate_V_ap_vld,
    inputs_offset_H1_V,
    inputs_offset_H1_V_ap_vld,
    COEF_V,
    COEF_V_ap_vld,
    tw_H1_V,
    tw_H1_V_ap_vld,
    phase_H1_comp_V,
    phase_H1_comp_V_ap_vld,
    offset_H1_comp_V,
    offset_H1_comp_V_ap_vld);
  input ap_clk;
  input ap_rst;
  input ap_start;
  output ap_done;
  output ap_idle;
  output ap_ready;
  input [47:0]inputs_ftw_H1_on_V;
  input inputs_ftw_H1_on_V_ap_vld;
  input [47:0]inputs_ftw_H1_V;
  input inputs_ftw_H1_V_ap_vld;
  input [31:0]inputs_delay_comp_V;
  input inputs_delay_comp_V_ap_vld;
  input [0:0]inputs_enable_FSK;
  input inputs_enable_FSK_ap_vld;
  input [2:0]inputs_rate_V;
  input inputs_rate_V_ap_vld;
  input [47:0]inputs_offset_H1_V;
  input inputs_offset_H1_V_ap_vld;
  output [31:0]COEF_V;
  output COEF_V_ap_vld;
  output [31:0]tw_H1_V;
  output tw_H1_V_ap_vld;
  output [47:0]phase_H1_comp_V;
  output phase_H1_comp_V_ap_vld;
  output [47:0]offset_H1_comp_V;
  output offset_H1_comp_V_ap_vld;

  wire \<const0> ;
  wire \<const1> ;
  wire [31:0]COEF_V;
  wire COEF_V_1_data_reg0;
  wire \COEF_V_1_data_reg[13]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[13]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[13]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[13]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[17]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[17]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[17]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[17]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_10_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_11_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_13_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_14_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_15_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_16_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_17_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_18_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_19_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_6_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_8_n_0 ;
  wire \COEF_V_1_data_reg[1]_i_9_n_0 ;
  wire \COEF_V_1_data_reg[21]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[21]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[21]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[21]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[25]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[25]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[25]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[25]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[29]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[29]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[29]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[29]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[31]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[31]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[5]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[5]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[5]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[5]_i_5_n_0 ;
  wire \COEF_V_1_data_reg[9]_i_2_n_0 ;
  wire \COEF_V_1_data_reg[9]_i_3_n_0 ;
  wire \COEF_V_1_data_reg[9]_i_4_n_0 ;
  wire \COEF_V_1_data_reg[9]_i_5_n_0 ;
  wire \COEF_V_1_data_reg_reg[13]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[13]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[13]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[13]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[17]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[17]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[17]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[17]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[1]_i_12_n_0 ;
  wire \COEF_V_1_data_reg_reg[1]_i_12_n_1 ;
  wire \COEF_V_1_data_reg_reg[1]_i_12_n_2 ;
  wire \COEF_V_1_data_reg_reg[1]_i_12_n_3 ;
  wire \COEF_V_1_data_reg_reg[1]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[1]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[1]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[1]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[1]_i_2_n_0 ;
  wire \COEF_V_1_data_reg_reg[1]_i_2_n_1 ;
  wire \COEF_V_1_data_reg_reg[1]_i_2_n_2 ;
  wire \COEF_V_1_data_reg_reg[1]_i_2_n_3 ;
  wire \COEF_V_1_data_reg_reg[1]_i_7_n_0 ;
  wire \COEF_V_1_data_reg_reg[1]_i_7_n_1 ;
  wire \COEF_V_1_data_reg_reg[1]_i_7_n_2 ;
  wire \COEF_V_1_data_reg_reg[1]_i_7_n_3 ;
  wire \COEF_V_1_data_reg_reg[21]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[21]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[21]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[21]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[25]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[25]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[25]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[25]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[29]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[29]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[29]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[29]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[31]_i_2_n_3 ;
  wire \COEF_V_1_data_reg_reg[5]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[5]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[5]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[5]_i_1_n_3 ;
  wire \COEF_V_1_data_reg_reg[9]_i_1_n_0 ;
  wire \COEF_V_1_data_reg_reg[9]_i_1_n_1 ;
  wire \COEF_V_1_data_reg_reg[9]_i_1_n_2 ;
  wire \COEF_V_1_data_reg_reg[9]_i_1_n_3 ;
  wire COEF_V_1_vld_reg_i_1_n_0;
  wire COEF_V_ap_vld;
  wire [36:0]FTW_comp_V_fu_278_p3;
  wire GND_2;
  wire RFNCO_Divider_HLSbkb_U1_n_2;
  wire VCC_2;
  wire \ap_CS_fsm[1]_i_10_n_0 ;
  wire \ap_CS_fsm[1]_i_11_n_0 ;
  wire \ap_CS_fsm[1]_i_12_n_0 ;
  wire \ap_CS_fsm[1]_i_13_n_0 ;
  wire \ap_CS_fsm[1]_i_14_n_0 ;
  wire \ap_CS_fsm[1]_i_15_n_0 ;
  wire \ap_CS_fsm[1]_i_16_n_0 ;
  wire \ap_CS_fsm[1]_i_2_n_0 ;
  wire \ap_CS_fsm[1]_i_3_n_0 ;
  wire \ap_CS_fsm[1]_i_4_n_0 ;
  wire \ap_CS_fsm[1]_i_5_n_0 ;
  wire \ap_CS_fsm[1]_i_6_n_0 ;
  wire \ap_CS_fsm[1]_i_7_n_0 ;
  wire \ap_CS_fsm[1]_i_8_n_0 ;
  wire \ap_CS_fsm[1]_i_9_n_0 ;
  wire \ap_CS_fsm_reg_n_0_[0] ;
  wire \ap_CS_fsm_reg_n_0_[10] ;
  wire \ap_CS_fsm_reg_n_0_[11] ;
  wire \ap_CS_fsm_reg_n_0_[12] ;
  wire \ap_CS_fsm_reg_n_0_[13] ;
  wire \ap_CS_fsm_reg_n_0_[14] ;
  wire \ap_CS_fsm_reg_n_0_[15] ;
  wire \ap_CS_fsm_reg_n_0_[16] ;
  wire \ap_CS_fsm_reg_n_0_[17] ;
  wire \ap_CS_fsm_reg_n_0_[18] ;
  wire \ap_CS_fsm_reg_n_0_[19] ;
  wire \ap_CS_fsm_reg_n_0_[20] ;
  wire \ap_CS_fsm_reg_n_0_[21] ;
  wire \ap_CS_fsm_reg_n_0_[22] ;
  wire \ap_CS_fsm_reg_n_0_[23] ;
  wire \ap_CS_fsm_reg_n_0_[24] ;
  wire \ap_CS_fsm_reg_n_0_[25] ;
  wire \ap_CS_fsm_reg_n_0_[26] ;
  wire \ap_CS_fsm_reg_n_0_[27] ;
  wire \ap_CS_fsm_reg_n_0_[28] ;
  wire \ap_CS_fsm_reg_n_0_[29] ;
  wire \ap_CS_fsm_reg_n_0_[30] ;
  wire \ap_CS_fsm_reg_n_0_[31] ;
  wire \ap_CS_fsm_reg_n_0_[32] ;
  wire \ap_CS_fsm_reg_n_0_[33] ;
  wire \ap_CS_fsm_reg_n_0_[34] ;
  wire \ap_CS_fsm_reg_n_0_[35] ;
  wire \ap_CS_fsm_reg_n_0_[36] ;
  wire \ap_CS_fsm_reg_n_0_[37] ;
  wire \ap_CS_fsm_reg_n_0_[38] ;
  wire \ap_CS_fsm_reg_n_0_[39] ;
  wire \ap_CS_fsm_reg_n_0_[3] ;
  wire \ap_CS_fsm_reg_n_0_[40] ;
  wire \ap_CS_fsm_reg_n_0_[41] ;
  wire \ap_CS_fsm_reg_n_0_[42] ;
  wire \ap_CS_fsm_reg_n_0_[43] ;
  wire \ap_CS_fsm_reg_n_0_[44] ;
  wire \ap_CS_fsm_reg_n_0_[45] ;
  wire \ap_CS_fsm_reg_n_0_[46] ;
  wire \ap_CS_fsm_reg_n_0_[47] ;
  wire \ap_CS_fsm_reg_n_0_[48] ;
  wire \ap_CS_fsm_reg_n_0_[49] ;
  wire \ap_CS_fsm_reg_n_0_[4] ;
  wire \ap_CS_fsm_reg_n_0_[50] ;
  wire \ap_CS_fsm_reg_n_0_[51] ;
  wire \ap_CS_fsm_reg_n_0_[52] ;
  wire \ap_CS_fsm_reg_n_0_[53] ;
  wire \ap_CS_fsm_reg_n_0_[54] ;
  wire \ap_CS_fsm_reg_n_0_[55] ;
  wire \ap_CS_fsm_reg_n_0_[56] ;
  wire \ap_CS_fsm_reg_n_0_[57] ;
  wire \ap_CS_fsm_reg_n_0_[58] ;
  wire \ap_CS_fsm_reg_n_0_[59] ;
  wire \ap_CS_fsm_reg_n_0_[5] ;
  wire \ap_CS_fsm_reg_n_0_[60] ;
  wire \ap_CS_fsm_reg_n_0_[61] ;
  wire \ap_CS_fsm_reg_n_0_[62] ;
  wire \ap_CS_fsm_reg_n_0_[63] ;
  wire \ap_CS_fsm_reg_n_0_[64] ;
  wire \ap_CS_fsm_reg_n_0_[65] ;
  wire \ap_CS_fsm_reg_n_0_[66] ;
  wire \ap_CS_fsm_reg_n_0_[67] ;
  wire \ap_CS_fsm_reg_n_0_[68] ;
  wire \ap_CS_fsm_reg_n_0_[69] ;
  wire \ap_CS_fsm_reg_n_0_[6] ;
  wire \ap_CS_fsm_reg_n_0_[70] ;
  wire \ap_CS_fsm_reg_n_0_[71] ;
  wire \ap_CS_fsm_reg_n_0_[72] ;
  wire \ap_CS_fsm_reg_n_0_[7] ;
  wire \ap_CS_fsm_reg_n_0_[8] ;
  wire \ap_CS_fsm_reg_n_0_[9] ;
  wire ap_CS_fsm_state2;
  wire ap_CS_fsm_state74;
  wire ap_CS_fsm_state76;
  wire ap_CS_fsm_state77;
  wire [1:0]ap_NS_fsm;
  wire ap_clk;
  wire ap_done;
  wire ap_idle;
  wire ap_rst;
  wire ap_start;
  wire [31:0]dividend_tmp;
  wire done0;
  wire [31:0]inputs_delay_comp_V;
  wire inputs_delay_comp_V_ap_vld;
  wire inputs_delay_comp_V_ap_vld_preg;
  wire inputs_delay_comp_V_ap_vld_preg0;
  wire inputs_delay_comp_V_ap_vld_preg_i_1_n_0;
  wire [31:0]inputs_delay_comp_V_preg;
  wire [0:0]inputs_enable_FSK;
  wire inputs_enable_FSK_ap_vld;
  wire inputs_enable_FSK_ap_vld_preg;
  wire inputs_enable_FSK_ap_vld_preg_i_1_n_0;
  wire inputs_enable_FSK_preg;
  wire \inputs_enable_FSK_preg[0]_i_1_n_0 ;
  wire [47:0]inputs_ftw_H1_V;
  wire inputs_ftw_H1_V_ap_vld;
  wire inputs_ftw_H1_V_ap_vld_preg;
  wire inputs_ftw_H1_V_ap_vld_preg0;
  wire inputs_ftw_H1_V_ap_vld_preg_i_1_n_0;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[0] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[10] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[11] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[12] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[13] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[14] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[15] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[16] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[17] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[18] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[19] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[1] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[20] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[21] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[22] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[23] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[24] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[25] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[26] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[27] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[28] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[29] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[2] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[30] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[31] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[32] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[33] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[34] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[35] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[36] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[37] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[38] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[39] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[3] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[40] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[41] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[42] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[43] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[44] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[45] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[46] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[47] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[4] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[5] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[6] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[7] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[8] ;
  wire \inputs_ftw_H1_V_preg_reg_n_0_[9] ;
  wire [47:0]inputs_ftw_H1_on_V;
  wire inputs_ftw_H1_on_V_ap_vld;
  wire inputs_ftw_H1_on_V_ap_vld_preg;
  wire inputs_ftw_H1_on_V_ap_vld_preg0;
  wire inputs_ftw_H1_on_V_ap_vld_preg_i_1_n_0;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[0] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[10] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[11] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[12] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[13] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[14] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[15] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[16] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[17] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[18] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[19] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[1] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[20] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[21] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[22] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[23] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[24] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[25] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[26] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[27] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[28] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[29] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[2] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[30] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[31] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[32] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[33] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[34] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[35] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[36] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[37] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[38] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[39] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[3] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[40] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[41] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[42] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[43] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[44] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[45] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[46] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[47] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[4] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[5] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[6] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[7] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[8] ;
  wire \inputs_ftw_H1_on_V_preg_reg_n_0_[9] ;
  wire [47:0]inputs_offset_H1_V;
  wire inputs_offset_H1_V_ap_vld;
  wire inputs_offset_H1_V_ap_vld_preg;
  wire inputs_offset_H1_V_ap_vld_preg0;
  wire inputs_offset_H1_V_ap_vld_preg_i_1_n_0;
  wire [2:0]inputs_rate_V;
  wire inputs_rate_V_ap_vld;
  wire inputs_rate_V_ap_vld_preg;
  wire inputs_rate_V_ap_vld_preg_i_1_n_0;
  wire [2:0]inputs_rate_V_preg;
  wire \inputs_rate_V_preg[0]_i_1_n_0 ;
  wire \inputs_rate_V_preg[1]_i_1_n_0 ;
  wire \inputs_rate_V_preg[2]_i_1_n_0 ;
  wire [42:0]\^offset_H1_comp_V ;
  wire \offset_H1_comp_V[13]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[13]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[13]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[13]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[13]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[17]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[17]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[17]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[17]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_10_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_11_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_11_n_1 ;
  wire \offset_H1_comp_V[1]_INST_0_i_11_n_2 ;
  wire \offset_H1_comp_V[1]_INST_0_i_11_n_3 ;
  wire \offset_H1_comp_V[1]_INST_0_i_12_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_13_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_14_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_15_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_16_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_17_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_17_n_1 ;
  wire \offset_H1_comp_V[1]_INST_0_i_17_n_2 ;
  wire \offset_H1_comp_V[1]_INST_0_i_17_n_3 ;
  wire \offset_H1_comp_V[1]_INST_0_i_18_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_19_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[1]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[1]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[1]_INST_0_i_20_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_21_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_22_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_22_n_1 ;
  wire \offset_H1_comp_V[1]_INST_0_i_22_n_2 ;
  wire \offset_H1_comp_V[1]_INST_0_i_22_n_3 ;
  wire \offset_H1_comp_V[1]_INST_0_i_23_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_24_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_25_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_26_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_27_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_27_n_1 ;
  wire \offset_H1_comp_V[1]_INST_0_i_27_n_2 ;
  wire \offset_H1_comp_V[1]_INST_0_i_27_n_3 ;
  wire \offset_H1_comp_V[1]_INST_0_i_28_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_29_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_2_n_1 ;
  wire \offset_H1_comp_V[1]_INST_0_i_2_n_2 ;
  wire \offset_H1_comp_V[1]_INST_0_i_2_n_3 ;
  wire \offset_H1_comp_V[1]_INST_0_i_30_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_31_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_32_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_33_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_34_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[1]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[21]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[21]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[21]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[21]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[25]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[25]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[25]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[25]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[29]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[29]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[29]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[29]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[33]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[33]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[33]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[33]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[37]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[37]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[37]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[37]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[41]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[41]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[41]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[41]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[42]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[5]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[5]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[5]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[5]_INST_0_i_9_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_1_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_1_n_1 ;
  wire \offset_H1_comp_V[9]_INST_0_i_1_n_2 ;
  wire \offset_H1_comp_V[9]_INST_0_i_1_n_3 ;
  wire \offset_H1_comp_V[9]_INST_0_i_2_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_3_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_4_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_5_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_6_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_7_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_8_n_0 ;
  wire \offset_H1_comp_V[9]_INST_0_i_9_n_0 ;
  wire or_cond_reg_403;
  wire \or_cond_reg_403[0]_i_1_n_0 ;
  wire \p_0_out[0]__1_n_0 ;
  wire \p_0_out[0]__2_n_0 ;
  wire \p_0_out[10]__1_n_0 ;
  wire \p_0_out[10]__2_n_0 ;
  wire \p_0_out[11]__1_n_0 ;
  wire \p_0_out[11]__2_n_0 ;
  wire \p_0_out[12]__1_n_0 ;
  wire \p_0_out[12]__2_n_0 ;
  wire \p_0_out[13]__1_n_0 ;
  wire \p_0_out[13]__2_n_0 ;
  wire \p_0_out[14]__1_n_0 ;
  wire \p_0_out[14]__2_n_0 ;
  wire \p_0_out[15]__1_n_0 ;
  wire \p_0_out[15]__2_n_0 ;
  wire \p_0_out[16]__0_n_0 ;
  wire \p_0_out[16]__1_i_1_n_0 ;
  wire \p_0_out[16]__1_n_0 ;
  wire \p_0_out[16]__2_n_0 ;
  wire \p_0_out[16]__3_n_0 ;
  wire \p_0_out[1]__1_n_0 ;
  wire \p_0_out[1]__2_n_0 ;
  wire \p_0_out[2]__1_n_0 ;
  wire \p_0_out[2]__2_n_0 ;
  wire \p_0_out[3]__1_n_0 ;
  wire \p_0_out[3]__2_n_0 ;
  wire \p_0_out[4]__1_n_0 ;
  wire \p_0_out[4]__2_n_0 ;
  wire \p_0_out[5]__1_n_0 ;
  wire \p_0_out[5]__2_n_0 ;
  wire \p_0_out[6]__1_n_0 ;
  wire \p_0_out[6]__2_n_0 ;
  wire \p_0_out[7]__1_n_0 ;
  wire \p_0_out[7]__2_n_0 ;
  wire \p_0_out[8]__1_n_0 ;
  wire \p_0_out[8]__2_n_0 ;
  wire \p_0_out[9]__1_n_0 ;
  wire \p_0_out[9]__2_n_0 ;
  wire p_0_out__0_n_100;
  wire p_0_out__0_n_101;
  wire p_0_out__0_n_102;
  wire p_0_out__0_n_103;
  wire p_0_out__0_n_104;
  wire p_0_out__0_n_105;
  wire p_0_out__0_n_58;
  wire p_0_out__0_n_59;
  wire p_0_out__0_n_60;
  wire p_0_out__0_n_61;
  wire p_0_out__0_n_62;
  wire p_0_out__0_n_63;
  wire p_0_out__0_n_64;
  wire p_0_out__0_n_65;
  wire p_0_out__0_n_66;
  wire p_0_out__0_n_67;
  wire p_0_out__0_n_68;
  wire p_0_out__0_n_69;
  wire p_0_out__0_n_70;
  wire p_0_out__0_n_71;
  wire p_0_out__0_n_72;
  wire p_0_out__0_n_73;
  wire p_0_out__0_n_74;
  wire p_0_out__0_n_75;
  wire p_0_out__0_n_76;
  wire p_0_out__0_n_77;
  wire p_0_out__0_n_78;
  wire p_0_out__0_n_79;
  wire p_0_out__0_n_80;
  wire p_0_out__0_n_81;
  wire p_0_out__0_n_82;
  wire p_0_out__0_n_83;
  wire p_0_out__0_n_84;
  wire p_0_out__0_n_85;
  wire p_0_out__0_n_86;
  wire p_0_out__0_n_87;
  wire p_0_out__0_n_88;
  wire p_0_out__0_n_89;
  wire p_0_out__0_n_90;
  wire p_0_out__0_n_91;
  wire p_0_out__0_n_92;
  wire p_0_out__0_n_93;
  wire p_0_out__0_n_94;
  wire p_0_out__0_n_95;
  wire p_0_out__0_n_96;
  wire p_0_out__0_n_97;
  wire p_0_out__0_n_98;
  wire p_0_out__0_n_99;
  wire p_0_out__1_n_100;
  wire p_0_out__1_n_101;
  wire p_0_out__1_n_102;
  wire p_0_out__1_n_103;
  wire p_0_out__1_n_104;
  wire p_0_out__1_n_105;
  wire p_0_out__1_n_58;
  wire p_0_out__1_n_59;
  wire p_0_out__1_n_60;
  wire p_0_out__1_n_61;
  wire p_0_out__1_n_62;
  wire p_0_out__1_n_63;
  wire p_0_out__1_n_64;
  wire p_0_out__1_n_65;
  wire p_0_out__1_n_66;
  wire p_0_out__1_n_67;
  wire p_0_out__1_n_68;
  wire p_0_out__1_n_69;
  wire p_0_out__1_n_70;
  wire p_0_out__1_n_71;
  wire p_0_out__1_n_72;
  wire p_0_out__1_n_73;
  wire p_0_out__1_n_74;
  wire p_0_out__1_n_75;
  wire p_0_out__1_n_76;
  wire p_0_out__1_n_77;
  wire p_0_out__1_n_78;
  wire p_0_out__1_n_79;
  wire p_0_out__1_n_80;
  wire p_0_out__1_n_81;
  wire p_0_out__1_n_82;
  wire p_0_out__1_n_83;
  wire p_0_out__1_n_84;
  wire p_0_out__1_n_85;
  wire p_0_out__1_n_86;
  wire p_0_out__1_n_87;
  wire p_0_out__1_n_88;
  wire p_0_out__1_n_89;
  wire p_0_out__1_n_90;
  wire p_0_out__1_n_91;
  wire p_0_out__1_n_92;
  wire p_0_out__1_n_93;
  wire p_0_out__1_n_94;
  wire p_0_out__1_n_95;
  wire p_0_out__1_n_96;
  wire p_0_out__1_n_97;
  wire p_0_out__1_n_98;
  wire p_0_out__1_n_99;
  wire p_0_out__2_i_10_n_0;
  wire p_0_out__2_i_11_n_0;
  wire p_0_out__2_i_12_n_0;
  wire p_0_out__2_i_13_n_0;
  wire p_0_out__2_i_14_n_0;
  wire p_0_out__2_i_15_n_0;
  wire p_0_out__2_i_16_n_0;
  wire p_0_out__2_i_1_n_7;
  wire p_0_out__2_i_2_n_0;
  wire p_0_out__2_i_2_n_1;
  wire p_0_out__2_i_2_n_2;
  wire p_0_out__2_i_2_n_3;
  wire p_0_out__2_i_2_n_4;
  wire p_0_out__2_i_2_n_5;
  wire p_0_out__2_i_2_n_6;
  wire p_0_out__2_i_2_n_7;
  wire p_0_out__2_i_3_n_0;
  wire p_0_out__2_i_3_n_1;
  wire p_0_out__2_i_3_n_2;
  wire p_0_out__2_i_3_n_3;
  wire p_0_out__2_i_3_n_4;
  wire p_0_out__2_i_3_n_5;
  wire p_0_out__2_i_3_n_6;
  wire p_0_out__2_i_3_n_7;
  wire p_0_out__2_i_4_n_0;
  wire p_0_out__2_i_4_n_1;
  wire p_0_out__2_i_4_n_2;
  wire p_0_out__2_i_4_n_3;
  wire p_0_out__2_i_4_n_4;
  wire p_0_out__2_i_4_n_5;
  wire p_0_out__2_i_4_n_6;
  wire p_0_out__2_i_4_n_7;
  wire p_0_out__2_i_5_n_0;
  wire p_0_out__2_i_6_n_0;
  wire p_0_out__2_i_7_n_0;
  wire p_0_out__2_i_8_n_0;
  wire p_0_out__2_i_9_n_0;
  wire p_0_out__2_n_100;
  wire p_0_out__2_n_101;
  wire p_0_out__2_n_102;
  wire p_0_out__2_n_103;
  wire p_0_out__2_n_104;
  wire p_0_out__2_n_105;
  wire p_0_out__2_n_58;
  wire p_0_out__2_n_59;
  wire p_0_out__2_n_60;
  wire p_0_out__2_n_61;
  wire p_0_out__2_n_62;
  wire p_0_out__2_n_63;
  wire p_0_out__2_n_64;
  wire p_0_out__2_n_65;
  wire p_0_out__2_n_66;
  wire p_0_out__2_n_67;
  wire p_0_out__2_n_68;
  wire p_0_out__2_n_69;
  wire p_0_out__2_n_70;
  wire p_0_out__2_n_71;
  wire p_0_out__2_n_72;
  wire p_0_out__2_n_73;
  wire p_0_out__2_n_74;
  wire p_0_out__2_n_75;
  wire p_0_out__2_n_76;
  wire p_0_out__2_n_77;
  wire p_0_out__2_n_78;
  wire p_0_out__2_n_79;
  wire p_0_out__2_n_80;
  wire p_0_out__2_n_81;
  wire p_0_out__2_n_82;
  wire p_0_out__2_n_83;
  wire p_0_out__2_n_84;
  wire p_0_out__2_n_85;
  wire p_0_out__2_n_86;
  wire p_0_out__2_n_87;
  wire p_0_out__2_n_88;
  wire p_0_out__2_n_89;
  wire p_0_out__2_n_90;
  wire p_0_out__2_n_91;
  wire p_0_out__2_n_92;
  wire p_0_out__2_n_93;
  wire p_0_out__2_n_94;
  wire p_0_out__2_n_95;
  wire p_0_out__2_n_96;
  wire p_0_out__2_n_97;
  wire p_0_out__2_n_98;
  wire p_0_out__2_n_99;
  wire p_0_out__4_n_100;
  wire p_0_out__4_n_101;
  wire p_0_out__4_n_102;
  wire p_0_out__4_n_103;
  wire p_0_out__4_n_104;
  wire p_0_out__4_n_105;
  wire p_0_out__4_n_58;
  wire p_0_out__4_n_59;
  wire p_0_out__4_n_60;
  wire p_0_out__4_n_61;
  wire p_0_out__4_n_62;
  wire p_0_out__4_n_63;
  wire p_0_out__4_n_64;
  wire p_0_out__4_n_65;
  wire p_0_out__4_n_66;
  wire p_0_out__4_n_67;
  wire p_0_out__4_n_68;
  wire p_0_out__4_n_69;
  wire p_0_out__4_n_70;
  wire p_0_out__4_n_71;
  wire p_0_out__4_n_72;
  wire p_0_out__4_n_73;
  wire p_0_out__4_n_74;
  wire p_0_out__4_n_75;
  wire p_0_out__4_n_76;
  wire p_0_out__4_n_77;
  wire p_0_out__4_n_78;
  wire p_0_out__4_n_79;
  wire p_0_out__4_n_80;
  wire p_0_out__4_n_81;
  wire p_0_out__4_n_82;
  wire p_0_out__4_n_83;
  wire p_0_out__4_n_84;
  wire p_0_out__4_n_85;
  wire p_0_out__4_n_86;
  wire p_0_out__4_n_87;
  wire p_0_out__4_n_88;
  wire p_0_out__4_n_89;
  wire p_0_out__4_n_90;
  wire p_0_out__4_n_91;
  wire p_0_out__4_n_92;
  wire p_0_out__4_n_93;
  wire p_0_out__4_n_94;
  wire p_0_out__4_n_95;
  wire p_0_out__4_n_96;
  wire p_0_out__4_n_97;
  wire p_0_out__4_n_98;
  wire p_0_out__4_n_99;
  wire p_0_out__6_n_100;
  wire p_0_out__6_n_101;
  wire p_0_out__6_n_102;
  wire p_0_out__6_n_103;
  wire p_0_out__6_n_104;
  wire p_0_out__6_n_105;
  wire p_0_out__6_n_58;
  wire p_0_out__6_n_59;
  wire p_0_out__6_n_60;
  wire p_0_out__6_n_61;
  wire p_0_out__6_n_62;
  wire p_0_out__6_n_63;
  wire p_0_out__6_n_64;
  wire p_0_out__6_n_65;
  wire p_0_out__6_n_66;
  wire p_0_out__6_n_67;
  wire p_0_out__6_n_68;
  wire p_0_out__6_n_69;
  wire p_0_out__6_n_70;
  wire p_0_out__6_n_71;
  wire p_0_out__6_n_72;
  wire p_0_out__6_n_73;
  wire p_0_out__6_n_74;
  wire p_0_out__6_n_75;
  wire p_0_out__6_n_76;
  wire p_0_out__6_n_77;
  wire p_0_out__6_n_78;
  wire p_0_out__6_n_79;
  wire p_0_out__6_n_80;
  wire p_0_out__6_n_81;
  wire p_0_out__6_n_82;
  wire p_0_out__6_n_83;
  wire p_0_out__6_n_84;
  wire p_0_out__6_n_85;
  wire p_0_out__6_n_86;
  wire p_0_out__6_n_87;
  wire p_0_out__6_n_88;
  wire p_0_out__6_n_89;
  wire p_0_out__6_n_90;
  wire p_0_out__6_n_91;
  wire p_0_out__6_n_92;
  wire p_0_out__6_n_93;
  wire p_0_out__6_n_94;
  wire p_0_out__6_n_95;
  wire p_0_out__6_n_96;
  wire p_0_out__6_n_97;
  wire p_0_out__6_n_98;
  wire p_0_out__6_n_99;
  wire \p_0_out_n_0_[0] ;
  wire \p_0_out_n_0_[10] ;
  wire \p_0_out_n_0_[11] ;
  wire \p_0_out_n_0_[12] ;
  wire \p_0_out_n_0_[13] ;
  wire \p_0_out_n_0_[14] ;
  wire \p_0_out_n_0_[15] ;
  wire \p_0_out_n_0_[16] ;
  wire \p_0_out_n_0_[1] ;
  wire \p_0_out_n_0_[2] ;
  wire \p_0_out_n_0_[3] ;
  wire \p_0_out_n_0_[4] ;
  wire \p_0_out_n_0_[5] ;
  wire \p_0_out_n_0_[6] ;
  wire \p_0_out_n_0_[7] ;
  wire \p_0_out_n_0_[8] ;
  wire \p_0_out_n_0_[9] ;
  wire p_Val2_3_fu_330_p2__0_i_18_n_0;
  wire p_Val2_3_fu_330_p2__0_i_18_n_1;
  wire p_Val2_3_fu_330_p2__0_i_18_n_2;
  wire p_Val2_3_fu_330_p2__0_i_18_n_3;
  wire p_Val2_3_fu_330_p2__0_i_18_n_4;
  wire p_Val2_3_fu_330_p2__0_i_18_n_5;
  wire p_Val2_3_fu_330_p2__0_i_18_n_6;
  wire p_Val2_3_fu_330_p2__0_i_18_n_7;
  wire p_Val2_3_fu_330_p2__0_i_19_n_0;
  wire p_Val2_3_fu_330_p2__0_i_19_n_1;
  wire p_Val2_3_fu_330_p2__0_i_19_n_2;
  wire p_Val2_3_fu_330_p2__0_i_19_n_3;
  wire p_Val2_3_fu_330_p2__0_i_19_n_4;
  wire p_Val2_3_fu_330_p2__0_i_19_n_5;
  wire p_Val2_3_fu_330_p2__0_i_19_n_6;
  wire p_Val2_3_fu_330_p2__0_i_19_n_7;
  wire p_Val2_3_fu_330_p2__0_i_20_n_0;
  wire p_Val2_3_fu_330_p2__0_i_20_n_1;
  wire p_Val2_3_fu_330_p2__0_i_20_n_2;
  wire p_Val2_3_fu_330_p2__0_i_20_n_3;
  wire p_Val2_3_fu_330_p2__0_i_20_n_4;
  wire p_Val2_3_fu_330_p2__0_i_20_n_5;
  wire p_Val2_3_fu_330_p2__0_i_20_n_6;
  wire p_Val2_3_fu_330_p2__0_i_20_n_7;
  wire p_Val2_3_fu_330_p2__0_i_21_n_0;
  wire p_Val2_3_fu_330_p2__0_i_21_n_1;
  wire p_Val2_3_fu_330_p2__0_i_21_n_2;
  wire p_Val2_3_fu_330_p2__0_i_21_n_3;
  wire p_Val2_3_fu_330_p2__0_i_21_n_4;
  wire p_Val2_3_fu_330_p2__0_i_21_n_5;
  wire p_Val2_3_fu_330_p2__0_i_21_n_6;
  wire p_Val2_3_fu_330_p2__0_i_21_n_7;
  wire p_Val2_3_fu_330_p2__0_i_22_n_0;
  wire p_Val2_3_fu_330_p2__0_i_23_n_0;
  wire p_Val2_3_fu_330_p2__0_i_24_n_0;
  wire p_Val2_3_fu_330_p2__0_i_25_n_0;
  wire p_Val2_3_fu_330_p2__0_i_26_n_0;
  wire p_Val2_3_fu_330_p2__0_i_27_n_0;
  wire p_Val2_3_fu_330_p2__0_i_28_n_0;
  wire p_Val2_3_fu_330_p2__0_i_29_n_0;
  wire p_Val2_3_fu_330_p2__0_i_30_n_0;
  wire p_Val2_3_fu_330_p2__0_i_31_n_0;
  wire p_Val2_3_fu_330_p2__0_i_32_n_0;
  wire p_Val2_3_fu_330_p2__0_i_33_n_0;
  wire p_Val2_3_fu_330_p2__0_i_34_n_0;
  wire p_Val2_3_fu_330_p2__0_i_35_n_0;
  wire p_Val2_3_fu_330_p2__0_i_36_n_0;
  wire p_Val2_3_fu_330_p2__0_i_37_n_0;
  wire p_Val2_3_fu_330_p2__0_n_100;
  wire p_Val2_3_fu_330_p2__0_n_101;
  wire p_Val2_3_fu_330_p2__0_n_102;
  wire p_Val2_3_fu_330_p2__0_n_103;
  wire p_Val2_3_fu_330_p2__0_n_104;
  wire p_Val2_3_fu_330_p2__0_n_105;
  wire p_Val2_3_fu_330_p2__0_n_106;
  wire p_Val2_3_fu_330_p2__0_n_107;
  wire p_Val2_3_fu_330_p2__0_n_108;
  wire p_Val2_3_fu_330_p2__0_n_109;
  wire p_Val2_3_fu_330_p2__0_n_110;
  wire p_Val2_3_fu_330_p2__0_n_111;
  wire p_Val2_3_fu_330_p2__0_n_112;
  wire p_Val2_3_fu_330_p2__0_n_113;
  wire p_Val2_3_fu_330_p2__0_n_114;
  wire p_Val2_3_fu_330_p2__0_n_115;
  wire p_Val2_3_fu_330_p2__0_n_116;
  wire p_Val2_3_fu_330_p2__0_n_117;
  wire p_Val2_3_fu_330_p2__0_n_118;
  wire p_Val2_3_fu_330_p2__0_n_119;
  wire p_Val2_3_fu_330_p2__0_n_120;
  wire p_Val2_3_fu_330_p2__0_n_121;
  wire p_Val2_3_fu_330_p2__0_n_122;
  wire p_Val2_3_fu_330_p2__0_n_123;
  wire p_Val2_3_fu_330_p2__0_n_124;
  wire p_Val2_3_fu_330_p2__0_n_125;
  wire p_Val2_3_fu_330_p2__0_n_126;
  wire p_Val2_3_fu_330_p2__0_n_127;
  wire p_Val2_3_fu_330_p2__0_n_128;
  wire p_Val2_3_fu_330_p2__0_n_129;
  wire p_Val2_3_fu_330_p2__0_n_130;
  wire p_Val2_3_fu_330_p2__0_n_131;
  wire p_Val2_3_fu_330_p2__0_n_132;
  wire p_Val2_3_fu_330_p2__0_n_133;
  wire p_Val2_3_fu_330_p2__0_n_134;
  wire p_Val2_3_fu_330_p2__0_n_135;
  wire p_Val2_3_fu_330_p2__0_n_136;
  wire p_Val2_3_fu_330_p2__0_n_137;
  wire p_Val2_3_fu_330_p2__0_n_138;
  wire p_Val2_3_fu_330_p2__0_n_139;
  wire p_Val2_3_fu_330_p2__0_n_140;
  wire p_Val2_3_fu_330_p2__0_n_141;
  wire p_Val2_3_fu_330_p2__0_n_142;
  wire p_Val2_3_fu_330_p2__0_n_143;
  wire p_Val2_3_fu_330_p2__0_n_144;
  wire p_Val2_3_fu_330_p2__0_n_145;
  wire p_Val2_3_fu_330_p2__0_n_146;
  wire p_Val2_3_fu_330_p2__0_n_147;
  wire p_Val2_3_fu_330_p2__0_n_148;
  wire p_Val2_3_fu_330_p2__0_n_149;
  wire p_Val2_3_fu_330_p2__0_n_150;
  wire p_Val2_3_fu_330_p2__0_n_151;
  wire p_Val2_3_fu_330_p2__0_n_152;
  wire p_Val2_3_fu_330_p2__0_n_153;
  wire p_Val2_3_fu_330_p2__0_n_24;
  wire p_Val2_3_fu_330_p2__0_n_25;
  wire p_Val2_3_fu_330_p2__0_n_26;
  wire p_Val2_3_fu_330_p2__0_n_27;
  wire p_Val2_3_fu_330_p2__0_n_28;
  wire p_Val2_3_fu_330_p2__0_n_29;
  wire p_Val2_3_fu_330_p2__0_n_30;
  wire p_Val2_3_fu_330_p2__0_n_31;
  wire p_Val2_3_fu_330_p2__0_n_32;
  wire p_Val2_3_fu_330_p2__0_n_33;
  wire p_Val2_3_fu_330_p2__0_n_34;
  wire p_Val2_3_fu_330_p2__0_n_35;
  wire p_Val2_3_fu_330_p2__0_n_36;
  wire p_Val2_3_fu_330_p2__0_n_37;
  wire p_Val2_3_fu_330_p2__0_n_38;
  wire p_Val2_3_fu_330_p2__0_n_39;
  wire p_Val2_3_fu_330_p2__0_n_40;
  wire p_Val2_3_fu_330_p2__0_n_41;
  wire p_Val2_3_fu_330_p2__0_n_42;
  wire p_Val2_3_fu_330_p2__0_n_43;
  wire p_Val2_3_fu_330_p2__0_n_44;
  wire p_Val2_3_fu_330_p2__0_n_45;
  wire p_Val2_3_fu_330_p2__0_n_46;
  wire p_Val2_3_fu_330_p2__0_n_47;
  wire p_Val2_3_fu_330_p2__0_n_48;
  wire p_Val2_3_fu_330_p2__0_n_49;
  wire p_Val2_3_fu_330_p2__0_n_50;
  wire p_Val2_3_fu_330_p2__0_n_51;
  wire p_Val2_3_fu_330_p2__0_n_52;
  wire p_Val2_3_fu_330_p2__0_n_53;
  wire p_Val2_3_fu_330_p2__0_n_58;
  wire p_Val2_3_fu_330_p2__0_n_59;
  wire p_Val2_3_fu_330_p2__0_n_60;
  wire p_Val2_3_fu_330_p2__0_n_61;
  wire p_Val2_3_fu_330_p2__0_n_62;
  wire p_Val2_3_fu_330_p2__0_n_63;
  wire p_Val2_3_fu_330_p2__0_n_64;
  wire p_Val2_3_fu_330_p2__0_n_65;
  wire p_Val2_3_fu_330_p2__0_n_66;
  wire p_Val2_3_fu_330_p2__0_n_67;
  wire p_Val2_3_fu_330_p2__0_n_68;
  wire p_Val2_3_fu_330_p2__0_n_69;
  wire p_Val2_3_fu_330_p2__0_n_70;
  wire p_Val2_3_fu_330_p2__0_n_71;
  wire p_Val2_3_fu_330_p2__0_n_72;
  wire p_Val2_3_fu_330_p2__0_n_73;
  wire p_Val2_3_fu_330_p2__0_n_74;
  wire p_Val2_3_fu_330_p2__0_n_75;
  wire p_Val2_3_fu_330_p2__0_n_76;
  wire p_Val2_3_fu_330_p2__0_n_77;
  wire p_Val2_3_fu_330_p2__0_n_78;
  wire p_Val2_3_fu_330_p2__0_n_79;
  wire p_Val2_3_fu_330_p2__0_n_80;
  wire p_Val2_3_fu_330_p2__0_n_81;
  wire p_Val2_3_fu_330_p2__0_n_82;
  wire p_Val2_3_fu_330_p2__0_n_83;
  wire p_Val2_3_fu_330_p2__0_n_84;
  wire p_Val2_3_fu_330_p2__0_n_85;
  wire p_Val2_3_fu_330_p2__0_n_86;
  wire p_Val2_3_fu_330_p2__0_n_87;
  wire p_Val2_3_fu_330_p2__0_n_88;
  wire p_Val2_3_fu_330_p2__0_n_89;
  wire p_Val2_3_fu_330_p2__0_n_90;
  wire p_Val2_3_fu_330_p2__0_n_91;
  wire p_Val2_3_fu_330_p2__0_n_92;
  wire p_Val2_3_fu_330_p2__0_n_93;
  wire p_Val2_3_fu_330_p2__0_n_94;
  wire p_Val2_3_fu_330_p2__0_n_95;
  wire p_Val2_3_fu_330_p2__0_n_96;
  wire p_Val2_3_fu_330_p2__0_n_97;
  wire p_Val2_3_fu_330_p2__0_n_98;
  wire p_Val2_3_fu_330_p2__0_n_99;
  wire p_Val2_3_fu_330_p2_i_16_n_3;
  wire p_Val2_3_fu_330_p2_i_17_n_0;
  wire p_Val2_3_fu_330_p2_i_18_n_0;
  wire p_Val2_3_fu_330_p2_i_18_n_1;
  wire p_Val2_3_fu_330_p2_i_18_n_2;
  wire p_Val2_3_fu_330_p2_i_18_n_3;
  wire p_Val2_3_fu_330_p2_i_18_n_4;
  wire p_Val2_3_fu_330_p2_i_18_n_5;
  wire p_Val2_3_fu_330_p2_i_18_n_6;
  wire p_Val2_3_fu_330_p2_i_18_n_7;
  wire p_Val2_3_fu_330_p2_i_19_n_0;
  wire p_Val2_3_fu_330_p2_i_19_n_1;
  wire p_Val2_3_fu_330_p2_i_19_n_2;
  wire p_Val2_3_fu_330_p2_i_19_n_3;
  wire p_Val2_3_fu_330_p2_i_19_n_4;
  wire p_Val2_3_fu_330_p2_i_19_n_5;
  wire p_Val2_3_fu_330_p2_i_19_n_6;
  wire p_Val2_3_fu_330_p2_i_19_n_7;
  wire p_Val2_3_fu_330_p2_i_20_n_0;
  wire p_Val2_3_fu_330_p2_i_20_n_1;
  wire p_Val2_3_fu_330_p2_i_20_n_2;
  wire p_Val2_3_fu_330_p2_i_20_n_3;
  wire p_Val2_3_fu_330_p2_i_20_n_4;
  wire p_Val2_3_fu_330_p2_i_20_n_5;
  wire p_Val2_3_fu_330_p2_i_20_n_6;
  wire p_Val2_3_fu_330_p2_i_20_n_7;
  wire p_Val2_3_fu_330_p2_i_21_n_0;
  wire p_Val2_3_fu_330_p2_i_21_n_1;
  wire p_Val2_3_fu_330_p2_i_21_n_2;
  wire p_Val2_3_fu_330_p2_i_21_n_3;
  wire p_Val2_3_fu_330_p2_i_21_n_4;
  wire p_Val2_3_fu_330_p2_i_21_n_5;
  wire p_Val2_3_fu_330_p2_i_21_n_6;
  wire p_Val2_3_fu_330_p2_i_21_n_7;
  wire p_Val2_3_fu_330_p2_i_22_n_0;
  wire p_Val2_3_fu_330_p2_i_22_n_1;
  wire p_Val2_3_fu_330_p2_i_22_n_2;
  wire p_Val2_3_fu_330_p2_i_22_n_3;
  wire p_Val2_3_fu_330_p2_i_23_n_0;
  wire p_Val2_3_fu_330_p2_i_24_n_0;
  wire p_Val2_3_fu_330_p2_i_24_n_1;
  wire p_Val2_3_fu_330_p2_i_24_n_2;
  wire p_Val2_3_fu_330_p2_i_24_n_3;
  wire p_Val2_3_fu_330_p2_i_25_n_0;
  wire p_Val2_3_fu_330_p2_i_26_n_0;
  wire p_Val2_3_fu_330_p2_i_27_n_0;
  wire p_Val2_3_fu_330_p2_i_28_n_0;
  wire p_Val2_3_fu_330_p2_i_29_n_0;
  wire p_Val2_3_fu_330_p2_i_30_n_0;
  wire p_Val2_3_fu_330_p2_i_31_n_0;
  wire p_Val2_3_fu_330_p2_i_32_n_0;
  wire p_Val2_3_fu_330_p2_i_33_n_0;
  wire p_Val2_3_fu_330_p2_i_34_n_0;
  wire p_Val2_3_fu_330_p2_i_35_n_0;
  wire p_Val2_3_fu_330_p2_i_36_n_0;
  wire p_Val2_3_fu_330_p2_i_37_n_0;
  wire p_Val2_3_fu_330_p2_i_38_n_0;
  wire p_Val2_3_fu_330_p2_i_39_n_0;
  wire p_Val2_3_fu_330_p2_i_40_n_0;
  wire p_Val2_3_fu_330_p2_i_41_n_0;
  wire p_Val2_3_fu_330_p2_i_42_n_0;
  wire p_Val2_3_fu_330_p2_i_43_n_0;
  wire p_Val2_3_fu_330_p2_i_44_n_0;
  wire p_Val2_3_fu_330_p2_i_45_n_0;
  wire p_Val2_3_fu_330_p2_i_46_n_0;
  wire p_Val2_3_fu_330_p2_i_47_n_0;
  wire p_Val2_3_fu_330_p2_i_47_n_1;
  wire p_Val2_3_fu_330_p2_i_47_n_2;
  wire p_Val2_3_fu_330_p2_i_47_n_3;
  wire p_Val2_3_fu_330_p2_i_48_n_0;
  wire p_Val2_3_fu_330_p2_i_49_n_0;
  wire p_Val2_3_fu_330_p2_i_50_n_0;
  wire p_Val2_3_fu_330_p2_i_51_n_0;
  wire p_Val2_3_fu_330_p2_i_52_n_0;
  wire p_Val2_3_fu_330_p2_i_52_n_1;
  wire p_Val2_3_fu_330_p2_i_52_n_2;
  wire p_Val2_3_fu_330_p2_i_52_n_3;
  wire p_Val2_3_fu_330_p2_i_53_n_0;
  wire p_Val2_3_fu_330_p2_i_54_n_0;
  wire p_Val2_3_fu_330_p2_i_55_n_0;
  wire p_Val2_3_fu_330_p2_i_56_n_0;
  wire p_Val2_3_fu_330_p2_i_57_n_0;
  wire p_Val2_3_fu_330_p2_i_58_n_0;
  wire p_Val2_3_fu_330_p2_i_59_n_0;
  wire p_Val2_3_fu_330_p2_i_60_n_0;
  wire p_Val2_3_fu_330_p2_n_100;
  wire p_Val2_3_fu_330_p2_n_101;
  wire p_Val2_3_fu_330_p2_n_102;
  wire p_Val2_3_fu_330_p2_n_103;
  wire p_Val2_3_fu_330_p2_n_104;
  wire p_Val2_3_fu_330_p2_n_105;
  wire p_Val2_3_fu_330_p2_n_106;
  wire p_Val2_3_fu_330_p2_n_107;
  wire p_Val2_3_fu_330_p2_n_108;
  wire p_Val2_3_fu_330_p2_n_109;
  wire p_Val2_3_fu_330_p2_n_110;
  wire p_Val2_3_fu_330_p2_n_111;
  wire p_Val2_3_fu_330_p2_n_112;
  wire p_Val2_3_fu_330_p2_n_113;
  wire p_Val2_3_fu_330_p2_n_114;
  wire p_Val2_3_fu_330_p2_n_115;
  wire p_Val2_3_fu_330_p2_n_116;
  wire p_Val2_3_fu_330_p2_n_117;
  wire p_Val2_3_fu_330_p2_n_118;
  wire p_Val2_3_fu_330_p2_n_119;
  wire p_Val2_3_fu_330_p2_n_120;
  wire p_Val2_3_fu_330_p2_n_121;
  wire p_Val2_3_fu_330_p2_n_122;
  wire p_Val2_3_fu_330_p2_n_123;
  wire p_Val2_3_fu_330_p2_n_124;
  wire p_Val2_3_fu_330_p2_n_125;
  wire p_Val2_3_fu_330_p2_n_126;
  wire p_Val2_3_fu_330_p2_n_127;
  wire p_Val2_3_fu_330_p2_n_128;
  wire p_Val2_3_fu_330_p2_n_129;
  wire p_Val2_3_fu_330_p2_n_130;
  wire p_Val2_3_fu_330_p2_n_131;
  wire p_Val2_3_fu_330_p2_n_132;
  wire p_Val2_3_fu_330_p2_n_133;
  wire p_Val2_3_fu_330_p2_n_134;
  wire p_Val2_3_fu_330_p2_n_135;
  wire p_Val2_3_fu_330_p2_n_136;
  wire p_Val2_3_fu_330_p2_n_137;
  wire p_Val2_3_fu_330_p2_n_138;
  wire p_Val2_3_fu_330_p2_n_139;
  wire p_Val2_3_fu_330_p2_n_140;
  wire p_Val2_3_fu_330_p2_n_141;
  wire p_Val2_3_fu_330_p2_n_142;
  wire p_Val2_3_fu_330_p2_n_143;
  wire p_Val2_3_fu_330_p2_n_144;
  wire p_Val2_3_fu_330_p2_n_145;
  wire p_Val2_3_fu_330_p2_n_146;
  wire p_Val2_3_fu_330_p2_n_147;
  wire p_Val2_3_fu_330_p2_n_148;
  wire p_Val2_3_fu_330_p2_n_149;
  wire p_Val2_3_fu_330_p2_n_150;
  wire p_Val2_3_fu_330_p2_n_151;
  wire p_Val2_3_fu_330_p2_n_152;
  wire p_Val2_3_fu_330_p2_n_153;
  wire p_Val2_3_fu_330_p2_n_58;
  wire p_Val2_3_fu_330_p2_n_59;
  wire p_Val2_3_fu_330_p2_n_60;
  wire p_Val2_3_fu_330_p2_n_61;
  wire p_Val2_3_fu_330_p2_n_62;
  wire p_Val2_3_fu_330_p2_n_63;
  wire p_Val2_3_fu_330_p2_n_64;
  wire p_Val2_3_fu_330_p2_n_65;
  wire p_Val2_3_fu_330_p2_n_66;
  wire p_Val2_3_fu_330_p2_n_67;
  wire p_Val2_3_fu_330_p2_n_68;
  wire p_Val2_3_fu_330_p2_n_69;
  wire p_Val2_3_fu_330_p2_n_70;
  wire p_Val2_3_fu_330_p2_n_71;
  wire p_Val2_3_fu_330_p2_n_72;
  wire p_Val2_3_fu_330_p2_n_73;
  wire p_Val2_3_fu_330_p2_n_74;
  wire p_Val2_3_fu_330_p2_n_75;
  wire p_Val2_3_fu_330_p2_n_76;
  wire p_Val2_3_fu_330_p2_n_77;
  wire p_Val2_3_fu_330_p2_n_78;
  wire p_Val2_3_fu_330_p2_n_79;
  wire p_Val2_3_fu_330_p2_n_80;
  wire p_Val2_3_fu_330_p2_n_81;
  wire p_Val2_3_fu_330_p2_n_82;
  wire p_Val2_3_fu_330_p2_n_83;
  wire p_Val2_3_fu_330_p2_n_84;
  wire p_Val2_3_fu_330_p2_n_85;
  wire p_Val2_3_fu_330_p2_n_86;
  wire p_Val2_3_fu_330_p2_n_87;
  wire p_Val2_3_fu_330_p2_n_88;
  wire p_Val2_3_fu_330_p2_n_89;
  wire p_Val2_3_fu_330_p2_n_90;
  wire p_Val2_3_fu_330_p2_n_91;
  wire p_Val2_3_fu_330_p2_n_92;
  wire p_Val2_3_fu_330_p2_n_93;
  wire p_Val2_3_fu_330_p2_n_94;
  wire p_Val2_3_fu_330_p2_n_95;
  wire p_Val2_3_fu_330_p2_n_96;
  wire p_Val2_3_fu_330_p2_n_97;
  wire p_Val2_3_fu_330_p2_n_98;
  wire p_Val2_3_fu_330_p2_n_99;
  wire [31:0]p_Val2_4_reg_423_reg;
  wire p_Val2_5_fu_361_p2__0_n_100;
  wire p_Val2_5_fu_361_p2__0_n_101;
  wire p_Val2_5_fu_361_p2__0_n_102;
  wire p_Val2_5_fu_361_p2__0_n_103;
  wire p_Val2_5_fu_361_p2__0_n_104;
  wire p_Val2_5_fu_361_p2__0_n_105;
  wire p_Val2_5_fu_361_p2__0_n_106;
  wire p_Val2_5_fu_361_p2__0_n_107;
  wire p_Val2_5_fu_361_p2__0_n_108;
  wire p_Val2_5_fu_361_p2__0_n_109;
  wire p_Val2_5_fu_361_p2__0_n_110;
  wire p_Val2_5_fu_361_p2__0_n_111;
  wire p_Val2_5_fu_361_p2__0_n_112;
  wire p_Val2_5_fu_361_p2__0_n_113;
  wire p_Val2_5_fu_361_p2__0_n_114;
  wire p_Val2_5_fu_361_p2__0_n_115;
  wire p_Val2_5_fu_361_p2__0_n_116;
  wire p_Val2_5_fu_361_p2__0_n_117;
  wire p_Val2_5_fu_361_p2__0_n_118;
  wire p_Val2_5_fu_361_p2__0_n_119;
  wire p_Val2_5_fu_361_p2__0_n_120;
  wire p_Val2_5_fu_361_p2__0_n_121;
  wire p_Val2_5_fu_361_p2__0_n_122;
  wire p_Val2_5_fu_361_p2__0_n_123;
  wire p_Val2_5_fu_361_p2__0_n_124;
  wire p_Val2_5_fu_361_p2__0_n_125;
  wire p_Val2_5_fu_361_p2__0_n_126;
  wire p_Val2_5_fu_361_p2__0_n_127;
  wire p_Val2_5_fu_361_p2__0_n_128;
  wire p_Val2_5_fu_361_p2__0_n_129;
  wire p_Val2_5_fu_361_p2__0_n_130;
  wire p_Val2_5_fu_361_p2__0_n_131;
  wire p_Val2_5_fu_361_p2__0_n_132;
  wire p_Val2_5_fu_361_p2__0_n_133;
  wire p_Val2_5_fu_361_p2__0_n_134;
  wire p_Val2_5_fu_361_p2__0_n_135;
  wire p_Val2_5_fu_361_p2__0_n_136;
  wire p_Val2_5_fu_361_p2__0_n_137;
  wire p_Val2_5_fu_361_p2__0_n_138;
  wire p_Val2_5_fu_361_p2__0_n_139;
  wire p_Val2_5_fu_361_p2__0_n_140;
  wire p_Val2_5_fu_361_p2__0_n_141;
  wire p_Val2_5_fu_361_p2__0_n_142;
  wire p_Val2_5_fu_361_p2__0_n_143;
  wire p_Val2_5_fu_361_p2__0_n_144;
  wire p_Val2_5_fu_361_p2__0_n_145;
  wire p_Val2_5_fu_361_p2__0_n_146;
  wire p_Val2_5_fu_361_p2__0_n_147;
  wire p_Val2_5_fu_361_p2__0_n_148;
  wire p_Val2_5_fu_361_p2__0_n_149;
  wire p_Val2_5_fu_361_p2__0_n_150;
  wire p_Val2_5_fu_361_p2__0_n_151;
  wire p_Val2_5_fu_361_p2__0_n_152;
  wire p_Val2_5_fu_361_p2__0_n_153;
  wire p_Val2_5_fu_361_p2__0_n_24;
  wire p_Val2_5_fu_361_p2__0_n_25;
  wire p_Val2_5_fu_361_p2__0_n_26;
  wire p_Val2_5_fu_361_p2__0_n_27;
  wire p_Val2_5_fu_361_p2__0_n_28;
  wire p_Val2_5_fu_361_p2__0_n_29;
  wire p_Val2_5_fu_361_p2__0_n_30;
  wire p_Val2_5_fu_361_p2__0_n_31;
  wire p_Val2_5_fu_361_p2__0_n_32;
  wire p_Val2_5_fu_361_p2__0_n_33;
  wire p_Val2_5_fu_361_p2__0_n_34;
  wire p_Val2_5_fu_361_p2__0_n_35;
  wire p_Val2_5_fu_361_p2__0_n_36;
  wire p_Val2_5_fu_361_p2__0_n_37;
  wire p_Val2_5_fu_361_p2__0_n_38;
  wire p_Val2_5_fu_361_p2__0_n_39;
  wire p_Val2_5_fu_361_p2__0_n_40;
  wire p_Val2_5_fu_361_p2__0_n_41;
  wire p_Val2_5_fu_361_p2__0_n_42;
  wire p_Val2_5_fu_361_p2__0_n_43;
  wire p_Val2_5_fu_361_p2__0_n_44;
  wire p_Val2_5_fu_361_p2__0_n_45;
  wire p_Val2_5_fu_361_p2__0_n_46;
  wire p_Val2_5_fu_361_p2__0_n_47;
  wire p_Val2_5_fu_361_p2__0_n_48;
  wire p_Val2_5_fu_361_p2__0_n_49;
  wire p_Val2_5_fu_361_p2__0_n_50;
  wire p_Val2_5_fu_361_p2__0_n_51;
  wire p_Val2_5_fu_361_p2__0_n_52;
  wire p_Val2_5_fu_361_p2__0_n_53;
  wire p_Val2_5_fu_361_p2__0_n_58;
  wire p_Val2_5_fu_361_p2__0_n_59;
  wire p_Val2_5_fu_361_p2__0_n_60;
  wire p_Val2_5_fu_361_p2__0_n_61;
  wire p_Val2_5_fu_361_p2__0_n_62;
  wire p_Val2_5_fu_361_p2__0_n_63;
  wire p_Val2_5_fu_361_p2__0_n_64;
  wire p_Val2_5_fu_361_p2__0_n_65;
  wire p_Val2_5_fu_361_p2__0_n_66;
  wire p_Val2_5_fu_361_p2__0_n_67;
  wire p_Val2_5_fu_361_p2__0_n_68;
  wire p_Val2_5_fu_361_p2__0_n_69;
  wire p_Val2_5_fu_361_p2__0_n_70;
  wire p_Val2_5_fu_361_p2__0_n_71;
  wire p_Val2_5_fu_361_p2__0_n_72;
  wire p_Val2_5_fu_361_p2__0_n_73;
  wire p_Val2_5_fu_361_p2__0_n_74;
  wire p_Val2_5_fu_361_p2__0_n_75;
  wire p_Val2_5_fu_361_p2__0_n_76;
  wire p_Val2_5_fu_361_p2__0_n_77;
  wire p_Val2_5_fu_361_p2__0_n_78;
  wire p_Val2_5_fu_361_p2__0_n_79;
  wire p_Val2_5_fu_361_p2__0_n_80;
  wire p_Val2_5_fu_361_p2__0_n_81;
  wire p_Val2_5_fu_361_p2__0_n_82;
  wire p_Val2_5_fu_361_p2__0_n_83;
  wire p_Val2_5_fu_361_p2__0_n_84;
  wire p_Val2_5_fu_361_p2__0_n_85;
  wire p_Val2_5_fu_361_p2__0_n_86;
  wire p_Val2_5_fu_361_p2__0_n_87;
  wire p_Val2_5_fu_361_p2__0_n_88;
  wire p_Val2_5_fu_361_p2__0_n_89;
  wire p_Val2_5_fu_361_p2__0_n_90;
  wire p_Val2_5_fu_361_p2__0_n_91;
  wire p_Val2_5_fu_361_p2__0_n_92;
  wire p_Val2_5_fu_361_p2__0_n_93;
  wire p_Val2_5_fu_361_p2__0_n_94;
  wire p_Val2_5_fu_361_p2__0_n_95;
  wire p_Val2_5_fu_361_p2__0_n_96;
  wire p_Val2_5_fu_361_p2__0_n_97;
  wire p_Val2_5_fu_361_p2__0_n_98;
  wire p_Val2_5_fu_361_p2__0_n_99;
  wire p_Val2_5_fu_361_p2__1_n_100;
  wire p_Val2_5_fu_361_p2__1_n_101;
  wire p_Val2_5_fu_361_p2__1_n_102;
  wire p_Val2_5_fu_361_p2__1_n_103;
  wire p_Val2_5_fu_361_p2__1_n_104;
  wire p_Val2_5_fu_361_p2__1_n_105;
  wire p_Val2_5_fu_361_p2__1_n_106;
  wire p_Val2_5_fu_361_p2__1_n_107;
  wire p_Val2_5_fu_361_p2__1_n_108;
  wire p_Val2_5_fu_361_p2__1_n_109;
  wire p_Val2_5_fu_361_p2__1_n_110;
  wire p_Val2_5_fu_361_p2__1_n_111;
  wire p_Val2_5_fu_361_p2__1_n_112;
  wire p_Val2_5_fu_361_p2__1_n_113;
  wire p_Val2_5_fu_361_p2__1_n_114;
  wire p_Val2_5_fu_361_p2__1_n_115;
  wire p_Val2_5_fu_361_p2__1_n_116;
  wire p_Val2_5_fu_361_p2__1_n_117;
  wire p_Val2_5_fu_361_p2__1_n_118;
  wire p_Val2_5_fu_361_p2__1_n_119;
  wire p_Val2_5_fu_361_p2__1_n_120;
  wire p_Val2_5_fu_361_p2__1_n_121;
  wire p_Val2_5_fu_361_p2__1_n_122;
  wire p_Val2_5_fu_361_p2__1_n_123;
  wire p_Val2_5_fu_361_p2__1_n_124;
  wire p_Val2_5_fu_361_p2__1_n_125;
  wire p_Val2_5_fu_361_p2__1_n_126;
  wire p_Val2_5_fu_361_p2__1_n_127;
  wire p_Val2_5_fu_361_p2__1_n_128;
  wire p_Val2_5_fu_361_p2__1_n_129;
  wire p_Val2_5_fu_361_p2__1_n_130;
  wire p_Val2_5_fu_361_p2__1_n_131;
  wire p_Val2_5_fu_361_p2__1_n_132;
  wire p_Val2_5_fu_361_p2__1_n_133;
  wire p_Val2_5_fu_361_p2__1_n_134;
  wire p_Val2_5_fu_361_p2__1_n_135;
  wire p_Val2_5_fu_361_p2__1_n_136;
  wire p_Val2_5_fu_361_p2__1_n_137;
  wire p_Val2_5_fu_361_p2__1_n_138;
  wire p_Val2_5_fu_361_p2__1_n_139;
  wire p_Val2_5_fu_361_p2__1_n_140;
  wire p_Val2_5_fu_361_p2__1_n_141;
  wire p_Val2_5_fu_361_p2__1_n_142;
  wire p_Val2_5_fu_361_p2__1_n_143;
  wire p_Val2_5_fu_361_p2__1_n_144;
  wire p_Val2_5_fu_361_p2__1_n_145;
  wire p_Val2_5_fu_361_p2__1_n_146;
  wire p_Val2_5_fu_361_p2__1_n_147;
  wire p_Val2_5_fu_361_p2__1_n_148;
  wire p_Val2_5_fu_361_p2__1_n_149;
  wire p_Val2_5_fu_361_p2__1_n_150;
  wire p_Val2_5_fu_361_p2__1_n_151;
  wire p_Val2_5_fu_361_p2__1_n_152;
  wire p_Val2_5_fu_361_p2__1_n_153;
  wire p_Val2_5_fu_361_p2__1_n_24;
  wire p_Val2_5_fu_361_p2__1_n_25;
  wire p_Val2_5_fu_361_p2__1_n_26;
  wire p_Val2_5_fu_361_p2__1_n_27;
  wire p_Val2_5_fu_361_p2__1_n_28;
  wire p_Val2_5_fu_361_p2__1_n_29;
  wire p_Val2_5_fu_361_p2__1_n_30;
  wire p_Val2_5_fu_361_p2__1_n_31;
  wire p_Val2_5_fu_361_p2__1_n_32;
  wire p_Val2_5_fu_361_p2__1_n_33;
  wire p_Val2_5_fu_361_p2__1_n_34;
  wire p_Val2_5_fu_361_p2__1_n_35;
  wire p_Val2_5_fu_361_p2__1_n_36;
  wire p_Val2_5_fu_361_p2__1_n_37;
  wire p_Val2_5_fu_361_p2__1_n_38;
  wire p_Val2_5_fu_361_p2__1_n_39;
  wire p_Val2_5_fu_361_p2__1_n_40;
  wire p_Val2_5_fu_361_p2__1_n_41;
  wire p_Val2_5_fu_361_p2__1_n_42;
  wire p_Val2_5_fu_361_p2__1_n_43;
  wire p_Val2_5_fu_361_p2__1_n_44;
  wire p_Val2_5_fu_361_p2__1_n_45;
  wire p_Val2_5_fu_361_p2__1_n_46;
  wire p_Val2_5_fu_361_p2__1_n_47;
  wire p_Val2_5_fu_361_p2__1_n_48;
  wire p_Val2_5_fu_361_p2__1_n_49;
  wire p_Val2_5_fu_361_p2__1_n_50;
  wire p_Val2_5_fu_361_p2__1_n_51;
  wire p_Val2_5_fu_361_p2__1_n_52;
  wire p_Val2_5_fu_361_p2__1_n_53;
  wire p_Val2_5_fu_361_p2__1_n_58;
  wire p_Val2_5_fu_361_p2__1_n_59;
  wire p_Val2_5_fu_361_p2__1_n_60;
  wire p_Val2_5_fu_361_p2__1_n_61;
  wire p_Val2_5_fu_361_p2__1_n_62;
  wire p_Val2_5_fu_361_p2__1_n_63;
  wire p_Val2_5_fu_361_p2__1_n_64;
  wire p_Val2_5_fu_361_p2__1_n_65;
  wire p_Val2_5_fu_361_p2__1_n_66;
  wire p_Val2_5_fu_361_p2__1_n_67;
  wire p_Val2_5_fu_361_p2__1_n_68;
  wire p_Val2_5_fu_361_p2__1_n_69;
  wire p_Val2_5_fu_361_p2__1_n_70;
  wire p_Val2_5_fu_361_p2__1_n_71;
  wire p_Val2_5_fu_361_p2__1_n_72;
  wire p_Val2_5_fu_361_p2__1_n_73;
  wire p_Val2_5_fu_361_p2__1_n_74;
  wire p_Val2_5_fu_361_p2__1_n_75;
  wire p_Val2_5_fu_361_p2__1_n_76;
  wire p_Val2_5_fu_361_p2__1_n_77;
  wire p_Val2_5_fu_361_p2__1_n_78;
  wire p_Val2_5_fu_361_p2__1_n_79;
  wire p_Val2_5_fu_361_p2__1_n_80;
  wire p_Val2_5_fu_361_p2__1_n_81;
  wire p_Val2_5_fu_361_p2__1_n_82;
  wire p_Val2_5_fu_361_p2__1_n_83;
  wire p_Val2_5_fu_361_p2__1_n_84;
  wire p_Val2_5_fu_361_p2__1_n_85;
  wire p_Val2_5_fu_361_p2__1_n_86;
  wire p_Val2_5_fu_361_p2__1_n_87;
  wire p_Val2_5_fu_361_p2__1_n_88;
  wire p_Val2_5_fu_361_p2__1_n_89;
  wire p_Val2_5_fu_361_p2__1_n_90;
  wire p_Val2_5_fu_361_p2__1_n_91;
  wire p_Val2_5_fu_361_p2__1_n_92;
  wire p_Val2_5_fu_361_p2__1_n_93;
  wire p_Val2_5_fu_361_p2__1_n_94;
  wire p_Val2_5_fu_361_p2__1_n_95;
  wire p_Val2_5_fu_361_p2__1_n_96;
  wire p_Val2_5_fu_361_p2__1_n_97;
  wire p_Val2_5_fu_361_p2__1_n_98;
  wire p_Val2_5_fu_361_p2__1_n_99;
  wire p_Val2_5_fu_361_p2_i_10_n_0;
  wire p_Val2_5_fu_361_p2_i_11_n_0;
  wire p_Val2_5_fu_361_p2_i_12_n_0;
  wire p_Val2_5_fu_361_p2_i_13_n_0;
  wire p_Val2_5_fu_361_p2_i_14_n_0;
  wire p_Val2_5_fu_361_p2_i_15_n_0;
  wire p_Val2_5_fu_361_p2_i_16_n_0;
  wire p_Val2_5_fu_361_p2_i_17_n_0;
  wire p_Val2_5_fu_361_p2_i_18_n_0;
  wire p_Val2_5_fu_361_p2_i_19_n_0;
  wire p_Val2_5_fu_361_p2_i_1_n_0;
  wire p_Val2_5_fu_361_p2_i_20_n_0;
  wire p_Val2_5_fu_361_p2_i_21_n_0;
  wire p_Val2_5_fu_361_p2_i_22_n_0;
  wire p_Val2_5_fu_361_p2_i_23_n_0;
  wire p_Val2_5_fu_361_p2_i_24_n_0;
  wire p_Val2_5_fu_361_p2_i_25_n_0;
  wire p_Val2_5_fu_361_p2_i_26_n_0;
  wire p_Val2_5_fu_361_p2_i_3_n_0;
  wire p_Val2_5_fu_361_p2_i_3_n_1;
  wire p_Val2_5_fu_361_p2_i_3_n_2;
  wire p_Val2_5_fu_361_p2_i_3_n_3;
  wire p_Val2_5_fu_361_p2_i_3_n_4;
  wire p_Val2_5_fu_361_p2_i_3_n_5;
  wire p_Val2_5_fu_361_p2_i_3_n_6;
  wire p_Val2_5_fu_361_p2_i_3_n_7;
  wire p_Val2_5_fu_361_p2_i_4_n_0;
  wire p_Val2_5_fu_361_p2_i_4_n_1;
  wire p_Val2_5_fu_361_p2_i_4_n_2;
  wire p_Val2_5_fu_361_p2_i_4_n_3;
  wire p_Val2_5_fu_361_p2_i_4_n_4;
  wire p_Val2_5_fu_361_p2_i_4_n_5;
  wire p_Val2_5_fu_361_p2_i_4_n_6;
  wire p_Val2_5_fu_361_p2_i_4_n_7;
  wire p_Val2_5_fu_361_p2_i_5_n_0;
  wire p_Val2_5_fu_361_p2_i_5_n_1;
  wire p_Val2_5_fu_361_p2_i_5_n_2;
  wire p_Val2_5_fu_361_p2_i_5_n_3;
  wire p_Val2_5_fu_361_p2_i_5_n_4;
  wire p_Val2_5_fu_361_p2_i_5_n_5;
  wire p_Val2_5_fu_361_p2_i_5_n_6;
  wire p_Val2_5_fu_361_p2_i_5_n_7;
  wire p_Val2_5_fu_361_p2_i_6_n_0;
  wire p_Val2_5_fu_361_p2_i_6_n_1;
  wire p_Val2_5_fu_361_p2_i_6_n_2;
  wire p_Val2_5_fu_361_p2_i_6_n_3;
  wire p_Val2_5_fu_361_p2_i_6_n_4;
  wire p_Val2_5_fu_361_p2_i_6_n_5;
  wire p_Val2_5_fu_361_p2_i_6_n_6;
  wire p_Val2_5_fu_361_p2_i_6_n_7;
  wire p_Val2_5_fu_361_p2_i_7_n_0;
  wire p_Val2_5_fu_361_p2_i_7_n_1;
  wire p_Val2_5_fu_361_p2_i_7_n_2;
  wire p_Val2_5_fu_361_p2_i_7_n_3;
  wire p_Val2_5_fu_361_p2_i_7_n_4;
  wire p_Val2_5_fu_361_p2_i_7_n_5;
  wire p_Val2_5_fu_361_p2_i_7_n_6;
  wire p_Val2_5_fu_361_p2_i_7_n_7;
  wire p_Val2_5_fu_361_p2_i_8_n_0;
  wire p_Val2_5_fu_361_p2_i_9_n_0;
  wire p_Val2_5_fu_361_p2_n_10;
  wire p_Val2_5_fu_361_p2_n_100;
  wire p_Val2_5_fu_361_p2_n_101;
  wire p_Val2_5_fu_361_p2_n_102;
  wire p_Val2_5_fu_361_p2_n_103;
  wire p_Val2_5_fu_361_p2_n_104;
  wire p_Val2_5_fu_361_p2_n_105;
  wire p_Val2_5_fu_361_p2_n_106;
  wire p_Val2_5_fu_361_p2_n_107;
  wire p_Val2_5_fu_361_p2_n_108;
  wire p_Val2_5_fu_361_p2_n_109;
  wire p_Val2_5_fu_361_p2_n_11;
  wire p_Val2_5_fu_361_p2_n_110;
  wire p_Val2_5_fu_361_p2_n_111;
  wire p_Val2_5_fu_361_p2_n_112;
  wire p_Val2_5_fu_361_p2_n_113;
  wire p_Val2_5_fu_361_p2_n_114;
  wire p_Val2_5_fu_361_p2_n_115;
  wire p_Val2_5_fu_361_p2_n_116;
  wire p_Val2_5_fu_361_p2_n_117;
  wire p_Val2_5_fu_361_p2_n_118;
  wire p_Val2_5_fu_361_p2_n_119;
  wire p_Val2_5_fu_361_p2_n_12;
  wire p_Val2_5_fu_361_p2_n_120;
  wire p_Val2_5_fu_361_p2_n_121;
  wire p_Val2_5_fu_361_p2_n_122;
  wire p_Val2_5_fu_361_p2_n_123;
  wire p_Val2_5_fu_361_p2_n_124;
  wire p_Val2_5_fu_361_p2_n_125;
  wire p_Val2_5_fu_361_p2_n_126;
  wire p_Val2_5_fu_361_p2_n_127;
  wire p_Val2_5_fu_361_p2_n_128;
  wire p_Val2_5_fu_361_p2_n_129;
  wire p_Val2_5_fu_361_p2_n_13;
  wire p_Val2_5_fu_361_p2_n_130;
  wire p_Val2_5_fu_361_p2_n_131;
  wire p_Val2_5_fu_361_p2_n_132;
  wire p_Val2_5_fu_361_p2_n_133;
  wire p_Val2_5_fu_361_p2_n_134;
  wire p_Val2_5_fu_361_p2_n_135;
  wire p_Val2_5_fu_361_p2_n_136;
  wire p_Val2_5_fu_361_p2_n_137;
  wire p_Val2_5_fu_361_p2_n_138;
  wire p_Val2_5_fu_361_p2_n_139;
  wire p_Val2_5_fu_361_p2_n_14;
  wire p_Val2_5_fu_361_p2_n_140;
  wire p_Val2_5_fu_361_p2_n_141;
  wire p_Val2_5_fu_361_p2_n_142;
  wire p_Val2_5_fu_361_p2_n_143;
  wire p_Val2_5_fu_361_p2_n_144;
  wire p_Val2_5_fu_361_p2_n_145;
  wire p_Val2_5_fu_361_p2_n_146;
  wire p_Val2_5_fu_361_p2_n_147;
  wire p_Val2_5_fu_361_p2_n_148;
  wire p_Val2_5_fu_361_p2_n_149;
  wire p_Val2_5_fu_361_p2_n_15;
  wire p_Val2_5_fu_361_p2_n_150;
  wire p_Val2_5_fu_361_p2_n_151;
  wire p_Val2_5_fu_361_p2_n_152;
  wire p_Val2_5_fu_361_p2_n_153;
  wire p_Val2_5_fu_361_p2_n_16;
  wire p_Val2_5_fu_361_p2_n_17;
  wire p_Val2_5_fu_361_p2_n_18;
  wire p_Val2_5_fu_361_p2_n_19;
  wire p_Val2_5_fu_361_p2_n_20;
  wire p_Val2_5_fu_361_p2_n_21;
  wire p_Val2_5_fu_361_p2_n_22;
  wire p_Val2_5_fu_361_p2_n_23;
  wire p_Val2_5_fu_361_p2_n_58;
  wire p_Val2_5_fu_361_p2_n_59;
  wire p_Val2_5_fu_361_p2_n_6;
  wire p_Val2_5_fu_361_p2_n_60;
  wire p_Val2_5_fu_361_p2_n_61;
  wire p_Val2_5_fu_361_p2_n_62;
  wire p_Val2_5_fu_361_p2_n_63;
  wire p_Val2_5_fu_361_p2_n_64;
  wire p_Val2_5_fu_361_p2_n_65;
  wire p_Val2_5_fu_361_p2_n_66;
  wire p_Val2_5_fu_361_p2_n_67;
  wire p_Val2_5_fu_361_p2_n_68;
  wire p_Val2_5_fu_361_p2_n_69;
  wire p_Val2_5_fu_361_p2_n_7;
  wire p_Val2_5_fu_361_p2_n_70;
  wire p_Val2_5_fu_361_p2_n_71;
  wire p_Val2_5_fu_361_p2_n_72;
  wire p_Val2_5_fu_361_p2_n_73;
  wire p_Val2_5_fu_361_p2_n_74;
  wire p_Val2_5_fu_361_p2_n_75;
  wire p_Val2_5_fu_361_p2_n_76;
  wire p_Val2_5_fu_361_p2_n_77;
  wire p_Val2_5_fu_361_p2_n_78;
  wire p_Val2_5_fu_361_p2_n_79;
  wire p_Val2_5_fu_361_p2_n_8;
  wire p_Val2_5_fu_361_p2_n_80;
  wire p_Val2_5_fu_361_p2_n_81;
  wire p_Val2_5_fu_361_p2_n_82;
  wire p_Val2_5_fu_361_p2_n_83;
  wire p_Val2_5_fu_361_p2_n_84;
  wire p_Val2_5_fu_361_p2_n_85;
  wire p_Val2_5_fu_361_p2_n_86;
  wire p_Val2_5_fu_361_p2_n_87;
  wire p_Val2_5_fu_361_p2_n_88;
  wire p_Val2_5_fu_361_p2_n_89;
  wire p_Val2_5_fu_361_p2_n_9;
  wire p_Val2_5_fu_361_p2_n_90;
  wire p_Val2_5_fu_361_p2_n_91;
  wire p_Val2_5_fu_361_p2_n_92;
  wire p_Val2_5_fu_361_p2_n_93;
  wire p_Val2_5_fu_361_p2_n_94;
  wire p_Val2_5_fu_361_p2_n_95;
  wire p_Val2_5_fu_361_p2_n_96;
  wire p_Val2_5_fu_361_p2_n_97;
  wire p_Val2_5_fu_361_p2_n_98;
  wire p_Val2_5_fu_361_p2_n_99;
  wire p_Val2_6_fu_302_p2__0_i_10_n_0;
  wire p_Val2_6_fu_302_p2__0_i_11_n_0;
  wire p_Val2_6_fu_302_p2__0_i_12_n_0;
  wire p_Val2_6_fu_302_p2__0_i_13_n_0;
  wire p_Val2_6_fu_302_p2__0_i_14_n_0;
  wire p_Val2_6_fu_302_p2__0_i_15_n_0;
  wire p_Val2_6_fu_302_p2__0_i_16_n_0;
  wire p_Val2_6_fu_302_p2__0_i_1_n_7;
  wire p_Val2_6_fu_302_p2__0_i_2_n_0;
  wire p_Val2_6_fu_302_p2__0_i_2_n_1;
  wire p_Val2_6_fu_302_p2__0_i_2_n_2;
  wire p_Val2_6_fu_302_p2__0_i_2_n_3;
  wire p_Val2_6_fu_302_p2__0_i_2_n_4;
  wire p_Val2_6_fu_302_p2__0_i_2_n_5;
  wire p_Val2_6_fu_302_p2__0_i_2_n_6;
  wire p_Val2_6_fu_302_p2__0_i_2_n_7;
  wire p_Val2_6_fu_302_p2__0_i_3_n_0;
  wire p_Val2_6_fu_302_p2__0_i_3_n_1;
  wire p_Val2_6_fu_302_p2__0_i_3_n_2;
  wire p_Val2_6_fu_302_p2__0_i_3_n_3;
  wire p_Val2_6_fu_302_p2__0_i_3_n_4;
  wire p_Val2_6_fu_302_p2__0_i_3_n_5;
  wire p_Val2_6_fu_302_p2__0_i_3_n_6;
  wire p_Val2_6_fu_302_p2__0_i_3_n_7;
  wire p_Val2_6_fu_302_p2__0_i_4_n_0;
  wire p_Val2_6_fu_302_p2__0_i_4_n_1;
  wire p_Val2_6_fu_302_p2__0_i_4_n_2;
  wire p_Val2_6_fu_302_p2__0_i_4_n_3;
  wire p_Val2_6_fu_302_p2__0_i_4_n_4;
  wire p_Val2_6_fu_302_p2__0_i_4_n_5;
  wire p_Val2_6_fu_302_p2__0_i_4_n_6;
  wire p_Val2_6_fu_302_p2__0_i_4_n_7;
  wire p_Val2_6_fu_302_p2__0_i_5_n_0;
  wire p_Val2_6_fu_302_p2__0_i_6_n_0;
  wire p_Val2_6_fu_302_p2__0_i_7_n_0;
  wire p_Val2_6_fu_302_p2__0_i_8_n_0;
  wire p_Val2_6_fu_302_p2__0_i_9_n_0;
  wire p_Val2_6_fu_302_p2__0_n_100;
  wire p_Val2_6_fu_302_p2__0_n_101;
  wire p_Val2_6_fu_302_p2__0_n_102;
  wire p_Val2_6_fu_302_p2__0_n_103;
  wire p_Val2_6_fu_302_p2__0_n_104;
  wire p_Val2_6_fu_302_p2__0_n_105;
  wire p_Val2_6_fu_302_p2__0_n_58;
  wire p_Val2_6_fu_302_p2__0_n_59;
  wire p_Val2_6_fu_302_p2__0_n_60;
  wire p_Val2_6_fu_302_p2__0_n_61;
  wire p_Val2_6_fu_302_p2__0_n_62;
  wire p_Val2_6_fu_302_p2__0_n_63;
  wire p_Val2_6_fu_302_p2__0_n_64;
  wire p_Val2_6_fu_302_p2__0_n_65;
  wire p_Val2_6_fu_302_p2__0_n_66;
  wire p_Val2_6_fu_302_p2__0_n_67;
  wire p_Val2_6_fu_302_p2__0_n_68;
  wire p_Val2_6_fu_302_p2__0_n_69;
  wire p_Val2_6_fu_302_p2__0_n_70;
  wire p_Val2_6_fu_302_p2__0_n_71;
  wire p_Val2_6_fu_302_p2__0_n_72;
  wire p_Val2_6_fu_302_p2__0_n_73;
  wire p_Val2_6_fu_302_p2__0_n_74;
  wire p_Val2_6_fu_302_p2__0_n_75;
  wire p_Val2_6_fu_302_p2__0_n_76;
  wire p_Val2_6_fu_302_p2__0_n_77;
  wire p_Val2_6_fu_302_p2__0_n_78;
  wire p_Val2_6_fu_302_p2__0_n_79;
  wire p_Val2_6_fu_302_p2__0_n_80;
  wire p_Val2_6_fu_302_p2__0_n_81;
  wire p_Val2_6_fu_302_p2__0_n_82;
  wire p_Val2_6_fu_302_p2__0_n_83;
  wire p_Val2_6_fu_302_p2__0_n_84;
  wire p_Val2_6_fu_302_p2__0_n_85;
  wire p_Val2_6_fu_302_p2__0_n_86;
  wire p_Val2_6_fu_302_p2__0_n_87;
  wire p_Val2_6_fu_302_p2__0_n_88;
  wire p_Val2_6_fu_302_p2__0_n_89;
  wire p_Val2_6_fu_302_p2__0_n_90;
  wire p_Val2_6_fu_302_p2__0_n_91;
  wire p_Val2_6_fu_302_p2__0_n_92;
  wire p_Val2_6_fu_302_p2__0_n_93;
  wire p_Val2_6_fu_302_p2__0_n_94;
  wire p_Val2_6_fu_302_p2__0_n_95;
  wire p_Val2_6_fu_302_p2__0_n_96;
  wire p_Val2_6_fu_302_p2__0_n_97;
  wire p_Val2_6_fu_302_p2__0_n_98;
  wire p_Val2_6_fu_302_p2__0_n_99;
  wire p_Val2_6_fu_302_p2__1_n_100;
  wire p_Val2_6_fu_302_p2__1_n_101;
  wire p_Val2_6_fu_302_p2__1_n_102;
  wire p_Val2_6_fu_302_p2__1_n_103;
  wire p_Val2_6_fu_302_p2__1_n_104;
  wire p_Val2_6_fu_302_p2__1_n_105;
  wire p_Val2_6_fu_302_p2__1_n_106;
  wire p_Val2_6_fu_302_p2__1_n_107;
  wire p_Val2_6_fu_302_p2__1_n_108;
  wire p_Val2_6_fu_302_p2__1_n_109;
  wire p_Val2_6_fu_302_p2__1_n_110;
  wire p_Val2_6_fu_302_p2__1_n_111;
  wire p_Val2_6_fu_302_p2__1_n_112;
  wire p_Val2_6_fu_302_p2__1_n_113;
  wire p_Val2_6_fu_302_p2__1_n_114;
  wire p_Val2_6_fu_302_p2__1_n_115;
  wire p_Val2_6_fu_302_p2__1_n_116;
  wire p_Val2_6_fu_302_p2__1_n_117;
  wire p_Val2_6_fu_302_p2__1_n_118;
  wire p_Val2_6_fu_302_p2__1_n_119;
  wire p_Val2_6_fu_302_p2__1_n_120;
  wire p_Val2_6_fu_302_p2__1_n_121;
  wire p_Val2_6_fu_302_p2__1_n_122;
  wire p_Val2_6_fu_302_p2__1_n_123;
  wire p_Val2_6_fu_302_p2__1_n_124;
  wire p_Val2_6_fu_302_p2__1_n_125;
  wire p_Val2_6_fu_302_p2__1_n_126;
  wire p_Val2_6_fu_302_p2__1_n_127;
  wire p_Val2_6_fu_302_p2__1_n_128;
  wire p_Val2_6_fu_302_p2__1_n_129;
  wire p_Val2_6_fu_302_p2__1_n_130;
  wire p_Val2_6_fu_302_p2__1_n_131;
  wire p_Val2_6_fu_302_p2__1_n_132;
  wire p_Val2_6_fu_302_p2__1_n_133;
  wire p_Val2_6_fu_302_p2__1_n_134;
  wire p_Val2_6_fu_302_p2__1_n_135;
  wire p_Val2_6_fu_302_p2__1_n_136;
  wire p_Val2_6_fu_302_p2__1_n_137;
  wire p_Val2_6_fu_302_p2__1_n_138;
  wire p_Val2_6_fu_302_p2__1_n_139;
  wire p_Val2_6_fu_302_p2__1_n_140;
  wire p_Val2_6_fu_302_p2__1_n_141;
  wire p_Val2_6_fu_302_p2__1_n_142;
  wire p_Val2_6_fu_302_p2__1_n_143;
  wire p_Val2_6_fu_302_p2__1_n_144;
  wire p_Val2_6_fu_302_p2__1_n_145;
  wire p_Val2_6_fu_302_p2__1_n_146;
  wire p_Val2_6_fu_302_p2__1_n_147;
  wire p_Val2_6_fu_302_p2__1_n_148;
  wire p_Val2_6_fu_302_p2__1_n_149;
  wire p_Val2_6_fu_302_p2__1_n_150;
  wire p_Val2_6_fu_302_p2__1_n_151;
  wire p_Val2_6_fu_302_p2__1_n_152;
  wire p_Val2_6_fu_302_p2__1_n_153;
  wire p_Val2_6_fu_302_p2__1_n_24;
  wire p_Val2_6_fu_302_p2__1_n_25;
  wire p_Val2_6_fu_302_p2__1_n_26;
  wire p_Val2_6_fu_302_p2__1_n_27;
  wire p_Val2_6_fu_302_p2__1_n_28;
  wire p_Val2_6_fu_302_p2__1_n_29;
  wire p_Val2_6_fu_302_p2__1_n_30;
  wire p_Val2_6_fu_302_p2__1_n_31;
  wire p_Val2_6_fu_302_p2__1_n_32;
  wire p_Val2_6_fu_302_p2__1_n_33;
  wire p_Val2_6_fu_302_p2__1_n_34;
  wire p_Val2_6_fu_302_p2__1_n_35;
  wire p_Val2_6_fu_302_p2__1_n_36;
  wire p_Val2_6_fu_302_p2__1_n_37;
  wire p_Val2_6_fu_302_p2__1_n_38;
  wire p_Val2_6_fu_302_p2__1_n_39;
  wire p_Val2_6_fu_302_p2__1_n_40;
  wire p_Val2_6_fu_302_p2__1_n_41;
  wire p_Val2_6_fu_302_p2__1_n_42;
  wire p_Val2_6_fu_302_p2__1_n_43;
  wire p_Val2_6_fu_302_p2__1_n_44;
  wire p_Val2_6_fu_302_p2__1_n_45;
  wire p_Val2_6_fu_302_p2__1_n_46;
  wire p_Val2_6_fu_302_p2__1_n_47;
  wire p_Val2_6_fu_302_p2__1_n_48;
  wire p_Val2_6_fu_302_p2__1_n_49;
  wire p_Val2_6_fu_302_p2__1_n_50;
  wire p_Val2_6_fu_302_p2__1_n_51;
  wire p_Val2_6_fu_302_p2__1_n_52;
  wire p_Val2_6_fu_302_p2__1_n_53;
  wire p_Val2_6_fu_302_p2__1_n_58;
  wire p_Val2_6_fu_302_p2__1_n_59;
  wire p_Val2_6_fu_302_p2__1_n_60;
  wire p_Val2_6_fu_302_p2__1_n_61;
  wire p_Val2_6_fu_302_p2__1_n_62;
  wire p_Val2_6_fu_302_p2__1_n_63;
  wire p_Val2_6_fu_302_p2__1_n_64;
  wire p_Val2_6_fu_302_p2__1_n_65;
  wire p_Val2_6_fu_302_p2__1_n_66;
  wire p_Val2_6_fu_302_p2__1_n_67;
  wire p_Val2_6_fu_302_p2__1_n_68;
  wire p_Val2_6_fu_302_p2__1_n_69;
  wire p_Val2_6_fu_302_p2__1_n_70;
  wire p_Val2_6_fu_302_p2__1_n_71;
  wire p_Val2_6_fu_302_p2__1_n_72;
  wire p_Val2_6_fu_302_p2__1_n_73;
  wire p_Val2_6_fu_302_p2__1_n_74;
  wire p_Val2_6_fu_302_p2__1_n_75;
  wire p_Val2_6_fu_302_p2__1_n_76;
  wire p_Val2_6_fu_302_p2__1_n_77;
  wire p_Val2_6_fu_302_p2__1_n_78;
  wire p_Val2_6_fu_302_p2__1_n_79;
  wire p_Val2_6_fu_302_p2__1_n_80;
  wire p_Val2_6_fu_302_p2__1_n_81;
  wire p_Val2_6_fu_302_p2__1_n_82;
  wire p_Val2_6_fu_302_p2__1_n_83;
  wire p_Val2_6_fu_302_p2__1_n_84;
  wire p_Val2_6_fu_302_p2__1_n_85;
  wire p_Val2_6_fu_302_p2__1_n_86;
  wire p_Val2_6_fu_302_p2__1_n_87;
  wire p_Val2_6_fu_302_p2__1_n_88;
  wire p_Val2_6_fu_302_p2__1_n_89;
  wire p_Val2_6_fu_302_p2__1_n_90;
  wire p_Val2_6_fu_302_p2__1_n_91;
  wire p_Val2_6_fu_302_p2__1_n_92;
  wire p_Val2_6_fu_302_p2__1_n_93;
  wire p_Val2_6_fu_302_p2__1_n_94;
  wire p_Val2_6_fu_302_p2__1_n_95;
  wire p_Val2_6_fu_302_p2__1_n_96;
  wire p_Val2_6_fu_302_p2__1_n_97;
  wire p_Val2_6_fu_302_p2__1_n_98;
  wire p_Val2_6_fu_302_p2__1_n_99;
  wire p_Val2_6_fu_302_p2__2_n_100;
  wire p_Val2_6_fu_302_p2__2_n_101;
  wire p_Val2_6_fu_302_p2__2_n_102;
  wire p_Val2_6_fu_302_p2__2_n_103;
  wire p_Val2_6_fu_302_p2__2_n_104;
  wire p_Val2_6_fu_302_p2__2_n_105;
  wire p_Val2_6_fu_302_p2__2_n_58;
  wire p_Val2_6_fu_302_p2__2_n_59;
  wire p_Val2_6_fu_302_p2__2_n_60;
  wire p_Val2_6_fu_302_p2__2_n_61;
  wire p_Val2_6_fu_302_p2__2_n_62;
  wire p_Val2_6_fu_302_p2__2_n_63;
  wire p_Val2_6_fu_302_p2__2_n_64;
  wire p_Val2_6_fu_302_p2__2_n_65;
  wire p_Val2_6_fu_302_p2__2_n_66;
  wire p_Val2_6_fu_302_p2__2_n_67;
  wire p_Val2_6_fu_302_p2__2_n_68;
  wire p_Val2_6_fu_302_p2__2_n_69;
  wire p_Val2_6_fu_302_p2__2_n_70;
  wire p_Val2_6_fu_302_p2__2_n_71;
  wire p_Val2_6_fu_302_p2__2_n_72;
  wire p_Val2_6_fu_302_p2__2_n_73;
  wire p_Val2_6_fu_302_p2__2_n_74;
  wire p_Val2_6_fu_302_p2__2_n_75;
  wire p_Val2_6_fu_302_p2__2_n_76;
  wire p_Val2_6_fu_302_p2__2_n_77;
  wire p_Val2_6_fu_302_p2__2_n_78;
  wire p_Val2_6_fu_302_p2__2_n_79;
  wire p_Val2_6_fu_302_p2__2_n_80;
  wire p_Val2_6_fu_302_p2__2_n_81;
  wire p_Val2_6_fu_302_p2__2_n_82;
  wire p_Val2_6_fu_302_p2__2_n_83;
  wire p_Val2_6_fu_302_p2__2_n_84;
  wire p_Val2_6_fu_302_p2__2_n_85;
  wire p_Val2_6_fu_302_p2__2_n_86;
  wire p_Val2_6_fu_302_p2__2_n_87;
  wire p_Val2_6_fu_302_p2__2_n_88;
  wire p_Val2_6_fu_302_p2__2_n_89;
  wire p_Val2_6_fu_302_p2__2_n_90;
  wire p_Val2_6_fu_302_p2__2_n_91;
  wire p_Val2_6_fu_302_p2__2_n_92;
  wire p_Val2_6_fu_302_p2__2_n_93;
  wire p_Val2_6_fu_302_p2__2_n_94;
  wire p_Val2_6_fu_302_p2__2_n_95;
  wire p_Val2_6_fu_302_p2__2_n_96;
  wire p_Val2_6_fu_302_p2__2_n_97;
  wire p_Val2_6_fu_302_p2__2_n_98;
  wire p_Val2_6_fu_302_p2__2_n_99;
  wire p_Val2_6_fu_302_p2_i_1_n_0;
  wire p_Val2_6_fu_302_p2_i_1_n_1;
  wire p_Val2_6_fu_302_p2_i_1_n_2;
  wire p_Val2_6_fu_302_p2_i_1_n_3;
  wire p_Val2_6_fu_302_p2_i_1_n_4;
  wire p_Val2_6_fu_302_p2_i_1_n_5;
  wire p_Val2_6_fu_302_p2_i_1_n_6;
  wire p_Val2_6_fu_302_p2_i_1_n_7;
  wire p_Val2_6_fu_302_p2_i_26_n_0;
  wire p_Val2_6_fu_302_p2_i_27_n_0;
  wire p_Val2_6_fu_302_p2_i_28_n_0;
  wire p_Val2_6_fu_302_p2_i_29_n_0;
  wire p_Val2_6_fu_302_p2_i_2_n_0;
  wire p_Val2_6_fu_302_p2_i_2_n_1;
  wire p_Val2_6_fu_302_p2_i_2_n_2;
  wire p_Val2_6_fu_302_p2_i_2_n_3;
  wire p_Val2_6_fu_302_p2_i_2_n_4;
  wire p_Val2_6_fu_302_p2_i_2_n_5;
  wire p_Val2_6_fu_302_p2_i_2_n_6;
  wire p_Val2_6_fu_302_p2_i_2_n_7;
  wire p_Val2_6_fu_302_p2_i_30_n_0;
  wire p_Val2_6_fu_302_p2_i_31_n_0;
  wire p_Val2_6_fu_302_p2_i_32_n_0;
  wire p_Val2_6_fu_302_p2_i_33_n_0;
  wire p_Val2_6_fu_302_p2_i_34_n_0;
  wire p_Val2_6_fu_302_p2_i_35_n_0;
  wire p_Val2_6_fu_302_p2_i_36_n_0;
  wire p_Val2_6_fu_302_p2_i_37_n_0;
  wire p_Val2_6_fu_302_p2_i_38_n_0;
  wire p_Val2_6_fu_302_p2_i_39_n_0;
  wire p_Val2_6_fu_302_p2_i_3_n_0;
  wire p_Val2_6_fu_302_p2_i_3_n_1;
  wire p_Val2_6_fu_302_p2_i_3_n_2;
  wire p_Val2_6_fu_302_p2_i_3_n_3;
  wire p_Val2_6_fu_302_p2_i_3_n_4;
  wire p_Val2_6_fu_302_p2_i_3_n_5;
  wire p_Val2_6_fu_302_p2_i_3_n_6;
  wire p_Val2_6_fu_302_p2_i_3_n_7;
  wire p_Val2_6_fu_302_p2_i_40_n_0;
  wire p_Val2_6_fu_302_p2_i_41_n_0;
  wire p_Val2_6_fu_302_p2_i_42_n_0;
  wire p_Val2_6_fu_302_p2_i_43_n_0;
  wire p_Val2_6_fu_302_p2_i_44_n_0;
  wire p_Val2_6_fu_302_p2_i_45_n_0;
  wire p_Val2_6_fu_302_p2_i_46_n_0;
  wire p_Val2_6_fu_302_p2_i_47_n_0;
  wire p_Val2_6_fu_302_p2_i_48_n_0;
  wire p_Val2_6_fu_302_p2_i_49_n_0;
  wire p_Val2_6_fu_302_p2_i_4_n_0;
  wire p_Val2_6_fu_302_p2_i_4_n_1;
  wire p_Val2_6_fu_302_p2_i_4_n_2;
  wire p_Val2_6_fu_302_p2_i_4_n_3;
  wire p_Val2_6_fu_302_p2_i_4_n_4;
  wire p_Val2_6_fu_302_p2_i_4_n_5;
  wire p_Val2_6_fu_302_p2_i_4_n_6;
  wire p_Val2_6_fu_302_p2_i_4_n_7;
  wire p_Val2_6_fu_302_p2_i_50_n_0;
  wire p_Val2_6_fu_302_p2_i_51_n_0;
  wire p_Val2_6_fu_302_p2_i_52_n_0;
  wire p_Val2_6_fu_302_p2_i_53_n_0;
  wire p_Val2_6_fu_302_p2_i_54_n_0;
  wire p_Val2_6_fu_302_p2_i_55_n_0;
  wire p_Val2_6_fu_302_p2_i_5_n_0;
  wire p_Val2_6_fu_302_p2_i_5_n_1;
  wire p_Val2_6_fu_302_p2_i_5_n_2;
  wire p_Val2_6_fu_302_p2_i_5_n_3;
  wire p_Val2_6_fu_302_p2_i_5_n_4;
  wire p_Val2_6_fu_302_p2_i_5_n_5;
  wire p_Val2_6_fu_302_p2_i_5_n_6;
  wire p_Val2_6_fu_302_p2_i_5_n_7;
  wire p_Val2_6_fu_302_p2_n_100;
  wire p_Val2_6_fu_302_p2_n_101;
  wire p_Val2_6_fu_302_p2_n_102;
  wire p_Val2_6_fu_302_p2_n_103;
  wire p_Val2_6_fu_302_p2_n_104;
  wire p_Val2_6_fu_302_p2_n_105;
  wire p_Val2_6_fu_302_p2_n_106;
  wire p_Val2_6_fu_302_p2_n_107;
  wire p_Val2_6_fu_302_p2_n_108;
  wire p_Val2_6_fu_302_p2_n_109;
  wire p_Val2_6_fu_302_p2_n_110;
  wire p_Val2_6_fu_302_p2_n_111;
  wire p_Val2_6_fu_302_p2_n_112;
  wire p_Val2_6_fu_302_p2_n_113;
  wire p_Val2_6_fu_302_p2_n_114;
  wire p_Val2_6_fu_302_p2_n_115;
  wire p_Val2_6_fu_302_p2_n_116;
  wire p_Val2_6_fu_302_p2_n_117;
  wire p_Val2_6_fu_302_p2_n_118;
  wire p_Val2_6_fu_302_p2_n_119;
  wire p_Val2_6_fu_302_p2_n_120;
  wire p_Val2_6_fu_302_p2_n_121;
  wire p_Val2_6_fu_302_p2_n_122;
  wire p_Val2_6_fu_302_p2_n_123;
  wire p_Val2_6_fu_302_p2_n_124;
  wire p_Val2_6_fu_302_p2_n_125;
  wire p_Val2_6_fu_302_p2_n_126;
  wire p_Val2_6_fu_302_p2_n_127;
  wire p_Val2_6_fu_302_p2_n_128;
  wire p_Val2_6_fu_302_p2_n_129;
  wire p_Val2_6_fu_302_p2_n_130;
  wire p_Val2_6_fu_302_p2_n_131;
  wire p_Val2_6_fu_302_p2_n_132;
  wire p_Val2_6_fu_302_p2_n_133;
  wire p_Val2_6_fu_302_p2_n_134;
  wire p_Val2_6_fu_302_p2_n_135;
  wire p_Val2_6_fu_302_p2_n_136;
  wire p_Val2_6_fu_302_p2_n_137;
  wire p_Val2_6_fu_302_p2_n_138;
  wire p_Val2_6_fu_302_p2_n_139;
  wire p_Val2_6_fu_302_p2_n_140;
  wire p_Val2_6_fu_302_p2_n_141;
  wire p_Val2_6_fu_302_p2_n_142;
  wire p_Val2_6_fu_302_p2_n_143;
  wire p_Val2_6_fu_302_p2_n_144;
  wire p_Val2_6_fu_302_p2_n_145;
  wire p_Val2_6_fu_302_p2_n_146;
  wire p_Val2_6_fu_302_p2_n_147;
  wire p_Val2_6_fu_302_p2_n_148;
  wire p_Val2_6_fu_302_p2_n_149;
  wire p_Val2_6_fu_302_p2_n_150;
  wire p_Val2_6_fu_302_p2_n_151;
  wire p_Val2_6_fu_302_p2_n_152;
  wire p_Val2_6_fu_302_p2_n_153;
  wire p_Val2_6_fu_302_p2_n_24;
  wire p_Val2_6_fu_302_p2_n_25;
  wire p_Val2_6_fu_302_p2_n_26;
  wire p_Val2_6_fu_302_p2_n_27;
  wire p_Val2_6_fu_302_p2_n_28;
  wire p_Val2_6_fu_302_p2_n_29;
  wire p_Val2_6_fu_302_p2_n_30;
  wire p_Val2_6_fu_302_p2_n_31;
  wire p_Val2_6_fu_302_p2_n_32;
  wire p_Val2_6_fu_302_p2_n_33;
  wire p_Val2_6_fu_302_p2_n_34;
  wire p_Val2_6_fu_302_p2_n_35;
  wire p_Val2_6_fu_302_p2_n_36;
  wire p_Val2_6_fu_302_p2_n_37;
  wire p_Val2_6_fu_302_p2_n_38;
  wire p_Val2_6_fu_302_p2_n_39;
  wire p_Val2_6_fu_302_p2_n_40;
  wire p_Val2_6_fu_302_p2_n_41;
  wire p_Val2_6_fu_302_p2_n_42;
  wire p_Val2_6_fu_302_p2_n_43;
  wire p_Val2_6_fu_302_p2_n_44;
  wire p_Val2_6_fu_302_p2_n_45;
  wire p_Val2_6_fu_302_p2_n_46;
  wire p_Val2_6_fu_302_p2_n_47;
  wire p_Val2_6_fu_302_p2_n_48;
  wire p_Val2_6_fu_302_p2_n_49;
  wire p_Val2_6_fu_302_p2_n_50;
  wire p_Val2_6_fu_302_p2_n_51;
  wire p_Val2_6_fu_302_p2_n_52;
  wire p_Val2_6_fu_302_p2_n_53;
  wire p_Val2_6_fu_302_p2_n_58;
  wire p_Val2_6_fu_302_p2_n_59;
  wire p_Val2_6_fu_302_p2_n_60;
  wire p_Val2_6_fu_302_p2_n_61;
  wire p_Val2_6_fu_302_p2_n_62;
  wire p_Val2_6_fu_302_p2_n_63;
  wire p_Val2_6_fu_302_p2_n_64;
  wire p_Val2_6_fu_302_p2_n_65;
  wire p_Val2_6_fu_302_p2_n_66;
  wire p_Val2_6_fu_302_p2_n_67;
  wire p_Val2_6_fu_302_p2_n_68;
  wire p_Val2_6_fu_302_p2_n_69;
  wire p_Val2_6_fu_302_p2_n_70;
  wire p_Val2_6_fu_302_p2_n_71;
  wire p_Val2_6_fu_302_p2_n_72;
  wire p_Val2_6_fu_302_p2_n_73;
  wire p_Val2_6_fu_302_p2_n_74;
  wire p_Val2_6_fu_302_p2_n_75;
  wire p_Val2_6_fu_302_p2_n_76;
  wire p_Val2_6_fu_302_p2_n_77;
  wire p_Val2_6_fu_302_p2_n_78;
  wire p_Val2_6_fu_302_p2_n_79;
  wire p_Val2_6_fu_302_p2_n_80;
  wire p_Val2_6_fu_302_p2_n_81;
  wire p_Val2_6_fu_302_p2_n_82;
  wire p_Val2_6_fu_302_p2_n_83;
  wire p_Val2_6_fu_302_p2_n_84;
  wire p_Val2_6_fu_302_p2_n_85;
  wire p_Val2_6_fu_302_p2_n_86;
  wire p_Val2_6_fu_302_p2_n_87;
  wire p_Val2_6_fu_302_p2_n_88;
  wire p_Val2_6_fu_302_p2_n_89;
  wire p_Val2_6_fu_302_p2_n_90;
  wire p_Val2_6_fu_302_p2_n_91;
  wire p_Val2_6_fu_302_p2_n_92;
  wire p_Val2_6_fu_302_p2_n_93;
  wire p_Val2_6_fu_302_p2_n_94;
  wire p_Val2_6_fu_302_p2_n_95;
  wire p_Val2_6_fu_302_p2_n_96;
  wire p_Val2_6_fu_302_p2_n_97;
  wire p_Val2_6_fu_302_p2_n_98;
  wire p_Val2_6_fu_302_p2_n_99;
  wire [47:0]phase_H1_comp_V;
  wire \phase_H1_comp_V[0]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[0]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[0]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[0]_INST_0_n_0 ;
  wire \phase_H1_comp_V[0]_INST_0_n_1 ;
  wire \phase_H1_comp_V[0]_INST_0_n_2 ;
  wire \phase_H1_comp_V[0]_INST_0_n_3 ;
  wire \phase_H1_comp_V[10]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[10]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[10]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[10]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[10]_INST_0_n_0 ;
  wire \phase_H1_comp_V[10]_INST_0_n_1 ;
  wire \phase_H1_comp_V[10]_INST_0_n_2 ;
  wire \phase_H1_comp_V[10]_INST_0_n_3 ;
  wire \phase_H1_comp_V[14]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[14]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[14]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[14]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[14]_INST_0_n_0 ;
  wire \phase_H1_comp_V[14]_INST_0_n_1 ;
  wire \phase_H1_comp_V[14]_INST_0_n_2 ;
  wire \phase_H1_comp_V[14]_INST_0_n_3 ;
  wire \phase_H1_comp_V[18]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[18]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[18]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[18]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[18]_INST_0_n_0 ;
  wire \phase_H1_comp_V[18]_INST_0_n_1 ;
  wire \phase_H1_comp_V[18]_INST_0_n_2 ;
  wire \phase_H1_comp_V[18]_INST_0_n_3 ;
  wire \phase_H1_comp_V[22]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[22]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[22]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[22]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[22]_INST_0_n_0 ;
  wire \phase_H1_comp_V[22]_INST_0_n_1 ;
  wire \phase_H1_comp_V[22]_INST_0_n_2 ;
  wire \phase_H1_comp_V[22]_INST_0_n_3 ;
  wire \phase_H1_comp_V[26]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[26]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[26]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[26]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[26]_INST_0_n_0 ;
  wire \phase_H1_comp_V[26]_INST_0_n_1 ;
  wire \phase_H1_comp_V[26]_INST_0_n_2 ;
  wire \phase_H1_comp_V[26]_INST_0_n_3 ;
  wire \phase_H1_comp_V[2]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[2]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[2]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[2]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[2]_INST_0_n_0 ;
  wire \phase_H1_comp_V[2]_INST_0_n_1 ;
  wire \phase_H1_comp_V[2]_INST_0_n_2 ;
  wire \phase_H1_comp_V[2]_INST_0_n_3 ;
  wire \phase_H1_comp_V[30]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[30]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[30]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[30]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[30]_INST_0_n_0 ;
  wire \phase_H1_comp_V[30]_INST_0_n_1 ;
  wire \phase_H1_comp_V[30]_INST_0_n_2 ;
  wire \phase_H1_comp_V[30]_INST_0_n_3 ;
  wire \phase_H1_comp_V[34]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[34]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[34]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[34]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[34]_INST_0_n_0 ;
  wire \phase_H1_comp_V[34]_INST_0_n_1 ;
  wire \phase_H1_comp_V[34]_INST_0_n_2 ;
  wire \phase_H1_comp_V[34]_INST_0_n_3 ;
  wire \phase_H1_comp_V[38]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[38]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[38]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[38]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[38]_INST_0_n_0 ;
  wire \phase_H1_comp_V[38]_INST_0_n_1 ;
  wire \phase_H1_comp_V[38]_INST_0_n_2 ;
  wire \phase_H1_comp_V[38]_INST_0_n_3 ;
  wire \phase_H1_comp_V[42]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[42]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[42]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[42]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[42]_INST_0_n_0 ;
  wire \phase_H1_comp_V[42]_INST_0_n_1 ;
  wire \phase_H1_comp_V[42]_INST_0_n_2 ;
  wire \phase_H1_comp_V[42]_INST_0_n_3 ;
  wire \phase_H1_comp_V[46]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[46]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[46]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[46]_INST_0_n_3 ;
  wire \phase_H1_comp_V[6]_INST_0_i_1_n_0 ;
  wire \phase_H1_comp_V[6]_INST_0_i_2_n_0 ;
  wire \phase_H1_comp_V[6]_INST_0_i_3_n_0 ;
  wire \phase_H1_comp_V[6]_INST_0_i_4_n_0 ;
  wire \phase_H1_comp_V[6]_INST_0_n_0 ;
  wire \phase_H1_comp_V[6]_INST_0_n_1 ;
  wire \phase_H1_comp_V[6]_INST_0_n_2 ;
  wire \phase_H1_comp_V[6]_INST_0_n_3 ;
  wire phase_H1_comp_V_ap_vld;
  wire [31:0]quot;
  wire [31:0]sel0;
  wire [15:0]sel0__0;
  wire start;
  wire [42:0]tmp_s_reg_434_reg;
  wire [31:0]tw_H1_V;
  wire tw_H1_V_ap_vld;
  wire [3:0]\NLW_COEF_V_1_data_reg_reg[1]_i_1_O_UNCONNECTED ;
  wire [3:0]\NLW_offset_H1_comp_V[1]_INST_0_i_1_O_UNCONNECTED ;
  wire [3:0]\NLW_phase_H1_comp_V[0]_INST_0_O_UNCONNECTED ;

  assign ap_ready = ap_done;
  assign offset_H1_comp_V[47] = \^offset_H1_comp_V [42];
  assign offset_H1_comp_V[46] = \^offset_H1_comp_V [42];
  assign offset_H1_comp_V[45] = \^offset_H1_comp_V [42];
  assign offset_H1_comp_V[44] = \^offset_H1_comp_V [42];
  assign offset_H1_comp_V[43] = \^offset_H1_comp_V [42];
  assign offset_H1_comp_V[42:0] = \^offset_H1_comp_V [42:0];
  assign offset_H1_comp_V_ap_vld = ap_done;
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[13]_i_2 
       (.I0(p_0_out__1_n_79),
        .I1(p_0_out__0_n_96),
        .O(\COEF_V_1_data_reg[13]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[13]_i_3 
       (.I0(p_0_out__1_n_80),
        .I1(p_0_out__0_n_97),
        .O(\COEF_V_1_data_reg[13]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[13]_i_4 
       (.I0(p_0_out__1_n_81),
        .I1(p_0_out__0_n_98),
        .O(\COEF_V_1_data_reg[13]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[13]_i_5 
       (.I0(p_0_out__1_n_82),
        .I1(p_0_out__0_n_99),
        .O(\COEF_V_1_data_reg[13]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[17]_i_2 
       (.I0(p_0_out__1_n_75),
        .I1(p_0_out__0_n_92),
        .O(\COEF_V_1_data_reg[17]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[17]_i_3 
       (.I0(p_0_out__1_n_76),
        .I1(p_0_out__0_n_93),
        .O(\COEF_V_1_data_reg[17]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[17]_i_4 
       (.I0(p_0_out__1_n_77),
        .I1(p_0_out__0_n_94),
        .O(\COEF_V_1_data_reg[17]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[17]_i_5 
       (.I0(p_0_out__1_n_78),
        .I1(p_0_out__0_n_95),
        .O(\COEF_V_1_data_reg[17]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_10 
       (.I0(p_0_out__1_n_97),
        .I1(\p_0_out_n_0_[8] ),
        .O(\COEF_V_1_data_reg[1]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_11 
       (.I0(p_0_out__1_n_98),
        .I1(\p_0_out_n_0_[7] ),
        .O(\COEF_V_1_data_reg[1]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_13 
       (.I0(p_0_out__1_n_99),
        .I1(\p_0_out_n_0_[6] ),
        .O(\COEF_V_1_data_reg[1]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_14 
       (.I0(p_0_out__1_n_100),
        .I1(\p_0_out_n_0_[5] ),
        .O(\COEF_V_1_data_reg[1]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_15 
       (.I0(p_0_out__1_n_101),
        .I1(\p_0_out_n_0_[4] ),
        .O(\COEF_V_1_data_reg[1]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_16 
       (.I0(p_0_out__1_n_102),
        .I1(\p_0_out_n_0_[3] ),
        .O(\COEF_V_1_data_reg[1]_i_16_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_17 
       (.I0(p_0_out__1_n_103),
        .I1(\p_0_out_n_0_[2] ),
        .O(\COEF_V_1_data_reg[1]_i_17_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_18 
       (.I0(p_0_out__1_n_104),
        .I1(\p_0_out_n_0_[1] ),
        .O(\COEF_V_1_data_reg[1]_i_18_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_19 
       (.I0(p_0_out__1_n_105),
        .I1(\p_0_out_n_0_[0] ),
        .O(\COEF_V_1_data_reg[1]_i_19_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_3 
       (.I0(p_0_out__1_n_91),
        .I1(\p_0_out_n_0_[14] ),
        .O(\COEF_V_1_data_reg[1]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_4 
       (.I0(p_0_out__1_n_92),
        .I1(\p_0_out_n_0_[13] ),
        .O(\COEF_V_1_data_reg[1]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_5 
       (.I0(p_0_out__1_n_93),
        .I1(\p_0_out_n_0_[12] ),
        .O(\COEF_V_1_data_reg[1]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_6 
       (.I0(p_0_out__1_n_94),
        .I1(\p_0_out_n_0_[11] ),
        .O(\COEF_V_1_data_reg[1]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_8 
       (.I0(p_0_out__1_n_95),
        .I1(\p_0_out_n_0_[10] ),
        .O(\COEF_V_1_data_reg[1]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[1]_i_9 
       (.I0(p_0_out__1_n_96),
        .I1(\p_0_out_n_0_[9] ),
        .O(\COEF_V_1_data_reg[1]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[21]_i_2 
       (.I0(p_0_out__1_n_71),
        .I1(p_0_out__0_n_88),
        .O(\COEF_V_1_data_reg[21]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[21]_i_3 
       (.I0(p_0_out__1_n_72),
        .I1(p_0_out__0_n_89),
        .O(\COEF_V_1_data_reg[21]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[21]_i_4 
       (.I0(p_0_out__1_n_73),
        .I1(p_0_out__0_n_90),
        .O(\COEF_V_1_data_reg[21]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[21]_i_5 
       (.I0(p_0_out__1_n_74),
        .I1(p_0_out__0_n_91),
        .O(\COEF_V_1_data_reg[21]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[25]_i_2 
       (.I0(p_0_out__1_n_67),
        .I1(p_0_out__0_n_84),
        .O(\COEF_V_1_data_reg[25]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[25]_i_3 
       (.I0(p_0_out__1_n_68),
        .I1(p_0_out__0_n_85),
        .O(\COEF_V_1_data_reg[25]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[25]_i_4 
       (.I0(p_0_out__1_n_69),
        .I1(p_0_out__0_n_86),
        .O(\COEF_V_1_data_reg[25]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[25]_i_5 
       (.I0(p_0_out__1_n_70),
        .I1(p_0_out__0_n_87),
        .O(\COEF_V_1_data_reg[25]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[29]_i_2 
       (.I0(p_0_out__1_n_63),
        .I1(p_0_out__0_n_80),
        .O(\COEF_V_1_data_reg[29]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[29]_i_3 
       (.I0(p_0_out__1_n_64),
        .I1(p_0_out__0_n_81),
        .O(\COEF_V_1_data_reg[29]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[29]_i_4 
       (.I0(p_0_out__1_n_65),
        .I1(p_0_out__0_n_82),
        .O(\COEF_V_1_data_reg[29]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[29]_i_5 
       (.I0(p_0_out__1_n_66),
        .I1(p_0_out__0_n_83),
        .O(\COEF_V_1_data_reg[29]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hD0)) 
    \COEF_V_1_data_reg[31]_i_1 
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .I2(ap_CS_fsm_state76),
        .O(COEF_V_1_data_reg0));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[31]_i_3 
       (.I0(p_0_out__1_n_61),
        .I1(p_0_out__0_n_78),
        .O(\COEF_V_1_data_reg[31]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[31]_i_4 
       (.I0(p_0_out__1_n_62),
        .I1(p_0_out__0_n_79),
        .O(\COEF_V_1_data_reg[31]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[5]_i_2 
       (.I0(p_0_out__1_n_87),
        .I1(p_0_out__0_n_104),
        .O(\COEF_V_1_data_reg[5]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[5]_i_3 
       (.I0(p_0_out__1_n_88),
        .I1(p_0_out__0_n_105),
        .O(\COEF_V_1_data_reg[5]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[5]_i_4 
       (.I0(p_0_out__1_n_89),
        .I1(\p_0_out_n_0_[16] ),
        .O(\COEF_V_1_data_reg[5]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[5]_i_5 
       (.I0(p_0_out__1_n_90),
        .I1(\p_0_out_n_0_[15] ),
        .O(\COEF_V_1_data_reg[5]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[9]_i_2 
       (.I0(p_0_out__1_n_83),
        .I1(p_0_out__0_n_100),
        .O(\COEF_V_1_data_reg[9]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[9]_i_3 
       (.I0(p_0_out__1_n_84),
        .I1(p_0_out__0_n_101),
        .O(\COEF_V_1_data_reg[9]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[9]_i_4 
       (.I0(p_0_out__1_n_85),
        .I1(p_0_out__0_n_102),
        .O(\COEF_V_1_data_reg[9]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \COEF_V_1_data_reg[9]_i_5 
       (.I0(p_0_out__1_n_86),
        .I1(p_0_out__0_n_103),
        .O(\COEF_V_1_data_reg[9]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[0]),
        .Q(COEF_V[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[10]),
        .Q(COEF_V[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[11]),
        .Q(COEF_V[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[12]),
        .Q(COEF_V[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[13]),
        .Q(COEF_V[13]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[13]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[9]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[13]_i_1_n_0 ,\COEF_V_1_data_reg_reg[13]_i_1_n_1 ,\COEF_V_1_data_reg_reg[13]_i_1_n_2 ,\COEF_V_1_data_reg_reg[13]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_79,p_0_out__1_n_80,p_0_out__1_n_81,p_0_out__1_n_82}),
        .O(p_Val2_4_reg_423_reg[13:10]),
        .S({\COEF_V_1_data_reg[13]_i_2_n_0 ,\COEF_V_1_data_reg[13]_i_3_n_0 ,\COEF_V_1_data_reg[13]_i_4_n_0 ,\COEF_V_1_data_reg[13]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[14]),
        .Q(COEF_V[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[15]),
        .Q(COEF_V[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[16]),
        .Q(COEF_V[16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[17]),
        .Q(COEF_V[17]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[17]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[13]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[17]_i_1_n_0 ,\COEF_V_1_data_reg_reg[17]_i_1_n_1 ,\COEF_V_1_data_reg_reg[17]_i_1_n_2 ,\COEF_V_1_data_reg_reg[17]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_75,p_0_out__1_n_76,p_0_out__1_n_77,p_0_out__1_n_78}),
        .O(p_Val2_4_reg_423_reg[17:14]),
        .S({\COEF_V_1_data_reg[17]_i_2_n_0 ,\COEF_V_1_data_reg[17]_i_3_n_0 ,\COEF_V_1_data_reg[17]_i_4_n_0 ,\COEF_V_1_data_reg[17]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[18]),
        .Q(COEF_V[18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[19]),
        .Q(COEF_V[19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[1]),
        .Q(COEF_V[1]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[1]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[1]_i_2_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[1]_i_1_n_0 ,\COEF_V_1_data_reg_reg[1]_i_1_n_1 ,\COEF_V_1_data_reg_reg[1]_i_1_n_2 ,\COEF_V_1_data_reg_reg[1]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_91,p_0_out__1_n_92,p_0_out__1_n_93,p_0_out__1_n_94}),
        .O({p_Val2_4_reg_423_reg[1:0],\NLW_COEF_V_1_data_reg_reg[1]_i_1_O_UNCONNECTED [1:0]}),
        .S({\COEF_V_1_data_reg[1]_i_3_n_0 ,\COEF_V_1_data_reg[1]_i_4_n_0 ,\COEF_V_1_data_reg[1]_i_5_n_0 ,\COEF_V_1_data_reg[1]_i_6_n_0 }));
  CARRY4 \COEF_V_1_data_reg_reg[1]_i_12 
       (.CI(\<const0> ),
        .CO({\COEF_V_1_data_reg_reg[1]_i_12_n_0 ,\COEF_V_1_data_reg_reg[1]_i_12_n_1 ,\COEF_V_1_data_reg_reg[1]_i_12_n_2 ,\COEF_V_1_data_reg_reg[1]_i_12_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_103,p_0_out__1_n_104,p_0_out__1_n_105,\<const0> }),
        .S({\COEF_V_1_data_reg[1]_i_17_n_0 ,\COEF_V_1_data_reg[1]_i_18_n_0 ,\COEF_V_1_data_reg[1]_i_19_n_0 ,\p_0_out[16]__0_n_0 }));
  CARRY4 \COEF_V_1_data_reg_reg[1]_i_2 
       (.CI(\COEF_V_1_data_reg_reg[1]_i_7_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[1]_i_2_n_0 ,\COEF_V_1_data_reg_reg[1]_i_2_n_1 ,\COEF_V_1_data_reg_reg[1]_i_2_n_2 ,\COEF_V_1_data_reg_reg[1]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_95,p_0_out__1_n_96,p_0_out__1_n_97,p_0_out__1_n_98}),
        .S({\COEF_V_1_data_reg[1]_i_8_n_0 ,\COEF_V_1_data_reg[1]_i_9_n_0 ,\COEF_V_1_data_reg[1]_i_10_n_0 ,\COEF_V_1_data_reg[1]_i_11_n_0 }));
  CARRY4 \COEF_V_1_data_reg_reg[1]_i_7 
       (.CI(\COEF_V_1_data_reg_reg[1]_i_12_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[1]_i_7_n_0 ,\COEF_V_1_data_reg_reg[1]_i_7_n_1 ,\COEF_V_1_data_reg_reg[1]_i_7_n_2 ,\COEF_V_1_data_reg_reg[1]_i_7_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_99,p_0_out__1_n_100,p_0_out__1_n_101,p_0_out__1_n_102}),
        .S({\COEF_V_1_data_reg[1]_i_13_n_0 ,\COEF_V_1_data_reg[1]_i_14_n_0 ,\COEF_V_1_data_reg[1]_i_15_n_0 ,\COEF_V_1_data_reg[1]_i_16_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[20]),
        .Q(COEF_V[20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[21]),
        .Q(COEF_V[21]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[21]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[17]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[21]_i_1_n_0 ,\COEF_V_1_data_reg_reg[21]_i_1_n_1 ,\COEF_V_1_data_reg_reg[21]_i_1_n_2 ,\COEF_V_1_data_reg_reg[21]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_71,p_0_out__1_n_72,p_0_out__1_n_73,p_0_out__1_n_74}),
        .O(p_Val2_4_reg_423_reg[21:18]),
        .S({\COEF_V_1_data_reg[21]_i_2_n_0 ,\COEF_V_1_data_reg[21]_i_3_n_0 ,\COEF_V_1_data_reg[21]_i_4_n_0 ,\COEF_V_1_data_reg[21]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[22]),
        .Q(COEF_V[22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[23]),
        .Q(COEF_V[23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[24]),
        .Q(COEF_V[24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[25]),
        .Q(COEF_V[25]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[25]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[21]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[25]_i_1_n_0 ,\COEF_V_1_data_reg_reg[25]_i_1_n_1 ,\COEF_V_1_data_reg_reg[25]_i_1_n_2 ,\COEF_V_1_data_reg_reg[25]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_67,p_0_out__1_n_68,p_0_out__1_n_69,p_0_out__1_n_70}),
        .O(p_Val2_4_reg_423_reg[25:22]),
        .S({\COEF_V_1_data_reg[25]_i_2_n_0 ,\COEF_V_1_data_reg[25]_i_3_n_0 ,\COEF_V_1_data_reg[25]_i_4_n_0 ,\COEF_V_1_data_reg[25]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[26]),
        .Q(COEF_V[26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[27]),
        .Q(COEF_V[27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[28]),
        .Q(COEF_V[28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[29]),
        .Q(COEF_V[29]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[29]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[25]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[29]_i_1_n_0 ,\COEF_V_1_data_reg_reg[29]_i_1_n_1 ,\COEF_V_1_data_reg_reg[29]_i_1_n_2 ,\COEF_V_1_data_reg_reg[29]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_63,p_0_out__1_n_64,p_0_out__1_n_65,p_0_out__1_n_66}),
        .O(p_Val2_4_reg_423_reg[29:26]),
        .S({\COEF_V_1_data_reg[29]_i_2_n_0 ,\COEF_V_1_data_reg[29]_i_3_n_0 ,\COEF_V_1_data_reg[29]_i_4_n_0 ,\COEF_V_1_data_reg[29]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[2]),
        .Q(COEF_V[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[30]),
        .Q(COEF_V[30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[31]),
        .Q(COEF_V[31]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[31]_i_2 
       (.CI(\COEF_V_1_data_reg_reg[29]_i_1_n_0 ),
        .CO(\COEF_V_1_data_reg_reg[31]_i_2_n_3 ),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,p_0_out__1_n_62}),
        .O(p_Val2_4_reg_423_reg[31:30]),
        .S({\<const0> ,\<const0> ,\COEF_V_1_data_reg[31]_i_3_n_0 ,\COEF_V_1_data_reg[31]_i_4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[3]),
        .Q(COEF_V[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[4]),
        .Q(COEF_V[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[5]),
        .Q(COEF_V[5]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[5]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[1]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[5]_i_1_n_0 ,\COEF_V_1_data_reg_reg[5]_i_1_n_1 ,\COEF_V_1_data_reg_reg[5]_i_1_n_2 ,\COEF_V_1_data_reg_reg[5]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_87,p_0_out__1_n_88,p_0_out__1_n_89,p_0_out__1_n_90}),
        .O(p_Val2_4_reg_423_reg[5:2]),
        .S({\COEF_V_1_data_reg[5]_i_2_n_0 ,\COEF_V_1_data_reg[5]_i_3_n_0 ,\COEF_V_1_data_reg[5]_i_4_n_0 ,\COEF_V_1_data_reg[5]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[6]),
        .Q(COEF_V[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[7]),
        .Q(COEF_V[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[8]),
        .Q(COEF_V[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \COEF_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(COEF_V_1_data_reg0),
        .D(p_Val2_4_reg_423_reg[9]),
        .Q(COEF_V[9]),
        .R(\<const0> ));
  CARRY4 \COEF_V_1_data_reg_reg[9]_i_1 
       (.CI(\COEF_V_1_data_reg_reg[5]_i_1_n_0 ),
        .CO({\COEF_V_1_data_reg_reg[9]_i_1_n_0 ,\COEF_V_1_data_reg_reg[9]_i_1_n_1 ,\COEF_V_1_data_reg_reg[9]_i_1_n_2 ,\COEF_V_1_data_reg_reg[9]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__1_n_83,p_0_out__1_n_84,p_0_out__1_n_85,p_0_out__1_n_86}),
        .O(p_Val2_4_reg_423_reg[9:6]),
        .S({\COEF_V_1_data_reg[9]_i_2_n_0 ,\COEF_V_1_data_reg[9]_i_3_n_0 ,\COEF_V_1_data_reg[9]_i_4_n_0 ,\COEF_V_1_data_reg[9]_i_5_n_0 }));
  LUT4 #(
    .INIT(16'hFB00)) 
    COEF_V_1_vld_reg_i_1
       (.I0(ap_start),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(COEF_V_ap_vld),
        .I3(ap_CS_fsm_state76),
        .O(COEF_V_1_vld_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    COEF_V_1_vld_reg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(COEF_V_1_vld_reg_i_1_n_0),
        .Q(COEF_V_ap_vld),
        .R(\<const0> ));
  GND GND
       (.G(\<const0> ));
  GND GND_1
       (.G(GND_2));
  RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLSbkb RFNCO_Divider_HLSbkb_U1
       (.Q({ap_done,ap_CS_fsm_state77,ap_CS_fsm_state76,tw_H1_V_ap_vld,ap_CS_fsm_state2,\ap_CS_fsm_reg_n_0_[0] }),
        .ap_clk(ap_clk),
        .ap_rst(ap_rst),
        .done0(done0),
        .inputs_delay_comp_V_ap_vld_preg(inputs_delay_comp_V_ap_vld_preg),
        .inputs_enable_FSK_ap_vld_preg(inputs_enable_FSK_ap_vld_preg),
        .inputs_ftw_H1_V_ap_vld_preg(inputs_ftw_H1_V_ap_vld_preg),
        .\inputs_ftw_H1_V_preg_reg[36] ({\inputs_ftw_H1_V_preg_reg_n_0_[36] ,\inputs_ftw_H1_V_preg_reg_n_0_[35] ,\inputs_ftw_H1_V_preg_reg_n_0_[34] ,\inputs_ftw_H1_V_preg_reg_n_0_[33] ,\inputs_ftw_H1_V_preg_reg_n_0_[32] ,\inputs_ftw_H1_V_preg_reg_n_0_[31] ,\inputs_ftw_H1_V_preg_reg_n_0_[30] ,\inputs_ftw_H1_V_preg_reg_n_0_[29] ,\inputs_ftw_H1_V_preg_reg_n_0_[28] ,\inputs_ftw_H1_V_preg_reg_n_0_[27] ,\inputs_ftw_H1_V_preg_reg_n_0_[26] ,\inputs_ftw_H1_V_preg_reg_n_0_[25] ,\inputs_ftw_H1_V_preg_reg_n_0_[24] ,\inputs_ftw_H1_V_preg_reg_n_0_[23] ,\inputs_ftw_H1_V_preg_reg_n_0_[22] ,\inputs_ftw_H1_V_preg_reg_n_0_[21] ,\inputs_ftw_H1_V_preg_reg_n_0_[20] ,\inputs_ftw_H1_V_preg_reg_n_0_[19] ,\inputs_ftw_H1_V_preg_reg_n_0_[18] ,\inputs_ftw_H1_V_preg_reg_n_0_[17] ,\inputs_ftw_H1_V_preg_reg_n_0_[16] ,\inputs_ftw_H1_V_preg_reg_n_0_[15] ,\inputs_ftw_H1_V_preg_reg_n_0_[14] ,\inputs_ftw_H1_V_preg_reg_n_0_[13] ,\inputs_ftw_H1_V_preg_reg_n_0_[12] ,\inputs_ftw_H1_V_preg_reg_n_0_[11] ,\inputs_ftw_H1_V_preg_reg_n_0_[10] ,\inputs_ftw_H1_V_preg_reg_n_0_[9] ,\inputs_ftw_H1_V_preg_reg_n_0_[8] ,\inputs_ftw_H1_V_preg_reg_n_0_[7] ,\inputs_ftw_H1_V_preg_reg_n_0_[6] ,\inputs_ftw_H1_V_preg_reg_n_0_[5] ,\inputs_ftw_H1_V_preg_reg_n_0_[4] ,\inputs_ftw_H1_V_preg_reg_n_0_[3] ,\inputs_ftw_H1_V_preg_reg_n_0_[2] ,\inputs_ftw_H1_V_preg_reg_n_0_[1] ,\inputs_ftw_H1_V_preg_reg_n_0_[0] }),
        .inputs_ftw_H1_on_V_ap_vld_preg(inputs_ftw_H1_on_V_ap_vld_preg),
        .inputs_offset_H1_V_ap_vld_preg(inputs_offset_H1_V_ap_vld_preg),
        .inputs_rate_V_ap_vld_preg(inputs_rate_V_ap_vld_preg),
        .\p_Val2_2_reg_418_reg[31] (quot),
        .\quot_reg[31] (dividend_tmp),
        .start(start),
        .start0_reg(RFNCO_Divider_HLSbkb_U1_n_2));
  VCC VCC
       (.P(\<const1> ));
  VCC VCC_1
       (.P(VCC_2));
  LUT3 #(
    .INIT(8'hAE)) 
    \ap_CS_fsm[0]_i_1 
       (.I0(ap_done),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(ap_start),
        .O(ap_NS_fsm[0]));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT5 #(
    .INIT(32'hF8888888)) 
    \ap_CS_fsm[1]_i_1 
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .I2(\ap_CS_fsm[1]_i_2_n_0 ),
        .I3(\ap_CS_fsm[1]_i_3_n_0 ),
        .I4(\ap_CS_fsm[1]_i_4_n_0 ),
        .O(ap_NS_fsm[1]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_10 
       (.I0(\ap_CS_fsm_reg_n_0_[44] ),
        .I1(\ap_CS_fsm_reg_n_0_[45] ),
        .I2(\ap_CS_fsm_reg_n_0_[42] ),
        .I3(\ap_CS_fsm_reg_n_0_[43] ),
        .I4(\ap_CS_fsm_reg_n_0_[47] ),
        .I5(\ap_CS_fsm_reg_n_0_[46] ),
        .O(\ap_CS_fsm[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_11 
       (.I0(\ap_CS_fsm_reg_n_0_[14] ),
        .I1(\ap_CS_fsm_reg_n_0_[15] ),
        .I2(\ap_CS_fsm_reg_n_0_[12] ),
        .I3(\ap_CS_fsm_reg_n_0_[13] ),
        .I4(\ap_CS_fsm_reg_n_0_[17] ),
        .I5(\ap_CS_fsm_reg_n_0_[16] ),
        .O(\ap_CS_fsm[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_12 
       (.I0(\ap_CS_fsm_reg_n_0_[8] ),
        .I1(\ap_CS_fsm_reg_n_0_[9] ),
        .I2(\ap_CS_fsm_reg_n_0_[6] ),
        .I3(\ap_CS_fsm_reg_n_0_[7] ),
        .I4(\ap_CS_fsm_reg_n_0_[11] ),
        .I5(\ap_CS_fsm_reg_n_0_[10] ),
        .O(\ap_CS_fsm[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \ap_CS_fsm[1]_i_13 
       (.I0(\ap_CS_fsm_reg_n_0_[5] ),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(\ap_CS_fsm_reg_n_0_[4] ),
        .I3(\ap_CS_fsm_reg_n_0_[3] ),
        .I4(phase_H1_comp_V_ap_vld),
        .I5(RFNCO_Divider_HLSbkb_U1_n_2),
        .O(\ap_CS_fsm[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_14 
       (.I0(\ap_CS_fsm_reg_n_0_[32] ),
        .I1(\ap_CS_fsm_reg_n_0_[33] ),
        .I2(\ap_CS_fsm_reg_n_0_[30] ),
        .I3(\ap_CS_fsm_reg_n_0_[31] ),
        .I4(\ap_CS_fsm_reg_n_0_[35] ),
        .I5(\ap_CS_fsm_reg_n_0_[34] ),
        .O(\ap_CS_fsm[1]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_15 
       (.I0(\ap_CS_fsm_reg_n_0_[26] ),
        .I1(\ap_CS_fsm_reg_n_0_[27] ),
        .I2(\ap_CS_fsm_reg_n_0_[24] ),
        .I3(\ap_CS_fsm_reg_n_0_[25] ),
        .I4(\ap_CS_fsm_reg_n_0_[29] ),
        .I5(\ap_CS_fsm_reg_n_0_[28] ),
        .O(\ap_CS_fsm[1]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_16 
       (.I0(\ap_CS_fsm_reg_n_0_[20] ),
        .I1(\ap_CS_fsm_reg_n_0_[21] ),
        .I2(\ap_CS_fsm_reg_n_0_[18] ),
        .I3(\ap_CS_fsm_reg_n_0_[19] ),
        .I4(\ap_CS_fsm_reg_n_0_[23] ),
        .I5(\ap_CS_fsm_reg_n_0_[22] ),
        .O(\ap_CS_fsm[1]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \ap_CS_fsm[1]_i_2 
       (.I0(\ap_CS_fsm[1]_i_5_n_0 ),
        .I1(\ap_CS_fsm[1]_i_6_n_0 ),
        .I2(\ap_CS_fsm[1]_i_7_n_0 ),
        .I3(\ap_CS_fsm[1]_i_8_n_0 ),
        .I4(\ap_CS_fsm[1]_i_9_n_0 ),
        .I5(\ap_CS_fsm[1]_i_10_n_0 ),
        .O(\ap_CS_fsm[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \ap_CS_fsm[1]_i_3 
       (.I0(\ap_CS_fsm[1]_i_11_n_0 ),
        .I1(\ap_CS_fsm[1]_i_12_n_0 ),
        .I2(\ap_CS_fsm[1]_i_13_n_0 ),
        .I3(\ap_CS_fsm[1]_i_14_n_0 ),
        .I4(\ap_CS_fsm[1]_i_15_n_0 ),
        .I5(\ap_CS_fsm[1]_i_16_n_0 ),
        .O(\ap_CS_fsm[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_4 
       (.I0(tw_H1_V_ap_vld),
        .I1(ap_CS_fsm_state76),
        .I2(\ap_CS_fsm_reg_n_0_[72] ),
        .I3(ap_CS_fsm_state74),
        .I4(ap_done),
        .I5(ap_CS_fsm_state77),
        .O(\ap_CS_fsm[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_5 
       (.I0(\ap_CS_fsm_reg_n_0_[56] ),
        .I1(\ap_CS_fsm_reg_n_0_[57] ),
        .I2(\ap_CS_fsm_reg_n_0_[54] ),
        .I3(\ap_CS_fsm_reg_n_0_[55] ),
        .I4(\ap_CS_fsm_reg_n_0_[59] ),
        .I5(\ap_CS_fsm_reg_n_0_[58] ),
        .O(\ap_CS_fsm[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_6 
       (.I0(\ap_CS_fsm_reg_n_0_[50] ),
        .I1(\ap_CS_fsm_reg_n_0_[51] ),
        .I2(\ap_CS_fsm_reg_n_0_[48] ),
        .I3(\ap_CS_fsm_reg_n_0_[49] ),
        .I4(\ap_CS_fsm_reg_n_0_[53] ),
        .I5(\ap_CS_fsm_reg_n_0_[52] ),
        .O(\ap_CS_fsm[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_7 
       (.I0(\ap_CS_fsm_reg_n_0_[68] ),
        .I1(\ap_CS_fsm_reg_n_0_[69] ),
        .I2(\ap_CS_fsm_reg_n_0_[66] ),
        .I3(\ap_CS_fsm_reg_n_0_[67] ),
        .I4(\ap_CS_fsm_reg_n_0_[71] ),
        .I5(\ap_CS_fsm_reg_n_0_[70] ),
        .O(\ap_CS_fsm[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_8 
       (.I0(\ap_CS_fsm_reg_n_0_[62] ),
        .I1(\ap_CS_fsm_reg_n_0_[63] ),
        .I2(\ap_CS_fsm_reg_n_0_[60] ),
        .I3(\ap_CS_fsm_reg_n_0_[61] ),
        .I4(\ap_CS_fsm_reg_n_0_[65] ),
        .I5(\ap_CS_fsm_reg_n_0_[64] ),
        .O(\ap_CS_fsm[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ap_CS_fsm[1]_i_9 
       (.I0(\ap_CS_fsm_reg_n_0_[38] ),
        .I1(\ap_CS_fsm_reg_n_0_[39] ),
        .I2(\ap_CS_fsm_reg_n_0_[36] ),
        .I3(\ap_CS_fsm_reg_n_0_[37] ),
        .I4(\ap_CS_fsm_reg_n_0_[41] ),
        .I5(\ap_CS_fsm_reg_n_0_[40] ),
        .O(\ap_CS_fsm[1]_i_9_n_0 ));
  (* FSM_ENCODING = "none" *) 
  FDSE #(
    .INIT(1'b1)) 
    \ap_CS_fsm_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(ap_NS_fsm[0]),
        .Q(\ap_CS_fsm_reg_n_0_[0] ),
        .S(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[10] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[9] ),
        .Q(\ap_CS_fsm_reg_n_0_[10] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[11] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[10] ),
        .Q(\ap_CS_fsm_reg_n_0_[11] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[12] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[11] ),
        .Q(\ap_CS_fsm_reg_n_0_[12] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[13] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[12] ),
        .Q(\ap_CS_fsm_reg_n_0_[13] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[14] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[13] ),
        .Q(\ap_CS_fsm_reg_n_0_[14] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[15] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[14] ),
        .Q(\ap_CS_fsm_reg_n_0_[15] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[16] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[15] ),
        .Q(\ap_CS_fsm_reg_n_0_[16] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[17] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[16] ),
        .Q(\ap_CS_fsm_reg_n_0_[17] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[18] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[17] ),
        .Q(\ap_CS_fsm_reg_n_0_[18] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[19] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[18] ),
        .Q(\ap_CS_fsm_reg_n_0_[19] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[1] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(ap_NS_fsm[1]),
        .Q(ap_CS_fsm_state2),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[20] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[19] ),
        .Q(\ap_CS_fsm_reg_n_0_[20] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[21] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[20] ),
        .Q(\ap_CS_fsm_reg_n_0_[21] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[22] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[21] ),
        .Q(\ap_CS_fsm_reg_n_0_[22] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[23] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[22] ),
        .Q(\ap_CS_fsm_reg_n_0_[23] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[24] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[23] ),
        .Q(\ap_CS_fsm_reg_n_0_[24] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[25] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[24] ),
        .Q(\ap_CS_fsm_reg_n_0_[25] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[26] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[25] ),
        .Q(\ap_CS_fsm_reg_n_0_[26] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[27] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[26] ),
        .Q(\ap_CS_fsm_reg_n_0_[27] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[28] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[27] ),
        .Q(\ap_CS_fsm_reg_n_0_[28] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[29] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[28] ),
        .Q(\ap_CS_fsm_reg_n_0_[29] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[2] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(start),
        .Q(phase_H1_comp_V_ap_vld),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[30] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[29] ),
        .Q(\ap_CS_fsm_reg_n_0_[30] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[31] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[30] ),
        .Q(\ap_CS_fsm_reg_n_0_[31] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[32] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[31] ),
        .Q(\ap_CS_fsm_reg_n_0_[32] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[33] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[32] ),
        .Q(\ap_CS_fsm_reg_n_0_[33] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[34] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[33] ),
        .Q(\ap_CS_fsm_reg_n_0_[34] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[35] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[34] ),
        .Q(\ap_CS_fsm_reg_n_0_[35] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[36] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[35] ),
        .Q(\ap_CS_fsm_reg_n_0_[36] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[37] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[36] ),
        .Q(\ap_CS_fsm_reg_n_0_[37] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[38] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[37] ),
        .Q(\ap_CS_fsm_reg_n_0_[38] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[39] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[38] ),
        .Q(\ap_CS_fsm_reg_n_0_[39] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[3] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(phase_H1_comp_V_ap_vld),
        .Q(\ap_CS_fsm_reg_n_0_[3] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[40] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[39] ),
        .Q(\ap_CS_fsm_reg_n_0_[40] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[41] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[40] ),
        .Q(\ap_CS_fsm_reg_n_0_[41] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[42] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[41] ),
        .Q(\ap_CS_fsm_reg_n_0_[42] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[43] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[42] ),
        .Q(\ap_CS_fsm_reg_n_0_[43] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[44] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[43] ),
        .Q(\ap_CS_fsm_reg_n_0_[44] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[45] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[44] ),
        .Q(\ap_CS_fsm_reg_n_0_[45] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[46] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[45] ),
        .Q(\ap_CS_fsm_reg_n_0_[46] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[47] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[46] ),
        .Q(\ap_CS_fsm_reg_n_0_[47] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[48] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[47] ),
        .Q(\ap_CS_fsm_reg_n_0_[48] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[49] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[48] ),
        .Q(\ap_CS_fsm_reg_n_0_[49] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[4] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[3] ),
        .Q(\ap_CS_fsm_reg_n_0_[4] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[50] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[49] ),
        .Q(\ap_CS_fsm_reg_n_0_[50] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[51] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[50] ),
        .Q(\ap_CS_fsm_reg_n_0_[51] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[52] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[51] ),
        .Q(\ap_CS_fsm_reg_n_0_[52] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[53] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[52] ),
        .Q(\ap_CS_fsm_reg_n_0_[53] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[54] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[53] ),
        .Q(\ap_CS_fsm_reg_n_0_[54] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[55] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[54] ),
        .Q(\ap_CS_fsm_reg_n_0_[55] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[56] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[55] ),
        .Q(\ap_CS_fsm_reg_n_0_[56] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[57] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[56] ),
        .Q(\ap_CS_fsm_reg_n_0_[57] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[58] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[57] ),
        .Q(\ap_CS_fsm_reg_n_0_[58] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[59] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[58] ),
        .Q(\ap_CS_fsm_reg_n_0_[59] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[5] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[4] ),
        .Q(\ap_CS_fsm_reg_n_0_[5] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[60] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[59] ),
        .Q(\ap_CS_fsm_reg_n_0_[60] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[61] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[60] ),
        .Q(\ap_CS_fsm_reg_n_0_[61] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[62] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[61] ),
        .Q(\ap_CS_fsm_reg_n_0_[62] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[63] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[62] ),
        .Q(\ap_CS_fsm_reg_n_0_[63] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[64] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[63] ),
        .Q(\ap_CS_fsm_reg_n_0_[64] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[65] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[64] ),
        .Q(\ap_CS_fsm_reg_n_0_[65] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[66] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[65] ),
        .Q(\ap_CS_fsm_reg_n_0_[66] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[67] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[66] ),
        .Q(\ap_CS_fsm_reg_n_0_[67] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[68] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[67] ),
        .Q(\ap_CS_fsm_reg_n_0_[68] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[69] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[68] ),
        .Q(\ap_CS_fsm_reg_n_0_[69] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[6] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[5] ),
        .Q(\ap_CS_fsm_reg_n_0_[6] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[70] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[69] ),
        .Q(\ap_CS_fsm_reg_n_0_[70] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[71] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[70] ),
        .Q(\ap_CS_fsm_reg_n_0_[71] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[72] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[71] ),
        .Q(\ap_CS_fsm_reg_n_0_[72] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[73] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[72] ),
        .Q(ap_CS_fsm_state74),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[74] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(ap_CS_fsm_state74),
        .Q(tw_H1_V_ap_vld),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[75] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(tw_H1_V_ap_vld),
        .Q(ap_CS_fsm_state76),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[76] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(ap_CS_fsm_state76),
        .Q(ap_CS_fsm_state77),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[77] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(ap_CS_fsm_state77),
        .Q(ap_done),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[7] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[6] ),
        .Q(\ap_CS_fsm_reg_n_0_[7] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[8] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[7] ),
        .Q(\ap_CS_fsm_reg_n_0_[8] ),
        .R(ap_rst));
  (* FSM_ENCODING = "none" *) 
  FDRE #(
    .INIT(1'b0)) 
    \ap_CS_fsm_reg[9] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_CS_fsm_reg_n_0_[8] ),
        .Q(\ap_CS_fsm_reg_n_0_[9] ),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT2 #(
    .INIT(4'h2)) 
    ap_idle_INST_0
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .O(ap_idle));
  LUT5 #(
    .INIT(32'h8AFF8A8A)) 
    inputs_delay_comp_V_ap_vld_preg_i_1
       (.I0(inputs_delay_comp_V_ap_vld),
        .I1(ap_start),
        .I2(\ap_CS_fsm_reg_n_0_[0] ),
        .I3(ap_done),
        .I4(inputs_delay_comp_V_ap_vld_preg),
        .O(inputs_delay_comp_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_delay_comp_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_delay_comp_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_delay_comp_V_ap_vld_preg),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'hD0)) 
    \inputs_delay_comp_V_preg[31]_i_1 
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .I2(inputs_delay_comp_V_ap_vld),
        .O(inputs_delay_comp_V_ap_vld_preg0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[0]),
        .Q(inputs_delay_comp_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[10]),
        .Q(inputs_delay_comp_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[11]),
        .Q(inputs_delay_comp_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[12]),
        .Q(inputs_delay_comp_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[13]),
        .Q(inputs_delay_comp_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[14]),
        .Q(inputs_delay_comp_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[15]),
        .Q(inputs_delay_comp_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[16]),
        .Q(inputs_delay_comp_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[17]),
        .Q(inputs_delay_comp_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[18]),
        .Q(inputs_delay_comp_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[19]),
        .Q(inputs_delay_comp_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[1]),
        .Q(inputs_delay_comp_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[20]),
        .Q(inputs_delay_comp_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[21]),
        .Q(inputs_delay_comp_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[22]),
        .Q(inputs_delay_comp_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[23]),
        .Q(inputs_delay_comp_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[24]),
        .Q(inputs_delay_comp_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[25]),
        .Q(inputs_delay_comp_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[26]),
        .Q(inputs_delay_comp_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[27]),
        .Q(inputs_delay_comp_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[28]),
        .Q(inputs_delay_comp_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[29]),
        .Q(inputs_delay_comp_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[2]),
        .Q(inputs_delay_comp_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[30]),
        .Q(inputs_delay_comp_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[31]),
        .Q(inputs_delay_comp_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[3]),
        .Q(inputs_delay_comp_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[4]),
        .Q(inputs_delay_comp_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[5]),
        .Q(inputs_delay_comp_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[6]),
        .Q(inputs_delay_comp_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[7]),
        .Q(inputs_delay_comp_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[8]),
        .Q(inputs_delay_comp_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delay_comp_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_delay_comp_V_ap_vld_preg0),
        .D(inputs_delay_comp_V[9]),
        .Q(inputs_delay_comp_V_preg[9]),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h8AFF8A8A)) 
    inputs_enable_FSK_ap_vld_preg_i_1
       (.I0(inputs_enable_FSK_ap_vld),
        .I1(ap_start),
        .I2(\ap_CS_fsm_reg_n_0_[0] ),
        .I3(ap_done),
        .I4(inputs_enable_FSK_ap_vld_preg),
        .O(inputs_enable_FSK_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_enable_FSK_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_enable_FSK_ap_vld_preg_i_1_n_0),
        .Q(inputs_enable_FSK_ap_vld_preg),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'hAEFFA200)) 
    \inputs_enable_FSK_preg[0]_i_1 
       (.I0(inputs_enable_FSK),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(ap_start),
        .I3(inputs_enable_FSK_ap_vld),
        .I4(inputs_enable_FSK_preg),
        .O(\inputs_enable_FSK_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_enable_FSK_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_enable_FSK_preg[0]_i_1_n_0 ),
        .Q(inputs_enable_FSK_preg),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h8AFF8A8A)) 
    inputs_ftw_H1_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_H1_V_ap_vld),
        .I1(ap_start),
        .I2(\ap_CS_fsm_reg_n_0_[0] ),
        .I3(ap_done),
        .I4(inputs_ftw_H1_V_ap_vld_preg),
        .O(inputs_ftw_H1_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_H1_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_H1_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_H1_V_ap_vld_preg),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'hD0)) 
    \inputs_ftw_H1_V_preg[47]_i_1 
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .I2(inputs_ftw_H1_V_ap_vld),
        .O(inputs_ftw_H1_V_ap_vld_preg0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[0]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[10]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[11]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[12]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[13]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[14]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[15]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[16]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[17]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[17] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[18]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[18] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[19]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[19] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[1]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[20]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[20] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[21]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[21] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[22]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[22] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[23]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[23] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[24]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[24] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[25]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[25] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[26]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[26] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[27]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[27] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[28]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[28] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[29]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[29] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[2]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[30]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[30] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[31]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[31] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[32]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[32] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[33]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[33] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[34]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[34] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[35]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[35] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[36]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[36] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[37]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[37] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[38]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[38] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[39]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[39] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[3]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[40]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[40] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[41]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[41] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[42]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[42] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[43]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[43] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[44]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[44] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[45]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[45] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[46]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[46] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[47]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[47] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[4]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[5]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[6]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[7]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[8]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld_preg0),
        .D(inputs_ftw_H1_V[9]),
        .Q(\inputs_ftw_H1_V_preg_reg_n_0_[9] ),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h8AFF8A8A)) 
    inputs_ftw_H1_on_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_H1_on_V_ap_vld),
        .I1(ap_start),
        .I2(\ap_CS_fsm_reg_n_0_[0] ),
        .I3(ap_done),
        .I4(inputs_ftw_H1_on_V_ap_vld_preg),
        .O(inputs_ftw_H1_on_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_H1_on_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_H1_on_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_H1_on_V_ap_vld_preg),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'hD0)) 
    \inputs_ftw_H1_on_V_preg[47]_i_1 
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .I2(inputs_ftw_H1_on_V_ap_vld),
        .O(inputs_ftw_H1_on_V_ap_vld_preg0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[0]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[10]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[11]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[12]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[13]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[14]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[15]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[16]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[17]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[17] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[18]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[18] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[19]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[19] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[1]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[20]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[20] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[21]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[21] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[22]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[22] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[23]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[23] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[24]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[24] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[25]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[25] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[26]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[26] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[27]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[27] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[28]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[28] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[29]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[29] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[2]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[30]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[30] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[31]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[31] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[32]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[32] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[33]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[33] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[34]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[34] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[35]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[35] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[36]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[36] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[37]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[37] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[38]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[38] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[39]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[39] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[3]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[40]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[40] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[41]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[41] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[42]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[42] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[43]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[43] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[44]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[44] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[45]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[45] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[46]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[46] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[47]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[47] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[4]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[5]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[6]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[7]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[8]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld_preg0),
        .D(inputs_ftw_H1_on_V[9]),
        .Q(\inputs_ftw_H1_on_V_preg_reg_n_0_[9] ),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h8AFF8A8A)) 
    inputs_offset_H1_V_ap_vld_preg_i_1
       (.I0(inputs_offset_H1_V_ap_vld),
        .I1(ap_start),
        .I2(\ap_CS_fsm_reg_n_0_[0] ),
        .I3(ap_done),
        .I4(inputs_offset_H1_V_ap_vld_preg),
        .O(inputs_offset_H1_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_offset_H1_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_offset_H1_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_offset_H1_V_ap_vld_preg),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h8AFF8A8A)) 
    inputs_rate_V_ap_vld_preg_i_1
       (.I0(inputs_rate_V_ap_vld),
        .I1(ap_start),
        .I2(\ap_CS_fsm_reg_n_0_[0] ),
        .I3(ap_done),
        .I4(inputs_rate_V_ap_vld_preg),
        .O(inputs_rate_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_rate_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_rate_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_rate_V_ap_vld_preg),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'hAEFFA200)) 
    \inputs_rate_V_preg[0]_i_1 
       (.I0(inputs_rate_V[0]),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(ap_start),
        .I3(inputs_rate_V_ap_vld),
        .I4(inputs_rate_V_preg[0]),
        .O(\inputs_rate_V_preg[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAEFFA200)) 
    \inputs_rate_V_preg[1]_i_1 
       (.I0(inputs_rate_V[1]),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(ap_start),
        .I3(inputs_rate_V_ap_vld),
        .I4(inputs_rate_V_preg[1]),
        .O(\inputs_rate_V_preg[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAEFFA200)) 
    \inputs_rate_V_preg[2]_i_1 
       (.I0(inputs_rate_V[2]),
        .I1(\ap_CS_fsm_reg_n_0_[0] ),
        .I2(ap_start),
        .I3(inputs_rate_V_ap_vld),
        .I4(inputs_rate_V_preg[2]),
        .O(\inputs_rate_V_preg[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_rate_V_preg[0]_i_1_n_0 ),
        .Q(inputs_rate_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_rate_V_preg[1]_i_1_n_0 ),
        .Q(inputs_rate_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_rate_V_preg[2]_i_1_n_0 ),
        .Q(inputs_rate_V_preg[2]),
        .R(ap_rst));
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[0]_INST_0 
       (.I0(tmp_s_reg_434_reg[0]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [0]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[10]_INST_0 
       (.I0(tmp_s_reg_434_reg[10]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [10]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[11]_INST_0 
       (.I0(tmp_s_reg_434_reg[11]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [11]));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[12]_INST_0 
       (.I0(tmp_s_reg_434_reg[12]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [12]));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[13]_INST_0 
       (.I0(tmp_s_reg_434_reg[13]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [13]));
  CARRY4 \offset_H1_comp_V[13]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[9]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[13]_INST_0_i_1_n_0 ,\offset_H1_comp_V[13]_INST_0_i_1_n_1 ,\offset_H1_comp_V[13]_INST_0_i_1_n_2 ,\offset_H1_comp_V[13]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[13]_INST_0_i_2_n_0 ,\offset_H1_comp_V[13]_INST_0_i_3_n_0 ,\offset_H1_comp_V[13]_INST_0_i_4_n_0 ,\offset_H1_comp_V[13]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[13:10]),
        .S({\offset_H1_comp_V[13]_INST_0_i_6_n_0 ,\offset_H1_comp_V[13]_INST_0_i_7_n_0 ,\offset_H1_comp_V[13]_INST_0_i_8_n_0 ,\offset_H1_comp_V[13]_INST_0_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[13]_INST_0_i_2 
       (.I0(p_0_out__6_n_72),
        .I1(p_0_out__4_n_89),
        .I2(\p_0_out[16]__1_n_0 ),
        .O(\offset_H1_comp_V[13]_INST_0_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[13]_INST_0_i_3 
       (.I0(p_0_out__6_n_73),
        .I1(p_0_out__4_n_90),
        .I2(\p_0_out[15]__1_n_0 ),
        .O(\offset_H1_comp_V[13]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[13]_INST_0_i_4 
       (.I0(p_0_out__6_n_74),
        .I1(p_0_out__4_n_91),
        .I2(\p_0_out[14]__1_n_0 ),
        .O(\offset_H1_comp_V[13]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[13]_INST_0_i_5 
       (.I0(p_0_out__6_n_75),
        .I1(p_0_out__4_n_92),
        .I2(\p_0_out[13]__1_n_0 ),
        .O(\offset_H1_comp_V[13]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[13]_INST_0_i_6 
       (.I0(\p_0_out[16]__1_n_0 ),
        .I1(p_0_out__4_n_89),
        .I2(p_0_out__6_n_72),
        .I3(p_0_out__2_n_105),
        .I4(p_0_out__4_n_88),
        .I5(p_0_out__6_n_71),
        .O(\offset_H1_comp_V[13]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[13]_INST_0_i_7 
       (.I0(\p_0_out[15]__1_n_0 ),
        .I1(p_0_out__4_n_90),
        .I2(p_0_out__6_n_73),
        .I3(\p_0_out[16]__1_n_0 ),
        .I4(p_0_out__4_n_89),
        .I5(p_0_out__6_n_72),
        .O(\offset_H1_comp_V[13]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[13]_INST_0_i_8 
       (.I0(\p_0_out[14]__1_n_0 ),
        .I1(p_0_out__4_n_91),
        .I2(p_0_out__6_n_74),
        .I3(\p_0_out[15]__1_n_0 ),
        .I4(p_0_out__4_n_90),
        .I5(p_0_out__6_n_73),
        .O(\offset_H1_comp_V[13]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[13]_INST_0_i_9 
       (.I0(\p_0_out[13]__1_n_0 ),
        .I1(p_0_out__4_n_92),
        .I2(p_0_out__6_n_75),
        .I3(\p_0_out[14]__1_n_0 ),
        .I4(p_0_out__4_n_91),
        .I5(p_0_out__6_n_74),
        .O(\offset_H1_comp_V[13]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[14]_INST_0 
       (.I0(tmp_s_reg_434_reg[14]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [14]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[15]_INST_0 
       (.I0(tmp_s_reg_434_reg[15]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [15]));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[16]_INST_0 
       (.I0(tmp_s_reg_434_reg[16]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [16]));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[17]_INST_0 
       (.I0(tmp_s_reg_434_reg[17]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [17]));
  CARRY4 \offset_H1_comp_V[17]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[13]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[17]_INST_0_i_1_n_0 ,\offset_H1_comp_V[17]_INST_0_i_1_n_1 ,\offset_H1_comp_V[17]_INST_0_i_1_n_2 ,\offset_H1_comp_V[17]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[17]_INST_0_i_2_n_0 ,\offset_H1_comp_V[17]_INST_0_i_3_n_0 ,\offset_H1_comp_V[17]_INST_0_i_4_n_0 ,\offset_H1_comp_V[17]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[17:14]),
        .S({\offset_H1_comp_V[17]_INST_0_i_6_n_0 ,\offset_H1_comp_V[17]_INST_0_i_7_n_0 ,\offset_H1_comp_V[17]_INST_0_i_8_n_0 ,\offset_H1_comp_V[17]_INST_0_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[17]_INST_0_i_2 
       (.I0(p_0_out__6_n_68),
        .I1(p_0_out__4_n_85),
        .I2(p_0_out__2_n_102),
        .O(\offset_H1_comp_V[17]_INST_0_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[17]_INST_0_i_3 
       (.I0(p_0_out__6_n_69),
        .I1(p_0_out__4_n_86),
        .I2(p_0_out__2_n_103),
        .O(\offset_H1_comp_V[17]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[17]_INST_0_i_4 
       (.I0(p_0_out__6_n_70),
        .I1(p_0_out__4_n_87),
        .I2(p_0_out__2_n_104),
        .O(\offset_H1_comp_V[17]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[17]_INST_0_i_5 
       (.I0(p_0_out__6_n_71),
        .I1(p_0_out__4_n_88),
        .I2(p_0_out__2_n_105),
        .O(\offset_H1_comp_V[17]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[17]_INST_0_i_6 
       (.I0(p_0_out__2_n_102),
        .I1(p_0_out__4_n_85),
        .I2(p_0_out__6_n_68),
        .I3(p_0_out__2_n_101),
        .I4(p_0_out__4_n_84),
        .I5(p_0_out__6_n_67),
        .O(\offset_H1_comp_V[17]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[17]_INST_0_i_7 
       (.I0(p_0_out__2_n_103),
        .I1(p_0_out__4_n_86),
        .I2(p_0_out__6_n_69),
        .I3(p_0_out__2_n_102),
        .I4(p_0_out__4_n_85),
        .I5(p_0_out__6_n_68),
        .O(\offset_H1_comp_V[17]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[17]_INST_0_i_8 
       (.I0(p_0_out__2_n_104),
        .I1(p_0_out__4_n_87),
        .I2(p_0_out__6_n_70),
        .I3(p_0_out__2_n_103),
        .I4(p_0_out__4_n_86),
        .I5(p_0_out__6_n_69),
        .O(\offset_H1_comp_V[17]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[17]_INST_0_i_9 
       (.I0(p_0_out__2_n_105),
        .I1(p_0_out__4_n_88),
        .I2(p_0_out__6_n_71),
        .I3(p_0_out__2_n_104),
        .I4(p_0_out__4_n_87),
        .I5(p_0_out__6_n_70),
        .O(\offset_H1_comp_V[17]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[18]_INST_0 
       (.I0(tmp_s_reg_434_reg[18]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [18]));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[19]_INST_0 
       (.I0(tmp_s_reg_434_reg[19]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [19]));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[1]_INST_0 
       (.I0(tmp_s_reg_434_reg[1]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [1]));
  CARRY4 \offset_H1_comp_V[1]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[1]_INST_0_i_2_n_0 ),
        .CO({\offset_H1_comp_V[1]_INST_0_i_1_n_0 ,\offset_H1_comp_V[1]_INST_0_i_1_n_1 ,\offset_H1_comp_V[1]_INST_0_i_1_n_2 ,\offset_H1_comp_V[1]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[1]_INST_0_i_3_n_0 ,\offset_H1_comp_V[1]_INST_0_i_4_n_0 ,\offset_H1_comp_V[1]_INST_0_i_5_n_0 ,\offset_H1_comp_V[1]_INST_0_i_6_n_0 }),
        .O({tmp_s_reg_434_reg[1:0],\NLW_offset_H1_comp_V[1]_INST_0_i_1_O_UNCONNECTED [1:0]}),
        .S({\offset_H1_comp_V[1]_INST_0_i_7_n_0 ,\offset_H1_comp_V[1]_INST_0_i_8_n_0 ,\offset_H1_comp_V[1]_INST_0_i_9_n_0 ,\offset_H1_comp_V[1]_INST_0_i_10_n_0 }));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[1]_INST_0_i_10 
       (.I0(p_0_out__6_n_87),
        .I1(\p_0_out[1]__1_n_0 ),
        .I2(p_0_out__4_n_104),
        .I3(\p_0_out[2]__1_n_0 ),
        .I4(p_0_out__4_n_103),
        .I5(p_0_out__6_n_86),
        .O(\offset_H1_comp_V[1]_INST_0_i_10_n_0 ));
  CARRY4 \offset_H1_comp_V[1]_INST_0_i_11 
       (.CI(\offset_H1_comp_V[1]_INST_0_i_17_n_0 ),
        .CO({\offset_H1_comp_V[1]_INST_0_i_11_n_0 ,\offset_H1_comp_V[1]_INST_0_i_11_n_1 ,\offset_H1_comp_V[1]_INST_0_i_11_n_2 ,\offset_H1_comp_V[1]_INST_0_i_11_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__6_n_91,p_0_out__6_n_92,p_0_out__6_n_93,p_0_out__6_n_94}),
        .S({\offset_H1_comp_V[1]_INST_0_i_18_n_0 ,\offset_H1_comp_V[1]_INST_0_i_19_n_0 ,\offset_H1_comp_V[1]_INST_0_i_20_n_0 ,\offset_H1_comp_V[1]_INST_0_i_21_n_0 }));
  LUT3 #(
    .INIT(8'h96)) 
    \offset_H1_comp_V[1]_INST_0_i_12 
       (.I0(p_0_out__6_n_87),
        .I1(\p_0_out[1]__1_n_0 ),
        .I2(p_0_out__4_n_104),
        .O(\offset_H1_comp_V[1]_INST_0_i_12_n_0 ));
  LUT5 #(
    .INIT(32'h69969696)) 
    \offset_H1_comp_V[1]_INST_0_i_13 
       (.I0(p_0_out__4_n_104),
        .I1(\p_0_out[1]__1_n_0 ),
        .I2(p_0_out__6_n_87),
        .I3(p_0_out__4_n_105),
        .I4(\p_0_out[0]__1_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_13_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \offset_H1_comp_V[1]_INST_0_i_14 
       (.I0(\p_0_out[0]__1_n_0 ),
        .I1(p_0_out__4_n_105),
        .I2(p_0_out__6_n_88),
        .O(\offset_H1_comp_V[1]_INST_0_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_15 
       (.I0(p_0_out__6_n_89),
        .I1(\p_0_out[16]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_16 
       (.I0(p_0_out__6_n_90),
        .I1(\p_0_out[15]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_16_n_0 ));
  CARRY4 \offset_H1_comp_V[1]_INST_0_i_17 
       (.CI(\offset_H1_comp_V[1]_INST_0_i_22_n_0 ),
        .CO({\offset_H1_comp_V[1]_INST_0_i_17_n_0 ,\offset_H1_comp_V[1]_INST_0_i_17_n_1 ,\offset_H1_comp_V[1]_INST_0_i_17_n_2 ,\offset_H1_comp_V[1]_INST_0_i_17_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__6_n_95,p_0_out__6_n_96,p_0_out__6_n_97,p_0_out__6_n_98}),
        .S({\offset_H1_comp_V[1]_INST_0_i_23_n_0 ,\offset_H1_comp_V[1]_INST_0_i_24_n_0 ,\offset_H1_comp_V[1]_INST_0_i_25_n_0 ,\offset_H1_comp_V[1]_INST_0_i_26_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_18 
       (.I0(p_0_out__6_n_91),
        .I1(\p_0_out[14]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_18_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_19 
       (.I0(p_0_out__6_n_92),
        .I1(\p_0_out[13]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_19_n_0 ));
  CARRY4 \offset_H1_comp_V[1]_INST_0_i_2 
       (.CI(\offset_H1_comp_V[1]_INST_0_i_11_n_0 ),
        .CO({\offset_H1_comp_V[1]_INST_0_i_2_n_0 ,\offset_H1_comp_V[1]_INST_0_i_2_n_1 ,\offset_H1_comp_V[1]_INST_0_i_2_n_2 ,\offset_H1_comp_V[1]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[1]_INST_0_i_12_n_0 ,p_0_out__6_n_88,p_0_out__6_n_89,p_0_out__6_n_90}),
        .S({\offset_H1_comp_V[1]_INST_0_i_13_n_0 ,\offset_H1_comp_V[1]_INST_0_i_14_n_0 ,\offset_H1_comp_V[1]_INST_0_i_15_n_0 ,\offset_H1_comp_V[1]_INST_0_i_16_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_20 
       (.I0(p_0_out__6_n_93),
        .I1(\p_0_out[12]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_20_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_21 
       (.I0(p_0_out__6_n_94),
        .I1(\p_0_out[11]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_21_n_0 ));
  CARRY4 \offset_H1_comp_V[1]_INST_0_i_22 
       (.CI(\offset_H1_comp_V[1]_INST_0_i_27_n_0 ),
        .CO({\offset_H1_comp_V[1]_INST_0_i_22_n_0 ,\offset_H1_comp_V[1]_INST_0_i_22_n_1 ,\offset_H1_comp_V[1]_INST_0_i_22_n_2 ,\offset_H1_comp_V[1]_INST_0_i_22_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__6_n_99,p_0_out__6_n_100,p_0_out__6_n_101,p_0_out__6_n_102}),
        .S({\offset_H1_comp_V[1]_INST_0_i_28_n_0 ,\offset_H1_comp_V[1]_INST_0_i_29_n_0 ,\offset_H1_comp_V[1]_INST_0_i_30_n_0 ,\offset_H1_comp_V[1]_INST_0_i_31_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_23 
       (.I0(p_0_out__6_n_95),
        .I1(\p_0_out[10]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_23_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_24 
       (.I0(p_0_out__6_n_96),
        .I1(\p_0_out[9]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_24_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_25 
       (.I0(p_0_out__6_n_97),
        .I1(\p_0_out[8]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_25_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_26 
       (.I0(p_0_out__6_n_98),
        .I1(\p_0_out[7]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_26_n_0 ));
  CARRY4 \offset_H1_comp_V[1]_INST_0_i_27 
       (.CI(\<const0> ),
        .CO({\offset_H1_comp_V[1]_INST_0_i_27_n_0 ,\offset_H1_comp_V[1]_INST_0_i_27_n_1 ,\offset_H1_comp_V[1]_INST_0_i_27_n_2 ,\offset_H1_comp_V[1]_INST_0_i_27_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__6_n_103,p_0_out__6_n_104,p_0_out__6_n_105,\<const0> }),
        .S({\offset_H1_comp_V[1]_INST_0_i_32_n_0 ,\offset_H1_comp_V[1]_INST_0_i_33_n_0 ,\offset_H1_comp_V[1]_INST_0_i_34_n_0 ,\p_0_out[16]__3_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_28 
       (.I0(p_0_out__6_n_99),
        .I1(\p_0_out[6]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_28_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_29 
       (.I0(p_0_out__6_n_100),
        .I1(\p_0_out[5]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_29_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[1]_INST_0_i_3 
       (.I0(p_0_out__6_n_84),
        .I1(p_0_out__4_n_101),
        .I2(\p_0_out[4]__1_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_30 
       (.I0(p_0_out__6_n_101),
        .I1(\p_0_out[4]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_30_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_31 
       (.I0(p_0_out__6_n_102),
        .I1(\p_0_out[3]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_31_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_32 
       (.I0(p_0_out__6_n_103),
        .I1(\p_0_out[2]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_32_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_33 
       (.I0(p_0_out__6_n_104),
        .I1(\p_0_out[1]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_33_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \offset_H1_comp_V[1]_INST_0_i_34 
       (.I0(p_0_out__6_n_105),
        .I1(\p_0_out[0]__2_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_34_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[1]_INST_0_i_4 
       (.I0(p_0_out__6_n_85),
        .I1(p_0_out__4_n_102),
        .I2(\p_0_out[3]__1_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[1]_INST_0_i_5 
       (.I0(p_0_out__6_n_86),
        .I1(p_0_out__4_n_103),
        .I2(\p_0_out[2]__1_n_0 ),
        .O(\offset_H1_comp_V[1]_INST_0_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[1]_INST_0_i_6 
       (.I0(p_0_out__4_n_104),
        .I1(\p_0_out[1]__1_n_0 ),
        .I2(p_0_out__6_n_87),
        .O(\offset_H1_comp_V[1]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[1]_INST_0_i_7 
       (.I0(\p_0_out[4]__1_n_0 ),
        .I1(p_0_out__4_n_101),
        .I2(p_0_out__6_n_84),
        .I3(\p_0_out[5]__1_n_0 ),
        .I4(p_0_out__4_n_100),
        .I5(p_0_out__6_n_83),
        .O(\offset_H1_comp_V[1]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[1]_INST_0_i_8 
       (.I0(\p_0_out[3]__1_n_0 ),
        .I1(p_0_out__4_n_102),
        .I2(p_0_out__6_n_85),
        .I3(\p_0_out[4]__1_n_0 ),
        .I4(p_0_out__4_n_101),
        .I5(p_0_out__6_n_84),
        .O(\offset_H1_comp_V[1]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[1]_INST_0_i_9 
       (.I0(\p_0_out[2]__1_n_0 ),
        .I1(p_0_out__4_n_103),
        .I2(p_0_out__6_n_86),
        .I3(\p_0_out[3]__1_n_0 ),
        .I4(p_0_out__4_n_102),
        .I5(p_0_out__6_n_85),
        .O(\offset_H1_comp_V[1]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[20]_INST_0 
       (.I0(tmp_s_reg_434_reg[20]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [20]));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[21]_INST_0 
       (.I0(tmp_s_reg_434_reg[21]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [21]));
  CARRY4 \offset_H1_comp_V[21]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[17]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[21]_INST_0_i_1_n_0 ,\offset_H1_comp_V[21]_INST_0_i_1_n_1 ,\offset_H1_comp_V[21]_INST_0_i_1_n_2 ,\offset_H1_comp_V[21]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[21]_INST_0_i_2_n_0 ,\offset_H1_comp_V[21]_INST_0_i_3_n_0 ,\offset_H1_comp_V[21]_INST_0_i_4_n_0 ,\offset_H1_comp_V[21]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[21:18]),
        .S({\offset_H1_comp_V[21]_INST_0_i_6_n_0 ,\offset_H1_comp_V[21]_INST_0_i_7_n_0 ,\offset_H1_comp_V[21]_INST_0_i_8_n_0 ,\offset_H1_comp_V[21]_INST_0_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[21]_INST_0_i_2 
       (.I0(p_0_out__6_n_64),
        .I1(p_0_out__4_n_81),
        .I2(p_0_out__2_n_98),
        .O(\offset_H1_comp_V[21]_INST_0_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[21]_INST_0_i_3 
       (.I0(p_0_out__6_n_65),
        .I1(p_0_out__4_n_82),
        .I2(p_0_out__2_n_99),
        .O(\offset_H1_comp_V[21]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[21]_INST_0_i_4 
       (.I0(p_0_out__6_n_66),
        .I1(p_0_out__4_n_83),
        .I2(p_0_out__2_n_100),
        .O(\offset_H1_comp_V[21]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[21]_INST_0_i_5 
       (.I0(p_0_out__6_n_67),
        .I1(p_0_out__4_n_84),
        .I2(p_0_out__2_n_101),
        .O(\offset_H1_comp_V[21]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[21]_INST_0_i_6 
       (.I0(p_0_out__2_n_98),
        .I1(p_0_out__4_n_81),
        .I2(p_0_out__6_n_64),
        .I3(p_0_out__2_n_97),
        .I4(p_0_out__4_n_80),
        .I5(p_0_out__6_n_63),
        .O(\offset_H1_comp_V[21]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[21]_INST_0_i_7 
       (.I0(p_0_out__2_n_99),
        .I1(p_0_out__4_n_82),
        .I2(p_0_out__6_n_65),
        .I3(p_0_out__2_n_98),
        .I4(p_0_out__4_n_81),
        .I5(p_0_out__6_n_64),
        .O(\offset_H1_comp_V[21]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[21]_INST_0_i_8 
       (.I0(p_0_out__2_n_100),
        .I1(p_0_out__4_n_83),
        .I2(p_0_out__6_n_66),
        .I3(p_0_out__2_n_99),
        .I4(p_0_out__4_n_82),
        .I5(p_0_out__6_n_65),
        .O(\offset_H1_comp_V[21]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[21]_INST_0_i_9 
       (.I0(p_0_out__2_n_101),
        .I1(p_0_out__4_n_84),
        .I2(p_0_out__6_n_67),
        .I3(p_0_out__2_n_100),
        .I4(p_0_out__4_n_83),
        .I5(p_0_out__6_n_66),
        .O(\offset_H1_comp_V[21]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[22]_INST_0 
       (.I0(tmp_s_reg_434_reg[22]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [22]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[23]_INST_0 
       (.I0(tmp_s_reg_434_reg[23]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [23]));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[24]_INST_0 
       (.I0(tmp_s_reg_434_reg[24]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [24]));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[25]_INST_0 
       (.I0(tmp_s_reg_434_reg[25]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [25]));
  CARRY4 \offset_H1_comp_V[25]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[21]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[25]_INST_0_i_1_n_0 ,\offset_H1_comp_V[25]_INST_0_i_1_n_1 ,\offset_H1_comp_V[25]_INST_0_i_1_n_2 ,\offset_H1_comp_V[25]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[25]_INST_0_i_2_n_0 ,\offset_H1_comp_V[25]_INST_0_i_3_n_0 ,\offset_H1_comp_V[25]_INST_0_i_4_n_0 ,\offset_H1_comp_V[25]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[25:22]),
        .S({\offset_H1_comp_V[25]_INST_0_i_6_n_0 ,\offset_H1_comp_V[25]_INST_0_i_7_n_0 ,\offset_H1_comp_V[25]_INST_0_i_8_n_0 ,\offset_H1_comp_V[25]_INST_0_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[25]_INST_0_i_2 
       (.I0(p_0_out__6_n_60),
        .I1(p_0_out__4_n_77),
        .I2(p_0_out__2_n_94),
        .O(\offset_H1_comp_V[25]_INST_0_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[25]_INST_0_i_3 
       (.I0(p_0_out__6_n_61),
        .I1(p_0_out__4_n_78),
        .I2(p_0_out__2_n_95),
        .O(\offset_H1_comp_V[25]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[25]_INST_0_i_4 
       (.I0(p_0_out__6_n_62),
        .I1(p_0_out__4_n_79),
        .I2(p_0_out__2_n_96),
        .O(\offset_H1_comp_V[25]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[25]_INST_0_i_5 
       (.I0(p_0_out__6_n_63),
        .I1(p_0_out__4_n_80),
        .I2(p_0_out__2_n_97),
        .O(\offset_H1_comp_V[25]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[25]_INST_0_i_6 
       (.I0(p_0_out__2_n_94),
        .I1(p_0_out__4_n_77),
        .I2(p_0_out__6_n_60),
        .I3(p_0_out__2_n_93),
        .I4(p_0_out__4_n_76),
        .I5(p_0_out__6_n_59),
        .O(\offset_H1_comp_V[25]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[25]_INST_0_i_7 
       (.I0(p_0_out__2_n_95),
        .I1(p_0_out__4_n_78),
        .I2(p_0_out__6_n_61),
        .I3(p_0_out__2_n_94),
        .I4(p_0_out__4_n_77),
        .I5(p_0_out__6_n_60),
        .O(\offset_H1_comp_V[25]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[25]_INST_0_i_8 
       (.I0(p_0_out__2_n_96),
        .I1(p_0_out__4_n_79),
        .I2(p_0_out__6_n_62),
        .I3(p_0_out__2_n_95),
        .I4(p_0_out__4_n_78),
        .I5(p_0_out__6_n_61),
        .O(\offset_H1_comp_V[25]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[25]_INST_0_i_9 
       (.I0(p_0_out__2_n_97),
        .I1(p_0_out__4_n_80),
        .I2(p_0_out__6_n_63),
        .I3(p_0_out__2_n_96),
        .I4(p_0_out__4_n_79),
        .I5(p_0_out__6_n_62),
        .O(\offset_H1_comp_V[25]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[26]_INST_0 
       (.I0(tmp_s_reg_434_reg[26]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [26]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[27]_INST_0 
       (.I0(tmp_s_reg_434_reg[27]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [27]));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[28]_INST_0 
       (.I0(tmp_s_reg_434_reg[28]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [28]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[29]_INST_0 
       (.I0(tmp_s_reg_434_reg[29]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [29]));
  CARRY4 \offset_H1_comp_V[29]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[25]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[29]_INST_0_i_1_n_0 ,\offset_H1_comp_V[29]_INST_0_i_1_n_1 ,\offset_H1_comp_V[29]_INST_0_i_1_n_2 ,\offset_H1_comp_V[29]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[29]_INST_0_i_2_n_0 ,\offset_H1_comp_V[29]_INST_0_i_3_n_0 ,\offset_H1_comp_V[29]_INST_0_i_4_n_0 ,\offset_H1_comp_V[29]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[29:26]),
        .S({\offset_H1_comp_V[29]_INST_0_i_6_n_0 ,\offset_H1_comp_V[29]_INST_0_i_7_n_0 ,\offset_H1_comp_V[29]_INST_0_i_8_n_0 ,\offset_H1_comp_V[29]_INST_0_i_9_n_0 }));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[29]_INST_0_i_2 
       (.I0(p_0_out__2_n_90),
        .I1(p_0_out__4_n_73),
        .I2(p_0_out__4_n_74),
        .I3(p_0_out__2_n_91),
        .O(\offset_H1_comp_V[29]_INST_0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[29]_INST_0_i_3 
       (.I0(p_0_out__2_n_91),
        .I1(p_0_out__4_n_74),
        .I2(p_0_out__4_n_75),
        .I3(p_0_out__2_n_92),
        .O(\offset_H1_comp_V[29]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h09)) 
    \offset_H1_comp_V[29]_INST_0_i_4 
       (.I0(p_0_out__2_n_92),
        .I1(p_0_out__4_n_75),
        .I2(p_0_out__6_n_58),
        .O(\offset_H1_comp_V[29]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \offset_H1_comp_V[29]_INST_0_i_5 
       (.I0(p_0_out__6_n_58),
        .I1(p_0_out__4_n_75),
        .I2(p_0_out__2_n_92),
        .O(\offset_H1_comp_V[29]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[29]_INST_0_i_6 
       (.I0(p_0_out__2_n_91),
        .I1(p_0_out__4_n_74),
        .I2(p_0_out__2_n_89),
        .I3(p_0_out__4_n_72),
        .I4(p_0_out__4_n_73),
        .I5(p_0_out__2_n_90),
        .O(\offset_H1_comp_V[29]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[29]_INST_0_i_7 
       (.I0(p_0_out__2_n_92),
        .I1(p_0_out__4_n_75),
        .I2(p_0_out__2_n_90),
        .I3(p_0_out__4_n_73),
        .I4(p_0_out__4_n_74),
        .I5(p_0_out__2_n_91),
        .O(\offset_H1_comp_V[29]_INST_0_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h693C3C96)) 
    \offset_H1_comp_V[29]_INST_0_i_8 
       (.I0(p_0_out__6_n_58),
        .I1(p_0_out__2_n_91),
        .I2(p_0_out__4_n_74),
        .I3(p_0_out__4_n_75),
        .I4(p_0_out__2_n_92),
        .O(\offset_H1_comp_V[29]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h6969699669969696)) 
    \offset_H1_comp_V[29]_INST_0_i_9 
       (.I0(p_0_out__2_n_92),
        .I1(p_0_out__4_n_75),
        .I2(p_0_out__6_n_58),
        .I3(p_0_out__2_n_93),
        .I4(p_0_out__4_n_76),
        .I5(p_0_out__6_n_59),
        .O(\offset_H1_comp_V[29]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[2]_INST_0 
       (.I0(tmp_s_reg_434_reg[2]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [2]));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[30]_INST_0 
       (.I0(tmp_s_reg_434_reg[30]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [30]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[31]_INST_0 
       (.I0(tmp_s_reg_434_reg[31]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [31]));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[32]_INST_0 
       (.I0(tmp_s_reg_434_reg[32]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [32]));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[33]_INST_0 
       (.I0(tmp_s_reg_434_reg[33]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [33]));
  CARRY4 \offset_H1_comp_V[33]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[29]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[33]_INST_0_i_1_n_0 ,\offset_H1_comp_V[33]_INST_0_i_1_n_1 ,\offset_H1_comp_V[33]_INST_0_i_1_n_2 ,\offset_H1_comp_V[33]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[33]_INST_0_i_2_n_0 ,\offset_H1_comp_V[33]_INST_0_i_3_n_0 ,\offset_H1_comp_V[33]_INST_0_i_4_n_0 ,\offset_H1_comp_V[33]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[33:30]),
        .S({\offset_H1_comp_V[33]_INST_0_i_6_n_0 ,\offset_H1_comp_V[33]_INST_0_i_7_n_0 ,\offset_H1_comp_V[33]_INST_0_i_8_n_0 ,\offset_H1_comp_V[33]_INST_0_i_9_n_0 }));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[33]_INST_0_i_2 
       (.I0(p_0_out__2_n_86),
        .I1(p_0_out__4_n_69),
        .I2(p_0_out__4_n_70),
        .I3(p_0_out__2_n_87),
        .O(\offset_H1_comp_V[33]_INST_0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[33]_INST_0_i_3 
       (.I0(p_0_out__2_n_87),
        .I1(p_0_out__4_n_70),
        .I2(p_0_out__4_n_71),
        .I3(p_0_out__2_n_88),
        .O(\offset_H1_comp_V[33]_INST_0_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[33]_INST_0_i_4 
       (.I0(p_0_out__2_n_88),
        .I1(p_0_out__4_n_71),
        .I2(p_0_out__4_n_72),
        .I3(p_0_out__2_n_89),
        .O(\offset_H1_comp_V[33]_INST_0_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[33]_INST_0_i_5 
       (.I0(p_0_out__2_n_89),
        .I1(p_0_out__4_n_72),
        .I2(p_0_out__4_n_73),
        .I3(p_0_out__2_n_90),
        .O(\offset_H1_comp_V[33]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[33]_INST_0_i_6 
       (.I0(p_0_out__2_n_87),
        .I1(p_0_out__4_n_70),
        .I2(p_0_out__2_n_85),
        .I3(p_0_out__4_n_68),
        .I4(p_0_out__4_n_69),
        .I5(p_0_out__2_n_86),
        .O(\offset_H1_comp_V[33]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[33]_INST_0_i_7 
       (.I0(p_0_out__2_n_88),
        .I1(p_0_out__4_n_71),
        .I2(p_0_out__2_n_86),
        .I3(p_0_out__4_n_69),
        .I4(p_0_out__4_n_70),
        .I5(p_0_out__2_n_87),
        .O(\offset_H1_comp_V[33]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[33]_INST_0_i_8 
       (.I0(p_0_out__2_n_89),
        .I1(p_0_out__4_n_72),
        .I2(p_0_out__2_n_87),
        .I3(p_0_out__4_n_70),
        .I4(p_0_out__4_n_71),
        .I5(p_0_out__2_n_88),
        .O(\offset_H1_comp_V[33]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[33]_INST_0_i_9 
       (.I0(p_0_out__2_n_90),
        .I1(p_0_out__4_n_73),
        .I2(p_0_out__2_n_88),
        .I3(p_0_out__4_n_71),
        .I4(p_0_out__4_n_72),
        .I5(p_0_out__2_n_89),
        .O(\offset_H1_comp_V[33]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[34]_INST_0 
       (.I0(tmp_s_reg_434_reg[34]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [34]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[35]_INST_0 
       (.I0(tmp_s_reg_434_reg[35]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [35]));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[36]_INST_0 
       (.I0(tmp_s_reg_434_reg[36]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [36]));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[37]_INST_0 
       (.I0(tmp_s_reg_434_reg[37]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [37]));
  CARRY4 \offset_H1_comp_V[37]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[33]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[37]_INST_0_i_1_n_0 ,\offset_H1_comp_V[37]_INST_0_i_1_n_1 ,\offset_H1_comp_V[37]_INST_0_i_1_n_2 ,\offset_H1_comp_V[37]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[37]_INST_0_i_2_n_0 ,\offset_H1_comp_V[37]_INST_0_i_3_n_0 ,\offset_H1_comp_V[37]_INST_0_i_4_n_0 ,\offset_H1_comp_V[37]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[37:34]),
        .S({\offset_H1_comp_V[37]_INST_0_i_6_n_0 ,\offset_H1_comp_V[37]_INST_0_i_7_n_0 ,\offset_H1_comp_V[37]_INST_0_i_8_n_0 ,\offset_H1_comp_V[37]_INST_0_i_9_n_0 }));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[37]_INST_0_i_2 
       (.I0(p_0_out__2_n_82),
        .I1(p_0_out__4_n_65),
        .I2(p_0_out__4_n_66),
        .I3(p_0_out__2_n_83),
        .O(\offset_H1_comp_V[37]_INST_0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[37]_INST_0_i_3 
       (.I0(p_0_out__2_n_83),
        .I1(p_0_out__4_n_66),
        .I2(p_0_out__4_n_67),
        .I3(p_0_out__2_n_84),
        .O(\offset_H1_comp_V[37]_INST_0_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[37]_INST_0_i_4 
       (.I0(p_0_out__2_n_84),
        .I1(p_0_out__4_n_67),
        .I2(p_0_out__4_n_68),
        .I3(p_0_out__2_n_85),
        .O(\offset_H1_comp_V[37]_INST_0_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[37]_INST_0_i_5 
       (.I0(p_0_out__2_n_85),
        .I1(p_0_out__4_n_68),
        .I2(p_0_out__4_n_69),
        .I3(p_0_out__2_n_86),
        .O(\offset_H1_comp_V[37]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[37]_INST_0_i_6 
       (.I0(p_0_out__2_n_83),
        .I1(p_0_out__4_n_66),
        .I2(p_0_out__2_n_81),
        .I3(p_0_out__4_n_64),
        .I4(p_0_out__4_n_65),
        .I5(p_0_out__2_n_82),
        .O(\offset_H1_comp_V[37]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[37]_INST_0_i_7 
       (.I0(p_0_out__2_n_84),
        .I1(p_0_out__4_n_67),
        .I2(p_0_out__2_n_82),
        .I3(p_0_out__4_n_65),
        .I4(p_0_out__4_n_66),
        .I5(p_0_out__2_n_83),
        .O(\offset_H1_comp_V[37]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[37]_INST_0_i_8 
       (.I0(p_0_out__2_n_85),
        .I1(p_0_out__4_n_68),
        .I2(p_0_out__2_n_83),
        .I3(p_0_out__4_n_66),
        .I4(p_0_out__4_n_67),
        .I5(p_0_out__2_n_84),
        .O(\offset_H1_comp_V[37]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[37]_INST_0_i_9 
       (.I0(p_0_out__2_n_86),
        .I1(p_0_out__4_n_69),
        .I2(p_0_out__2_n_84),
        .I3(p_0_out__4_n_67),
        .I4(p_0_out__4_n_68),
        .I5(p_0_out__2_n_85),
        .O(\offset_H1_comp_V[37]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[38]_INST_0 
       (.I0(tmp_s_reg_434_reg[38]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [38]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[39]_INST_0 
       (.I0(tmp_s_reg_434_reg[39]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [39]));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[3]_INST_0 
       (.I0(tmp_s_reg_434_reg[3]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [3]));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[40]_INST_0 
       (.I0(tmp_s_reg_434_reg[40]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [40]));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[41]_INST_0 
       (.I0(tmp_s_reg_434_reg[41]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [41]));
  CARRY4 \offset_H1_comp_V[41]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[37]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[41]_INST_0_i_1_n_0 ,\offset_H1_comp_V[41]_INST_0_i_1_n_1 ,\offset_H1_comp_V[41]_INST_0_i_1_n_2 ,\offset_H1_comp_V[41]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[41]_INST_0_i_2_n_0 ,\offset_H1_comp_V[41]_INST_0_i_3_n_0 ,\offset_H1_comp_V[41]_INST_0_i_4_n_0 ,\offset_H1_comp_V[41]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[41:38]),
        .S({\offset_H1_comp_V[41]_INST_0_i_6_n_0 ,\offset_H1_comp_V[41]_INST_0_i_7_n_0 ,\offset_H1_comp_V[41]_INST_0_i_8_n_0 ,\offset_H1_comp_V[41]_INST_0_i_9_n_0 }));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[41]_INST_0_i_2 
       (.I0(p_0_out__2_n_78),
        .I1(p_0_out__4_n_61),
        .I2(p_0_out__4_n_62),
        .I3(p_0_out__2_n_79),
        .O(\offset_H1_comp_V[41]_INST_0_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[41]_INST_0_i_3 
       (.I0(p_0_out__2_n_79),
        .I1(p_0_out__4_n_62),
        .I2(p_0_out__4_n_63),
        .I3(p_0_out__2_n_80),
        .O(\offset_H1_comp_V[41]_INST_0_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[41]_INST_0_i_4 
       (.I0(p_0_out__2_n_80),
        .I1(p_0_out__4_n_63),
        .I2(p_0_out__4_n_64),
        .I3(p_0_out__2_n_81),
        .O(\offset_H1_comp_V[41]_INST_0_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h9990)) 
    \offset_H1_comp_V[41]_INST_0_i_5 
       (.I0(p_0_out__2_n_81),
        .I1(p_0_out__4_n_64),
        .I2(p_0_out__4_n_65),
        .I3(p_0_out__2_n_82),
        .O(\offset_H1_comp_V[41]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hE10F0F1E1EF0F0E1)) 
    \offset_H1_comp_V[41]_INST_0_i_6 
       (.I0(p_0_out__2_n_79),
        .I1(p_0_out__4_n_62),
        .I2(p_0_out__4_n_60),
        .I3(p_0_out__2_n_78),
        .I4(p_0_out__4_n_61),
        .I5(p_0_out__2_n_77),
        .O(\offset_H1_comp_V[41]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[41]_INST_0_i_7 
       (.I0(p_0_out__2_n_80),
        .I1(p_0_out__4_n_63),
        .I2(p_0_out__2_n_78),
        .I3(p_0_out__4_n_61),
        .I4(p_0_out__4_n_62),
        .I5(p_0_out__2_n_79),
        .O(\offset_H1_comp_V[41]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[41]_INST_0_i_8 
       (.I0(p_0_out__2_n_81),
        .I1(p_0_out__4_n_64),
        .I2(p_0_out__2_n_79),
        .I3(p_0_out__4_n_62),
        .I4(p_0_out__4_n_63),
        .I5(p_0_out__2_n_80),
        .O(\offset_H1_comp_V[41]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \offset_H1_comp_V[41]_INST_0_i_9 
       (.I0(p_0_out__2_n_82),
        .I1(p_0_out__4_n_65),
        .I2(p_0_out__2_n_80),
        .I3(p_0_out__4_n_63),
        .I4(p_0_out__4_n_64),
        .I5(p_0_out__2_n_81),
        .O(\offset_H1_comp_V[41]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[42]_INST_0 
       (.I0(tmp_s_reg_434_reg[42]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [42]));
  CARRY4 \offset_H1_comp_V[42]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[41]_INST_0_i_1_n_0 ),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(tmp_s_reg_434_reg[42]),
        .S({\<const0> ,\<const0> ,\<const0> ,\offset_H1_comp_V[42]_INST_0_i_2_n_0 }));
  LUT6 #(
    .INIT(64'h9666966696666669)) 
    \offset_H1_comp_V[42]_INST_0_i_2 
       (.I0(p_0_out__2_n_76),
        .I1(p_0_out__4_n_59),
        .I2(p_0_out__2_n_77),
        .I3(p_0_out__4_n_60),
        .I4(p_0_out__4_n_61),
        .I5(p_0_out__2_n_78),
        .O(\offset_H1_comp_V[42]_INST_0_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[4]_INST_0 
       (.I0(tmp_s_reg_434_reg[4]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [4]));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[5]_INST_0 
       (.I0(tmp_s_reg_434_reg[5]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [5]));
  CARRY4 \offset_H1_comp_V[5]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[1]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[5]_INST_0_i_1_n_0 ,\offset_H1_comp_V[5]_INST_0_i_1_n_1 ,\offset_H1_comp_V[5]_INST_0_i_1_n_2 ,\offset_H1_comp_V[5]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[5]_INST_0_i_2_n_0 ,\offset_H1_comp_V[5]_INST_0_i_3_n_0 ,\offset_H1_comp_V[5]_INST_0_i_4_n_0 ,\offset_H1_comp_V[5]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[5:2]),
        .S({\offset_H1_comp_V[5]_INST_0_i_6_n_0 ,\offset_H1_comp_V[5]_INST_0_i_7_n_0 ,\offset_H1_comp_V[5]_INST_0_i_8_n_0 ,\offset_H1_comp_V[5]_INST_0_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[5]_INST_0_i_2 
       (.I0(p_0_out__6_n_80),
        .I1(p_0_out__4_n_97),
        .I2(\p_0_out[8]__1_n_0 ),
        .O(\offset_H1_comp_V[5]_INST_0_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[5]_INST_0_i_3 
       (.I0(p_0_out__6_n_81),
        .I1(p_0_out__4_n_98),
        .I2(\p_0_out[7]__1_n_0 ),
        .O(\offset_H1_comp_V[5]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[5]_INST_0_i_4 
       (.I0(p_0_out__6_n_82),
        .I1(p_0_out__4_n_99),
        .I2(\p_0_out[6]__1_n_0 ),
        .O(\offset_H1_comp_V[5]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[5]_INST_0_i_5 
       (.I0(p_0_out__6_n_83),
        .I1(p_0_out__4_n_100),
        .I2(\p_0_out[5]__1_n_0 ),
        .O(\offset_H1_comp_V[5]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[5]_INST_0_i_6 
       (.I0(\p_0_out[8]__1_n_0 ),
        .I1(p_0_out__4_n_97),
        .I2(p_0_out__6_n_80),
        .I3(\p_0_out[9]__1_n_0 ),
        .I4(p_0_out__4_n_96),
        .I5(p_0_out__6_n_79),
        .O(\offset_H1_comp_V[5]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[5]_INST_0_i_7 
       (.I0(\p_0_out[7]__1_n_0 ),
        .I1(p_0_out__4_n_98),
        .I2(p_0_out__6_n_81),
        .I3(\p_0_out[8]__1_n_0 ),
        .I4(p_0_out__4_n_97),
        .I5(p_0_out__6_n_80),
        .O(\offset_H1_comp_V[5]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[5]_INST_0_i_8 
       (.I0(\p_0_out[6]__1_n_0 ),
        .I1(p_0_out__4_n_99),
        .I2(p_0_out__6_n_82),
        .I3(\p_0_out[7]__1_n_0 ),
        .I4(p_0_out__4_n_98),
        .I5(p_0_out__6_n_81),
        .O(\offset_H1_comp_V[5]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[5]_INST_0_i_9 
       (.I0(\p_0_out[5]__1_n_0 ),
        .I1(p_0_out__4_n_100),
        .I2(p_0_out__6_n_83),
        .I3(\p_0_out[6]__1_n_0 ),
        .I4(p_0_out__4_n_99),
        .I5(p_0_out__6_n_82),
        .O(\offset_H1_comp_V[5]_INST_0_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[6]_INST_0 
       (.I0(tmp_s_reg_434_reg[6]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [6]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[7]_INST_0 
       (.I0(tmp_s_reg_434_reg[7]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [7]));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[8]_INST_0 
       (.I0(tmp_s_reg_434_reg[8]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [8]));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \offset_H1_comp_V[9]_INST_0 
       (.I0(tmp_s_reg_434_reg[9]),
        .I1(or_cond_reg_403),
        .O(\^offset_H1_comp_V [9]));
  CARRY4 \offset_H1_comp_V[9]_INST_0_i_1 
       (.CI(\offset_H1_comp_V[5]_INST_0_i_1_n_0 ),
        .CO({\offset_H1_comp_V[9]_INST_0_i_1_n_0 ,\offset_H1_comp_V[9]_INST_0_i_1_n_1 ,\offset_H1_comp_V[9]_INST_0_i_1_n_2 ,\offset_H1_comp_V[9]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\offset_H1_comp_V[9]_INST_0_i_2_n_0 ,\offset_H1_comp_V[9]_INST_0_i_3_n_0 ,\offset_H1_comp_V[9]_INST_0_i_4_n_0 ,\offset_H1_comp_V[9]_INST_0_i_5_n_0 }),
        .O(tmp_s_reg_434_reg[9:6]),
        .S({\offset_H1_comp_V[9]_INST_0_i_6_n_0 ,\offset_H1_comp_V[9]_INST_0_i_7_n_0 ,\offset_H1_comp_V[9]_INST_0_i_8_n_0 ,\offset_H1_comp_V[9]_INST_0_i_9_n_0 }));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[9]_INST_0_i_2 
       (.I0(p_0_out__6_n_76),
        .I1(p_0_out__4_n_93),
        .I2(\p_0_out[12]__1_n_0 ),
        .O(\offset_H1_comp_V[9]_INST_0_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[9]_INST_0_i_3 
       (.I0(p_0_out__6_n_77),
        .I1(p_0_out__4_n_94),
        .I2(\p_0_out[11]__1_n_0 ),
        .O(\offset_H1_comp_V[9]_INST_0_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[9]_INST_0_i_4 
       (.I0(p_0_out__6_n_78),
        .I1(p_0_out__4_n_95),
        .I2(\p_0_out[10]__1_n_0 ),
        .O(\offset_H1_comp_V[9]_INST_0_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \offset_H1_comp_V[9]_INST_0_i_5 
       (.I0(p_0_out__6_n_79),
        .I1(p_0_out__4_n_96),
        .I2(\p_0_out[9]__1_n_0 ),
        .O(\offset_H1_comp_V[9]_INST_0_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[9]_INST_0_i_6 
       (.I0(\p_0_out[12]__1_n_0 ),
        .I1(p_0_out__4_n_93),
        .I2(p_0_out__6_n_76),
        .I3(\p_0_out[13]__1_n_0 ),
        .I4(p_0_out__4_n_92),
        .I5(p_0_out__6_n_75),
        .O(\offset_H1_comp_V[9]_INST_0_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[9]_INST_0_i_7 
       (.I0(\p_0_out[11]__1_n_0 ),
        .I1(p_0_out__4_n_94),
        .I2(p_0_out__6_n_77),
        .I3(\p_0_out[12]__1_n_0 ),
        .I4(p_0_out__4_n_93),
        .I5(p_0_out__6_n_76),
        .O(\offset_H1_comp_V[9]_INST_0_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[9]_INST_0_i_8 
       (.I0(\p_0_out[10]__1_n_0 ),
        .I1(p_0_out__4_n_95),
        .I2(p_0_out__6_n_78),
        .I3(\p_0_out[11]__1_n_0 ),
        .I4(p_0_out__4_n_94),
        .I5(p_0_out__6_n_77),
        .O(\offset_H1_comp_V[9]_INST_0_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \offset_H1_comp_V[9]_INST_0_i_9 
       (.I0(\p_0_out[9]__1_n_0 ),
        .I1(p_0_out__4_n_96),
        .I2(p_0_out__6_n_79),
        .I3(\p_0_out[10]__1_n_0 ),
        .I4(p_0_out__4_n_95),
        .I5(p_0_out__6_n_78),
        .O(\offset_H1_comp_V[9]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hBBBB8B88)) 
    \or_cond_reg_403[0]_i_1 
       (.I0(or_cond_reg_403),
        .I1(RFNCO_Divider_HLSbkb_U1_n_2),
        .I2(p_Val2_6_fu_302_p2_i_45_n_0),
        .I3(p_Val2_6_fu_302_p2_i_46_n_0),
        .I4(p_Val2_6_fu_302_p2_i_47_n_0),
        .O(\or_cond_reg_403[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \or_cond_reg_403_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\or_cond_reg_403[0]_i_1_n_0 ),
        .Q(or_cond_reg_403),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[0] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_105),
        .Q(\p_0_out_n_0_[0] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[0]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_105),
        .Q(\p_0_out[0]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[0]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_105),
        .Q(\p_0_out[0]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[10] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_95),
        .Q(\p_0_out_n_0_[10] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[10]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_95),
        .Q(\p_0_out[10]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[10]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_95),
        .Q(\p_0_out[10]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[11] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_94),
        .Q(\p_0_out_n_0_[11] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[11]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_94),
        .Q(\p_0_out[11]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[11]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_94),
        .Q(\p_0_out[11]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[12] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_93),
        .Q(\p_0_out_n_0_[12] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[12]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_93),
        .Q(\p_0_out[12]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[12]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_93),
        .Q(\p_0_out[12]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[13] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_92),
        .Q(\p_0_out_n_0_[13] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[13]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_92),
        .Q(\p_0_out[13]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[13]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_92),
        .Q(\p_0_out[13]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[14] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_91),
        .Q(\p_0_out_n_0_[14] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[14]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_91),
        .Q(\p_0_out[14]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[14]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_91),
        .Q(\p_0_out[14]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[15] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_90),
        .Q(\p_0_out_n_0_[15] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[15]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_90),
        .Q(\p_0_out[15]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[15]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_90),
        .Q(\p_0_out[15]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_89),
        .Q(\p_0_out_n_0_[16] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16]__0 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2__0_n_89),
        .Q(\p_0_out[16]__0_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_89),
        .Q(\p_0_out[16]__1_n_0 ),
        .R(\<const0> ));
  LUT2 #(
    .INIT(4'h2)) 
    \p_0_out[16]__1_i_1 
       (.I0(ap_CS_fsm_state77),
        .I1(or_cond_reg_403),
        .O(\p_0_out[16]__1_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_89),
        .Q(\p_0_out[16]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16]__3 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__1_n_89),
        .Q(\p_0_out[16]__3_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[1] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_104),
        .Q(\p_0_out_n_0_[1] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[1]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_104),
        .Q(\p_0_out[1]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[1]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_104),
        .Q(\p_0_out[1]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[2] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_103),
        .Q(\p_0_out_n_0_[2] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[2]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_103),
        .Q(\p_0_out[2]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[2]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_103),
        .Q(\p_0_out[2]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[3] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_102),
        .Q(\p_0_out_n_0_[3] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[3]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_102),
        .Q(\p_0_out[3]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[3]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_102),
        .Q(\p_0_out[3]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[4] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_101),
        .Q(\p_0_out_n_0_[4] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[4]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_101),
        .Q(\p_0_out[4]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[4]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_101),
        .Q(\p_0_out[4]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[5] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_100),
        .Q(\p_0_out_n_0_[5] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[5]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_100),
        .Q(\p_0_out[5]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[5]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_100),
        .Q(\p_0_out[5]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[6] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_99),
        .Q(\p_0_out_n_0_[6] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[6]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_99),
        .Q(\p_0_out[6]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[6]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_99),
        .Q(\p_0_out[6]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[7] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_98),
        .Q(\p_0_out_n_0_[7] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[7]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_98),
        .Q(\p_0_out[7]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[7]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_98),
        .Q(\p_0_out[7]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[8] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_97),
        .Q(\p_0_out_n_0_[8] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[8]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_97),
        .Q(\p_0_out[8]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[8]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_97),
        .Q(\p_0_out[8]__2_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[9] 
       (.C(ap_clk),
        .CE(tw_H1_V_ap_vld),
        .D(p_Val2_3_fu_330_p2_n_96),
        .Q(\p_0_out_n_0_[9] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[9]__1 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2_n_96),
        .Q(\p_0_out[9]__1_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[9]__2 
       (.C(ap_clk),
        .CE(\p_0_out[16]__1_i_1_n_0 ),
        .D(p_Val2_5_fu_361_p2__0_n_96),
        .Q(\p_0_out[9]__2_n_0 ),
        .R(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 16x16 4}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__0
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,sel0[31:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,dividend_tmp[31:17]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(start),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(done0),
        .CEB2(ap_CS_fsm_state74),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(tw_H1_V_ap_vld),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__0_n_58,p_0_out__0_n_59,p_0_out__0_n_60,p_0_out__0_n_61,p_0_out__0_n_62,p_0_out__0_n_63,p_0_out__0_n_64,p_0_out__0_n_65,p_0_out__0_n_66,p_0_out__0_n_67,p_0_out__0_n_68,p_0_out__0_n_69,p_0_out__0_n_70,p_0_out__0_n_71,p_0_out__0_n_72,p_0_out__0_n_73,p_0_out__0_n_74,p_0_out__0_n_75,p_0_out__0_n_76,p_0_out__0_n_77,p_0_out__0_n_78,p_0_out__0_n_79,p_0_out__0_n_80,p_0_out__0_n_81,p_0_out__0_n_82,p_0_out__0_n_83,p_0_out__0_n_84,p_0_out__0_n_85,p_0_out__0_n_86,p_0_out__0_n_87,p_0_out__0_n_88,p_0_out__0_n_89,p_0_out__0_n_90,p_0_out__0_n_91,p_0_out__0_n_92,p_0_out__0_n_93,p_0_out__0_n_94,p_0_out__0_n_95,p_0_out__0_n_96,p_0_out__0_n_97,p_0_out__0_n_98,p_0_out__0_n_99,p_0_out__0_n_100,p_0_out__0_n_101,p_0_out__0_n_102,p_0_out__0_n_103,p_0_out__0_n_104,p_0_out__0_n_105}),
        .PCIN({p_Val2_3_fu_330_p2_n_106,p_Val2_3_fu_330_p2_n_107,p_Val2_3_fu_330_p2_n_108,p_Val2_3_fu_330_p2_n_109,p_Val2_3_fu_330_p2_n_110,p_Val2_3_fu_330_p2_n_111,p_Val2_3_fu_330_p2_n_112,p_Val2_3_fu_330_p2_n_113,p_Val2_3_fu_330_p2_n_114,p_Val2_3_fu_330_p2_n_115,p_Val2_3_fu_330_p2_n_116,p_Val2_3_fu_330_p2_n_117,p_Val2_3_fu_330_p2_n_118,p_Val2_3_fu_330_p2_n_119,p_Val2_3_fu_330_p2_n_120,p_Val2_3_fu_330_p2_n_121,p_Val2_3_fu_330_p2_n_122,p_Val2_3_fu_330_p2_n_123,p_Val2_3_fu_330_p2_n_124,p_Val2_3_fu_330_p2_n_125,p_Val2_3_fu_330_p2_n_126,p_Val2_3_fu_330_p2_n_127,p_Val2_3_fu_330_p2_n_128,p_Val2_3_fu_330_p2_n_129,p_Val2_3_fu_330_p2_n_130,p_Val2_3_fu_330_p2_n_131,p_Val2_3_fu_330_p2_n_132,p_Val2_3_fu_330_p2_n_133,p_Val2_3_fu_330_p2_n_134,p_Val2_3_fu_330_p2_n_135,p_Val2_3_fu_330_p2_n_136,p_Val2_3_fu_330_p2_n_137,p_Val2_3_fu_330_p2_n_138,p_Val2_3_fu_330_p2_n_139,p_Val2_3_fu_330_p2_n_140,p_Val2_3_fu_330_p2_n_141,p_Val2_3_fu_330_p2_n_142,p_Val2_3_fu_330_p2_n_143,p_Val2_3_fu_330_p2_n_144,p_Val2_3_fu_330_p2_n_145,p_Val2_3_fu_330_p2_n_146,p_Val2_3_fu_330_p2_n_147,p_Val2_3_fu_330_p2_n_148,p_Val2_3_fu_330_p2_n_149,p_Val2_3_fu_330_p2_n_150,p_Val2_3_fu_330_p2_n_151,p_Val2_3_fu_330_p2_n_152,p_Val2_3_fu_330_p2_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x16 4}}" *) 
  DSP48E1 #(
    .ACASCREG(0),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(0),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("CASCADE"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__1
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACIN({p_Val2_3_fu_330_p2__0_n_24,p_Val2_3_fu_330_p2__0_n_25,p_Val2_3_fu_330_p2__0_n_26,p_Val2_3_fu_330_p2__0_n_27,p_Val2_3_fu_330_p2__0_n_28,p_Val2_3_fu_330_p2__0_n_29,p_Val2_3_fu_330_p2__0_n_30,p_Val2_3_fu_330_p2__0_n_31,p_Val2_3_fu_330_p2__0_n_32,p_Val2_3_fu_330_p2__0_n_33,p_Val2_3_fu_330_p2__0_n_34,p_Val2_3_fu_330_p2__0_n_35,p_Val2_3_fu_330_p2__0_n_36,p_Val2_3_fu_330_p2__0_n_37,p_Val2_3_fu_330_p2__0_n_38,p_Val2_3_fu_330_p2__0_n_39,p_Val2_3_fu_330_p2__0_n_40,p_Val2_3_fu_330_p2__0_n_41,p_Val2_3_fu_330_p2__0_n_42,p_Val2_3_fu_330_p2__0_n_43,p_Val2_3_fu_330_p2__0_n_44,p_Val2_3_fu_330_p2__0_n_45,p_Val2_3_fu_330_p2__0_n_46,p_Val2_3_fu_330_p2__0_n_47,p_Val2_3_fu_330_p2__0_n_48,p_Val2_3_fu_330_p2__0_n_49,p_Val2_3_fu_330_p2__0_n_50,p_Val2_3_fu_330_p2__0_n_51,p_Val2_3_fu_330_p2__0_n_52,p_Val2_3_fu_330_p2__0_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,dividend_tmp[31:17]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(\<const0> ),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(done0),
        .CEB2(ap_CS_fsm_state74),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(tw_H1_V_ap_vld),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__1_n_58,p_0_out__1_n_59,p_0_out__1_n_60,p_0_out__1_n_61,p_0_out__1_n_62,p_0_out__1_n_63,p_0_out__1_n_64,p_0_out__1_n_65,p_0_out__1_n_66,p_0_out__1_n_67,p_0_out__1_n_68,p_0_out__1_n_69,p_0_out__1_n_70,p_0_out__1_n_71,p_0_out__1_n_72,p_0_out__1_n_73,p_0_out__1_n_74,p_0_out__1_n_75,p_0_out__1_n_76,p_0_out__1_n_77,p_0_out__1_n_78,p_0_out__1_n_79,p_0_out__1_n_80,p_0_out__1_n_81,p_0_out__1_n_82,p_0_out__1_n_83,p_0_out__1_n_84,p_0_out__1_n_85,p_0_out__1_n_86,p_0_out__1_n_87,p_0_out__1_n_88,p_0_out__1_n_89,p_0_out__1_n_90,p_0_out__1_n_91,p_0_out__1_n_92,p_0_out__1_n_93,p_0_out__1_n_94,p_0_out__1_n_95,p_0_out__1_n_96,p_0_out__1_n_97,p_0_out__1_n_98,p_0_out__1_n_99,p_0_out__1_n_100,p_0_out__1_n_101,p_0_out__1_n_102,p_0_out__1_n_103,p_0_out__1_n_104,p_0_out__1_n_105}),
        .PCIN({p_Val2_3_fu_330_p2__0_n_106,p_Val2_3_fu_330_p2__0_n_107,p_Val2_3_fu_330_p2__0_n_108,p_Val2_3_fu_330_p2__0_n_109,p_Val2_3_fu_330_p2__0_n_110,p_Val2_3_fu_330_p2__0_n_111,p_Val2_3_fu_330_p2__0_n_112,p_Val2_3_fu_330_p2__0_n_113,p_Val2_3_fu_330_p2__0_n_114,p_Val2_3_fu_330_p2__0_n_115,p_Val2_3_fu_330_p2__0_n_116,p_Val2_3_fu_330_p2__0_n_117,p_Val2_3_fu_330_p2__0_n_118,p_Val2_3_fu_330_p2__0_n_119,p_Val2_3_fu_330_p2__0_n_120,p_Val2_3_fu_330_p2__0_n_121,p_Val2_3_fu_330_p2__0_n_122,p_Val2_3_fu_330_p2__0_n_123,p_Val2_3_fu_330_p2__0_n_124,p_Val2_3_fu_330_p2__0_n_125,p_Val2_3_fu_330_p2__0_n_126,p_Val2_3_fu_330_p2__0_n_127,p_Val2_3_fu_330_p2__0_n_128,p_Val2_3_fu_330_p2__0_n_129,p_Val2_3_fu_330_p2__0_n_130,p_Val2_3_fu_330_p2__0_n_131,p_Val2_3_fu_330_p2__0_n_132,p_Val2_3_fu_330_p2__0_n_133,p_Val2_3_fu_330_p2__0_n_134,p_Val2_3_fu_330_p2__0_n_135,p_Val2_3_fu_330_p2__0_n_136,p_Val2_3_fu_330_p2__0_n_137,p_Val2_3_fu_330_p2__0_n_138,p_Val2_3_fu_330_p2__0_n_139,p_Val2_3_fu_330_p2__0_n_140,p_Val2_3_fu_330_p2__0_n_141,p_Val2_3_fu_330_p2__0_n_142,p_Val2_3_fu_330_p2__0_n_143,p_Val2_3_fu_330_p2__0_n_144,p_Val2_3_fu_330_p2__0_n_145,p_Val2_3_fu_330_p2__0_n_146,p_Val2_3_fu_330_p2__0_n_147,p_Val2_3_fu_330_p2__0_n_148,p_Val2_3_fu_330_p2__0_n_149,p_Val2_3_fu_330_p2__0_n_150,p_Val2_3_fu_330_p2__0_n_151,p_Val2_3_fu_330_p2__0_n_152,p_Val2_3_fu_330_p2__0_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 15x16 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(0),
    .BREG(0),
    .B_INPUT("CASCADE"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__2
       (.A({p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_2_n_4,p_0_out__2_i_2_n_5,p_0_out__2_i_2_n_6,p_0_out__2_i_2_n_7,p_0_out__2_i_3_n_4,p_0_out__2_i_3_n_5,p_0_out__2_i_3_n_6,p_0_out__2_i_3_n_7,p_0_out__2_i_4_n_4,p_0_out__2_i_4_n_5,p_0_out__2_i_4_n_6,p_0_out__2_i_4_n_7,p_Val2_5_fu_361_p2_i_3_n_4,p_Val2_5_fu_361_p2_i_3_n_5,p_Val2_5_fu_361_p2_i_3_n_6}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .BCIN({p_Val2_5_fu_361_p2_n_6,p_Val2_5_fu_361_p2_n_7,p_Val2_5_fu_361_p2_n_8,p_Val2_5_fu_361_p2_n_9,p_Val2_5_fu_361_p2_n_10,p_Val2_5_fu_361_p2_n_11,p_Val2_5_fu_361_p2_n_12,p_Val2_5_fu_361_p2_n_13,p_Val2_5_fu_361_p2_n_14,p_Val2_5_fu_361_p2_n_15,p_Val2_5_fu_361_p2_n_16,p_Val2_5_fu_361_p2_n_17,p_Val2_5_fu_361_p2_n_18,p_Val2_5_fu_361_p2_n_19,p_Val2_5_fu_361_p2_n_20,p_Val2_5_fu_361_p2_n_21,p_Val2_5_fu_361_p2_n_22,p_Val2_5_fu_361_p2_n_23}),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_5_fu_361_p2_i_1_n_0),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(\<const0> ),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\p_0_out[16]__1_i_1_n_0 ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__2_n_58,p_0_out__2_n_59,p_0_out__2_n_60,p_0_out__2_n_61,p_0_out__2_n_62,p_0_out__2_n_63,p_0_out__2_n_64,p_0_out__2_n_65,p_0_out__2_n_66,p_0_out__2_n_67,p_0_out__2_n_68,p_0_out__2_n_69,p_0_out__2_n_70,p_0_out__2_n_71,p_0_out__2_n_72,p_0_out__2_n_73,p_0_out__2_n_74,p_0_out__2_n_75,p_0_out__2_n_76,p_0_out__2_n_77,p_0_out__2_n_78,p_0_out__2_n_79,p_0_out__2_n_80,p_0_out__2_n_81,p_0_out__2_n_82,p_0_out__2_n_83,p_0_out__2_n_84,p_0_out__2_n_85,p_0_out__2_n_86,p_0_out__2_n_87,p_0_out__2_n_88,p_0_out__2_n_89,p_0_out__2_n_90,p_0_out__2_n_91,p_0_out__2_n_92,p_0_out__2_n_93,p_0_out__2_n_94,p_0_out__2_n_95,p_0_out__2_n_96,p_0_out__2_n_97,p_0_out__2_n_98,p_0_out__2_n_99,p_0_out__2_n_100,p_0_out__2_n_101,p_0_out__2_n_102,p_0_out__2_n_103,p_0_out__2_n_104,p_0_out__2_n_105}),
        .PCIN({p_Val2_5_fu_361_p2_n_106,p_Val2_5_fu_361_p2_n_107,p_Val2_5_fu_361_p2_n_108,p_Val2_5_fu_361_p2_n_109,p_Val2_5_fu_361_p2_n_110,p_Val2_5_fu_361_p2_n_111,p_Val2_5_fu_361_p2_n_112,p_Val2_5_fu_361_p2_n_113,p_Val2_5_fu_361_p2_n_114,p_Val2_5_fu_361_p2_n_115,p_Val2_5_fu_361_p2_n_116,p_Val2_5_fu_361_p2_n_117,p_Val2_5_fu_361_p2_n_118,p_Val2_5_fu_361_p2_n_119,p_Val2_5_fu_361_p2_n_120,p_Val2_5_fu_361_p2_n_121,p_Val2_5_fu_361_p2_n_122,p_Val2_5_fu_361_p2_n_123,p_Val2_5_fu_361_p2_n_124,p_Val2_5_fu_361_p2_n_125,p_Val2_5_fu_361_p2_n_126,p_Val2_5_fu_361_p2_n_127,p_Val2_5_fu_361_p2_n_128,p_Val2_5_fu_361_p2_n_129,p_Val2_5_fu_361_p2_n_130,p_Val2_5_fu_361_p2_n_131,p_Val2_5_fu_361_p2_n_132,p_Val2_5_fu_361_p2_n_133,p_Val2_5_fu_361_p2_n_134,p_Val2_5_fu_361_p2_n_135,p_Val2_5_fu_361_p2_n_136,p_Val2_5_fu_361_p2_n_137,p_Val2_5_fu_361_p2_n_138,p_Val2_5_fu_361_p2_n_139,p_Val2_5_fu_361_p2_n_140,p_Val2_5_fu_361_p2_n_141,p_Val2_5_fu_361_p2_n_142,p_Val2_5_fu_361_p2_n_143,p_Val2_5_fu_361_p2_n_144,p_Val2_5_fu_361_p2_n_145,p_Val2_5_fu_361_p2_n_146,p_Val2_5_fu_361_p2_n_147,p_Val2_5_fu_361_p2_n_148,p_Val2_5_fu_361_p2_n_149,p_Val2_5_fu_361_p2_n_150,p_Val2_5_fu_361_p2_n_151,p_Val2_5_fu_361_p2_n_152,p_Val2_5_fu_361_p2_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  CARRY4 p_0_out__2_i_1
       (.CI(p_0_out__2_i_2_n_0),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(p_0_out__2_i_1_n_7),
        .S({\<const0> ,\<const0> ,\<const0> ,\<const1> }));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_10
       (.I0(p_Val2_4_reg_423_reg[26]),
        .O(p_0_out__2_i_10_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_11
       (.I0(p_Val2_4_reg_423_reg[25]),
        .O(p_0_out__2_i_11_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_12
       (.I0(p_Val2_4_reg_423_reg[24]),
        .O(p_0_out__2_i_12_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_13
       (.I0(p_Val2_4_reg_423_reg[23]),
        .O(p_0_out__2_i_13_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_14
       (.I0(p_Val2_4_reg_423_reg[22]),
        .O(p_0_out__2_i_14_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_15
       (.I0(p_Val2_4_reg_423_reg[21]),
        .O(p_0_out__2_i_15_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_16
       (.I0(p_Val2_4_reg_423_reg[20]),
        .O(p_0_out__2_i_16_n_0));
  CARRY4 p_0_out__2_i_2
       (.CI(p_0_out__2_i_3_n_0),
        .CO({p_0_out__2_i_2_n_0,p_0_out__2_i_2_n_1,p_0_out__2_i_2_n_2,p_0_out__2_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_0_out__2_i_2_n_4,p_0_out__2_i_2_n_5,p_0_out__2_i_2_n_6,p_0_out__2_i_2_n_7}),
        .S({p_0_out__2_i_5_n_0,p_0_out__2_i_6_n_0,p_0_out__2_i_7_n_0,p_0_out__2_i_8_n_0}));
  CARRY4 p_0_out__2_i_3
       (.CI(p_0_out__2_i_4_n_0),
        .CO({p_0_out__2_i_3_n_0,p_0_out__2_i_3_n_1,p_0_out__2_i_3_n_2,p_0_out__2_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_0_out__2_i_3_n_4,p_0_out__2_i_3_n_5,p_0_out__2_i_3_n_6,p_0_out__2_i_3_n_7}),
        .S({p_0_out__2_i_9_n_0,p_0_out__2_i_10_n_0,p_0_out__2_i_11_n_0,p_0_out__2_i_12_n_0}));
  CARRY4 p_0_out__2_i_4
       (.CI(p_Val2_5_fu_361_p2_i_3_n_0),
        .CO({p_0_out__2_i_4_n_0,p_0_out__2_i_4_n_1,p_0_out__2_i_4_n_2,p_0_out__2_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_0_out__2_i_4_n_4,p_0_out__2_i_4_n_5,p_0_out__2_i_4_n_6,p_0_out__2_i_4_n_7}),
        .S({p_0_out__2_i_13_n_0,p_0_out__2_i_14_n_0,p_0_out__2_i_15_n_0,p_0_out__2_i_16_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_5
       (.I0(p_Val2_4_reg_423_reg[31]),
        .O(p_0_out__2_i_5_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_6
       (.I0(p_Val2_4_reg_423_reg[30]),
        .O(p_0_out__2_i_6_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_7
       (.I0(p_Val2_4_reg_423_reg[29]),
        .O(p_0_out__2_i_7_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_8
       (.I0(p_Val2_4_reg_423_reg[28]),
        .O(p_0_out__2_i_8_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_0_out__2_i_9
       (.I0(p_Val2_4_reg_423_reg[27]),
        .O(p_0_out__2_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x16 6}}" *) 
  DSP48E1 #(
    .ACASCREG(0),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(0),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("CASCADE"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__4
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACIN({p_Val2_5_fu_361_p2__0_n_24,p_Val2_5_fu_361_p2__0_n_25,p_Val2_5_fu_361_p2__0_n_26,p_Val2_5_fu_361_p2__0_n_27,p_Val2_5_fu_361_p2__0_n_28,p_Val2_5_fu_361_p2__0_n_29,p_Val2_5_fu_361_p2__0_n_30,p_Val2_5_fu_361_p2__0_n_31,p_Val2_5_fu_361_p2__0_n_32,p_Val2_5_fu_361_p2__0_n_33,p_Val2_5_fu_361_p2__0_n_34,p_Val2_5_fu_361_p2__0_n_35,p_Val2_5_fu_361_p2__0_n_36,p_Val2_5_fu_361_p2__0_n_37,p_Val2_5_fu_361_p2__0_n_38,p_Val2_5_fu_361_p2__0_n_39,p_Val2_5_fu_361_p2__0_n_40,p_Val2_5_fu_361_p2__0_n_41,p_Val2_5_fu_361_p2__0_n_42,p_Val2_5_fu_361_p2__0_n_43,p_Val2_5_fu_361_p2__0_n_44,p_Val2_5_fu_361_p2__0_n_45,p_Val2_5_fu_361_p2__0_n_46,p_Val2_5_fu_361_p2__0_n_47,p_Val2_5_fu_361_p2__0_n_48,p_Val2_5_fu_361_p2__0_n_49,p_Val2_5_fu_361_p2__0_n_50,p_Val2_5_fu_361_p2__0_n_51,p_Val2_5_fu_361_p2__0_n_52,p_Val2_5_fu_361_p2__0_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_2_n_4,p_0_out__2_i_2_n_5,p_0_out__2_i_2_n_6,p_0_out__2_i_2_n_7,p_0_out__2_i_3_n_4,p_0_out__2_i_3_n_5,p_0_out__2_i_3_n_6,p_0_out__2_i_3_n_7,p_0_out__2_i_4_n_4,p_0_out__2_i_4_n_5,p_0_out__2_i_4_n_6,p_0_out__2_i_4_n_7,p_Val2_5_fu_361_p2_i_3_n_4,p_Val2_5_fu_361_p2_i_3_n_5,p_Val2_5_fu_361_p2_i_3_n_6}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(\<const0> ),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_5_fu_361_p2_i_1_n_0),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\p_0_out[16]__1_i_1_n_0 ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__4_n_58,p_0_out__4_n_59,p_0_out__4_n_60,p_0_out__4_n_61,p_0_out__4_n_62,p_0_out__4_n_63,p_0_out__4_n_64,p_0_out__4_n_65,p_0_out__4_n_66,p_0_out__4_n_67,p_0_out__4_n_68,p_0_out__4_n_69,p_0_out__4_n_70,p_0_out__4_n_71,p_0_out__4_n_72,p_0_out__4_n_73,p_0_out__4_n_74,p_0_out__4_n_75,p_0_out__4_n_76,p_0_out__4_n_77,p_0_out__4_n_78,p_0_out__4_n_79,p_0_out__4_n_80,p_0_out__4_n_81,p_0_out__4_n_82,p_0_out__4_n_83,p_0_out__4_n_84,p_0_out__4_n_85,p_0_out__4_n_86,p_0_out__4_n_87,p_0_out__4_n_88,p_0_out__4_n_89,p_0_out__4_n_90,p_0_out__4_n_91,p_0_out__4_n_92,p_0_out__4_n_93,p_0_out__4_n_94,p_0_out__4_n_95,p_0_out__4_n_96,p_0_out__4_n_97,p_0_out__4_n_98,p_0_out__4_n_99,p_0_out__4_n_100,p_0_out__4_n_101,p_0_out__4_n_102,p_0_out__4_n_103,p_0_out__4_n_104,p_0_out__4_n_105}),
        .PCIN({p_Val2_5_fu_361_p2__0_n_106,p_Val2_5_fu_361_p2__0_n_107,p_Val2_5_fu_361_p2__0_n_108,p_Val2_5_fu_361_p2__0_n_109,p_Val2_5_fu_361_p2__0_n_110,p_Val2_5_fu_361_p2__0_n_111,p_Val2_5_fu_361_p2__0_n_112,p_Val2_5_fu_361_p2__0_n_113,p_Val2_5_fu_361_p2__0_n_114,p_Val2_5_fu_361_p2__0_n_115,p_Val2_5_fu_361_p2__0_n_116,p_Val2_5_fu_361_p2__0_n_117,p_Val2_5_fu_361_p2__0_n_118,p_Val2_5_fu_361_p2__0_n_119,p_Val2_5_fu_361_p2__0_n_120,p_Val2_5_fu_361_p2__0_n_121,p_Val2_5_fu_361_p2__0_n_122,p_Val2_5_fu_361_p2__0_n_123,p_Val2_5_fu_361_p2__0_n_124,p_Val2_5_fu_361_p2__0_n_125,p_Val2_5_fu_361_p2__0_n_126,p_Val2_5_fu_361_p2__0_n_127,p_Val2_5_fu_361_p2__0_n_128,p_Val2_5_fu_361_p2__0_n_129,p_Val2_5_fu_361_p2__0_n_130,p_Val2_5_fu_361_p2__0_n_131,p_Val2_5_fu_361_p2__0_n_132,p_Val2_5_fu_361_p2__0_n_133,p_Val2_5_fu_361_p2__0_n_134,p_Val2_5_fu_361_p2__0_n_135,p_Val2_5_fu_361_p2__0_n_136,p_Val2_5_fu_361_p2__0_n_137,p_Val2_5_fu_361_p2__0_n_138,p_Val2_5_fu_361_p2__0_n_139,p_Val2_5_fu_361_p2__0_n_140,p_Val2_5_fu_361_p2__0_n_141,p_Val2_5_fu_361_p2__0_n_142,p_Val2_5_fu_361_p2__0_n_143,p_Val2_5_fu_361_p2__0_n_144,p_Val2_5_fu_361_p2__0_n_145,p_Val2_5_fu_361_p2__0_n_146,p_Val2_5_fu_361_p2__0_n_147,p_Val2_5_fu_361_p2__0_n_148,p_Val2_5_fu_361_p2__0_n_149,p_Val2_5_fu_361_p2__0_n_150,p_Val2_5_fu_361_p2__0_n_151,p_Val2_5_fu_361_p2__0_n_152,p_Val2_5_fu_361_p2__0_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x16 6}}" *) 
  DSP48E1 #(
    .ACASCREG(0),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(0),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("CASCADE"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__6
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACIN({p_Val2_5_fu_361_p2__1_n_24,p_Val2_5_fu_361_p2__1_n_25,p_Val2_5_fu_361_p2__1_n_26,p_Val2_5_fu_361_p2__1_n_27,p_Val2_5_fu_361_p2__1_n_28,p_Val2_5_fu_361_p2__1_n_29,p_Val2_5_fu_361_p2__1_n_30,p_Val2_5_fu_361_p2__1_n_31,p_Val2_5_fu_361_p2__1_n_32,p_Val2_5_fu_361_p2__1_n_33,p_Val2_5_fu_361_p2__1_n_34,p_Val2_5_fu_361_p2__1_n_35,p_Val2_5_fu_361_p2__1_n_36,p_Val2_5_fu_361_p2__1_n_37,p_Val2_5_fu_361_p2__1_n_38,p_Val2_5_fu_361_p2__1_n_39,p_Val2_5_fu_361_p2__1_n_40,p_Val2_5_fu_361_p2__1_n_41,p_Val2_5_fu_361_p2__1_n_42,p_Val2_5_fu_361_p2__1_n_43,p_Val2_5_fu_361_p2__1_n_44,p_Val2_5_fu_361_p2__1_n_45,p_Val2_5_fu_361_p2__1_n_46,p_Val2_5_fu_361_p2__1_n_47,p_Val2_5_fu_361_p2__1_n_48,p_Val2_5_fu_361_p2__1_n_49,p_Val2_5_fu_361_p2__1_n_50,p_Val2_5_fu_361_p2__1_n_51,p_Val2_5_fu_361_p2__1_n_52,p_Val2_5_fu_361_p2__1_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_1_n_7,p_0_out__2_i_2_n_4,p_0_out__2_i_2_n_5,p_0_out__2_i_2_n_6,p_0_out__2_i_2_n_7,p_0_out__2_i_3_n_4,p_0_out__2_i_3_n_5,p_0_out__2_i_3_n_6,p_0_out__2_i_3_n_7,p_0_out__2_i_4_n_4,p_0_out__2_i_4_n_5,p_0_out__2_i_4_n_6,p_0_out__2_i_4_n_7,p_Val2_5_fu_361_p2_i_3_n_4,p_Val2_5_fu_361_p2_i_3_n_5,p_Val2_5_fu_361_p2_i_3_n_6}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(\<const0> ),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_5_fu_361_p2_i_1_n_0),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\p_0_out[16]__1_i_1_n_0 ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__6_n_58,p_0_out__6_n_59,p_0_out__6_n_60,p_0_out__6_n_61,p_0_out__6_n_62,p_0_out__6_n_63,p_0_out__6_n_64,p_0_out__6_n_65,p_0_out__6_n_66,p_0_out__6_n_67,p_0_out__6_n_68,p_0_out__6_n_69,p_0_out__6_n_70,p_0_out__6_n_71,p_0_out__6_n_72,p_0_out__6_n_73,p_0_out__6_n_74,p_0_out__6_n_75,p_0_out__6_n_76,p_0_out__6_n_77,p_0_out__6_n_78,p_0_out__6_n_79,p_0_out__6_n_80,p_0_out__6_n_81,p_0_out__6_n_82,p_0_out__6_n_83,p_0_out__6_n_84,p_0_out__6_n_85,p_0_out__6_n_86,p_0_out__6_n_87,p_0_out__6_n_88,p_0_out__6_n_89,p_0_out__6_n_90,p_0_out__6_n_91,p_0_out__6_n_92,p_0_out__6_n_93,p_0_out__6_n_94,p_0_out__6_n_95,p_0_out__6_n_96,p_0_out__6_n_97,p_0_out__6_n_98,p_0_out__6_n_99,p_0_out__6_n_100,p_0_out__6_n_101,p_0_out__6_n_102,p_0_out__6_n_103,p_0_out__6_n_104,p_0_out__6_n_105}),
        .PCIN({p_Val2_5_fu_361_p2__1_n_106,p_Val2_5_fu_361_p2__1_n_107,p_Val2_5_fu_361_p2__1_n_108,p_Val2_5_fu_361_p2__1_n_109,p_Val2_5_fu_361_p2__1_n_110,p_Val2_5_fu_361_p2__1_n_111,p_Val2_5_fu_361_p2__1_n_112,p_Val2_5_fu_361_p2__1_n_113,p_Val2_5_fu_361_p2__1_n_114,p_Val2_5_fu_361_p2__1_n_115,p_Val2_5_fu_361_p2__1_n_116,p_Val2_5_fu_361_p2__1_n_117,p_Val2_5_fu_361_p2__1_n_118,p_Val2_5_fu_361_p2__1_n_119,p_Val2_5_fu_361_p2__1_n_120,p_Val2_5_fu_361_p2__1_n_121,p_Val2_5_fu_361_p2__1_n_122,p_Val2_5_fu_361_p2__1_n_123,p_Val2_5_fu_361_p2__1_n_124,p_Val2_5_fu_361_p2__1_n_125,p_Val2_5_fu_361_p2__1_n_126,p_Val2_5_fu_361_p2__1_n_127,p_Val2_5_fu_361_p2__1_n_128,p_Val2_5_fu_361_p2__1_n_129,p_Val2_5_fu_361_p2__1_n_130,p_Val2_5_fu_361_p2__1_n_131,p_Val2_5_fu_361_p2__1_n_132,p_Val2_5_fu_361_p2__1_n_133,p_Val2_5_fu_361_p2__1_n_134,p_Val2_5_fu_361_p2__1_n_135,p_Val2_5_fu_361_p2__1_n_136,p_Val2_5_fu_361_p2__1_n_137,p_Val2_5_fu_361_p2__1_n_138,p_Val2_5_fu_361_p2__1_n_139,p_Val2_5_fu_361_p2__1_n_140,p_Val2_5_fu_361_p2__1_n_141,p_Val2_5_fu_361_p2__1_n_142,p_Val2_5_fu_361_p2__1_n_143,p_Val2_5_fu_361_p2__1_n_144,p_Val2_5_fu_361_p2__1_n_145,p_Val2_5_fu_361_p2__1_n_146,p_Val2_5_fu_361_p2__1_n_147,p_Val2_5_fu_361_p2__1_n_148,p_Val2_5_fu_361_p2__1_n_149,p_Val2_5_fu_361_p2__1_n_150,p_Val2_5_fu_361_p2__1_n_151,p_Val2_5_fu_361_p2__1_n_152,p_Val2_5_fu_361_p2__1_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[0] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[0]),
        .Q(tw_H1_V[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[10] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[10]),
        .Q(tw_H1_V[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[11] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[11]),
        .Q(tw_H1_V[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[12] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[12]),
        .Q(tw_H1_V[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[13] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[13]),
        .Q(tw_H1_V[13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[14] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[14]),
        .Q(tw_H1_V[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[15] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[15]),
        .Q(tw_H1_V[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[16] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[16]),
        .Q(tw_H1_V[16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[17] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[17]),
        .Q(tw_H1_V[17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[18] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[18]),
        .Q(tw_H1_V[18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[19] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[19]),
        .Q(tw_H1_V[19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[1] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[1]),
        .Q(tw_H1_V[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[20] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[20]),
        .Q(tw_H1_V[20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[21] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[21]),
        .Q(tw_H1_V[21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[22] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[22]),
        .Q(tw_H1_V[22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[23] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[23]),
        .Q(tw_H1_V[23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[24] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[24]),
        .Q(tw_H1_V[24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[25] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[25]),
        .Q(tw_H1_V[25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[26] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[26]),
        .Q(tw_H1_V[26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[27] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[27]),
        .Q(tw_H1_V[27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[28] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[28]),
        .Q(tw_H1_V[28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[29] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[29]),
        .Q(tw_H1_V[29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[2] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[2]),
        .Q(tw_H1_V[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[30] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[30]),
        .Q(tw_H1_V[30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[31] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[31]),
        .Q(tw_H1_V[31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[3] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[3]),
        .Q(tw_H1_V[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[4] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[4]),
        .Q(tw_H1_V[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[5] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[5]),
        .Q(tw_H1_V[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[6] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[6]),
        .Q(tw_H1_V[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[7] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[7]),
        .Q(tw_H1_V[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[8] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[8]),
        .Q(tw_H1_V[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_2_reg_418_reg[9] 
       (.C(ap_clk),
        .CE(ap_CS_fsm_state74),
        .D(quot[9]),
        .Q(tw_H1_V[9]),
        .R(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 16x18 4}}" *) 
  DSP48E1 #(
    .ACASCREG(2),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(2),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_3_fu_330_p2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,dividend_tmp[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,sel0[31:17]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(done0),
        .CEA2(ap_CS_fsm_state74),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(start),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_3_fu_330_p2_n_58,p_Val2_3_fu_330_p2_n_59,p_Val2_3_fu_330_p2_n_60,p_Val2_3_fu_330_p2_n_61,p_Val2_3_fu_330_p2_n_62,p_Val2_3_fu_330_p2_n_63,p_Val2_3_fu_330_p2_n_64,p_Val2_3_fu_330_p2_n_65,p_Val2_3_fu_330_p2_n_66,p_Val2_3_fu_330_p2_n_67,p_Val2_3_fu_330_p2_n_68,p_Val2_3_fu_330_p2_n_69,p_Val2_3_fu_330_p2_n_70,p_Val2_3_fu_330_p2_n_71,p_Val2_3_fu_330_p2_n_72,p_Val2_3_fu_330_p2_n_73,p_Val2_3_fu_330_p2_n_74,p_Val2_3_fu_330_p2_n_75,p_Val2_3_fu_330_p2_n_76,p_Val2_3_fu_330_p2_n_77,p_Val2_3_fu_330_p2_n_78,p_Val2_3_fu_330_p2_n_79,p_Val2_3_fu_330_p2_n_80,p_Val2_3_fu_330_p2_n_81,p_Val2_3_fu_330_p2_n_82,p_Val2_3_fu_330_p2_n_83,p_Val2_3_fu_330_p2_n_84,p_Val2_3_fu_330_p2_n_85,p_Val2_3_fu_330_p2_n_86,p_Val2_3_fu_330_p2_n_87,p_Val2_3_fu_330_p2_n_88,p_Val2_3_fu_330_p2_n_89,p_Val2_3_fu_330_p2_n_90,p_Val2_3_fu_330_p2_n_91,p_Val2_3_fu_330_p2_n_92,p_Val2_3_fu_330_p2_n_93,p_Val2_3_fu_330_p2_n_94,p_Val2_3_fu_330_p2_n_95,p_Val2_3_fu_330_p2_n_96,p_Val2_3_fu_330_p2_n_97,p_Val2_3_fu_330_p2_n_98,p_Val2_3_fu_330_p2_n_99,p_Val2_3_fu_330_p2_n_100,p_Val2_3_fu_330_p2_n_101,p_Val2_3_fu_330_p2_n_102,p_Val2_3_fu_330_p2_n_103,p_Val2_3_fu_330_p2_n_104,p_Val2_3_fu_330_p2_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_3_fu_330_p2_n_106,p_Val2_3_fu_330_p2_n_107,p_Val2_3_fu_330_p2_n_108,p_Val2_3_fu_330_p2_n_109,p_Val2_3_fu_330_p2_n_110,p_Val2_3_fu_330_p2_n_111,p_Val2_3_fu_330_p2_n_112,p_Val2_3_fu_330_p2_n_113,p_Val2_3_fu_330_p2_n_114,p_Val2_3_fu_330_p2_n_115,p_Val2_3_fu_330_p2_n_116,p_Val2_3_fu_330_p2_n_117,p_Val2_3_fu_330_p2_n_118,p_Val2_3_fu_330_p2_n_119,p_Val2_3_fu_330_p2_n_120,p_Val2_3_fu_330_p2_n_121,p_Val2_3_fu_330_p2_n_122,p_Val2_3_fu_330_p2_n_123,p_Val2_3_fu_330_p2_n_124,p_Val2_3_fu_330_p2_n_125,p_Val2_3_fu_330_p2_n_126,p_Val2_3_fu_330_p2_n_127,p_Val2_3_fu_330_p2_n_128,p_Val2_3_fu_330_p2_n_129,p_Val2_3_fu_330_p2_n_130,p_Val2_3_fu_330_p2_n_131,p_Val2_3_fu_330_p2_n_132,p_Val2_3_fu_330_p2_n_133,p_Val2_3_fu_330_p2_n_134,p_Val2_3_fu_330_p2_n_135,p_Val2_3_fu_330_p2_n_136,p_Val2_3_fu_330_p2_n_137,p_Val2_3_fu_330_p2_n_138,p_Val2_3_fu_330_p2_n_139,p_Val2_3_fu_330_p2_n_140,p_Val2_3_fu_330_p2_n_141,p_Val2_3_fu_330_p2_n_142,p_Val2_3_fu_330_p2_n_143,p_Val2_3_fu_330_p2_n_144,p_Val2_3_fu_330_p2_n_145,p_Val2_3_fu_330_p2_n_146,p_Val2_3_fu_330_p2_n_147,p_Val2_3_fu_330_p2_n_148,p_Val2_3_fu_330_p2_n_149,p_Val2_3_fu_330_p2_n_150,p_Val2_3_fu_330_p2_n_151,p_Val2_3_fu_330_p2_n_152,p_Val2_3_fu_330_p2_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x18 4}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_3_fu_330_p2__0
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,sel0[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACOUT({p_Val2_3_fu_330_p2__0_n_24,p_Val2_3_fu_330_p2__0_n_25,p_Val2_3_fu_330_p2__0_n_26,p_Val2_3_fu_330_p2__0_n_27,p_Val2_3_fu_330_p2__0_n_28,p_Val2_3_fu_330_p2__0_n_29,p_Val2_3_fu_330_p2__0_n_30,p_Val2_3_fu_330_p2__0_n_31,p_Val2_3_fu_330_p2__0_n_32,p_Val2_3_fu_330_p2__0_n_33,p_Val2_3_fu_330_p2__0_n_34,p_Val2_3_fu_330_p2__0_n_35,p_Val2_3_fu_330_p2__0_n_36,p_Val2_3_fu_330_p2__0_n_37,p_Val2_3_fu_330_p2__0_n_38,p_Val2_3_fu_330_p2__0_n_39,p_Val2_3_fu_330_p2__0_n_40,p_Val2_3_fu_330_p2__0_n_41,p_Val2_3_fu_330_p2__0_n_42,p_Val2_3_fu_330_p2__0_n_43,p_Val2_3_fu_330_p2__0_n_44,p_Val2_3_fu_330_p2__0_n_45,p_Val2_3_fu_330_p2__0_n_46,p_Val2_3_fu_330_p2__0_n_47,p_Val2_3_fu_330_p2__0_n_48,p_Val2_3_fu_330_p2__0_n_49,p_Val2_3_fu_330_p2__0_n_50,p_Val2_3_fu_330_p2__0_n_51,p_Val2_3_fu_330_p2__0_n_52,p_Val2_3_fu_330_p2__0_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,dividend_tmp[16:0]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(start),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(done0),
        .CEB2(ap_CS_fsm_state74),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_3_fu_330_p2__0_n_58,p_Val2_3_fu_330_p2__0_n_59,p_Val2_3_fu_330_p2__0_n_60,p_Val2_3_fu_330_p2__0_n_61,p_Val2_3_fu_330_p2__0_n_62,p_Val2_3_fu_330_p2__0_n_63,p_Val2_3_fu_330_p2__0_n_64,p_Val2_3_fu_330_p2__0_n_65,p_Val2_3_fu_330_p2__0_n_66,p_Val2_3_fu_330_p2__0_n_67,p_Val2_3_fu_330_p2__0_n_68,p_Val2_3_fu_330_p2__0_n_69,p_Val2_3_fu_330_p2__0_n_70,p_Val2_3_fu_330_p2__0_n_71,p_Val2_3_fu_330_p2__0_n_72,p_Val2_3_fu_330_p2__0_n_73,p_Val2_3_fu_330_p2__0_n_74,p_Val2_3_fu_330_p2__0_n_75,p_Val2_3_fu_330_p2__0_n_76,p_Val2_3_fu_330_p2__0_n_77,p_Val2_3_fu_330_p2__0_n_78,p_Val2_3_fu_330_p2__0_n_79,p_Val2_3_fu_330_p2__0_n_80,p_Val2_3_fu_330_p2__0_n_81,p_Val2_3_fu_330_p2__0_n_82,p_Val2_3_fu_330_p2__0_n_83,p_Val2_3_fu_330_p2__0_n_84,p_Val2_3_fu_330_p2__0_n_85,p_Val2_3_fu_330_p2__0_n_86,p_Val2_3_fu_330_p2__0_n_87,p_Val2_3_fu_330_p2__0_n_88,p_Val2_3_fu_330_p2__0_n_89,p_Val2_3_fu_330_p2__0_n_90,p_Val2_3_fu_330_p2__0_n_91,p_Val2_3_fu_330_p2__0_n_92,p_Val2_3_fu_330_p2__0_n_93,p_Val2_3_fu_330_p2__0_n_94,p_Val2_3_fu_330_p2__0_n_95,p_Val2_3_fu_330_p2__0_n_96,p_Val2_3_fu_330_p2__0_n_97,p_Val2_3_fu_330_p2__0_n_98,p_Val2_3_fu_330_p2__0_n_99,p_Val2_3_fu_330_p2__0_n_100,p_Val2_3_fu_330_p2__0_n_101,p_Val2_3_fu_330_p2__0_n_102,p_Val2_3_fu_330_p2__0_n_103,p_Val2_3_fu_330_p2__0_n_104,p_Val2_3_fu_330_p2__0_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_3_fu_330_p2__0_n_106,p_Val2_3_fu_330_p2__0_n_107,p_Val2_3_fu_330_p2__0_n_108,p_Val2_3_fu_330_p2__0_n_109,p_Val2_3_fu_330_p2__0_n_110,p_Val2_3_fu_330_p2__0_n_111,p_Val2_3_fu_330_p2__0_n_112,p_Val2_3_fu_330_p2__0_n_113,p_Val2_3_fu_330_p2__0_n_114,p_Val2_3_fu_330_p2__0_n_115,p_Val2_3_fu_330_p2__0_n_116,p_Val2_3_fu_330_p2__0_n_117,p_Val2_3_fu_330_p2__0_n_118,p_Val2_3_fu_330_p2__0_n_119,p_Val2_3_fu_330_p2__0_n_120,p_Val2_3_fu_330_p2__0_n_121,p_Val2_3_fu_330_p2__0_n_122,p_Val2_3_fu_330_p2__0_n_123,p_Val2_3_fu_330_p2__0_n_124,p_Val2_3_fu_330_p2__0_n_125,p_Val2_3_fu_330_p2__0_n_126,p_Val2_3_fu_330_p2__0_n_127,p_Val2_3_fu_330_p2__0_n_128,p_Val2_3_fu_330_p2__0_n_129,p_Val2_3_fu_330_p2__0_n_130,p_Val2_3_fu_330_p2__0_n_131,p_Val2_3_fu_330_p2__0_n_132,p_Val2_3_fu_330_p2__0_n_133,p_Val2_3_fu_330_p2__0_n_134,p_Val2_3_fu_330_p2__0_n_135,p_Val2_3_fu_330_p2__0_n_136,p_Val2_3_fu_330_p2__0_n_137,p_Val2_3_fu_330_p2__0_n_138,p_Val2_3_fu_330_p2__0_n_139,p_Val2_3_fu_330_p2__0_n_140,p_Val2_3_fu_330_p2__0_n_141,p_Val2_3_fu_330_p2__0_n_142,p_Val2_3_fu_330_p2__0_n_143,p_Val2_3_fu_330_p2__0_n_144,p_Val2_3_fu_330_p2__0_n_145,p_Val2_3_fu_330_p2__0_n_146,p_Val2_3_fu_330_p2__0_n_147,p_Val2_3_fu_330_p2__0_n_148,p_Val2_3_fu_330_p2__0_n_149,p_Val2_3_fu_330_p2__0_n_150,p_Val2_3_fu_330_p2__0_n_151,p_Val2_3_fu_330_p2__0_n_152,p_Val2_3_fu_330_p2__0_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_1
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_21_n_7),
        .O(sel0[16]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_10
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_20_n_4),
        .O(sel0[7]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_11
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_20_n_5),
        .O(sel0[6]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_12
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_20_n_6),
        .O(sel0[5]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_13
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_20_n_7),
        .O(sel0[4]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_14
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_21_n_4),
        .O(sel0[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_15
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_21_n_5),
        .O(sel0[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_16
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_21_n_6),
        .O(sel0[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_17
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_21_n_7),
        .O(sel0[0]));
  CARRY4 p_Val2_3_fu_330_p2__0_i_18
       (.CI(p_Val2_3_fu_330_p2__0_i_19_n_0),
        .CO({p_Val2_3_fu_330_p2__0_i_18_n_0,p_Val2_3_fu_330_p2__0_i_18_n_1,p_Val2_3_fu_330_p2__0_i_18_n_2,p_Val2_3_fu_330_p2__0_i_18_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[15] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[14] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[13] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[12] }),
        .O({p_Val2_3_fu_330_p2__0_i_18_n_4,p_Val2_3_fu_330_p2__0_i_18_n_5,p_Val2_3_fu_330_p2__0_i_18_n_6,p_Val2_3_fu_330_p2__0_i_18_n_7}),
        .S({p_Val2_3_fu_330_p2__0_i_22_n_0,p_Val2_3_fu_330_p2__0_i_23_n_0,p_Val2_3_fu_330_p2__0_i_24_n_0,p_Val2_3_fu_330_p2__0_i_25_n_0}));
  CARRY4 p_Val2_3_fu_330_p2__0_i_19
       (.CI(p_Val2_3_fu_330_p2__0_i_20_n_0),
        .CO({p_Val2_3_fu_330_p2__0_i_19_n_0,p_Val2_3_fu_330_p2__0_i_19_n_1,p_Val2_3_fu_330_p2__0_i_19_n_2,p_Val2_3_fu_330_p2__0_i_19_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[11] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[10] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[9] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[8] }),
        .O({p_Val2_3_fu_330_p2__0_i_19_n_4,p_Val2_3_fu_330_p2__0_i_19_n_5,p_Val2_3_fu_330_p2__0_i_19_n_6,p_Val2_3_fu_330_p2__0_i_19_n_7}),
        .S({p_Val2_3_fu_330_p2__0_i_26_n_0,p_Val2_3_fu_330_p2__0_i_27_n_0,p_Val2_3_fu_330_p2__0_i_28_n_0,p_Val2_3_fu_330_p2__0_i_29_n_0}));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_2
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_18_n_4),
        .O(sel0[15]));
  CARRY4 p_Val2_3_fu_330_p2__0_i_20
       (.CI(p_Val2_3_fu_330_p2__0_i_21_n_0),
        .CO({p_Val2_3_fu_330_p2__0_i_20_n_0,p_Val2_3_fu_330_p2__0_i_20_n_1,p_Val2_3_fu_330_p2__0_i_20_n_2,p_Val2_3_fu_330_p2__0_i_20_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[7] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[6] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[5] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[4] }),
        .O({p_Val2_3_fu_330_p2__0_i_20_n_4,p_Val2_3_fu_330_p2__0_i_20_n_5,p_Val2_3_fu_330_p2__0_i_20_n_6,p_Val2_3_fu_330_p2__0_i_20_n_7}),
        .S({p_Val2_3_fu_330_p2__0_i_30_n_0,p_Val2_3_fu_330_p2__0_i_31_n_0,p_Val2_3_fu_330_p2__0_i_32_n_0,p_Val2_3_fu_330_p2__0_i_33_n_0}));
  CARRY4 p_Val2_3_fu_330_p2__0_i_21
       (.CI(\<const0> ),
        .CO({p_Val2_3_fu_330_p2__0_i_21_n_0,p_Val2_3_fu_330_p2__0_i_21_n_1,p_Val2_3_fu_330_p2__0_i_21_n_2,p_Val2_3_fu_330_p2__0_i_21_n_3}),
        .CYINIT(\<const1> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[3] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[2] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[1] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[0] }),
        .O({p_Val2_3_fu_330_p2__0_i_21_n_4,p_Val2_3_fu_330_p2__0_i_21_n_5,p_Val2_3_fu_330_p2__0_i_21_n_6,p_Val2_3_fu_330_p2__0_i_21_n_7}),
        .S({p_Val2_3_fu_330_p2__0_i_34_n_0,p_Val2_3_fu_330_p2__0_i_35_n_0,p_Val2_3_fu_330_p2__0_i_36_n_0,p_Val2_3_fu_330_p2__0_i_37_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_22
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[15] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[15] ),
        .O(p_Val2_3_fu_330_p2__0_i_22_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_23
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[14] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[14] ),
        .O(p_Val2_3_fu_330_p2__0_i_23_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_24
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[13] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[13] ),
        .O(p_Val2_3_fu_330_p2__0_i_24_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_25
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[12] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[12] ),
        .O(p_Val2_3_fu_330_p2__0_i_25_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_26
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[11] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[11] ),
        .O(p_Val2_3_fu_330_p2__0_i_26_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_27
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[10] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[10] ),
        .O(p_Val2_3_fu_330_p2__0_i_27_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_28
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[9] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[9] ),
        .O(p_Val2_3_fu_330_p2__0_i_28_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_29
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[8] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[8] ),
        .O(p_Val2_3_fu_330_p2__0_i_29_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_3
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_18_n_5),
        .O(sel0[14]));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_30
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[7] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[7] ),
        .O(p_Val2_3_fu_330_p2__0_i_30_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_31
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[6] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[6] ),
        .O(p_Val2_3_fu_330_p2__0_i_31_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_32
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[5] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[5] ),
        .O(p_Val2_3_fu_330_p2__0_i_32_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_33
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[4] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[4] ),
        .O(p_Val2_3_fu_330_p2__0_i_33_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_34
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[3] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[3] ),
        .O(p_Val2_3_fu_330_p2__0_i_34_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_35
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[2] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[2] ),
        .O(p_Val2_3_fu_330_p2__0_i_35_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_36
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[1] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[1] ),
        .O(p_Val2_3_fu_330_p2__0_i_36_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2__0_i_37
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[0] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[0] ),
        .O(p_Val2_3_fu_330_p2__0_i_37_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_4
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_18_n_6),
        .O(sel0[13]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_5
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_18_n_7),
        .O(sel0[12]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_6
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_19_n_4),
        .O(sel0[11]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_7
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_19_n_5),
        .O(sel0[10]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_8
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_19_n_6),
        .O(sel0[9]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2__0_i_9
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2__0_i_19_n_7),
        .O(sel0[8]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_1
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_18_n_4),
        .O(sel0[31]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_10
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_20_n_5),
        .O(sel0[22]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_11
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_20_n_6),
        .O(sel0[21]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_12
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_20_n_7),
        .O(sel0[20]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_13
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_21_n_4),
        .O(sel0[19]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_14
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_21_n_5),
        .O(sel0[18]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_15
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_21_n_6),
        .O(sel0[17]));
  CARRY4 p_Val2_3_fu_330_p2_i_16
       (.CI(p_Val2_3_fu_330_p2_i_22_n_0),
        .CO(p_Val2_3_fu_330_p2_i_16_n_3),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .S({\<const0> ,\<const0> ,\<const0> ,\<const1> }));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    p_Val2_3_fu_330_p2_i_17
       (.I0(p_Val2_3_fu_330_p2_i_23_n_0),
        .I1(sel0__0[12]),
        .I2(sel0__0[10]),
        .I3(sel0__0[13]),
        .I4(p_Val2_3_fu_330_p2_i_25_n_0),
        .I5(p_Val2_3_fu_330_p2_i_26_n_0),
        .O(p_Val2_3_fu_330_p2_i_17_n_0));
  CARRY4 p_Val2_3_fu_330_p2_i_18
       (.CI(p_Val2_3_fu_330_p2_i_19_n_0),
        .CO({p_Val2_3_fu_330_p2_i_18_n_0,p_Val2_3_fu_330_p2_i_18_n_1,p_Val2_3_fu_330_p2_i_18_n_2,p_Val2_3_fu_330_p2_i_18_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[31] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[30] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[29] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[28] }),
        .O({p_Val2_3_fu_330_p2_i_18_n_4,p_Val2_3_fu_330_p2_i_18_n_5,p_Val2_3_fu_330_p2_i_18_n_6,p_Val2_3_fu_330_p2_i_18_n_7}),
        .S({p_Val2_3_fu_330_p2_i_27_n_0,p_Val2_3_fu_330_p2_i_28_n_0,p_Val2_3_fu_330_p2_i_29_n_0,p_Val2_3_fu_330_p2_i_30_n_0}));
  CARRY4 p_Val2_3_fu_330_p2_i_19
       (.CI(p_Val2_3_fu_330_p2_i_20_n_0),
        .CO({p_Val2_3_fu_330_p2_i_19_n_0,p_Val2_3_fu_330_p2_i_19_n_1,p_Val2_3_fu_330_p2_i_19_n_2,p_Val2_3_fu_330_p2_i_19_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[27] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[26] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[25] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[24] }),
        .O({p_Val2_3_fu_330_p2_i_19_n_4,p_Val2_3_fu_330_p2_i_19_n_5,p_Val2_3_fu_330_p2_i_19_n_6,p_Val2_3_fu_330_p2_i_19_n_7}),
        .S({p_Val2_3_fu_330_p2_i_31_n_0,p_Val2_3_fu_330_p2_i_32_n_0,p_Val2_3_fu_330_p2_i_33_n_0,p_Val2_3_fu_330_p2_i_34_n_0}));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_2
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_18_n_5),
        .O(sel0[30]));
  CARRY4 p_Val2_3_fu_330_p2_i_20
       (.CI(p_Val2_3_fu_330_p2_i_21_n_0),
        .CO({p_Val2_3_fu_330_p2_i_20_n_0,p_Val2_3_fu_330_p2_i_20_n_1,p_Val2_3_fu_330_p2_i_20_n_2,p_Val2_3_fu_330_p2_i_20_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[23] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[22] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[21] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[20] }),
        .O({p_Val2_3_fu_330_p2_i_20_n_4,p_Val2_3_fu_330_p2_i_20_n_5,p_Val2_3_fu_330_p2_i_20_n_6,p_Val2_3_fu_330_p2_i_20_n_7}),
        .S({p_Val2_3_fu_330_p2_i_35_n_0,p_Val2_3_fu_330_p2_i_36_n_0,p_Val2_3_fu_330_p2_i_37_n_0,p_Val2_3_fu_330_p2_i_38_n_0}));
  CARRY4 p_Val2_3_fu_330_p2_i_21
       (.CI(p_Val2_3_fu_330_p2__0_i_18_n_0),
        .CO({p_Val2_3_fu_330_p2_i_21_n_0,p_Val2_3_fu_330_p2_i_21_n_1,p_Val2_3_fu_330_p2_i_21_n_2,p_Val2_3_fu_330_p2_i_21_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[19] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[18] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[17] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[16] }),
        .O({p_Val2_3_fu_330_p2_i_21_n_4,p_Val2_3_fu_330_p2_i_21_n_5,p_Val2_3_fu_330_p2_i_21_n_6,p_Val2_3_fu_330_p2_i_21_n_7}),
        .S({p_Val2_3_fu_330_p2_i_39_n_0,p_Val2_3_fu_330_p2_i_40_n_0,p_Val2_3_fu_330_p2_i_41_n_0,p_Val2_3_fu_330_p2_i_42_n_0}));
  CARRY4 p_Val2_3_fu_330_p2_i_22
       (.CI(p_Val2_3_fu_330_p2_i_24_n_0),
        .CO({p_Val2_3_fu_330_p2_i_22_n_0,p_Val2_3_fu_330_p2_i_22_n_1,p_Val2_3_fu_330_p2_i_22_n_2,p_Val2_3_fu_330_p2_i_22_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[47] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[46] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[45] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[44] }),
        .O(sel0__0[15:12]),
        .S({p_Val2_3_fu_330_p2_i_43_n_0,p_Val2_3_fu_330_p2_i_44_n_0,p_Val2_3_fu_330_p2_i_45_n_0,p_Val2_3_fu_330_p2_i_46_n_0}));
  LUT4 #(
    .INIT(16'hFFFE)) 
    p_Val2_3_fu_330_p2_i_23
       (.I0(sel0__0[5]),
        .I1(sel0__0[4]),
        .I2(sel0__0[6]),
        .I3(sel0__0[11]),
        .O(p_Val2_3_fu_330_p2_i_23_n_0));
  CARRY4 p_Val2_3_fu_330_p2_i_24
       (.CI(p_Val2_3_fu_330_p2_i_47_n_0),
        .CO({p_Val2_3_fu_330_p2_i_24_n_0,p_Val2_3_fu_330_p2_i_24_n_1,p_Val2_3_fu_330_p2_i_24_n_2,p_Val2_3_fu_330_p2_i_24_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[43] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[42] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[41] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[40] }),
        .O(sel0__0[11:8]),
        .S({p_Val2_3_fu_330_p2_i_48_n_0,p_Val2_3_fu_330_p2_i_49_n_0,p_Val2_3_fu_330_p2_i_50_n_0,p_Val2_3_fu_330_p2_i_51_n_0}));
  LUT4 #(
    .INIT(16'hFFFE)) 
    p_Val2_3_fu_330_p2_i_25
       (.I0(sel0__0[9]),
        .I1(sel0__0[8]),
        .I2(sel0__0[2]),
        .I3(sel0__0[7]),
        .O(p_Val2_3_fu_330_p2_i_25_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    p_Val2_3_fu_330_p2_i_26
       (.I0(sel0__0[1]),
        .I1(sel0__0[0]),
        .I2(sel0__0[3]),
        .I3(sel0__0[15]),
        .I4(sel0__0[14]),
        .I5(p_Val2_3_fu_330_p2_i_16_n_3),
        .O(p_Val2_3_fu_330_p2_i_26_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_27
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[31] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[31] ),
        .O(p_Val2_3_fu_330_p2_i_27_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_28
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[30] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[30] ),
        .O(p_Val2_3_fu_330_p2_i_28_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_29
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[29] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[29] ),
        .O(p_Val2_3_fu_330_p2_i_29_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_3
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_18_n_6),
        .O(sel0[29]));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_30
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[28] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[28] ),
        .O(p_Val2_3_fu_330_p2_i_30_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_31
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[27] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[27] ),
        .O(p_Val2_3_fu_330_p2_i_31_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_32
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[26] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[26] ),
        .O(p_Val2_3_fu_330_p2_i_32_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_33
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[25] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[25] ),
        .O(p_Val2_3_fu_330_p2_i_33_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_34
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[24] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[24] ),
        .O(p_Val2_3_fu_330_p2_i_34_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_35
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[23] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[23] ),
        .O(p_Val2_3_fu_330_p2_i_35_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_36
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[22] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[22] ),
        .O(p_Val2_3_fu_330_p2_i_36_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_37
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[21] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[21] ),
        .O(p_Val2_3_fu_330_p2_i_37_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_38
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[20] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[20] ),
        .O(p_Val2_3_fu_330_p2_i_38_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_39
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[19] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[19] ),
        .O(p_Val2_3_fu_330_p2_i_39_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_4
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_18_n_7),
        .O(sel0[28]));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_40
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[18] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[18] ),
        .O(p_Val2_3_fu_330_p2_i_40_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_41
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[17] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[17] ),
        .O(p_Val2_3_fu_330_p2_i_41_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_42
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[16] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[16] ),
        .O(p_Val2_3_fu_330_p2_i_42_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_43
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[47] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[47] ),
        .O(p_Val2_3_fu_330_p2_i_43_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_44
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[46] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[46] ),
        .O(p_Val2_3_fu_330_p2_i_44_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_45
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[45] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[45] ),
        .O(p_Val2_3_fu_330_p2_i_45_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_46
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[44] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[44] ),
        .O(p_Val2_3_fu_330_p2_i_46_n_0));
  CARRY4 p_Val2_3_fu_330_p2_i_47
       (.CI(p_Val2_3_fu_330_p2_i_52_n_0),
        .CO({p_Val2_3_fu_330_p2_i_47_n_0,p_Val2_3_fu_330_p2_i_47_n_1,p_Val2_3_fu_330_p2_i_47_n_2,p_Val2_3_fu_330_p2_i_47_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[39] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[38] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[37] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[36] }),
        .O(sel0__0[7:4]),
        .S({p_Val2_3_fu_330_p2_i_53_n_0,p_Val2_3_fu_330_p2_i_54_n_0,p_Val2_3_fu_330_p2_i_55_n_0,p_Val2_3_fu_330_p2_i_56_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_48
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[43] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[43] ),
        .O(p_Val2_3_fu_330_p2_i_48_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_49
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[42] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[42] ),
        .O(p_Val2_3_fu_330_p2_i_49_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_5
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_19_n_4),
        .O(sel0[27]));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_50
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[41] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[41] ),
        .O(p_Val2_3_fu_330_p2_i_50_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_51
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[40] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[40] ),
        .O(p_Val2_3_fu_330_p2_i_51_n_0));
  CARRY4 p_Val2_3_fu_330_p2_i_52
       (.CI(p_Val2_3_fu_330_p2_i_18_n_0),
        .CO({p_Val2_3_fu_330_p2_i_52_n_0,p_Val2_3_fu_330_p2_i_52_n_1,p_Val2_3_fu_330_p2_i_52_n_2,p_Val2_3_fu_330_p2_i_52_n_3}),
        .CYINIT(\<const0> ),
        .DI({\inputs_ftw_H1_on_V_preg_reg_n_0_[35] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[34] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[33] ,\inputs_ftw_H1_on_V_preg_reg_n_0_[32] }),
        .O(sel0__0[3:0]),
        .S({p_Val2_3_fu_330_p2_i_57_n_0,p_Val2_3_fu_330_p2_i_58_n_0,p_Val2_3_fu_330_p2_i_59_n_0,p_Val2_3_fu_330_p2_i_60_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_53
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[39] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[39] ),
        .O(p_Val2_3_fu_330_p2_i_53_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_54
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[38] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[38] ),
        .O(p_Val2_3_fu_330_p2_i_54_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_55
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[37] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[37] ),
        .O(p_Val2_3_fu_330_p2_i_55_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_56
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[36] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[36] ),
        .O(p_Val2_3_fu_330_p2_i_56_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_57
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[35] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[35] ),
        .O(p_Val2_3_fu_330_p2_i_57_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_58
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[34] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[34] ),
        .O(p_Val2_3_fu_330_p2_i_58_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_59
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[33] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[33] ),
        .O(p_Val2_3_fu_330_p2_i_59_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_6
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_19_n_5),
        .O(sel0[26]));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_3_fu_330_p2_i_60
       (.I0(\inputs_ftw_H1_on_V_preg_reg_n_0_[32] ),
        .I1(\inputs_ftw_H1_V_preg_reg_n_0_[32] ),
        .O(p_Val2_3_fu_330_p2_i_60_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_7
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_19_n_6),
        .O(sel0[25]));
  LUT3 #(
    .INIT(8'hB8)) 
    p_Val2_3_fu_330_p2_i_8
       (.I0(p_Val2_3_fu_330_p2_i_16_n_3),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_19_n_7),
        .O(sel0[24]));
  LUT3 #(
    .INIT(8'hE2)) 
    p_Val2_3_fu_330_p2_i_9
       (.I0(p_Val2_3_fu_330_p2_i_20_n_4),
        .I1(p_Val2_3_fu_330_p2_i_17_n_0),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .O(sel0[23]));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 15x18 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_5_fu_361_p2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_Val2_5_fu_361_p2_i_3_n_7,p_Val2_5_fu_361_p2_i_4_n_4,p_Val2_5_fu_361_p2_i_4_n_5,p_Val2_5_fu_361_p2_i_4_n_6,p_Val2_5_fu_361_p2_i_4_n_7,p_Val2_5_fu_361_p2_i_5_n_4,p_Val2_5_fu_361_p2_i_5_n_5,p_Val2_5_fu_361_p2_i_5_n_6,p_Val2_5_fu_361_p2_i_5_n_7,p_Val2_5_fu_361_p2_i_6_n_4,p_Val2_5_fu_361_p2_i_6_n_5,p_Val2_5_fu_361_p2_i_6_n_6,p_Val2_5_fu_361_p2_i_6_n_7,p_Val2_5_fu_361_p2_i_7_n_4,p_Val2_5_fu_361_p2_i_7_n_5,p_Val2_5_fu_361_p2_i_7_n_6,p_Val2_5_fu_361_p2_i_7_n_7}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,inputs_offset_H1_V[47:34]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .BCOUT({p_Val2_5_fu_361_p2_n_6,p_Val2_5_fu_361_p2_n_7,p_Val2_5_fu_361_p2_n_8,p_Val2_5_fu_361_p2_n_9,p_Val2_5_fu_361_p2_n_10,p_Val2_5_fu_361_p2_n_11,p_Val2_5_fu_361_p2_n_12,p_Val2_5_fu_361_p2_n_13,p_Val2_5_fu_361_p2_n_14,p_Val2_5_fu_361_p2_n_15,p_Val2_5_fu_361_p2_n_16,p_Val2_5_fu_361_p2_n_17,p_Val2_5_fu_361_p2_n_18,p_Val2_5_fu_361_p2_n_19,p_Val2_5_fu_361_p2_n_20,p_Val2_5_fu_361_p2_n_21,p_Val2_5_fu_361_p2_n_22,p_Val2_5_fu_361_p2_n_23}),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_5_fu_361_p2_i_1_n_0),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(inputs_offset_H1_V_ap_vld_preg0),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_5_fu_361_p2_n_58,p_Val2_5_fu_361_p2_n_59,p_Val2_5_fu_361_p2_n_60,p_Val2_5_fu_361_p2_n_61,p_Val2_5_fu_361_p2_n_62,p_Val2_5_fu_361_p2_n_63,p_Val2_5_fu_361_p2_n_64,p_Val2_5_fu_361_p2_n_65,p_Val2_5_fu_361_p2_n_66,p_Val2_5_fu_361_p2_n_67,p_Val2_5_fu_361_p2_n_68,p_Val2_5_fu_361_p2_n_69,p_Val2_5_fu_361_p2_n_70,p_Val2_5_fu_361_p2_n_71,p_Val2_5_fu_361_p2_n_72,p_Val2_5_fu_361_p2_n_73,p_Val2_5_fu_361_p2_n_74,p_Val2_5_fu_361_p2_n_75,p_Val2_5_fu_361_p2_n_76,p_Val2_5_fu_361_p2_n_77,p_Val2_5_fu_361_p2_n_78,p_Val2_5_fu_361_p2_n_79,p_Val2_5_fu_361_p2_n_80,p_Val2_5_fu_361_p2_n_81,p_Val2_5_fu_361_p2_n_82,p_Val2_5_fu_361_p2_n_83,p_Val2_5_fu_361_p2_n_84,p_Val2_5_fu_361_p2_n_85,p_Val2_5_fu_361_p2_n_86,p_Val2_5_fu_361_p2_n_87,p_Val2_5_fu_361_p2_n_88,p_Val2_5_fu_361_p2_n_89,p_Val2_5_fu_361_p2_n_90,p_Val2_5_fu_361_p2_n_91,p_Val2_5_fu_361_p2_n_92,p_Val2_5_fu_361_p2_n_93,p_Val2_5_fu_361_p2_n_94,p_Val2_5_fu_361_p2_n_95,p_Val2_5_fu_361_p2_n_96,p_Val2_5_fu_361_p2_n_97,p_Val2_5_fu_361_p2_n_98,p_Val2_5_fu_361_p2_n_99,p_Val2_5_fu_361_p2_n_100,p_Val2_5_fu_361_p2_n_101,p_Val2_5_fu_361_p2_n_102,p_Val2_5_fu_361_p2_n_103,p_Val2_5_fu_361_p2_n_104,p_Val2_5_fu_361_p2_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_5_fu_361_p2_n_106,p_Val2_5_fu_361_p2_n_107,p_Val2_5_fu_361_p2_n_108,p_Val2_5_fu_361_p2_n_109,p_Val2_5_fu_361_p2_n_110,p_Val2_5_fu_361_p2_n_111,p_Val2_5_fu_361_p2_n_112,p_Val2_5_fu_361_p2_n_113,p_Val2_5_fu_361_p2_n_114,p_Val2_5_fu_361_p2_n_115,p_Val2_5_fu_361_p2_n_116,p_Val2_5_fu_361_p2_n_117,p_Val2_5_fu_361_p2_n_118,p_Val2_5_fu_361_p2_n_119,p_Val2_5_fu_361_p2_n_120,p_Val2_5_fu_361_p2_n_121,p_Val2_5_fu_361_p2_n_122,p_Val2_5_fu_361_p2_n_123,p_Val2_5_fu_361_p2_n_124,p_Val2_5_fu_361_p2_n_125,p_Val2_5_fu_361_p2_n_126,p_Val2_5_fu_361_p2_n_127,p_Val2_5_fu_361_p2_n_128,p_Val2_5_fu_361_p2_n_129,p_Val2_5_fu_361_p2_n_130,p_Val2_5_fu_361_p2_n_131,p_Val2_5_fu_361_p2_n_132,p_Val2_5_fu_361_p2_n_133,p_Val2_5_fu_361_p2_n_134,p_Val2_5_fu_361_p2_n_135,p_Val2_5_fu_361_p2_n_136,p_Val2_5_fu_361_p2_n_137,p_Val2_5_fu_361_p2_n_138,p_Val2_5_fu_361_p2_n_139,p_Val2_5_fu_361_p2_n_140,p_Val2_5_fu_361_p2_n_141,p_Val2_5_fu_361_p2_n_142,p_Val2_5_fu_361_p2_n_143,p_Val2_5_fu_361_p2_n_144,p_Val2_5_fu_361_p2_n_145,p_Val2_5_fu_361_p2_n_146,p_Val2_5_fu_361_p2_n_147,p_Val2_5_fu_361_p2_n_148,p_Val2_5_fu_361_p2_n_149,p_Val2_5_fu_361_p2_n_150,p_Val2_5_fu_361_p2_n_151,p_Val2_5_fu_361_p2_n_152,p_Val2_5_fu_361_p2_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x18 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_5_fu_361_p2__0
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,inputs_offset_H1_V[33:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACOUT({p_Val2_5_fu_361_p2__0_n_24,p_Val2_5_fu_361_p2__0_n_25,p_Val2_5_fu_361_p2__0_n_26,p_Val2_5_fu_361_p2__0_n_27,p_Val2_5_fu_361_p2__0_n_28,p_Val2_5_fu_361_p2__0_n_29,p_Val2_5_fu_361_p2__0_n_30,p_Val2_5_fu_361_p2__0_n_31,p_Val2_5_fu_361_p2__0_n_32,p_Val2_5_fu_361_p2__0_n_33,p_Val2_5_fu_361_p2__0_n_34,p_Val2_5_fu_361_p2__0_n_35,p_Val2_5_fu_361_p2__0_n_36,p_Val2_5_fu_361_p2__0_n_37,p_Val2_5_fu_361_p2__0_n_38,p_Val2_5_fu_361_p2__0_n_39,p_Val2_5_fu_361_p2__0_n_40,p_Val2_5_fu_361_p2__0_n_41,p_Val2_5_fu_361_p2__0_n_42,p_Val2_5_fu_361_p2__0_n_43,p_Val2_5_fu_361_p2__0_n_44,p_Val2_5_fu_361_p2__0_n_45,p_Val2_5_fu_361_p2__0_n_46,p_Val2_5_fu_361_p2__0_n_47,p_Val2_5_fu_361_p2__0_n_48,p_Val2_5_fu_361_p2__0_n_49,p_Val2_5_fu_361_p2__0_n_50,p_Val2_5_fu_361_p2__0_n_51,p_Val2_5_fu_361_p2__0_n_52,p_Val2_5_fu_361_p2__0_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,p_Val2_5_fu_361_p2_i_3_n_7,p_Val2_5_fu_361_p2_i_4_n_4,p_Val2_5_fu_361_p2_i_4_n_5,p_Val2_5_fu_361_p2_i_4_n_6,p_Val2_5_fu_361_p2_i_4_n_7,p_Val2_5_fu_361_p2_i_5_n_4,p_Val2_5_fu_361_p2_i_5_n_5,p_Val2_5_fu_361_p2_i_5_n_6,p_Val2_5_fu_361_p2_i_5_n_7,p_Val2_5_fu_361_p2_i_6_n_4,p_Val2_5_fu_361_p2_i_6_n_5,p_Val2_5_fu_361_p2_i_6_n_6,p_Val2_5_fu_361_p2_i_6_n_7,p_Val2_5_fu_361_p2_i_7_n_4,p_Val2_5_fu_361_p2_i_7_n_5,p_Val2_5_fu_361_p2_i_7_n_6,p_Val2_5_fu_361_p2_i_7_n_7}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(inputs_offset_H1_V_ap_vld_preg0),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_5_fu_361_p2_i_1_n_0),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_5_fu_361_p2__0_n_58,p_Val2_5_fu_361_p2__0_n_59,p_Val2_5_fu_361_p2__0_n_60,p_Val2_5_fu_361_p2__0_n_61,p_Val2_5_fu_361_p2__0_n_62,p_Val2_5_fu_361_p2__0_n_63,p_Val2_5_fu_361_p2__0_n_64,p_Val2_5_fu_361_p2__0_n_65,p_Val2_5_fu_361_p2__0_n_66,p_Val2_5_fu_361_p2__0_n_67,p_Val2_5_fu_361_p2__0_n_68,p_Val2_5_fu_361_p2__0_n_69,p_Val2_5_fu_361_p2__0_n_70,p_Val2_5_fu_361_p2__0_n_71,p_Val2_5_fu_361_p2__0_n_72,p_Val2_5_fu_361_p2__0_n_73,p_Val2_5_fu_361_p2__0_n_74,p_Val2_5_fu_361_p2__0_n_75,p_Val2_5_fu_361_p2__0_n_76,p_Val2_5_fu_361_p2__0_n_77,p_Val2_5_fu_361_p2__0_n_78,p_Val2_5_fu_361_p2__0_n_79,p_Val2_5_fu_361_p2__0_n_80,p_Val2_5_fu_361_p2__0_n_81,p_Val2_5_fu_361_p2__0_n_82,p_Val2_5_fu_361_p2__0_n_83,p_Val2_5_fu_361_p2__0_n_84,p_Val2_5_fu_361_p2__0_n_85,p_Val2_5_fu_361_p2__0_n_86,p_Val2_5_fu_361_p2__0_n_87,p_Val2_5_fu_361_p2__0_n_88,p_Val2_5_fu_361_p2__0_n_89,p_Val2_5_fu_361_p2__0_n_90,p_Val2_5_fu_361_p2__0_n_91,p_Val2_5_fu_361_p2__0_n_92,p_Val2_5_fu_361_p2__0_n_93,p_Val2_5_fu_361_p2__0_n_94,p_Val2_5_fu_361_p2__0_n_95,p_Val2_5_fu_361_p2__0_n_96,p_Val2_5_fu_361_p2__0_n_97,p_Val2_5_fu_361_p2__0_n_98,p_Val2_5_fu_361_p2__0_n_99,p_Val2_5_fu_361_p2__0_n_100,p_Val2_5_fu_361_p2__0_n_101,p_Val2_5_fu_361_p2__0_n_102,p_Val2_5_fu_361_p2__0_n_103,p_Val2_5_fu_361_p2__0_n_104,p_Val2_5_fu_361_p2__0_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_5_fu_361_p2__0_n_106,p_Val2_5_fu_361_p2__0_n_107,p_Val2_5_fu_361_p2__0_n_108,p_Val2_5_fu_361_p2__0_n_109,p_Val2_5_fu_361_p2__0_n_110,p_Val2_5_fu_361_p2__0_n_111,p_Val2_5_fu_361_p2__0_n_112,p_Val2_5_fu_361_p2__0_n_113,p_Val2_5_fu_361_p2__0_n_114,p_Val2_5_fu_361_p2__0_n_115,p_Val2_5_fu_361_p2__0_n_116,p_Val2_5_fu_361_p2__0_n_117,p_Val2_5_fu_361_p2__0_n_118,p_Val2_5_fu_361_p2__0_n_119,p_Val2_5_fu_361_p2__0_n_120,p_Val2_5_fu_361_p2__0_n_121,p_Val2_5_fu_361_p2__0_n_122,p_Val2_5_fu_361_p2__0_n_123,p_Val2_5_fu_361_p2__0_n_124,p_Val2_5_fu_361_p2__0_n_125,p_Val2_5_fu_361_p2__0_n_126,p_Val2_5_fu_361_p2__0_n_127,p_Val2_5_fu_361_p2__0_n_128,p_Val2_5_fu_361_p2__0_n_129,p_Val2_5_fu_361_p2__0_n_130,p_Val2_5_fu_361_p2__0_n_131,p_Val2_5_fu_361_p2__0_n_132,p_Val2_5_fu_361_p2__0_n_133,p_Val2_5_fu_361_p2__0_n_134,p_Val2_5_fu_361_p2__0_n_135,p_Val2_5_fu_361_p2__0_n_136,p_Val2_5_fu_361_p2__0_n_137,p_Val2_5_fu_361_p2__0_n_138,p_Val2_5_fu_361_p2__0_n_139,p_Val2_5_fu_361_p2__0_n_140,p_Val2_5_fu_361_p2__0_n_141,p_Val2_5_fu_361_p2__0_n_142,p_Val2_5_fu_361_p2__0_n_143,p_Val2_5_fu_361_p2__0_n_144,p_Val2_5_fu_361_p2__0_n_145,p_Val2_5_fu_361_p2__0_n_146,p_Val2_5_fu_361_p2__0_n_147,p_Val2_5_fu_361_p2__0_n_148,p_Val2_5_fu_361_p2__0_n_149,p_Val2_5_fu_361_p2__0_n_150,p_Val2_5_fu_361_p2__0_n_151,p_Val2_5_fu_361_p2__0_n_152,p_Val2_5_fu_361_p2__0_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x18 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_5_fu_361_p2__1
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,inputs_offset_H1_V[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACOUT({p_Val2_5_fu_361_p2__1_n_24,p_Val2_5_fu_361_p2__1_n_25,p_Val2_5_fu_361_p2__1_n_26,p_Val2_5_fu_361_p2__1_n_27,p_Val2_5_fu_361_p2__1_n_28,p_Val2_5_fu_361_p2__1_n_29,p_Val2_5_fu_361_p2__1_n_30,p_Val2_5_fu_361_p2__1_n_31,p_Val2_5_fu_361_p2__1_n_32,p_Val2_5_fu_361_p2__1_n_33,p_Val2_5_fu_361_p2__1_n_34,p_Val2_5_fu_361_p2__1_n_35,p_Val2_5_fu_361_p2__1_n_36,p_Val2_5_fu_361_p2__1_n_37,p_Val2_5_fu_361_p2__1_n_38,p_Val2_5_fu_361_p2__1_n_39,p_Val2_5_fu_361_p2__1_n_40,p_Val2_5_fu_361_p2__1_n_41,p_Val2_5_fu_361_p2__1_n_42,p_Val2_5_fu_361_p2__1_n_43,p_Val2_5_fu_361_p2__1_n_44,p_Val2_5_fu_361_p2__1_n_45,p_Val2_5_fu_361_p2__1_n_46,p_Val2_5_fu_361_p2__1_n_47,p_Val2_5_fu_361_p2__1_n_48,p_Val2_5_fu_361_p2__1_n_49,p_Val2_5_fu_361_p2__1_n_50,p_Val2_5_fu_361_p2__1_n_51,p_Val2_5_fu_361_p2__1_n_52,p_Val2_5_fu_361_p2__1_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,p_Val2_5_fu_361_p2_i_3_n_7,p_Val2_5_fu_361_p2_i_4_n_4,p_Val2_5_fu_361_p2_i_4_n_5,p_Val2_5_fu_361_p2_i_4_n_6,p_Val2_5_fu_361_p2_i_4_n_7,p_Val2_5_fu_361_p2_i_5_n_4,p_Val2_5_fu_361_p2_i_5_n_5,p_Val2_5_fu_361_p2_i_5_n_6,p_Val2_5_fu_361_p2_i_5_n_7,p_Val2_5_fu_361_p2_i_6_n_4,p_Val2_5_fu_361_p2_i_6_n_5,p_Val2_5_fu_361_p2_i_6_n_6,p_Val2_5_fu_361_p2_i_6_n_7,p_Val2_5_fu_361_p2_i_7_n_4,p_Val2_5_fu_361_p2_i_7_n_5,p_Val2_5_fu_361_p2_i_7_n_6,p_Val2_5_fu_361_p2_i_7_n_7}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(inputs_offset_H1_V_ap_vld_preg0),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_5_fu_361_p2_i_1_n_0),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_5_fu_361_p2__1_n_58,p_Val2_5_fu_361_p2__1_n_59,p_Val2_5_fu_361_p2__1_n_60,p_Val2_5_fu_361_p2__1_n_61,p_Val2_5_fu_361_p2__1_n_62,p_Val2_5_fu_361_p2__1_n_63,p_Val2_5_fu_361_p2__1_n_64,p_Val2_5_fu_361_p2__1_n_65,p_Val2_5_fu_361_p2__1_n_66,p_Val2_5_fu_361_p2__1_n_67,p_Val2_5_fu_361_p2__1_n_68,p_Val2_5_fu_361_p2__1_n_69,p_Val2_5_fu_361_p2__1_n_70,p_Val2_5_fu_361_p2__1_n_71,p_Val2_5_fu_361_p2__1_n_72,p_Val2_5_fu_361_p2__1_n_73,p_Val2_5_fu_361_p2__1_n_74,p_Val2_5_fu_361_p2__1_n_75,p_Val2_5_fu_361_p2__1_n_76,p_Val2_5_fu_361_p2__1_n_77,p_Val2_5_fu_361_p2__1_n_78,p_Val2_5_fu_361_p2__1_n_79,p_Val2_5_fu_361_p2__1_n_80,p_Val2_5_fu_361_p2__1_n_81,p_Val2_5_fu_361_p2__1_n_82,p_Val2_5_fu_361_p2__1_n_83,p_Val2_5_fu_361_p2__1_n_84,p_Val2_5_fu_361_p2__1_n_85,p_Val2_5_fu_361_p2__1_n_86,p_Val2_5_fu_361_p2__1_n_87,p_Val2_5_fu_361_p2__1_n_88,p_Val2_5_fu_361_p2__1_n_89,p_Val2_5_fu_361_p2__1_n_90,p_Val2_5_fu_361_p2__1_n_91,p_Val2_5_fu_361_p2__1_n_92,p_Val2_5_fu_361_p2__1_n_93,p_Val2_5_fu_361_p2__1_n_94,p_Val2_5_fu_361_p2__1_n_95,p_Val2_5_fu_361_p2__1_n_96,p_Val2_5_fu_361_p2__1_n_97,p_Val2_5_fu_361_p2__1_n_98,p_Val2_5_fu_361_p2__1_n_99,p_Val2_5_fu_361_p2__1_n_100,p_Val2_5_fu_361_p2__1_n_101,p_Val2_5_fu_361_p2__1_n_102,p_Val2_5_fu_361_p2__1_n_103,p_Val2_5_fu_361_p2__1_n_104,p_Val2_5_fu_361_p2__1_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_5_fu_361_p2__1_n_106,p_Val2_5_fu_361_p2__1_n_107,p_Val2_5_fu_361_p2__1_n_108,p_Val2_5_fu_361_p2__1_n_109,p_Val2_5_fu_361_p2__1_n_110,p_Val2_5_fu_361_p2__1_n_111,p_Val2_5_fu_361_p2__1_n_112,p_Val2_5_fu_361_p2__1_n_113,p_Val2_5_fu_361_p2__1_n_114,p_Val2_5_fu_361_p2__1_n_115,p_Val2_5_fu_361_p2__1_n_116,p_Val2_5_fu_361_p2__1_n_117,p_Val2_5_fu_361_p2__1_n_118,p_Val2_5_fu_361_p2__1_n_119,p_Val2_5_fu_361_p2__1_n_120,p_Val2_5_fu_361_p2__1_n_121,p_Val2_5_fu_361_p2__1_n_122,p_Val2_5_fu_361_p2__1_n_123,p_Val2_5_fu_361_p2__1_n_124,p_Val2_5_fu_361_p2__1_n_125,p_Val2_5_fu_361_p2__1_n_126,p_Val2_5_fu_361_p2__1_n_127,p_Val2_5_fu_361_p2__1_n_128,p_Val2_5_fu_361_p2__1_n_129,p_Val2_5_fu_361_p2__1_n_130,p_Val2_5_fu_361_p2__1_n_131,p_Val2_5_fu_361_p2__1_n_132,p_Val2_5_fu_361_p2__1_n_133,p_Val2_5_fu_361_p2__1_n_134,p_Val2_5_fu_361_p2__1_n_135,p_Val2_5_fu_361_p2__1_n_136,p_Val2_5_fu_361_p2__1_n_137,p_Val2_5_fu_361_p2__1_n_138,p_Val2_5_fu_361_p2__1_n_139,p_Val2_5_fu_361_p2__1_n_140,p_Val2_5_fu_361_p2__1_n_141,p_Val2_5_fu_361_p2__1_n_142,p_Val2_5_fu_361_p2__1_n_143,p_Val2_5_fu_361_p2__1_n_144,p_Val2_5_fu_361_p2__1_n_145,p_Val2_5_fu_361_p2__1_n_146,p_Val2_5_fu_361_p2__1_n_147,p_Val2_5_fu_361_p2__1_n_148,p_Val2_5_fu_361_p2__1_n_149,p_Val2_5_fu_361_p2__1_n_150,p_Val2_5_fu_361_p2__1_n_151,p_Val2_5_fu_361_p2__1_n_152,p_Val2_5_fu_361_p2__1_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  LUT2 #(
    .INIT(4'h2)) 
    p_Val2_5_fu_361_p2_i_1
       (.I0(ap_CS_fsm_state76),
        .I1(or_cond_reg_403),
        .O(p_Val2_5_fu_361_p2_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_10
       (.I0(p_Val2_4_reg_423_reg[17]),
        .O(p_Val2_5_fu_361_p2_i_10_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_11
       (.I0(p_Val2_4_reg_423_reg[16]),
        .O(p_Val2_5_fu_361_p2_i_11_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_12
       (.I0(p_Val2_4_reg_423_reg[15]),
        .O(p_Val2_5_fu_361_p2_i_12_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_13
       (.I0(p_Val2_4_reg_423_reg[14]),
        .O(p_Val2_5_fu_361_p2_i_13_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_14
       (.I0(p_Val2_4_reg_423_reg[13]),
        .O(p_Val2_5_fu_361_p2_i_14_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_15
       (.I0(p_Val2_4_reg_423_reg[12]),
        .O(p_Val2_5_fu_361_p2_i_15_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_16
       (.I0(p_Val2_4_reg_423_reg[11]),
        .O(p_Val2_5_fu_361_p2_i_16_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_17
       (.I0(p_Val2_4_reg_423_reg[10]),
        .O(p_Val2_5_fu_361_p2_i_17_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_18
       (.I0(p_Val2_4_reg_423_reg[9]),
        .O(p_Val2_5_fu_361_p2_i_18_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_19
       (.I0(p_Val2_4_reg_423_reg[8]),
        .O(p_Val2_5_fu_361_p2_i_19_n_0));
  LUT3 #(
    .INIT(8'hD0)) 
    p_Val2_5_fu_361_p2_i_2
       (.I0(\ap_CS_fsm_reg_n_0_[0] ),
        .I1(ap_start),
        .I2(inputs_offset_H1_V_ap_vld),
        .O(inputs_offset_H1_V_ap_vld_preg0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_20
       (.I0(p_Val2_4_reg_423_reg[7]),
        .O(p_Val2_5_fu_361_p2_i_20_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_21
       (.I0(p_Val2_4_reg_423_reg[6]),
        .O(p_Val2_5_fu_361_p2_i_21_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_22
       (.I0(p_Val2_4_reg_423_reg[5]),
        .O(p_Val2_5_fu_361_p2_i_22_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_23
       (.I0(p_Val2_4_reg_423_reg[4]),
        .O(p_Val2_5_fu_361_p2_i_23_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_24
       (.I0(p_Val2_4_reg_423_reg[3]),
        .O(p_Val2_5_fu_361_p2_i_24_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_25
       (.I0(p_Val2_4_reg_423_reg[2]),
        .O(p_Val2_5_fu_361_p2_i_25_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_26
       (.I0(p_Val2_4_reg_423_reg[1]),
        .O(p_Val2_5_fu_361_p2_i_26_n_0));
  CARRY4 p_Val2_5_fu_361_p2_i_3
       (.CI(p_Val2_5_fu_361_p2_i_4_n_0),
        .CO({p_Val2_5_fu_361_p2_i_3_n_0,p_Val2_5_fu_361_p2_i_3_n_1,p_Val2_5_fu_361_p2_i_3_n_2,p_Val2_5_fu_361_p2_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_5_fu_361_p2_i_3_n_4,p_Val2_5_fu_361_p2_i_3_n_5,p_Val2_5_fu_361_p2_i_3_n_6,p_Val2_5_fu_361_p2_i_3_n_7}),
        .S({p_Val2_5_fu_361_p2_i_8_n_0,p_Val2_5_fu_361_p2_i_9_n_0,p_Val2_5_fu_361_p2_i_10_n_0,p_Val2_5_fu_361_p2_i_11_n_0}));
  CARRY4 p_Val2_5_fu_361_p2_i_4
       (.CI(p_Val2_5_fu_361_p2_i_5_n_0),
        .CO({p_Val2_5_fu_361_p2_i_4_n_0,p_Val2_5_fu_361_p2_i_4_n_1,p_Val2_5_fu_361_p2_i_4_n_2,p_Val2_5_fu_361_p2_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_5_fu_361_p2_i_4_n_4,p_Val2_5_fu_361_p2_i_4_n_5,p_Val2_5_fu_361_p2_i_4_n_6,p_Val2_5_fu_361_p2_i_4_n_7}),
        .S({p_Val2_5_fu_361_p2_i_12_n_0,p_Val2_5_fu_361_p2_i_13_n_0,p_Val2_5_fu_361_p2_i_14_n_0,p_Val2_5_fu_361_p2_i_15_n_0}));
  CARRY4 p_Val2_5_fu_361_p2_i_5
       (.CI(p_Val2_5_fu_361_p2_i_6_n_0),
        .CO({p_Val2_5_fu_361_p2_i_5_n_0,p_Val2_5_fu_361_p2_i_5_n_1,p_Val2_5_fu_361_p2_i_5_n_2,p_Val2_5_fu_361_p2_i_5_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_5_fu_361_p2_i_5_n_4,p_Val2_5_fu_361_p2_i_5_n_5,p_Val2_5_fu_361_p2_i_5_n_6,p_Val2_5_fu_361_p2_i_5_n_7}),
        .S({p_Val2_5_fu_361_p2_i_16_n_0,p_Val2_5_fu_361_p2_i_17_n_0,p_Val2_5_fu_361_p2_i_18_n_0,p_Val2_5_fu_361_p2_i_19_n_0}));
  CARRY4 p_Val2_5_fu_361_p2_i_6
       (.CI(p_Val2_5_fu_361_p2_i_7_n_0),
        .CO({p_Val2_5_fu_361_p2_i_6_n_0,p_Val2_5_fu_361_p2_i_6_n_1,p_Val2_5_fu_361_p2_i_6_n_2,p_Val2_5_fu_361_p2_i_6_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_5_fu_361_p2_i_6_n_4,p_Val2_5_fu_361_p2_i_6_n_5,p_Val2_5_fu_361_p2_i_6_n_6,p_Val2_5_fu_361_p2_i_6_n_7}),
        .S({p_Val2_5_fu_361_p2_i_20_n_0,p_Val2_5_fu_361_p2_i_21_n_0,p_Val2_5_fu_361_p2_i_22_n_0,p_Val2_5_fu_361_p2_i_23_n_0}));
  CARRY4 p_Val2_5_fu_361_p2_i_7
       (.CI(\<const0> ),
        .CO({p_Val2_5_fu_361_p2_i_7_n_0,p_Val2_5_fu_361_p2_i_7_n_1,p_Val2_5_fu_361_p2_i_7_n_2,p_Val2_5_fu_361_p2_i_7_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }),
        .O({p_Val2_5_fu_361_p2_i_7_n_4,p_Val2_5_fu_361_p2_i_7_n_5,p_Val2_5_fu_361_p2_i_7_n_6,p_Val2_5_fu_361_p2_i_7_n_7}),
        .S({p_Val2_5_fu_361_p2_i_24_n_0,p_Val2_5_fu_361_p2_i_25_n_0,p_Val2_5_fu_361_p2_i_26_n_0,p_Val2_4_reg_423_reg[0]}));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_8
       (.I0(p_Val2_4_reg_423_reg[19]),
        .O(p_Val2_5_fu_361_p2_i_8_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_5_fu_361_p2_i_9
       (.I0(p_Val2_4_reg_423_reg[18]),
        .O(p_Val2_5_fu_361_p2_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 21x18 4}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_6_fu_302_p2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,FTW_comp_V_fu_278_p3[36:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACOUT({p_Val2_6_fu_302_p2_n_24,p_Val2_6_fu_302_p2_n_25,p_Val2_6_fu_302_p2_n_26,p_Val2_6_fu_302_p2_n_27,p_Val2_6_fu_302_p2_n_28,p_Val2_6_fu_302_p2_n_29,p_Val2_6_fu_302_p2_n_30,p_Val2_6_fu_302_p2_n_31,p_Val2_6_fu_302_p2_n_32,p_Val2_6_fu_302_p2_n_33,p_Val2_6_fu_302_p2_n_34,p_Val2_6_fu_302_p2_n_35,p_Val2_6_fu_302_p2_n_36,p_Val2_6_fu_302_p2_n_37,p_Val2_6_fu_302_p2_n_38,p_Val2_6_fu_302_p2_n_39,p_Val2_6_fu_302_p2_n_40,p_Val2_6_fu_302_p2_n_41,p_Val2_6_fu_302_p2_n_42,p_Val2_6_fu_302_p2_n_43,p_Val2_6_fu_302_p2_n_44,p_Val2_6_fu_302_p2_n_45,p_Val2_6_fu_302_p2_n_46,p_Val2_6_fu_302_p2_n_47,p_Val2_6_fu_302_p2_n_48,p_Val2_6_fu_302_p2_n_49,p_Val2_6_fu_302_p2_n_50,p_Val2_6_fu_302_p2_n_51,p_Val2_6_fu_302_p2_n_52,p_Val2_6_fu_302_p2_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,p_Val2_6_fu_302_p2_i_1_n_7,p_Val2_6_fu_302_p2_i_2_n_4,p_Val2_6_fu_302_p2_i_2_n_5,p_Val2_6_fu_302_p2_i_2_n_6,p_Val2_6_fu_302_p2_i_2_n_7,p_Val2_6_fu_302_p2_i_3_n_4,p_Val2_6_fu_302_p2_i_3_n_5,p_Val2_6_fu_302_p2_i_3_n_6,p_Val2_6_fu_302_p2_i_3_n_7,p_Val2_6_fu_302_p2_i_4_n_4,p_Val2_6_fu_302_p2_i_4_n_5,p_Val2_6_fu_302_p2_i_4_n_6,p_Val2_6_fu_302_p2_i_4_n_7,p_Val2_6_fu_302_p2_i_5_n_4,p_Val2_6_fu_302_p2_i_5_n_5,p_Val2_6_fu_302_p2_i_5_n_6,p_Val2_6_fu_302_p2_i_5_n_7}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(start),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(start),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_6_fu_302_p2_n_58,p_Val2_6_fu_302_p2_n_59,p_Val2_6_fu_302_p2_n_60,p_Val2_6_fu_302_p2_n_61,p_Val2_6_fu_302_p2_n_62,p_Val2_6_fu_302_p2_n_63,p_Val2_6_fu_302_p2_n_64,p_Val2_6_fu_302_p2_n_65,p_Val2_6_fu_302_p2_n_66,p_Val2_6_fu_302_p2_n_67,p_Val2_6_fu_302_p2_n_68,p_Val2_6_fu_302_p2_n_69,p_Val2_6_fu_302_p2_n_70,p_Val2_6_fu_302_p2_n_71,p_Val2_6_fu_302_p2_n_72,p_Val2_6_fu_302_p2_n_73,p_Val2_6_fu_302_p2_n_74,p_Val2_6_fu_302_p2_n_75,p_Val2_6_fu_302_p2_n_76,p_Val2_6_fu_302_p2_n_77,p_Val2_6_fu_302_p2_n_78,p_Val2_6_fu_302_p2_n_79,p_Val2_6_fu_302_p2_n_80,p_Val2_6_fu_302_p2_n_81,p_Val2_6_fu_302_p2_n_82,p_Val2_6_fu_302_p2_n_83,p_Val2_6_fu_302_p2_n_84,p_Val2_6_fu_302_p2_n_85,p_Val2_6_fu_302_p2_n_86,p_Val2_6_fu_302_p2_n_87,p_Val2_6_fu_302_p2_n_88,p_Val2_6_fu_302_p2_n_89,p_Val2_6_fu_302_p2_n_90,p_Val2_6_fu_302_p2_n_91,p_Val2_6_fu_302_p2_n_92,p_Val2_6_fu_302_p2_n_93,p_Val2_6_fu_302_p2_n_94,p_Val2_6_fu_302_p2_n_95,p_Val2_6_fu_302_p2_n_96,p_Val2_6_fu_302_p2_n_97,p_Val2_6_fu_302_p2_n_98,p_Val2_6_fu_302_p2_n_99,p_Val2_6_fu_302_p2_n_100,p_Val2_6_fu_302_p2_n_101,p_Val2_6_fu_302_p2_n_102,p_Val2_6_fu_302_p2_n_103,p_Val2_6_fu_302_p2_n_104,p_Val2_6_fu_302_p2_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_6_fu_302_p2_n_106,p_Val2_6_fu_302_p2_n_107,p_Val2_6_fu_302_p2_n_108,p_Val2_6_fu_302_p2_n_109,p_Val2_6_fu_302_p2_n_110,p_Val2_6_fu_302_p2_n_111,p_Val2_6_fu_302_p2_n_112,p_Val2_6_fu_302_p2_n_113,p_Val2_6_fu_302_p2_n_114,p_Val2_6_fu_302_p2_n_115,p_Val2_6_fu_302_p2_n_116,p_Val2_6_fu_302_p2_n_117,p_Val2_6_fu_302_p2_n_118,p_Val2_6_fu_302_p2_n_119,p_Val2_6_fu_302_p2_n_120,p_Val2_6_fu_302_p2_n_121,p_Val2_6_fu_302_p2_n_122,p_Val2_6_fu_302_p2_n_123,p_Val2_6_fu_302_p2_n_124,p_Val2_6_fu_302_p2_n_125,p_Val2_6_fu_302_p2_n_126,p_Val2_6_fu_302_p2_n_127,p_Val2_6_fu_302_p2_n_128,p_Val2_6_fu_302_p2_n_129,p_Val2_6_fu_302_p2_n_130,p_Val2_6_fu_302_p2_n_131,p_Val2_6_fu_302_p2_n_132,p_Val2_6_fu_302_p2_n_133,p_Val2_6_fu_302_p2_n_134,p_Val2_6_fu_302_p2_n_135,p_Val2_6_fu_302_p2_n_136,p_Val2_6_fu_302_p2_n_137,p_Val2_6_fu_302_p2_n_138,p_Val2_6_fu_302_p2_n_139,p_Val2_6_fu_302_p2_n_140,p_Val2_6_fu_302_p2_n_141,p_Val2_6_fu_302_p2_n_142,p_Val2_6_fu_302_p2_n_143,p_Val2_6_fu_302_p2_n_144,p_Val2_6_fu_302_p2_n_145,p_Val2_6_fu_302_p2_n_146,p_Val2_6_fu_302_p2_n_147,p_Val2_6_fu_302_p2_n_148,p_Val2_6_fu_302_p2_n_149,p_Val2_6_fu_302_p2_n_150,p_Val2_6_fu_302_p2_n_151,p_Val2_6_fu_302_p2_n_152,p_Val2_6_fu_302_p2_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 21x16 4}}" *) 
  DSP48E1 #(
    .ACASCREG(0),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(0),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("CASCADE"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_6_fu_302_p2__0
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACIN({p_Val2_6_fu_302_p2_n_24,p_Val2_6_fu_302_p2_n_25,p_Val2_6_fu_302_p2_n_26,p_Val2_6_fu_302_p2_n_27,p_Val2_6_fu_302_p2_n_28,p_Val2_6_fu_302_p2_n_29,p_Val2_6_fu_302_p2_n_30,p_Val2_6_fu_302_p2_n_31,p_Val2_6_fu_302_p2_n_32,p_Val2_6_fu_302_p2_n_33,p_Val2_6_fu_302_p2_n_34,p_Val2_6_fu_302_p2_n_35,p_Val2_6_fu_302_p2_n_36,p_Val2_6_fu_302_p2_n_37,p_Val2_6_fu_302_p2_n_38,p_Val2_6_fu_302_p2_n_39,p_Val2_6_fu_302_p2_n_40,p_Val2_6_fu_302_p2_n_41,p_Val2_6_fu_302_p2_n_42,p_Val2_6_fu_302_p2_n_43,p_Val2_6_fu_302_p2_n_44,p_Val2_6_fu_302_p2_n_45,p_Val2_6_fu_302_p2_n_46,p_Val2_6_fu_302_p2_n_47,p_Val2_6_fu_302_p2_n_48,p_Val2_6_fu_302_p2_n_49,p_Val2_6_fu_302_p2_n_50,p_Val2_6_fu_302_p2_n_51,p_Val2_6_fu_302_p2_n_52,p_Val2_6_fu_302_p2_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({p_Val2_6_fu_302_p2__0_i_1_n_7,p_Val2_6_fu_302_p2__0_i_1_n_7,p_Val2_6_fu_302_p2__0_i_1_n_7,p_Val2_6_fu_302_p2__0_i_2_n_4,p_Val2_6_fu_302_p2__0_i_2_n_5,p_Val2_6_fu_302_p2__0_i_2_n_6,p_Val2_6_fu_302_p2__0_i_2_n_7,p_Val2_6_fu_302_p2__0_i_3_n_4,p_Val2_6_fu_302_p2__0_i_3_n_5,p_Val2_6_fu_302_p2__0_i_3_n_6,p_Val2_6_fu_302_p2__0_i_3_n_7,p_Val2_6_fu_302_p2__0_i_4_n_4,p_Val2_6_fu_302_p2__0_i_4_n_5,p_Val2_6_fu_302_p2__0_i_4_n_6,p_Val2_6_fu_302_p2__0_i_4_n_7,p_Val2_6_fu_302_p2_i_1_n_4,p_Val2_6_fu_302_p2_i_1_n_5,p_Val2_6_fu_302_p2_i_1_n_6}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(\<const0> ),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(start),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_6_fu_302_p2__0_n_58,p_Val2_6_fu_302_p2__0_n_59,p_Val2_6_fu_302_p2__0_n_60,p_Val2_6_fu_302_p2__0_n_61,p_Val2_6_fu_302_p2__0_n_62,p_Val2_6_fu_302_p2__0_n_63,p_Val2_6_fu_302_p2__0_n_64,p_Val2_6_fu_302_p2__0_n_65,p_Val2_6_fu_302_p2__0_n_66,p_Val2_6_fu_302_p2__0_n_67,p_Val2_6_fu_302_p2__0_n_68,p_Val2_6_fu_302_p2__0_n_69,p_Val2_6_fu_302_p2__0_n_70,p_Val2_6_fu_302_p2__0_n_71,p_Val2_6_fu_302_p2__0_n_72,p_Val2_6_fu_302_p2__0_n_73,p_Val2_6_fu_302_p2__0_n_74,p_Val2_6_fu_302_p2__0_n_75,p_Val2_6_fu_302_p2__0_n_76,p_Val2_6_fu_302_p2__0_n_77,p_Val2_6_fu_302_p2__0_n_78,p_Val2_6_fu_302_p2__0_n_79,p_Val2_6_fu_302_p2__0_n_80,p_Val2_6_fu_302_p2__0_n_81,p_Val2_6_fu_302_p2__0_n_82,p_Val2_6_fu_302_p2__0_n_83,p_Val2_6_fu_302_p2__0_n_84,p_Val2_6_fu_302_p2__0_n_85,p_Val2_6_fu_302_p2__0_n_86,p_Val2_6_fu_302_p2__0_n_87,p_Val2_6_fu_302_p2__0_n_88,p_Val2_6_fu_302_p2__0_n_89,p_Val2_6_fu_302_p2__0_n_90,p_Val2_6_fu_302_p2__0_n_91,p_Val2_6_fu_302_p2__0_n_92,p_Val2_6_fu_302_p2__0_n_93,p_Val2_6_fu_302_p2__0_n_94,p_Val2_6_fu_302_p2__0_n_95,p_Val2_6_fu_302_p2__0_n_96,p_Val2_6_fu_302_p2__0_n_97,p_Val2_6_fu_302_p2__0_n_98,p_Val2_6_fu_302_p2__0_n_99,p_Val2_6_fu_302_p2__0_n_100,p_Val2_6_fu_302_p2__0_n_101,p_Val2_6_fu_302_p2__0_n_102,p_Val2_6_fu_302_p2__0_n_103,p_Val2_6_fu_302_p2__0_n_104,p_Val2_6_fu_302_p2__0_n_105}),
        .PCIN({p_Val2_6_fu_302_p2_n_106,p_Val2_6_fu_302_p2_n_107,p_Val2_6_fu_302_p2_n_108,p_Val2_6_fu_302_p2_n_109,p_Val2_6_fu_302_p2_n_110,p_Val2_6_fu_302_p2_n_111,p_Val2_6_fu_302_p2_n_112,p_Val2_6_fu_302_p2_n_113,p_Val2_6_fu_302_p2_n_114,p_Val2_6_fu_302_p2_n_115,p_Val2_6_fu_302_p2_n_116,p_Val2_6_fu_302_p2_n_117,p_Val2_6_fu_302_p2_n_118,p_Val2_6_fu_302_p2_n_119,p_Val2_6_fu_302_p2_n_120,p_Val2_6_fu_302_p2_n_121,p_Val2_6_fu_302_p2_n_122,p_Val2_6_fu_302_p2_n_123,p_Val2_6_fu_302_p2_n_124,p_Val2_6_fu_302_p2_n_125,p_Val2_6_fu_302_p2_n_126,p_Val2_6_fu_302_p2_n_127,p_Val2_6_fu_302_p2_n_128,p_Val2_6_fu_302_p2_n_129,p_Val2_6_fu_302_p2_n_130,p_Val2_6_fu_302_p2_n_131,p_Val2_6_fu_302_p2_n_132,p_Val2_6_fu_302_p2_n_133,p_Val2_6_fu_302_p2_n_134,p_Val2_6_fu_302_p2_n_135,p_Val2_6_fu_302_p2_n_136,p_Val2_6_fu_302_p2_n_137,p_Val2_6_fu_302_p2_n_138,p_Val2_6_fu_302_p2_n_139,p_Val2_6_fu_302_p2_n_140,p_Val2_6_fu_302_p2_n_141,p_Val2_6_fu_302_p2_n_142,p_Val2_6_fu_302_p2_n_143,p_Val2_6_fu_302_p2_n_144,p_Val2_6_fu_302_p2_n_145,p_Val2_6_fu_302_p2_n_146,p_Val2_6_fu_302_p2_n_147,p_Val2_6_fu_302_p2_n_148,p_Val2_6_fu_302_p2_n_149,p_Val2_6_fu_302_p2_n_150,p_Val2_6_fu_302_p2_n_151,p_Val2_6_fu_302_p2_n_152,p_Val2_6_fu_302_p2_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  CARRY4 p_Val2_6_fu_302_p2__0_i_1
       (.CI(p_Val2_6_fu_302_p2__0_i_2_n_0),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(p_Val2_6_fu_302_p2__0_i_1_n_7),
        .S({\<const0> ,\<const0> ,\<const0> ,\<const1> }));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_10
       (.I0(inputs_delay_comp_V_preg[26]),
        .O(p_Val2_6_fu_302_p2__0_i_10_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_11
       (.I0(inputs_delay_comp_V_preg[25]),
        .O(p_Val2_6_fu_302_p2__0_i_11_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_12
       (.I0(inputs_delay_comp_V_preg[24]),
        .O(p_Val2_6_fu_302_p2__0_i_12_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_13
       (.I0(inputs_delay_comp_V_preg[23]),
        .O(p_Val2_6_fu_302_p2__0_i_13_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_14
       (.I0(inputs_delay_comp_V_preg[22]),
        .O(p_Val2_6_fu_302_p2__0_i_14_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_15
       (.I0(inputs_delay_comp_V_preg[21]),
        .O(p_Val2_6_fu_302_p2__0_i_15_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_16
       (.I0(inputs_delay_comp_V_preg[20]),
        .O(p_Val2_6_fu_302_p2__0_i_16_n_0));
  CARRY4 p_Val2_6_fu_302_p2__0_i_2
       (.CI(p_Val2_6_fu_302_p2__0_i_3_n_0),
        .CO({p_Val2_6_fu_302_p2__0_i_2_n_0,p_Val2_6_fu_302_p2__0_i_2_n_1,p_Val2_6_fu_302_p2__0_i_2_n_2,p_Val2_6_fu_302_p2__0_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI({inputs_delay_comp_V_preg[31],\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2__0_i_2_n_4,p_Val2_6_fu_302_p2__0_i_2_n_5,p_Val2_6_fu_302_p2__0_i_2_n_6,p_Val2_6_fu_302_p2__0_i_2_n_7}),
        .S({p_Val2_6_fu_302_p2__0_i_5_n_0,p_Val2_6_fu_302_p2__0_i_6_n_0,p_Val2_6_fu_302_p2__0_i_7_n_0,p_Val2_6_fu_302_p2__0_i_8_n_0}));
  CARRY4 p_Val2_6_fu_302_p2__0_i_3
       (.CI(p_Val2_6_fu_302_p2__0_i_4_n_0),
        .CO({p_Val2_6_fu_302_p2__0_i_3_n_0,p_Val2_6_fu_302_p2__0_i_3_n_1,p_Val2_6_fu_302_p2__0_i_3_n_2,p_Val2_6_fu_302_p2__0_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2__0_i_3_n_4,p_Val2_6_fu_302_p2__0_i_3_n_5,p_Val2_6_fu_302_p2__0_i_3_n_6,p_Val2_6_fu_302_p2__0_i_3_n_7}),
        .S({p_Val2_6_fu_302_p2__0_i_9_n_0,p_Val2_6_fu_302_p2__0_i_10_n_0,p_Val2_6_fu_302_p2__0_i_11_n_0,p_Val2_6_fu_302_p2__0_i_12_n_0}));
  CARRY4 p_Val2_6_fu_302_p2__0_i_4
       (.CI(p_Val2_6_fu_302_p2_i_1_n_0),
        .CO({p_Val2_6_fu_302_p2__0_i_4_n_0,p_Val2_6_fu_302_p2__0_i_4_n_1,p_Val2_6_fu_302_p2__0_i_4_n_2,p_Val2_6_fu_302_p2__0_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2__0_i_4_n_4,p_Val2_6_fu_302_p2__0_i_4_n_5,p_Val2_6_fu_302_p2__0_i_4_n_6,p_Val2_6_fu_302_p2__0_i_4_n_7}),
        .S({p_Val2_6_fu_302_p2__0_i_13_n_0,p_Val2_6_fu_302_p2__0_i_14_n_0,p_Val2_6_fu_302_p2__0_i_15_n_0,p_Val2_6_fu_302_p2__0_i_16_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_5
       (.I0(inputs_delay_comp_V_preg[31]),
        .O(p_Val2_6_fu_302_p2__0_i_5_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_6
       (.I0(inputs_delay_comp_V_preg[30]),
        .O(p_Val2_6_fu_302_p2__0_i_6_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_7
       (.I0(inputs_delay_comp_V_preg[29]),
        .O(p_Val2_6_fu_302_p2__0_i_7_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_8
       (.I0(inputs_delay_comp_V_preg[28]),
        .O(p_Val2_6_fu_302_p2__0_i_8_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2__0_i_9
       (.I0(inputs_delay_comp_V_preg[27]),
        .O(p_Val2_6_fu_302_p2__0_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x18 4}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_6_fu_302_p2__1
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,FTW_comp_V_fu_278_p3[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACOUT({p_Val2_6_fu_302_p2__1_n_24,p_Val2_6_fu_302_p2__1_n_25,p_Val2_6_fu_302_p2__1_n_26,p_Val2_6_fu_302_p2__1_n_27,p_Val2_6_fu_302_p2__1_n_28,p_Val2_6_fu_302_p2__1_n_29,p_Val2_6_fu_302_p2__1_n_30,p_Val2_6_fu_302_p2__1_n_31,p_Val2_6_fu_302_p2__1_n_32,p_Val2_6_fu_302_p2__1_n_33,p_Val2_6_fu_302_p2__1_n_34,p_Val2_6_fu_302_p2__1_n_35,p_Val2_6_fu_302_p2__1_n_36,p_Val2_6_fu_302_p2__1_n_37,p_Val2_6_fu_302_p2__1_n_38,p_Val2_6_fu_302_p2__1_n_39,p_Val2_6_fu_302_p2__1_n_40,p_Val2_6_fu_302_p2__1_n_41,p_Val2_6_fu_302_p2__1_n_42,p_Val2_6_fu_302_p2__1_n_43,p_Val2_6_fu_302_p2__1_n_44,p_Val2_6_fu_302_p2__1_n_45,p_Val2_6_fu_302_p2__1_n_46,p_Val2_6_fu_302_p2__1_n_47,p_Val2_6_fu_302_p2__1_n_48,p_Val2_6_fu_302_p2__1_n_49,p_Val2_6_fu_302_p2__1_n_50,p_Val2_6_fu_302_p2__1_n_51,p_Val2_6_fu_302_p2__1_n_52,p_Val2_6_fu_302_p2__1_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,p_Val2_6_fu_302_p2_i_1_n_7,p_Val2_6_fu_302_p2_i_2_n_4,p_Val2_6_fu_302_p2_i_2_n_5,p_Val2_6_fu_302_p2_i_2_n_6,p_Val2_6_fu_302_p2_i_2_n_7,p_Val2_6_fu_302_p2_i_3_n_4,p_Val2_6_fu_302_p2_i_3_n_5,p_Val2_6_fu_302_p2_i_3_n_6,p_Val2_6_fu_302_p2_i_3_n_7,p_Val2_6_fu_302_p2_i_4_n_4,p_Val2_6_fu_302_p2_i_4_n_5,p_Val2_6_fu_302_p2_i_4_n_6,p_Val2_6_fu_302_p2_i_4_n_7,p_Val2_6_fu_302_p2_i_5_n_4,p_Val2_6_fu_302_p2_i_5_n_5,p_Val2_6_fu_302_p2_i_5_n_6,p_Val2_6_fu_302_p2_i_5_n_7}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(start),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(start),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_6_fu_302_p2__1_n_58,p_Val2_6_fu_302_p2__1_n_59,p_Val2_6_fu_302_p2__1_n_60,p_Val2_6_fu_302_p2__1_n_61,p_Val2_6_fu_302_p2__1_n_62,p_Val2_6_fu_302_p2__1_n_63,p_Val2_6_fu_302_p2__1_n_64,p_Val2_6_fu_302_p2__1_n_65,p_Val2_6_fu_302_p2__1_n_66,p_Val2_6_fu_302_p2__1_n_67,p_Val2_6_fu_302_p2__1_n_68,p_Val2_6_fu_302_p2__1_n_69,p_Val2_6_fu_302_p2__1_n_70,p_Val2_6_fu_302_p2__1_n_71,p_Val2_6_fu_302_p2__1_n_72,p_Val2_6_fu_302_p2__1_n_73,p_Val2_6_fu_302_p2__1_n_74,p_Val2_6_fu_302_p2__1_n_75,p_Val2_6_fu_302_p2__1_n_76,p_Val2_6_fu_302_p2__1_n_77,p_Val2_6_fu_302_p2__1_n_78,p_Val2_6_fu_302_p2__1_n_79,p_Val2_6_fu_302_p2__1_n_80,p_Val2_6_fu_302_p2__1_n_81,p_Val2_6_fu_302_p2__1_n_82,p_Val2_6_fu_302_p2__1_n_83,p_Val2_6_fu_302_p2__1_n_84,p_Val2_6_fu_302_p2__1_n_85,p_Val2_6_fu_302_p2__1_n_86,p_Val2_6_fu_302_p2__1_n_87,p_Val2_6_fu_302_p2__1_n_88,p_Val2_6_fu_302_p2__1_n_89,p_Val2_6_fu_302_p2__1_n_90,p_Val2_6_fu_302_p2__1_n_91,p_Val2_6_fu_302_p2__1_n_92,p_Val2_6_fu_302_p2__1_n_93,p_Val2_6_fu_302_p2__1_n_94,p_Val2_6_fu_302_p2__1_n_95,p_Val2_6_fu_302_p2__1_n_96,p_Val2_6_fu_302_p2__1_n_97,p_Val2_6_fu_302_p2__1_n_98,p_Val2_6_fu_302_p2__1_n_99,p_Val2_6_fu_302_p2__1_n_100,p_Val2_6_fu_302_p2__1_n_101,p_Val2_6_fu_302_p2__1_n_102,p_Val2_6_fu_302_p2__1_n_103,p_Val2_6_fu_302_p2__1_n_104,p_Val2_6_fu_302_p2__1_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_6_fu_302_p2__1_n_106,p_Val2_6_fu_302_p2__1_n_107,p_Val2_6_fu_302_p2__1_n_108,p_Val2_6_fu_302_p2__1_n_109,p_Val2_6_fu_302_p2__1_n_110,p_Val2_6_fu_302_p2__1_n_111,p_Val2_6_fu_302_p2__1_n_112,p_Val2_6_fu_302_p2__1_n_113,p_Val2_6_fu_302_p2__1_n_114,p_Val2_6_fu_302_p2__1_n_115,p_Val2_6_fu_302_p2__1_n_116,p_Val2_6_fu_302_p2__1_n_117,p_Val2_6_fu_302_p2__1_n_118,p_Val2_6_fu_302_p2__1_n_119,p_Val2_6_fu_302_p2__1_n_120,p_Val2_6_fu_302_p2__1_n_121,p_Val2_6_fu_302_p2__1_n_122,p_Val2_6_fu_302_p2__1_n_123,p_Val2_6_fu_302_p2__1_n_124,p_Val2_6_fu_302_p2__1_n_125,p_Val2_6_fu_302_p2__1_n_126,p_Val2_6_fu_302_p2__1_n_127,p_Val2_6_fu_302_p2__1_n_128,p_Val2_6_fu_302_p2__1_n_129,p_Val2_6_fu_302_p2__1_n_130,p_Val2_6_fu_302_p2__1_n_131,p_Val2_6_fu_302_p2__1_n_132,p_Val2_6_fu_302_p2__1_n_133,p_Val2_6_fu_302_p2__1_n_134,p_Val2_6_fu_302_p2__1_n_135,p_Val2_6_fu_302_p2__1_n_136,p_Val2_6_fu_302_p2__1_n_137,p_Val2_6_fu_302_p2__1_n_138,p_Val2_6_fu_302_p2__1_n_139,p_Val2_6_fu_302_p2__1_n_140,p_Val2_6_fu_302_p2__1_n_141,p_Val2_6_fu_302_p2__1_n_142,p_Val2_6_fu_302_p2__1_n_143,p_Val2_6_fu_302_p2__1_n_144,p_Val2_6_fu_302_p2__1_n_145,p_Val2_6_fu_302_p2__1_n_146,p_Val2_6_fu_302_p2__1_n_147,p_Val2_6_fu_302_p2__1_n_148,p_Val2_6_fu_302_p2__1_n_149,p_Val2_6_fu_302_p2__1_n_150,p_Val2_6_fu_302_p2__1_n_151,p_Val2_6_fu_302_p2__1_n_152,p_Val2_6_fu_302_p2__1_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_1
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[16] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[16] ),
        .O(FTW_comp_V_fu_278_p3[16]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_10
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[7] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[7] ),
        .O(FTW_comp_V_fu_278_p3[7]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_11
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[6] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[6] ),
        .O(FTW_comp_V_fu_278_p3[6]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_12
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[5] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[5] ),
        .O(FTW_comp_V_fu_278_p3[5]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_13
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[4] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[4] ),
        .O(FTW_comp_V_fu_278_p3[4]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_14
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[3] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[3] ),
        .O(FTW_comp_V_fu_278_p3[3]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_15
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[2] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[2] ),
        .O(FTW_comp_V_fu_278_p3[2]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_16
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[1] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[1] ),
        .O(FTW_comp_V_fu_278_p3[1]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_17
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[0] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[0] ),
        .O(FTW_comp_V_fu_278_p3[0]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_2
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[15] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[15] ),
        .O(FTW_comp_V_fu_278_p3[15]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_3
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[14] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[14] ),
        .O(FTW_comp_V_fu_278_p3[14]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_4
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[13] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[13] ),
        .O(FTW_comp_V_fu_278_p3[13]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_5
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[12] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[12] ),
        .O(FTW_comp_V_fu_278_p3[12]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_6
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[11] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[11] ),
        .O(FTW_comp_V_fu_278_p3[11]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_7
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[10] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[10] ),
        .O(FTW_comp_V_fu_278_p3[10]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_8
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[9] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[9] ),
        .O(FTW_comp_V_fu_278_p3[9]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2__1_i_9
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[8] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[8] ),
        .O(FTW_comp_V_fu_278_p3[8]));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x16 4}}" *) 
  DSP48E1 #(
    .ACASCREG(0),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(0),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("CASCADE"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_6_fu_302_p2__2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ACIN({p_Val2_6_fu_302_p2__1_n_24,p_Val2_6_fu_302_p2__1_n_25,p_Val2_6_fu_302_p2__1_n_26,p_Val2_6_fu_302_p2__1_n_27,p_Val2_6_fu_302_p2__1_n_28,p_Val2_6_fu_302_p2__1_n_29,p_Val2_6_fu_302_p2__1_n_30,p_Val2_6_fu_302_p2__1_n_31,p_Val2_6_fu_302_p2__1_n_32,p_Val2_6_fu_302_p2__1_n_33,p_Val2_6_fu_302_p2__1_n_34,p_Val2_6_fu_302_p2__1_n_35,p_Val2_6_fu_302_p2__1_n_36,p_Val2_6_fu_302_p2__1_n_37,p_Val2_6_fu_302_p2__1_n_38,p_Val2_6_fu_302_p2__1_n_39,p_Val2_6_fu_302_p2__1_n_40,p_Val2_6_fu_302_p2__1_n_41,p_Val2_6_fu_302_p2__1_n_42,p_Val2_6_fu_302_p2__1_n_43,p_Val2_6_fu_302_p2__1_n_44,p_Val2_6_fu_302_p2__1_n_45,p_Val2_6_fu_302_p2__1_n_46,p_Val2_6_fu_302_p2__1_n_47,p_Val2_6_fu_302_p2__1_n_48,p_Val2_6_fu_302_p2__1_n_49,p_Val2_6_fu_302_p2__1_n_50,p_Val2_6_fu_302_p2__1_n_51,p_Val2_6_fu_302_p2__1_n_52,p_Val2_6_fu_302_p2__1_n_53}),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({p_Val2_6_fu_302_p2__0_i_1_n_7,p_Val2_6_fu_302_p2__0_i_1_n_7,p_Val2_6_fu_302_p2__0_i_1_n_7,p_Val2_6_fu_302_p2__0_i_2_n_4,p_Val2_6_fu_302_p2__0_i_2_n_5,p_Val2_6_fu_302_p2__0_i_2_n_6,p_Val2_6_fu_302_p2__0_i_2_n_7,p_Val2_6_fu_302_p2__0_i_3_n_4,p_Val2_6_fu_302_p2__0_i_3_n_5,p_Val2_6_fu_302_p2__0_i_3_n_6,p_Val2_6_fu_302_p2__0_i_3_n_7,p_Val2_6_fu_302_p2__0_i_4_n_4,p_Val2_6_fu_302_p2__0_i_4_n_5,p_Val2_6_fu_302_p2__0_i_4_n_6,p_Val2_6_fu_302_p2__0_i_4_n_7,p_Val2_6_fu_302_p2_i_1_n_4,p_Val2_6_fu_302_p2_i_1_n_5,p_Val2_6_fu_302_p2_i_1_n_6}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(\<const0> ),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(start),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_6_fu_302_p2__2_n_58,p_Val2_6_fu_302_p2__2_n_59,p_Val2_6_fu_302_p2__2_n_60,p_Val2_6_fu_302_p2__2_n_61,p_Val2_6_fu_302_p2__2_n_62,p_Val2_6_fu_302_p2__2_n_63,p_Val2_6_fu_302_p2__2_n_64,p_Val2_6_fu_302_p2__2_n_65,p_Val2_6_fu_302_p2__2_n_66,p_Val2_6_fu_302_p2__2_n_67,p_Val2_6_fu_302_p2__2_n_68,p_Val2_6_fu_302_p2__2_n_69,p_Val2_6_fu_302_p2__2_n_70,p_Val2_6_fu_302_p2__2_n_71,p_Val2_6_fu_302_p2__2_n_72,p_Val2_6_fu_302_p2__2_n_73,p_Val2_6_fu_302_p2__2_n_74,p_Val2_6_fu_302_p2__2_n_75,p_Val2_6_fu_302_p2__2_n_76,p_Val2_6_fu_302_p2__2_n_77,p_Val2_6_fu_302_p2__2_n_78,p_Val2_6_fu_302_p2__2_n_79,p_Val2_6_fu_302_p2__2_n_80,p_Val2_6_fu_302_p2__2_n_81,p_Val2_6_fu_302_p2__2_n_82,p_Val2_6_fu_302_p2__2_n_83,p_Val2_6_fu_302_p2__2_n_84,p_Val2_6_fu_302_p2__2_n_85,p_Val2_6_fu_302_p2__2_n_86,p_Val2_6_fu_302_p2__2_n_87,p_Val2_6_fu_302_p2__2_n_88,p_Val2_6_fu_302_p2__2_n_89,p_Val2_6_fu_302_p2__2_n_90,p_Val2_6_fu_302_p2__2_n_91,p_Val2_6_fu_302_p2__2_n_92,p_Val2_6_fu_302_p2__2_n_93,p_Val2_6_fu_302_p2__2_n_94,p_Val2_6_fu_302_p2__2_n_95,p_Val2_6_fu_302_p2__2_n_96,p_Val2_6_fu_302_p2__2_n_97,p_Val2_6_fu_302_p2__2_n_98,p_Val2_6_fu_302_p2__2_n_99,p_Val2_6_fu_302_p2__2_n_100,p_Val2_6_fu_302_p2__2_n_101,p_Val2_6_fu_302_p2__2_n_102,p_Val2_6_fu_302_p2__2_n_103,p_Val2_6_fu_302_p2__2_n_104,p_Val2_6_fu_302_p2__2_n_105}),
        .PCIN({p_Val2_6_fu_302_p2__1_n_106,p_Val2_6_fu_302_p2__1_n_107,p_Val2_6_fu_302_p2__1_n_108,p_Val2_6_fu_302_p2__1_n_109,p_Val2_6_fu_302_p2__1_n_110,p_Val2_6_fu_302_p2__1_n_111,p_Val2_6_fu_302_p2__1_n_112,p_Val2_6_fu_302_p2__1_n_113,p_Val2_6_fu_302_p2__1_n_114,p_Val2_6_fu_302_p2__1_n_115,p_Val2_6_fu_302_p2__1_n_116,p_Val2_6_fu_302_p2__1_n_117,p_Val2_6_fu_302_p2__1_n_118,p_Val2_6_fu_302_p2__1_n_119,p_Val2_6_fu_302_p2__1_n_120,p_Val2_6_fu_302_p2__1_n_121,p_Val2_6_fu_302_p2__1_n_122,p_Val2_6_fu_302_p2__1_n_123,p_Val2_6_fu_302_p2__1_n_124,p_Val2_6_fu_302_p2__1_n_125,p_Val2_6_fu_302_p2__1_n_126,p_Val2_6_fu_302_p2__1_n_127,p_Val2_6_fu_302_p2__1_n_128,p_Val2_6_fu_302_p2__1_n_129,p_Val2_6_fu_302_p2__1_n_130,p_Val2_6_fu_302_p2__1_n_131,p_Val2_6_fu_302_p2__1_n_132,p_Val2_6_fu_302_p2__1_n_133,p_Val2_6_fu_302_p2__1_n_134,p_Val2_6_fu_302_p2__1_n_135,p_Val2_6_fu_302_p2__1_n_136,p_Val2_6_fu_302_p2__1_n_137,p_Val2_6_fu_302_p2__1_n_138,p_Val2_6_fu_302_p2__1_n_139,p_Val2_6_fu_302_p2__1_n_140,p_Val2_6_fu_302_p2__1_n_141,p_Val2_6_fu_302_p2__1_n_142,p_Val2_6_fu_302_p2__1_n_143,p_Val2_6_fu_302_p2__1_n_144,p_Val2_6_fu_302_p2__1_n_145,p_Val2_6_fu_302_p2__1_n_146,p_Val2_6_fu_302_p2__1_n_147,p_Val2_6_fu_302_p2__1_n_148,p_Val2_6_fu_302_p2__1_n_149,p_Val2_6_fu_302_p2__1_n_150,p_Val2_6_fu_302_p2__1_n_151,p_Val2_6_fu_302_p2__1_n_152,p_Val2_6_fu_302_p2__1_n_153}),
        .RSTA(\<const0> ),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(\<const0> ),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  CARRY4 p_Val2_6_fu_302_p2_i_1
       (.CI(p_Val2_6_fu_302_p2_i_2_n_0),
        .CO({p_Val2_6_fu_302_p2_i_1_n_0,p_Val2_6_fu_302_p2_i_1_n_1,p_Val2_6_fu_302_p2_i_1_n_2,p_Val2_6_fu_302_p2_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2_i_1_n_4,p_Val2_6_fu_302_p2_i_1_n_5,p_Val2_6_fu_302_p2_i_1_n_6,p_Val2_6_fu_302_p2_i_1_n_7}),
        .S({p_Val2_6_fu_302_p2_i_26_n_0,p_Val2_6_fu_302_p2_i_27_n_0,p_Val2_6_fu_302_p2_i_28_n_0,p_Val2_6_fu_302_p2_i_29_n_0}));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_10
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[32] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[32] ),
        .O(FTW_comp_V_fu_278_p3[32]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_11
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[31] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[31] ),
        .O(FTW_comp_V_fu_278_p3[31]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_12
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[30] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[30] ),
        .O(FTW_comp_V_fu_278_p3[30]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_13
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[29] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[29] ),
        .O(FTW_comp_V_fu_278_p3[29]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_14
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[28] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[28] ),
        .O(FTW_comp_V_fu_278_p3[28]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_15
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[27] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[27] ),
        .O(FTW_comp_V_fu_278_p3[27]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_16
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[26] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[26] ),
        .O(FTW_comp_V_fu_278_p3[26]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_17
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[25] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[25] ),
        .O(FTW_comp_V_fu_278_p3[25]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_18
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[24] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[24] ),
        .O(FTW_comp_V_fu_278_p3[24]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_19
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[23] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[23] ),
        .O(FTW_comp_V_fu_278_p3[23]));
  CARRY4 p_Val2_6_fu_302_p2_i_2
       (.CI(p_Val2_6_fu_302_p2_i_3_n_0),
        .CO({p_Val2_6_fu_302_p2_i_2_n_0,p_Val2_6_fu_302_p2_i_2_n_1,p_Val2_6_fu_302_p2_i_2_n_2,p_Val2_6_fu_302_p2_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2_i_2_n_4,p_Val2_6_fu_302_p2_i_2_n_5,p_Val2_6_fu_302_p2_i_2_n_6,p_Val2_6_fu_302_p2_i_2_n_7}),
        .S({p_Val2_6_fu_302_p2_i_30_n_0,p_Val2_6_fu_302_p2_i_31_n_0,p_Val2_6_fu_302_p2_i_32_n_0,p_Val2_6_fu_302_p2_i_33_n_0}));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_20
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[22] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[22] ),
        .O(FTW_comp_V_fu_278_p3[22]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_21
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[21] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[21] ),
        .O(FTW_comp_V_fu_278_p3[21]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_22
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[20] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[20] ),
        .O(FTW_comp_V_fu_278_p3[20]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_23
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[19] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[19] ),
        .O(FTW_comp_V_fu_278_p3[19]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_24
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[18] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[18] ),
        .O(FTW_comp_V_fu_278_p3[18]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_25
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[17] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[17] ),
        .O(FTW_comp_V_fu_278_p3[17]));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_26
       (.I0(inputs_delay_comp_V_preg[19]),
        .O(p_Val2_6_fu_302_p2_i_26_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_27
       (.I0(inputs_delay_comp_V_preg[18]),
        .O(p_Val2_6_fu_302_p2_i_27_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_28
       (.I0(inputs_delay_comp_V_preg[17]),
        .O(p_Val2_6_fu_302_p2_i_28_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_29
       (.I0(inputs_delay_comp_V_preg[16]),
        .O(p_Val2_6_fu_302_p2_i_29_n_0));
  CARRY4 p_Val2_6_fu_302_p2_i_3
       (.CI(p_Val2_6_fu_302_p2_i_4_n_0),
        .CO({p_Val2_6_fu_302_p2_i_3_n_0,p_Val2_6_fu_302_p2_i_3_n_1,p_Val2_6_fu_302_p2_i_3_n_2,p_Val2_6_fu_302_p2_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2_i_3_n_4,p_Val2_6_fu_302_p2_i_3_n_5,p_Val2_6_fu_302_p2_i_3_n_6,p_Val2_6_fu_302_p2_i_3_n_7}),
        .S({p_Val2_6_fu_302_p2_i_34_n_0,p_Val2_6_fu_302_p2_i_35_n_0,p_Val2_6_fu_302_p2_i_36_n_0,p_Val2_6_fu_302_p2_i_37_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_30
       (.I0(inputs_delay_comp_V_preg[15]),
        .O(p_Val2_6_fu_302_p2_i_30_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_31
       (.I0(inputs_delay_comp_V_preg[14]),
        .O(p_Val2_6_fu_302_p2_i_31_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_32
       (.I0(inputs_delay_comp_V_preg[13]),
        .O(p_Val2_6_fu_302_p2_i_32_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_33
       (.I0(inputs_delay_comp_V_preg[12]),
        .O(p_Val2_6_fu_302_p2_i_33_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_34
       (.I0(inputs_delay_comp_V_preg[11]),
        .O(p_Val2_6_fu_302_p2_i_34_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_35
       (.I0(inputs_delay_comp_V_preg[10]),
        .O(p_Val2_6_fu_302_p2_i_35_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_36
       (.I0(inputs_delay_comp_V_preg[9]),
        .O(p_Val2_6_fu_302_p2_i_36_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_37
       (.I0(inputs_delay_comp_V_preg[8]),
        .O(p_Val2_6_fu_302_p2_i_37_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_38
       (.I0(inputs_delay_comp_V_preg[7]),
        .O(p_Val2_6_fu_302_p2_i_38_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_39
       (.I0(inputs_delay_comp_V_preg[6]),
        .O(p_Val2_6_fu_302_p2_i_39_n_0));
  CARRY4 p_Val2_6_fu_302_p2_i_4
       (.CI(p_Val2_6_fu_302_p2_i_5_n_0),
        .CO({p_Val2_6_fu_302_p2_i_4_n_0,p_Val2_6_fu_302_p2_i_4_n_1,p_Val2_6_fu_302_p2_i_4_n_2,p_Val2_6_fu_302_p2_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({p_Val2_6_fu_302_p2_i_4_n_4,p_Val2_6_fu_302_p2_i_4_n_5,p_Val2_6_fu_302_p2_i_4_n_6,p_Val2_6_fu_302_p2_i_4_n_7}),
        .S({p_Val2_6_fu_302_p2_i_38_n_0,p_Val2_6_fu_302_p2_i_39_n_0,p_Val2_6_fu_302_p2_i_40_n_0,p_Val2_6_fu_302_p2_i_41_n_0}));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_40
       (.I0(inputs_delay_comp_V_preg[5]),
        .O(p_Val2_6_fu_302_p2_i_40_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_41
       (.I0(inputs_delay_comp_V_preg[4]),
        .O(p_Val2_6_fu_302_p2_i_41_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_42
       (.I0(inputs_delay_comp_V_preg[3]),
        .O(p_Val2_6_fu_302_p2_i_42_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_43
       (.I0(inputs_delay_comp_V_preg[2]),
        .O(p_Val2_6_fu_302_p2_i_43_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    p_Val2_6_fu_302_p2_i_44
       (.I0(inputs_delay_comp_V_preg[1]),
        .O(p_Val2_6_fu_302_p2_i_44_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    p_Val2_6_fu_302_p2_i_45
       (.I0(p_Val2_6_fu_302_p2_i_48_n_0),
        .I1(p_Val2_6_fu_302_p2_i_49_n_0),
        .I2(p_Val2_6_fu_302_p2_i_50_n_0),
        .I3(p_Val2_6_fu_302_p2_i_51_n_0),
        .O(p_Val2_6_fu_302_p2_i_45_n_0));
  LUT4 #(
    .INIT(16'h0004)) 
    p_Val2_6_fu_302_p2_i_46
       (.I0(p_Val2_6_fu_302_p2_i_52_n_0),
        .I1(p_Val2_6_fu_302_p2_i_53_n_0),
        .I2(p_Val2_6_fu_302_p2_i_54_n_0),
        .I3(p_Val2_6_fu_302_p2_i_55_n_0),
        .O(p_Val2_6_fu_302_p2_i_46_n_0));
  LUT4 #(
    .INIT(16'h5557)) 
    p_Val2_6_fu_302_p2_i_47
       (.I0(inputs_enable_FSK_preg),
        .I1(inputs_rate_V_preg[1]),
        .I2(inputs_rate_V_preg[0]),
        .I3(inputs_rate_V_preg[2]),
        .O(p_Val2_6_fu_302_p2_i_47_n_0));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_48
       (.I0(p_Val2_3_fu_330_p2__0_i_21_n_5),
        .I1(p_Val2_3_fu_330_p2__0_i_21_n_4),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2__0_i_21_n_7),
        .I5(p_Val2_3_fu_330_p2__0_i_21_n_6),
        .O(p_Val2_6_fu_302_p2_i_48_n_0));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_49
       (.I0(p_Val2_3_fu_330_p2__0_i_20_n_7),
        .I1(p_Val2_3_fu_330_p2__0_i_20_n_6),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2__0_i_20_n_5),
        .I5(p_Val2_3_fu_330_p2__0_i_20_n_4),
        .O(p_Val2_6_fu_302_p2_i_49_n_0));
  CARRY4 p_Val2_6_fu_302_p2_i_5
       (.CI(\<const0> ),
        .CO({p_Val2_6_fu_302_p2_i_5_n_0,p_Val2_6_fu_302_p2_i_5_n_1,p_Val2_6_fu_302_p2_i_5_n_2,p_Val2_6_fu_302_p2_i_5_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }),
        .O({p_Val2_6_fu_302_p2_i_5_n_4,p_Val2_6_fu_302_p2_i_5_n_5,p_Val2_6_fu_302_p2_i_5_n_6,p_Val2_6_fu_302_p2_i_5_n_7}),
        .S({p_Val2_6_fu_302_p2_i_42_n_0,p_Val2_6_fu_302_p2_i_43_n_0,p_Val2_6_fu_302_p2_i_44_n_0,inputs_delay_comp_V_preg[0]}));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_50
       (.I0(p_Val2_3_fu_330_p2__0_i_18_n_5),
        .I1(p_Val2_3_fu_330_p2__0_i_18_n_7),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2__0_i_18_n_4),
        .I5(p_Val2_3_fu_330_p2__0_i_18_n_6),
        .O(p_Val2_6_fu_302_p2_i_50_n_0));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_51
       (.I0(p_Val2_3_fu_330_p2__0_i_19_n_7),
        .I1(p_Val2_3_fu_330_p2__0_i_19_n_6),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2__0_i_19_n_5),
        .I5(p_Val2_3_fu_330_p2__0_i_19_n_4),
        .O(p_Val2_6_fu_302_p2_i_51_n_0));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_52
       (.I0(p_Val2_3_fu_330_p2_i_21_n_5),
        .I1(p_Val2_3_fu_330_p2_i_21_n_4),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2_i_21_n_7),
        .I5(p_Val2_3_fu_330_p2_i_21_n_6),
        .O(p_Val2_6_fu_302_p2_i_52_n_0));
  LUT6 #(
    .INIT(64'h0F000F000F000F11)) 
    p_Val2_6_fu_302_p2_i_53
       (.I0(p_Val2_3_fu_330_p2_i_20_n_5),
        .I1(p_Val2_3_fu_330_p2_i_20_n_4),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2_i_20_n_7),
        .I5(p_Val2_3_fu_330_p2_i_20_n_6),
        .O(p_Val2_6_fu_302_p2_i_53_n_0));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_54
       (.I0(p_Val2_3_fu_330_p2_i_19_n_7),
        .I1(p_Val2_3_fu_330_p2_i_19_n_5),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2_i_19_n_6),
        .I5(p_Val2_3_fu_330_p2_i_19_n_4),
        .O(p_Val2_6_fu_302_p2_i_54_n_0));
  LUT6 #(
    .INIT(64'hF0FFF0FFF0FFF0EE)) 
    p_Val2_6_fu_302_p2_i_55
       (.I0(p_Val2_3_fu_330_p2_i_18_n_4),
        .I1(p_Val2_3_fu_330_p2_i_18_n_5),
        .I2(p_Val2_3_fu_330_p2_i_16_n_3),
        .I3(p_Val2_3_fu_330_p2_i_17_n_0),
        .I4(p_Val2_3_fu_330_p2_i_18_n_7),
        .I5(p_Val2_3_fu_330_p2_i_18_n_6),
        .O(p_Val2_6_fu_302_p2_i_55_n_0));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_6
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[36] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[36] ),
        .O(FTW_comp_V_fu_278_p3[36]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_7
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[35] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[35] ),
        .O(FTW_comp_V_fu_278_p3[35]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_8
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[34] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[34] ),
        .O(FTW_comp_V_fu_278_p3[34]));
  LUT5 #(
    .INIT(32'hAAEFAA20)) 
    p_Val2_6_fu_302_p2_i_9
       (.I0(\inputs_ftw_H1_V_preg_reg_n_0_[33] ),
        .I1(p_Val2_6_fu_302_p2_i_45_n_0),
        .I2(p_Val2_6_fu_302_p2_i_46_n_0),
        .I3(p_Val2_6_fu_302_p2_i_47_n_0),
        .I4(\inputs_ftw_H1_on_V_preg_reg_n_0_[33] ),
        .O(FTW_comp_V_fu_278_p3[33]));
  CARRY4 \phase_H1_comp_V[0]_INST_0 
       (.CI(\<const0> ),
        .CO({\phase_H1_comp_V[0]_INST_0_n_0 ,\phase_H1_comp_V[0]_INST_0_n_1 ,\phase_H1_comp_V[0]_INST_0_n_2 ,\phase_H1_comp_V[0]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_103,p_Val2_6_fu_302_p2__2_n_104,p_Val2_6_fu_302_p2__2_n_105,\<const0> }),
        .O({phase_H1_comp_V[1:0],\NLW_phase_H1_comp_V[0]_INST_0_O_UNCONNECTED [1:0]}),
        .S({\phase_H1_comp_V[0]_INST_0_i_1_n_0 ,\phase_H1_comp_V[0]_INST_0_i_2_n_0 ,\phase_H1_comp_V[0]_INST_0_i_3_n_0 ,p_Val2_6_fu_302_p2__1_n_89}));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[0]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_103),
        .I1(p_Val2_6_fu_302_p2_n_103),
        .O(\phase_H1_comp_V[0]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[0]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_104),
        .I1(p_Val2_6_fu_302_p2_n_104),
        .O(\phase_H1_comp_V[0]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[0]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_105),
        .I1(p_Val2_6_fu_302_p2_n_105),
        .O(\phase_H1_comp_V[0]_INST_0_i_3_n_0 ));
  CARRY4 \phase_H1_comp_V[10]_INST_0 
       (.CI(\phase_H1_comp_V[6]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[10]_INST_0_n_0 ,\phase_H1_comp_V[10]_INST_0_n_1 ,\phase_H1_comp_V[10]_INST_0_n_2 ,\phase_H1_comp_V[10]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_91,p_Val2_6_fu_302_p2__2_n_92,p_Val2_6_fu_302_p2__2_n_93,p_Val2_6_fu_302_p2__2_n_94}),
        .O(phase_H1_comp_V[13:10]),
        .S({\phase_H1_comp_V[10]_INST_0_i_1_n_0 ,\phase_H1_comp_V[10]_INST_0_i_2_n_0 ,\phase_H1_comp_V[10]_INST_0_i_3_n_0 ,\phase_H1_comp_V[10]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[10]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_91),
        .I1(p_Val2_6_fu_302_p2_n_91),
        .O(\phase_H1_comp_V[10]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[10]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_92),
        .I1(p_Val2_6_fu_302_p2_n_92),
        .O(\phase_H1_comp_V[10]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[10]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_93),
        .I1(p_Val2_6_fu_302_p2_n_93),
        .O(\phase_H1_comp_V[10]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[10]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_94),
        .I1(p_Val2_6_fu_302_p2_n_94),
        .O(\phase_H1_comp_V[10]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[14]_INST_0 
       (.CI(\phase_H1_comp_V[10]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[14]_INST_0_n_0 ,\phase_H1_comp_V[14]_INST_0_n_1 ,\phase_H1_comp_V[14]_INST_0_n_2 ,\phase_H1_comp_V[14]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_87,p_Val2_6_fu_302_p2__2_n_88,p_Val2_6_fu_302_p2__2_n_89,p_Val2_6_fu_302_p2__2_n_90}),
        .O(phase_H1_comp_V[17:14]),
        .S({\phase_H1_comp_V[14]_INST_0_i_1_n_0 ,\phase_H1_comp_V[14]_INST_0_i_2_n_0 ,\phase_H1_comp_V[14]_INST_0_i_3_n_0 ,\phase_H1_comp_V[14]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[14]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_87),
        .I1(p_Val2_6_fu_302_p2__0_n_104),
        .O(\phase_H1_comp_V[14]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[14]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_88),
        .I1(p_Val2_6_fu_302_p2__0_n_105),
        .O(\phase_H1_comp_V[14]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[14]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_89),
        .I1(p_Val2_6_fu_302_p2_n_89),
        .O(\phase_H1_comp_V[14]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[14]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_90),
        .I1(p_Val2_6_fu_302_p2_n_90),
        .O(\phase_H1_comp_V[14]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[18]_INST_0 
       (.CI(\phase_H1_comp_V[14]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[18]_INST_0_n_0 ,\phase_H1_comp_V[18]_INST_0_n_1 ,\phase_H1_comp_V[18]_INST_0_n_2 ,\phase_H1_comp_V[18]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_83,p_Val2_6_fu_302_p2__2_n_84,p_Val2_6_fu_302_p2__2_n_85,p_Val2_6_fu_302_p2__2_n_86}),
        .O(phase_H1_comp_V[21:18]),
        .S({\phase_H1_comp_V[18]_INST_0_i_1_n_0 ,\phase_H1_comp_V[18]_INST_0_i_2_n_0 ,\phase_H1_comp_V[18]_INST_0_i_3_n_0 ,\phase_H1_comp_V[18]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[18]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_83),
        .I1(p_Val2_6_fu_302_p2__0_n_100),
        .O(\phase_H1_comp_V[18]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[18]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_84),
        .I1(p_Val2_6_fu_302_p2__0_n_101),
        .O(\phase_H1_comp_V[18]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[18]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_85),
        .I1(p_Val2_6_fu_302_p2__0_n_102),
        .O(\phase_H1_comp_V[18]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[18]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_86),
        .I1(p_Val2_6_fu_302_p2__0_n_103),
        .O(\phase_H1_comp_V[18]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[22]_INST_0 
       (.CI(\phase_H1_comp_V[18]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[22]_INST_0_n_0 ,\phase_H1_comp_V[22]_INST_0_n_1 ,\phase_H1_comp_V[22]_INST_0_n_2 ,\phase_H1_comp_V[22]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_79,p_Val2_6_fu_302_p2__2_n_80,p_Val2_6_fu_302_p2__2_n_81,p_Val2_6_fu_302_p2__2_n_82}),
        .O(phase_H1_comp_V[25:22]),
        .S({\phase_H1_comp_V[22]_INST_0_i_1_n_0 ,\phase_H1_comp_V[22]_INST_0_i_2_n_0 ,\phase_H1_comp_V[22]_INST_0_i_3_n_0 ,\phase_H1_comp_V[22]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[22]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_79),
        .I1(p_Val2_6_fu_302_p2__0_n_96),
        .O(\phase_H1_comp_V[22]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[22]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_80),
        .I1(p_Val2_6_fu_302_p2__0_n_97),
        .O(\phase_H1_comp_V[22]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[22]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_81),
        .I1(p_Val2_6_fu_302_p2__0_n_98),
        .O(\phase_H1_comp_V[22]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[22]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_82),
        .I1(p_Val2_6_fu_302_p2__0_n_99),
        .O(\phase_H1_comp_V[22]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[26]_INST_0 
       (.CI(\phase_H1_comp_V[22]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[26]_INST_0_n_0 ,\phase_H1_comp_V[26]_INST_0_n_1 ,\phase_H1_comp_V[26]_INST_0_n_2 ,\phase_H1_comp_V[26]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_75,p_Val2_6_fu_302_p2__2_n_76,p_Val2_6_fu_302_p2__2_n_77,p_Val2_6_fu_302_p2__2_n_78}),
        .O(phase_H1_comp_V[29:26]),
        .S({\phase_H1_comp_V[26]_INST_0_i_1_n_0 ,\phase_H1_comp_V[26]_INST_0_i_2_n_0 ,\phase_H1_comp_V[26]_INST_0_i_3_n_0 ,\phase_H1_comp_V[26]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[26]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_75),
        .I1(p_Val2_6_fu_302_p2__0_n_92),
        .O(\phase_H1_comp_V[26]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[26]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_76),
        .I1(p_Val2_6_fu_302_p2__0_n_93),
        .O(\phase_H1_comp_V[26]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[26]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_77),
        .I1(p_Val2_6_fu_302_p2__0_n_94),
        .O(\phase_H1_comp_V[26]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[26]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_78),
        .I1(p_Val2_6_fu_302_p2__0_n_95),
        .O(\phase_H1_comp_V[26]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[2]_INST_0 
       (.CI(\phase_H1_comp_V[0]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[2]_INST_0_n_0 ,\phase_H1_comp_V[2]_INST_0_n_1 ,\phase_H1_comp_V[2]_INST_0_n_2 ,\phase_H1_comp_V[2]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_99,p_Val2_6_fu_302_p2__2_n_100,p_Val2_6_fu_302_p2__2_n_101,p_Val2_6_fu_302_p2__2_n_102}),
        .O(phase_H1_comp_V[5:2]),
        .S({\phase_H1_comp_V[2]_INST_0_i_1_n_0 ,\phase_H1_comp_V[2]_INST_0_i_2_n_0 ,\phase_H1_comp_V[2]_INST_0_i_3_n_0 ,\phase_H1_comp_V[2]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[2]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_99),
        .I1(p_Val2_6_fu_302_p2_n_99),
        .O(\phase_H1_comp_V[2]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[2]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_100),
        .I1(p_Val2_6_fu_302_p2_n_100),
        .O(\phase_H1_comp_V[2]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[2]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_101),
        .I1(p_Val2_6_fu_302_p2_n_101),
        .O(\phase_H1_comp_V[2]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[2]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_102),
        .I1(p_Val2_6_fu_302_p2_n_102),
        .O(\phase_H1_comp_V[2]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[30]_INST_0 
       (.CI(\phase_H1_comp_V[26]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[30]_INST_0_n_0 ,\phase_H1_comp_V[30]_INST_0_n_1 ,\phase_H1_comp_V[30]_INST_0_n_2 ,\phase_H1_comp_V[30]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_71,p_Val2_6_fu_302_p2__2_n_72,p_Val2_6_fu_302_p2__2_n_73,p_Val2_6_fu_302_p2__2_n_74}),
        .O(phase_H1_comp_V[33:30]),
        .S({\phase_H1_comp_V[30]_INST_0_i_1_n_0 ,\phase_H1_comp_V[30]_INST_0_i_2_n_0 ,\phase_H1_comp_V[30]_INST_0_i_3_n_0 ,\phase_H1_comp_V[30]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[30]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_71),
        .I1(p_Val2_6_fu_302_p2__0_n_88),
        .O(\phase_H1_comp_V[30]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[30]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_72),
        .I1(p_Val2_6_fu_302_p2__0_n_89),
        .O(\phase_H1_comp_V[30]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[30]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_73),
        .I1(p_Val2_6_fu_302_p2__0_n_90),
        .O(\phase_H1_comp_V[30]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[30]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_74),
        .I1(p_Val2_6_fu_302_p2__0_n_91),
        .O(\phase_H1_comp_V[30]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[34]_INST_0 
       (.CI(\phase_H1_comp_V[30]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[34]_INST_0_n_0 ,\phase_H1_comp_V[34]_INST_0_n_1 ,\phase_H1_comp_V[34]_INST_0_n_2 ,\phase_H1_comp_V[34]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_67,p_Val2_6_fu_302_p2__2_n_68,p_Val2_6_fu_302_p2__2_n_69,p_Val2_6_fu_302_p2__2_n_70}),
        .O(phase_H1_comp_V[37:34]),
        .S({\phase_H1_comp_V[34]_INST_0_i_1_n_0 ,\phase_H1_comp_V[34]_INST_0_i_2_n_0 ,\phase_H1_comp_V[34]_INST_0_i_3_n_0 ,\phase_H1_comp_V[34]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[34]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_67),
        .I1(p_Val2_6_fu_302_p2__0_n_84),
        .O(\phase_H1_comp_V[34]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[34]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_68),
        .I1(p_Val2_6_fu_302_p2__0_n_85),
        .O(\phase_H1_comp_V[34]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[34]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_69),
        .I1(p_Val2_6_fu_302_p2__0_n_86),
        .O(\phase_H1_comp_V[34]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[34]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_70),
        .I1(p_Val2_6_fu_302_p2__0_n_87),
        .O(\phase_H1_comp_V[34]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[38]_INST_0 
       (.CI(\phase_H1_comp_V[34]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[38]_INST_0_n_0 ,\phase_H1_comp_V[38]_INST_0_n_1 ,\phase_H1_comp_V[38]_INST_0_n_2 ,\phase_H1_comp_V[38]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_63,p_Val2_6_fu_302_p2__2_n_64,p_Val2_6_fu_302_p2__2_n_65,p_Val2_6_fu_302_p2__2_n_66}),
        .O(phase_H1_comp_V[41:38]),
        .S({\phase_H1_comp_V[38]_INST_0_i_1_n_0 ,\phase_H1_comp_V[38]_INST_0_i_2_n_0 ,\phase_H1_comp_V[38]_INST_0_i_3_n_0 ,\phase_H1_comp_V[38]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[38]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_63),
        .I1(p_Val2_6_fu_302_p2__0_n_80),
        .O(\phase_H1_comp_V[38]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[38]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_64),
        .I1(p_Val2_6_fu_302_p2__0_n_81),
        .O(\phase_H1_comp_V[38]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[38]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_65),
        .I1(p_Val2_6_fu_302_p2__0_n_82),
        .O(\phase_H1_comp_V[38]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[38]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_66),
        .I1(p_Val2_6_fu_302_p2__0_n_83),
        .O(\phase_H1_comp_V[38]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[42]_INST_0 
       (.CI(\phase_H1_comp_V[38]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[42]_INST_0_n_0 ,\phase_H1_comp_V[42]_INST_0_n_1 ,\phase_H1_comp_V[42]_INST_0_n_2 ,\phase_H1_comp_V[42]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_59,p_Val2_6_fu_302_p2__2_n_60,p_Val2_6_fu_302_p2__2_n_61,p_Val2_6_fu_302_p2__2_n_62}),
        .O(phase_H1_comp_V[45:42]),
        .S({\phase_H1_comp_V[42]_INST_0_i_1_n_0 ,\phase_H1_comp_V[42]_INST_0_i_2_n_0 ,\phase_H1_comp_V[42]_INST_0_i_3_n_0 ,\phase_H1_comp_V[42]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[42]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_59),
        .I1(p_Val2_6_fu_302_p2__0_n_76),
        .O(\phase_H1_comp_V[42]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[42]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_60),
        .I1(p_Val2_6_fu_302_p2__0_n_77),
        .O(\phase_H1_comp_V[42]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[42]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_61),
        .I1(p_Val2_6_fu_302_p2__0_n_78),
        .O(\phase_H1_comp_V[42]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[42]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_62),
        .I1(p_Val2_6_fu_302_p2__0_n_79),
        .O(\phase_H1_comp_V[42]_INST_0_i_4_n_0 ));
  CARRY4 \phase_H1_comp_V[46]_INST_0 
       (.CI(\phase_H1_comp_V[42]_INST_0_n_0 ),
        .CO(\phase_H1_comp_V[46]_INST_0_n_3 ),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\phase_H1_comp_V[46]_INST_0_i_1_n_0 }),
        .O(phase_H1_comp_V[47:46]),
        .S({\<const0> ,\<const0> ,\phase_H1_comp_V[46]_INST_0_i_2_n_0 ,\phase_H1_comp_V[46]_INST_0_i_3_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \phase_H1_comp_V[46]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__0_n_75),
        .O(\phase_H1_comp_V[46]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \phase_H1_comp_V[46]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__0_n_75),
        .I1(p_Val2_6_fu_302_p2__0_n_74),
        .O(\phase_H1_comp_V[46]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[46]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__0_n_75),
        .I1(p_Val2_6_fu_302_p2__2_n_58),
        .O(\phase_H1_comp_V[46]_INST_0_i_3_n_0 ));
  CARRY4 \phase_H1_comp_V[6]_INST_0 
       (.CI(\phase_H1_comp_V[2]_INST_0_n_0 ),
        .CO({\phase_H1_comp_V[6]_INST_0_n_0 ,\phase_H1_comp_V[6]_INST_0_n_1 ,\phase_H1_comp_V[6]_INST_0_n_2 ,\phase_H1_comp_V[6]_INST_0_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_6_fu_302_p2__2_n_95,p_Val2_6_fu_302_p2__2_n_96,p_Val2_6_fu_302_p2__2_n_97,p_Val2_6_fu_302_p2__2_n_98}),
        .O(phase_H1_comp_V[9:6]),
        .S({\phase_H1_comp_V[6]_INST_0_i_1_n_0 ,\phase_H1_comp_V[6]_INST_0_i_2_n_0 ,\phase_H1_comp_V[6]_INST_0_i_3_n_0 ,\phase_H1_comp_V[6]_INST_0_i_4_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[6]_INST_0_i_1 
       (.I0(p_Val2_6_fu_302_p2__2_n_95),
        .I1(p_Val2_6_fu_302_p2_n_95),
        .O(\phase_H1_comp_V[6]_INST_0_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[6]_INST_0_i_2 
       (.I0(p_Val2_6_fu_302_p2__2_n_96),
        .I1(p_Val2_6_fu_302_p2_n_96),
        .O(\phase_H1_comp_V[6]_INST_0_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[6]_INST_0_i_3 
       (.I0(p_Val2_6_fu_302_p2__2_n_97),
        .I1(p_Val2_6_fu_302_p2_n_97),
        .O(\phase_H1_comp_V[6]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_comp_V[6]_INST_0_i_4 
       (.I0(p_Val2_6_fu_302_p2__2_n_98),
        .I1(p_Val2_6_fu_302_p2_n_98),
        .O(\phase_H1_comp_V[6]_INST_0_i_4_n_0 ));
endmodule

(* ORIG_REF_NAME = "RFNCO_Divider_HLSbkb" *) 
module RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLSbkb
   (start,
    done0,
    start0_reg,
    \quot_reg[31] ,
    \p_Val2_2_reg_418_reg[31] ,
    ap_clk,
    ap_rst,
    inputs_offset_H1_V_ap_vld_preg,
    inputs_rate_V_ap_vld_preg,
    Q,
    inputs_ftw_H1_V_ap_vld_preg,
    inputs_ftw_H1_on_V_ap_vld_preg,
    inputs_enable_FSK_ap_vld_preg,
    inputs_delay_comp_V_ap_vld_preg,
    \inputs_ftw_H1_V_preg_reg[36] );
  output start;
  output done0;
  output start0_reg;
  output [31:0]\quot_reg[31] ;
  output [31:0]\p_Val2_2_reg_418_reg[31] ;
  input ap_clk;
  input ap_rst;
  input inputs_offset_H1_V_ap_vld_preg;
  input inputs_rate_V_ap_vld_preg;
  input [5:0]Q;
  input inputs_ftw_H1_V_ap_vld_preg;
  input inputs_ftw_H1_on_V_ap_vld_preg;
  input inputs_enable_FSK_ap_vld_preg;
  input inputs_delay_comp_V_ap_vld_preg;
  input [36:0]\inputs_ftw_H1_V_preg_reg[36] ;

  wire [5:0]Q;
  wire ap_clk;
  wire ap_rst;
  wire done0;
  wire inputs_delay_comp_V_ap_vld_preg;
  wire inputs_enable_FSK_ap_vld_preg;
  wire inputs_ftw_H1_V_ap_vld_preg;
  wire [36:0]\inputs_ftw_H1_V_preg_reg[36] ;
  wire inputs_ftw_H1_on_V_ap_vld_preg;
  wire inputs_offset_H1_V_ap_vld_preg;
  wire inputs_rate_V_ap_vld_preg;
  wire [31:0]\p_Val2_2_reg_418_reg[31] ;
  wire [31:0]\quot_reg[31] ;
  wire start;
  wire start0_reg;

  RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLSbkb_div RFNCO_Divider_HLSbkb_div_U
       (.E(done0),
        .Q(Q),
        .ap_clk(ap_clk),
        .ap_rst(ap_rst),
        .inputs_delay_comp_V_ap_vld_preg(inputs_delay_comp_V_ap_vld_preg),
        .inputs_enable_FSK_ap_vld_preg(inputs_enable_FSK_ap_vld_preg),
        .inputs_ftw_H1_V_ap_vld_preg(inputs_ftw_H1_V_ap_vld_preg),
        .\inputs_ftw_H1_V_preg_reg[36] (\inputs_ftw_H1_V_preg_reg[36] ),
        .inputs_ftw_H1_on_V_ap_vld_preg(inputs_ftw_H1_on_V_ap_vld_preg),
        .inputs_offset_H1_V_ap_vld_preg(inputs_offset_H1_V_ap_vld_preg),
        .inputs_rate_V_ap_vld_preg(inputs_rate_V_ap_vld_preg),
        .\p_Val2_2_reg_418_reg[31] (\p_Val2_2_reg_418_reg[31] ),
        .\quot_reg[31]_0 (\quot_reg[31] ),
        .start(start),
        .start0_reg_0(start0_reg));
endmodule

(* ORIG_REF_NAME = "RFNCO_Divider_HLSbkb_div" *) 
module RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLSbkb_div
   (start,
    E,
    start0_reg_0,
    \quot_reg[31]_0 ,
    \p_Val2_2_reg_418_reg[31] ,
    ap_clk,
    ap_rst,
    inputs_offset_H1_V_ap_vld_preg,
    inputs_rate_V_ap_vld_preg,
    Q,
    inputs_ftw_H1_V_ap_vld_preg,
    inputs_ftw_H1_on_V_ap_vld_preg,
    inputs_enable_FSK_ap_vld_preg,
    inputs_delay_comp_V_ap_vld_preg,
    \inputs_ftw_H1_V_preg_reg[36] );
  output start;
  output [0:0]E;
  output start0_reg_0;
  output [31:0]\quot_reg[31]_0 ;
  output [31:0]\p_Val2_2_reg_418_reg[31] ;
  input ap_clk;
  input ap_rst;
  input inputs_offset_H1_V_ap_vld_preg;
  input inputs_rate_V_ap_vld_preg;
  input [5:0]Q;
  input inputs_ftw_H1_V_ap_vld_preg;
  input inputs_ftw_H1_on_V_ap_vld_preg;
  input inputs_enable_FSK_ap_vld_preg;
  input inputs_delay_comp_V_ap_vld_preg;
  input [36:0]\inputs_ftw_H1_V_preg_reg[36] ;

  wire \<const0> ;
  wire [0:0]E;
  wire [5:0]Q;
  wire RFNCO_Divider_HLSbkb_div_u_0_n_0;
  wire \ap_CS_fsm[2]_i_3_n_0 ;
  wire ap_clk;
  wire ap_rst;
  wire [36:0]divisor;
  wire inputs_delay_comp_V_ap_vld_preg;
  wire inputs_enable_FSK_ap_vld_preg;
  wire inputs_ftw_H1_V_ap_vld_preg;
  wire [36:0]\inputs_ftw_H1_V_preg_reg[36] ;
  wire inputs_ftw_H1_on_V_ap_vld_preg;
  wire inputs_offset_H1_V_ap_vld_preg;
  wire inputs_rate_V_ap_vld_preg;
  wire [31:0]\p_Val2_2_reg_418_reg[31] ;
  wire [31:0]\quot_reg[31]_0 ;
  wire start;
  wire start0_reg_0;
  wire start0_reg_n_0;

  GND GND
       (.G(\<const0> ));
  RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLSbkb_div_u RFNCO_Divider_HLSbkb_div_u_0
       (.E(start0_reg_n_0),
        .Q({Q[5:2],Q[0]}),
        .ap_clk(ap_clk),
        .ap_rst(ap_rst),
        .\divisor0_reg[36]_0 (divisor),
        .\quot_reg[0] (E),
        .\quot_reg[31] (\quot_reg[31]_0 ),
        .\r_stage_reg[0]_0 (RFNCO_Divider_HLSbkb_div_u_0_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \ap_CS_fsm[2]_i_1 
       (.I0(start0_reg_0),
        .O(start));
  LUT4 #(
    .INIT(16'hBFFF)) 
    \ap_CS_fsm[2]_i_2 
       (.I0(\ap_CS_fsm[2]_i_3_n_0 ),
        .I1(inputs_offset_H1_V_ap_vld_preg),
        .I2(inputs_rate_V_ap_vld_preg),
        .I3(Q[1]),
        .O(start0_reg_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \ap_CS_fsm[2]_i_3 
       (.I0(inputs_ftw_H1_V_ap_vld_preg),
        .I1(inputs_ftw_H1_on_V_ap_vld_preg),
        .I2(inputs_enable_FSK_ap_vld_preg),
        .I3(inputs_delay_comp_V_ap_vld_preg),
        .O(\ap_CS_fsm[2]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[0] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [0]),
        .Q(divisor[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[10] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [10]),
        .Q(divisor[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[11] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [11]),
        .Q(divisor[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[12] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [12]),
        .Q(divisor[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[13] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [13]),
        .Q(divisor[13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[14] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [14]),
        .Q(divisor[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[15] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [15]),
        .Q(divisor[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[16] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [16]),
        .Q(divisor[16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[17] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [17]),
        .Q(divisor[17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[18] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [18]),
        .Q(divisor[18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[19] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [19]),
        .Q(divisor[19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[1] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [1]),
        .Q(divisor[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[20] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [20]),
        .Q(divisor[20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[21] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [21]),
        .Q(divisor[21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[22] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [22]),
        .Q(divisor[22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[23] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [23]),
        .Q(divisor[23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[24] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [24]),
        .Q(divisor[24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[25] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [25]),
        .Q(divisor[25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[26] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [26]),
        .Q(divisor[26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[27] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [27]),
        .Q(divisor[27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[28] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [28]),
        .Q(divisor[28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[29] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [29]),
        .Q(divisor[29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[2] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [2]),
        .Q(divisor[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[30] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [30]),
        .Q(divisor[30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[31] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [31]),
        .Q(divisor[31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[32] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [32]),
        .Q(divisor[32]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[33] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [33]),
        .Q(divisor[33]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[34] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [34]),
        .Q(divisor[34]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[35] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [35]),
        .Q(divisor[35]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[36] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [36]),
        .Q(divisor[36]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[3] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [3]),
        .Q(divisor[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[4] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [4]),
        .Q(divisor[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[5] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [5]),
        .Q(divisor[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[6] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [6]),
        .Q(divisor[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[7] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [7]),
        .Q(divisor[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[8] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [8]),
        .Q(divisor[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[9] 
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(\inputs_ftw_H1_V_preg_reg[36] [9]),
        .Q(divisor[9]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[0] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [0]),
        .Q(\p_Val2_2_reg_418_reg[31] [0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[10] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [10]),
        .Q(\p_Val2_2_reg_418_reg[31] [10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[11] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [11]),
        .Q(\p_Val2_2_reg_418_reg[31] [11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[12] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [12]),
        .Q(\p_Val2_2_reg_418_reg[31] [12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[13] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [13]),
        .Q(\p_Val2_2_reg_418_reg[31] [13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[14] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [14]),
        .Q(\p_Val2_2_reg_418_reg[31] [14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[15] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [15]),
        .Q(\p_Val2_2_reg_418_reg[31] [15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[16] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [16]),
        .Q(\p_Val2_2_reg_418_reg[31] [16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[17] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [17]),
        .Q(\p_Val2_2_reg_418_reg[31] [17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[18] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [18]),
        .Q(\p_Val2_2_reg_418_reg[31] [18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[19] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [19]),
        .Q(\p_Val2_2_reg_418_reg[31] [19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[1] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [1]),
        .Q(\p_Val2_2_reg_418_reg[31] [1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[20] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [20]),
        .Q(\p_Val2_2_reg_418_reg[31] [20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[21] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [21]),
        .Q(\p_Val2_2_reg_418_reg[31] [21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[22] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [22]),
        .Q(\p_Val2_2_reg_418_reg[31] [22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[23] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [23]),
        .Q(\p_Val2_2_reg_418_reg[31] [23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[24] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [24]),
        .Q(\p_Val2_2_reg_418_reg[31] [24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[25] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [25]),
        .Q(\p_Val2_2_reg_418_reg[31] [25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[26] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [26]),
        .Q(\p_Val2_2_reg_418_reg[31] [26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[27] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [27]),
        .Q(\p_Val2_2_reg_418_reg[31] [27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[28] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [28]),
        .Q(\p_Val2_2_reg_418_reg[31] [28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[29] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [29]),
        .Q(\p_Val2_2_reg_418_reg[31] [29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[2] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [2]),
        .Q(\p_Val2_2_reg_418_reg[31] [2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[30] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [30]),
        .Q(\p_Val2_2_reg_418_reg[31] [30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[31] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [31]),
        .Q(\p_Val2_2_reg_418_reg[31] [31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[3] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [3]),
        .Q(\p_Val2_2_reg_418_reg[31] [3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[4] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [4]),
        .Q(\p_Val2_2_reg_418_reg[31] [4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[5] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [5]),
        .Q(\p_Val2_2_reg_418_reg[31] [5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[6] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [6]),
        .Q(\p_Val2_2_reg_418_reg[31] [6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[7] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [7]),
        .Q(\p_Val2_2_reg_418_reg[31] [7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[8] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [8]),
        .Q(\p_Val2_2_reg_418_reg[31] [8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \quot_reg[9] 
       (.C(ap_clk),
        .CE(E),
        .D(\quot_reg[31]_0 [9]),
        .Q(\p_Val2_2_reg_418_reg[31] [9]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    start0_reg
       (.C(ap_clk),
        .CE(RFNCO_Divider_HLSbkb_div_u_0_n_0),
        .D(start),
        .Q(start0_reg_n_0),
        .R(\<const0> ));
endmodule

(* ORIG_REF_NAME = "RFNCO_Divider_HLSbkb_div_u" *) 
module RFNCO_cmp_RFNCO_Divider_HLS_0_RFNCO_Divider_HLSbkb_div_u
   (\r_stage_reg[0]_0 ,
    \quot_reg[0] ,
    \quot_reg[31] ,
    ap_rst,
    E,
    ap_clk,
    Q,
    \divisor0_reg[36]_0 );
  output \r_stage_reg[0]_0 ;
  output [0:0]\quot_reg[0] ;
  output [31:0]\quot_reg[31] ;
  input ap_rst;
  input [0:0]E;
  input ap_clk;
  input [4:0]Q;
  input [36:0]\divisor0_reg[36]_0 ;

  wire \<const0> ;
  wire \<const1> ;
  wire [0:0]E;
  wire [4:0]Q;
  wire ap_clk;
  wire ap_rst;
  wire cal_tmp_carry__0_i_5_n_0;
  wire cal_tmp_carry__0_i_6_n_0;
  wire cal_tmp_carry__0_i_7_n_0;
  wire cal_tmp_carry__0_i_8_n_0;
  wire cal_tmp_carry__0_n_0;
  wire cal_tmp_carry__0_n_1;
  wire cal_tmp_carry__0_n_2;
  wire cal_tmp_carry__0_n_3;
  wire cal_tmp_carry__0_n_4;
  wire cal_tmp_carry__0_n_5;
  wire cal_tmp_carry__0_n_6;
  wire cal_tmp_carry__0_n_7;
  wire cal_tmp_carry__10_i_1_n_0;
  wire cal_tmp_carry__10_i_2_n_0;
  wire cal_tmp_carry__10_i_3_n_0;
  wire cal_tmp_carry__10_i_4_n_0;
  wire cal_tmp_carry__10_n_0;
  wire cal_tmp_carry__10_n_1;
  wire cal_tmp_carry__10_n_2;
  wire cal_tmp_carry__10_n_3;
  wire cal_tmp_carry__10_n_4;
  wire cal_tmp_carry__10_n_5;
  wire cal_tmp_carry__10_n_6;
  wire cal_tmp_carry__10_n_7;
  wire cal_tmp_carry__11_i_1_n_0;
  wire cal_tmp_carry__11_i_2_n_0;
  wire cal_tmp_carry__11_i_3_n_0;
  wire cal_tmp_carry__11_i_4_n_0;
  wire cal_tmp_carry__11_n_0;
  wire cal_tmp_carry__11_n_1;
  wire cal_tmp_carry__11_n_2;
  wire cal_tmp_carry__11_n_3;
  wire cal_tmp_carry__11_n_4;
  wire cal_tmp_carry__11_n_5;
  wire cal_tmp_carry__11_n_6;
  wire cal_tmp_carry__11_n_7;
  wire cal_tmp_carry__12_i_1_n_0;
  wire cal_tmp_carry__12_i_2_n_0;
  wire cal_tmp_carry__12_i_3_n_0;
  wire cal_tmp_carry__12_i_4_n_0;
  wire cal_tmp_carry__12_n_0;
  wire cal_tmp_carry__12_n_1;
  wire cal_tmp_carry__12_n_2;
  wire cal_tmp_carry__12_n_3;
  wire cal_tmp_carry__12_n_4;
  wire cal_tmp_carry__12_n_5;
  wire cal_tmp_carry__12_n_6;
  wire cal_tmp_carry__12_n_7;
  wire cal_tmp_carry__13_i_1_n_0;
  wire cal_tmp_carry__13_i_2_n_0;
  wire cal_tmp_carry__13_i_3_n_0;
  wire cal_tmp_carry__13_i_4_n_0;
  wire cal_tmp_carry__13_n_0;
  wire cal_tmp_carry__13_n_1;
  wire cal_tmp_carry__13_n_2;
  wire cal_tmp_carry__13_n_3;
  wire cal_tmp_carry__13_n_4;
  wire cal_tmp_carry__13_n_5;
  wire cal_tmp_carry__13_n_6;
  wire cal_tmp_carry__13_n_7;
  wire cal_tmp_carry__14_i_1_n_0;
  wire cal_tmp_carry__14_i_2_n_0;
  wire cal_tmp_carry__14_i_3_n_0;
  wire cal_tmp_carry__14_i_4_n_0;
  wire cal_tmp_carry__14_n_0;
  wire cal_tmp_carry__14_n_1;
  wire cal_tmp_carry__14_n_2;
  wire cal_tmp_carry__14_n_3;
  wire cal_tmp_carry__14_n_4;
  wire cal_tmp_carry__14_n_5;
  wire cal_tmp_carry__14_n_6;
  wire cal_tmp_carry__14_n_7;
  wire cal_tmp_carry__15_i_1_n_0;
  wire cal_tmp_carry__15_i_2_n_0;
  wire cal_tmp_carry__15_i_3_n_0;
  wire cal_tmp_carry__15_i_4_n_0;
  wire cal_tmp_carry__15_n_0;
  wire cal_tmp_carry__15_n_1;
  wire cal_tmp_carry__15_n_2;
  wire cal_tmp_carry__15_n_3;
  wire cal_tmp_carry__15_n_4;
  wire cal_tmp_carry__15_n_5;
  wire cal_tmp_carry__15_n_6;
  wire cal_tmp_carry__15_n_7;
  wire cal_tmp_carry__16_i_1_n_0;
  wire cal_tmp_carry__1_i_5_n_0;
  wire cal_tmp_carry__1_i_6_n_0;
  wire cal_tmp_carry__1_i_7_n_0;
  wire cal_tmp_carry__1_i_8_n_0;
  wire cal_tmp_carry__1_n_0;
  wire cal_tmp_carry__1_n_1;
  wire cal_tmp_carry__1_n_2;
  wire cal_tmp_carry__1_n_3;
  wire cal_tmp_carry__1_n_4;
  wire cal_tmp_carry__1_n_5;
  wire cal_tmp_carry__1_n_6;
  wire cal_tmp_carry__1_n_7;
  wire cal_tmp_carry__2_i_5_n_0;
  wire cal_tmp_carry__2_i_6_n_0;
  wire cal_tmp_carry__2_i_7_n_0;
  wire cal_tmp_carry__2_i_8_n_0;
  wire cal_tmp_carry__2_n_0;
  wire cal_tmp_carry__2_n_1;
  wire cal_tmp_carry__2_n_2;
  wire cal_tmp_carry__2_n_3;
  wire cal_tmp_carry__2_n_4;
  wire cal_tmp_carry__2_n_5;
  wire cal_tmp_carry__2_n_6;
  wire cal_tmp_carry__2_n_7;
  wire cal_tmp_carry__3_i_5_n_0;
  wire cal_tmp_carry__3_i_6_n_0;
  wire cal_tmp_carry__3_i_7_n_0;
  wire cal_tmp_carry__3_i_8_n_0;
  wire cal_tmp_carry__3_n_0;
  wire cal_tmp_carry__3_n_1;
  wire cal_tmp_carry__3_n_2;
  wire cal_tmp_carry__3_n_3;
  wire cal_tmp_carry__3_n_4;
  wire cal_tmp_carry__3_n_5;
  wire cal_tmp_carry__3_n_6;
  wire cal_tmp_carry__3_n_7;
  wire cal_tmp_carry__4_i_5_n_0;
  wire cal_tmp_carry__4_i_6_n_0;
  wire cal_tmp_carry__4_i_7_n_0;
  wire cal_tmp_carry__4_i_8_n_0;
  wire cal_tmp_carry__4_n_0;
  wire cal_tmp_carry__4_n_1;
  wire cal_tmp_carry__4_n_2;
  wire cal_tmp_carry__4_n_3;
  wire cal_tmp_carry__4_n_4;
  wire cal_tmp_carry__4_n_5;
  wire cal_tmp_carry__4_n_6;
  wire cal_tmp_carry__4_n_7;
  wire cal_tmp_carry__5_i_5_n_0;
  wire cal_tmp_carry__5_i_6_n_0;
  wire cal_tmp_carry__5_i_7_n_0;
  wire cal_tmp_carry__5_i_8_n_0;
  wire cal_tmp_carry__5_n_0;
  wire cal_tmp_carry__5_n_1;
  wire cal_tmp_carry__5_n_2;
  wire cal_tmp_carry__5_n_3;
  wire cal_tmp_carry__5_n_4;
  wire cal_tmp_carry__5_n_5;
  wire cal_tmp_carry__5_n_6;
  wire cal_tmp_carry__5_n_7;
  wire cal_tmp_carry__6_i_5_n_0;
  wire cal_tmp_carry__6_i_6_n_0;
  wire cal_tmp_carry__6_i_7_n_0;
  wire cal_tmp_carry__6_i_8_n_0;
  wire cal_tmp_carry__6_n_0;
  wire cal_tmp_carry__6_n_1;
  wire cal_tmp_carry__6_n_2;
  wire cal_tmp_carry__6_n_3;
  wire cal_tmp_carry__6_n_4;
  wire cal_tmp_carry__6_n_5;
  wire cal_tmp_carry__6_n_6;
  wire cal_tmp_carry__6_n_7;
  wire cal_tmp_carry__7_i_5_n_0;
  wire cal_tmp_carry__7_i_6_n_0;
  wire cal_tmp_carry__7_i_7_n_0;
  wire cal_tmp_carry__7_i_8_n_0;
  wire cal_tmp_carry__7_n_0;
  wire cal_tmp_carry__7_n_1;
  wire cal_tmp_carry__7_n_2;
  wire cal_tmp_carry__7_n_3;
  wire cal_tmp_carry__7_n_4;
  wire cal_tmp_carry__7_n_5;
  wire cal_tmp_carry__7_n_6;
  wire cal_tmp_carry__7_n_7;
  wire cal_tmp_carry__8_i_2_n_0;
  wire cal_tmp_carry__8_i_3_n_0;
  wire cal_tmp_carry__8_i_4_n_0;
  wire cal_tmp_carry__8_i_5_n_0;
  wire cal_tmp_carry__8_n_0;
  wire cal_tmp_carry__8_n_1;
  wire cal_tmp_carry__8_n_2;
  wire cal_tmp_carry__8_n_3;
  wire cal_tmp_carry__8_n_4;
  wire cal_tmp_carry__8_n_5;
  wire cal_tmp_carry__8_n_6;
  wire cal_tmp_carry__8_n_7;
  wire cal_tmp_carry__9_i_1_n_0;
  wire cal_tmp_carry__9_i_2_n_0;
  wire cal_tmp_carry__9_i_3_n_0;
  wire cal_tmp_carry__9_i_4_n_0;
  wire cal_tmp_carry__9_n_0;
  wire cal_tmp_carry__9_n_1;
  wire cal_tmp_carry__9_n_2;
  wire cal_tmp_carry__9_n_3;
  wire cal_tmp_carry__9_n_4;
  wire cal_tmp_carry__9_n_5;
  wire cal_tmp_carry__9_n_6;
  wire cal_tmp_carry__9_n_7;
  wire cal_tmp_carry_i_4_n_0;
  wire cal_tmp_carry_i_5_n_0;
  wire cal_tmp_carry_i_6_n_0;
  wire cal_tmp_carry_i_7_n_0;
  wire cal_tmp_carry_i_8_n_0;
  wire cal_tmp_carry_n_0;
  wire cal_tmp_carry_n_1;
  wire cal_tmp_carry_n_2;
  wire cal_tmp_carry_n_3;
  wire cal_tmp_carry_n_4;
  wire cal_tmp_carry_n_5;
  wire cal_tmp_carry_n_6;
  wire cal_tmp_carry_n_7;
  wire [68:32]dividend_tmp;
  wire \dividend_tmp[10]_i_1_n_0 ;
  wire \dividend_tmp[11]_i_1_n_0 ;
  wire \dividend_tmp[12]_i_1_n_0 ;
  wire \dividend_tmp[13]_i_1_n_0 ;
  wire \dividend_tmp[14]_i_1_n_0 ;
  wire \dividend_tmp[15]_i_1_n_0 ;
  wire \dividend_tmp[16]_i_1_n_0 ;
  wire \dividend_tmp[17]_i_1_n_0 ;
  wire \dividend_tmp[18]_i_1_n_0 ;
  wire \dividend_tmp[19]_i_1_n_0 ;
  wire \dividend_tmp[1]_i_1_n_0 ;
  wire \dividend_tmp[20]_i_1_n_0 ;
  wire \dividend_tmp[21]_i_1_n_0 ;
  wire \dividend_tmp[22]_i_1_n_0 ;
  wire \dividend_tmp[23]_i_1_n_0 ;
  wire \dividend_tmp[24]_i_1_n_0 ;
  wire \dividend_tmp[25]_i_1_n_0 ;
  wire \dividend_tmp[26]_i_1_n_0 ;
  wire \dividend_tmp[27]_i_1_n_0 ;
  wire \dividend_tmp[28]_i_1_n_0 ;
  wire \dividend_tmp[29]_i_1_n_0 ;
  wire \dividend_tmp[2]_i_1_n_0 ;
  wire \dividend_tmp[30]_i_1_n_0 ;
  wire \dividend_tmp[31]_i_1_n_0 ;
  wire \dividend_tmp[32]_i_1_n_0 ;
  wire \dividend_tmp[33]_i_1_n_0 ;
  wire \dividend_tmp[34]_i_1_n_0 ;
  wire \dividend_tmp[35]_i_1_n_0 ;
  wire \dividend_tmp[36]_i_1_n_0 ;
  wire \dividend_tmp[37]_i_1_n_0 ;
  wire \dividend_tmp[38]_i_1_n_0 ;
  wire \dividend_tmp[39]_i_1_n_0 ;
  wire \dividend_tmp[3]_i_1_n_0 ;
  wire \dividend_tmp[40]_i_1_n_0 ;
  wire \dividend_tmp[41]_i_1_n_0 ;
  wire \dividend_tmp[42]_i_1_n_0 ;
  wire \dividend_tmp[43]_i_1_n_0 ;
  wire \dividend_tmp[44]_i_1_n_0 ;
  wire \dividend_tmp[45]_i_1_n_0 ;
  wire \dividend_tmp[46]_i_1_n_0 ;
  wire \dividend_tmp[47]_i_1_n_0 ;
  wire \dividend_tmp[48]_i_1_n_0 ;
  wire \dividend_tmp[49]_i_1_n_0 ;
  wire \dividend_tmp[4]_i_1_n_0 ;
  wire \dividend_tmp[50]_i_1_n_0 ;
  wire \dividend_tmp[51]_i_1_n_0 ;
  wire \dividend_tmp[52]_i_1_n_0 ;
  wire \dividend_tmp[53]_i_1_n_0 ;
  wire \dividend_tmp[54]_i_1_n_0 ;
  wire \dividend_tmp[55]_i_1_n_0 ;
  wire \dividend_tmp[56]_i_1_n_0 ;
  wire \dividend_tmp[57]_i_1_n_0 ;
  wire \dividend_tmp[58]_i_1_n_0 ;
  wire \dividend_tmp[59]_i_1_n_0 ;
  wire \dividend_tmp[5]_i_1_n_0 ;
  wire \dividend_tmp[60]_i_1_n_0 ;
  wire \dividend_tmp[61]_i_1_n_0 ;
  wire \dividend_tmp[62]_i_1_n_0 ;
  wire \dividend_tmp[63]_i_1_n_0 ;
  wire \dividend_tmp[64]_i_1_n_0 ;
  wire \dividend_tmp[65]_i_1_n_0 ;
  wire \dividend_tmp[66]_i_1_n_0 ;
  wire \dividend_tmp[67]_i_1_n_0 ;
  wire \dividend_tmp[68]_i_1_n_0 ;
  wire \dividend_tmp[6]_i_1_n_0 ;
  wire \dividend_tmp[7]_i_1_n_0 ;
  wire \dividend_tmp[8]_i_1_n_0 ;
  wire \dividend_tmp[9]_i_1_n_0 ;
  wire [36:0]divisor0;
  wire [36:0]\divisor0_reg[36]_0 ;
  wire p_0_in;
  wire [0:0]p_2_out;
  wire [0:0]\quot_reg[0] ;
  wire [31:0]\quot_reg[31] ;
  wire \r_stage_reg[0]_0 ;
  wire \r_stage_reg[0]_rep_n_0 ;
  wire \r_stage_reg[32]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_30_n_1 ;
  wire \r_stage_reg[64]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_62_n_1 ;
  wire \r_stage_reg[67]_srl3___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_65_n_0 ;
  wire \r_stage_reg[68]_RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_66_n_0 ;
  wire r_stage_reg_gate_n_0;
  wire \r_stage_reg_n_0_[0] ;
  wire r_stage_reg_r_0_n_0;
  wire r_stage_reg_r_10_n_0;
  wire r_stage_reg_r_11_n_0;
  wire r_stage_reg_r_12_n_0;
  wire r_stage_reg_r_13_n_0;
  wire r_stage_reg_r_14_n_0;
  wire r_stage_reg_r_15_n_0;
  wire r_stage_reg_r_16_n_0;
  wire r_stage_reg_r_17_n_0;
  wire r_stage_reg_r_18_n_0;
  wire r_stage_reg_r_19_n_0;
  wire r_stage_reg_r_1_n_0;
  wire r_stage_reg_r_20_n_0;
  wire r_stage_reg_r_21_n_0;
  wire r_stage_reg_r_22_n_0;
  wire r_stage_reg_r_23_n_0;
  wire r_stage_reg_r_24_n_0;
  wire r_stage_reg_r_25_n_0;
  wire r_stage_reg_r_26_n_0;
  wire r_stage_reg_r_27_n_0;
  wire r_stage_reg_r_28_n_0;
  wire r_stage_reg_r_29_n_0;
  wire r_stage_reg_r_2_n_0;
  wire r_stage_reg_r_30_n_0;
  wire r_stage_reg_r_31_n_0;
  wire r_stage_reg_r_32_n_0;
  wire r_stage_reg_r_33_n_0;
  wire r_stage_reg_r_34_n_0;
  wire r_stage_reg_r_35_n_0;
  wire r_stage_reg_r_36_n_0;
  wire r_stage_reg_r_37_n_0;
  wire r_stage_reg_r_38_n_0;
  wire r_stage_reg_r_39_n_0;
  wire r_stage_reg_r_3_n_0;
  wire r_stage_reg_r_40_n_0;
  wire r_stage_reg_r_41_n_0;
  wire r_stage_reg_r_42_n_0;
  wire r_stage_reg_r_43_n_0;
  wire r_stage_reg_r_44_n_0;
  wire r_stage_reg_r_45_n_0;
  wire r_stage_reg_r_46_n_0;
  wire r_stage_reg_r_47_n_0;
  wire r_stage_reg_r_48_n_0;
  wire r_stage_reg_r_49_n_0;
  wire r_stage_reg_r_4_n_0;
  wire r_stage_reg_r_50_n_0;
  wire r_stage_reg_r_51_n_0;
  wire r_stage_reg_r_52_n_0;
  wire r_stage_reg_r_53_n_0;
  wire r_stage_reg_r_54_n_0;
  wire r_stage_reg_r_55_n_0;
  wire r_stage_reg_r_56_n_0;
  wire r_stage_reg_r_57_n_0;
  wire r_stage_reg_r_58_n_0;
  wire r_stage_reg_r_59_n_0;
  wire r_stage_reg_r_5_n_0;
  wire r_stage_reg_r_60_n_0;
  wire r_stage_reg_r_61_n_0;
  wire r_stage_reg_r_62_n_0;
  wire r_stage_reg_r_63_n_0;
  wire r_stage_reg_r_64_n_0;
  wire r_stage_reg_r_65_n_0;
  wire r_stage_reg_r_66_n_0;
  wire r_stage_reg_r_6_n_0;
  wire r_stage_reg_r_7_n_0;
  wire r_stage_reg_r_8_n_0;
  wire r_stage_reg_r_9_n_0;
  wire r_stage_reg_r_n_0;
  wire [67:0]remd_tmp;
  wire \remd_tmp[0]_i_1_n_0 ;
  wire \remd_tmp[10]_i_1_n_0 ;
  wire \remd_tmp[11]_i_1_n_0 ;
  wire \remd_tmp[12]_i_1_n_0 ;
  wire \remd_tmp[13]_i_1_n_0 ;
  wire \remd_tmp[14]_i_1_n_0 ;
  wire \remd_tmp[15]_i_1_n_0 ;
  wire \remd_tmp[16]_i_1_n_0 ;
  wire \remd_tmp[17]_i_1_n_0 ;
  wire \remd_tmp[18]_i_1_n_0 ;
  wire \remd_tmp[19]_i_1_n_0 ;
  wire \remd_tmp[1]_i_1_n_0 ;
  wire \remd_tmp[20]_i_1_n_0 ;
  wire \remd_tmp[21]_i_1_n_0 ;
  wire \remd_tmp[22]_i_1_n_0 ;
  wire \remd_tmp[23]_i_1_n_0 ;
  wire \remd_tmp[24]_i_1_n_0 ;
  wire \remd_tmp[25]_i_1_n_0 ;
  wire \remd_tmp[26]_i_1_n_0 ;
  wire \remd_tmp[27]_i_1_n_0 ;
  wire \remd_tmp[28]_i_1_n_0 ;
  wire \remd_tmp[29]_i_1_n_0 ;
  wire \remd_tmp[2]_i_1_n_0 ;
  wire \remd_tmp[30]_i_1_n_0 ;
  wire \remd_tmp[31]_i_1_n_0 ;
  wire \remd_tmp[32]_i_1_n_0 ;
  wire \remd_tmp[33]_i_1_n_0 ;
  wire \remd_tmp[34]_i_1_n_0 ;
  wire \remd_tmp[35]_i_1_n_0 ;
  wire \remd_tmp[36]_i_1_n_0 ;
  wire \remd_tmp[37]_i_1_n_0 ;
  wire \remd_tmp[38]_i_1_n_0 ;
  wire \remd_tmp[39]_i_1_n_0 ;
  wire \remd_tmp[3]_i_1_n_0 ;
  wire \remd_tmp[40]_i_1_n_0 ;
  wire \remd_tmp[41]_i_1_n_0 ;
  wire \remd_tmp[42]_i_1_n_0 ;
  wire \remd_tmp[43]_i_1_n_0 ;
  wire \remd_tmp[44]_i_1_n_0 ;
  wire \remd_tmp[45]_i_1_n_0 ;
  wire \remd_tmp[46]_i_1_n_0 ;
  wire \remd_tmp[47]_i_1_n_0 ;
  wire \remd_tmp[48]_i_1_n_0 ;
  wire \remd_tmp[49]_i_1_n_0 ;
  wire \remd_tmp[4]_i_1_n_0 ;
  wire \remd_tmp[50]_i_1_n_0 ;
  wire \remd_tmp[51]_i_1_n_0 ;
  wire \remd_tmp[52]_i_1_n_0 ;
  wire \remd_tmp[53]_i_1_n_0 ;
  wire \remd_tmp[54]_i_1_n_0 ;
  wire \remd_tmp[55]_i_1_n_0 ;
  wire \remd_tmp[56]_i_1_n_0 ;
  wire \remd_tmp[57]_i_1_n_0 ;
  wire \remd_tmp[58]_i_1_n_0 ;
  wire \remd_tmp[59]_i_1_n_0 ;
  wire \remd_tmp[5]_i_1_n_0 ;
  wire \remd_tmp[60]_i_1_n_0 ;
  wire \remd_tmp[61]_i_1_n_0 ;
  wire \remd_tmp[62]_i_1_n_0 ;
  wire \remd_tmp[63]_i_1_n_0 ;
  wire \remd_tmp[64]_i_1_n_0 ;
  wire \remd_tmp[65]_i_1_n_0 ;
  wire \remd_tmp[66]_i_1_n_0 ;
  wire \remd_tmp[67]_i_1_n_0 ;
  wire \remd_tmp[6]_i_1_n_0 ;
  wire \remd_tmp[7]_i_1_n_0 ;
  wire \remd_tmp[8]_i_1_n_0 ;
  wire \remd_tmp[9]_i_1_n_0 ;
  wire [35:0]remd_tmp_mux;
  wire [3:0]NLW_cal_tmp_carry__16_O_UNCONNECTED;

  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  CARRY4 cal_tmp_carry
       (.CI(\<const0> ),
        .CO({cal_tmp_carry_n_0,cal_tmp_carry_n_1,cal_tmp_carry_n_2,cal_tmp_carry_n_3}),
        .CYINIT(\<const1> ),
        .DI({remd_tmp_mux[2:0],cal_tmp_carry_i_4_n_0}),
        .O({cal_tmp_carry_n_4,cal_tmp_carry_n_5,cal_tmp_carry_n_6,cal_tmp_carry_n_7}),
        .S({cal_tmp_carry_i_5_n_0,cal_tmp_carry_i_6_n_0,cal_tmp_carry_i_7_n_0,cal_tmp_carry_i_8_n_0}));
  CARRY4 cal_tmp_carry__0
       (.CI(cal_tmp_carry_n_0),
        .CO({cal_tmp_carry__0_n_0,cal_tmp_carry__0_n_1,cal_tmp_carry__0_n_2,cal_tmp_carry__0_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[6:3]),
        .O({cal_tmp_carry__0_n_4,cal_tmp_carry__0_n_5,cal_tmp_carry__0_n_6,cal_tmp_carry__0_n_7}),
        .S({cal_tmp_carry__0_i_5_n_0,cal_tmp_carry__0_i_6_n_0,cal_tmp_carry__0_i_7_n_0,cal_tmp_carry__0_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__0_i_1
       (.I0(remd_tmp[6]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[6]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__0_i_2
       (.I0(remd_tmp[5]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[5]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__0_i_3
       (.I0(remd_tmp[4]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[4]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__0_i_4
       (.I0(remd_tmp[3]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[3]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__0_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[6]),
        .I2(divisor0[7]),
        .O(cal_tmp_carry__0_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__0_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[5]),
        .I2(divisor0[6]),
        .O(cal_tmp_carry__0_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__0_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[4]),
        .I2(divisor0[5]),
        .O(cal_tmp_carry__0_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__0_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[3]),
        .I2(divisor0[4]),
        .O(cal_tmp_carry__0_i_8_n_0));
  CARRY4 cal_tmp_carry__1
       (.CI(cal_tmp_carry__0_n_0),
        .CO({cal_tmp_carry__1_n_0,cal_tmp_carry__1_n_1,cal_tmp_carry__1_n_2,cal_tmp_carry__1_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[10:7]),
        .O({cal_tmp_carry__1_n_4,cal_tmp_carry__1_n_5,cal_tmp_carry__1_n_6,cal_tmp_carry__1_n_7}),
        .S({cal_tmp_carry__1_i_5_n_0,cal_tmp_carry__1_i_6_n_0,cal_tmp_carry__1_i_7_n_0,cal_tmp_carry__1_i_8_n_0}));
  CARRY4 cal_tmp_carry__10
       (.CI(cal_tmp_carry__9_n_0),
        .CO({cal_tmp_carry__10_n_0,cal_tmp_carry__10_n_1,cal_tmp_carry__10_n_2,cal_tmp_carry__10_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__10_n_4,cal_tmp_carry__10_n_5,cal_tmp_carry__10_n_6,cal_tmp_carry__10_n_7}),
        .S({cal_tmp_carry__10_i_1_n_0,cal_tmp_carry__10_i_2_n_0,cal_tmp_carry__10_i_3_n_0,cal_tmp_carry__10_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__10_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[46]),
        .O(cal_tmp_carry__10_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__10_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[45]),
        .O(cal_tmp_carry__10_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__10_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[44]),
        .O(cal_tmp_carry__10_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__10_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[43]),
        .O(cal_tmp_carry__10_i_4_n_0));
  CARRY4 cal_tmp_carry__11
       (.CI(cal_tmp_carry__10_n_0),
        .CO({cal_tmp_carry__11_n_0,cal_tmp_carry__11_n_1,cal_tmp_carry__11_n_2,cal_tmp_carry__11_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__11_n_4,cal_tmp_carry__11_n_5,cal_tmp_carry__11_n_6,cal_tmp_carry__11_n_7}),
        .S({cal_tmp_carry__11_i_1_n_0,cal_tmp_carry__11_i_2_n_0,cal_tmp_carry__11_i_3_n_0,cal_tmp_carry__11_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__11_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[50]),
        .O(cal_tmp_carry__11_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__11_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[49]),
        .O(cal_tmp_carry__11_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__11_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[48]),
        .O(cal_tmp_carry__11_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__11_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[47]),
        .O(cal_tmp_carry__11_i_4_n_0));
  CARRY4 cal_tmp_carry__12
       (.CI(cal_tmp_carry__11_n_0),
        .CO({cal_tmp_carry__12_n_0,cal_tmp_carry__12_n_1,cal_tmp_carry__12_n_2,cal_tmp_carry__12_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__12_n_4,cal_tmp_carry__12_n_5,cal_tmp_carry__12_n_6,cal_tmp_carry__12_n_7}),
        .S({cal_tmp_carry__12_i_1_n_0,cal_tmp_carry__12_i_2_n_0,cal_tmp_carry__12_i_3_n_0,cal_tmp_carry__12_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__12_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[54]),
        .O(cal_tmp_carry__12_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__12_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[53]),
        .O(cal_tmp_carry__12_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__12_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[52]),
        .O(cal_tmp_carry__12_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__12_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[51]),
        .O(cal_tmp_carry__12_i_4_n_0));
  CARRY4 cal_tmp_carry__13
       (.CI(cal_tmp_carry__12_n_0),
        .CO({cal_tmp_carry__13_n_0,cal_tmp_carry__13_n_1,cal_tmp_carry__13_n_2,cal_tmp_carry__13_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__13_n_4,cal_tmp_carry__13_n_5,cal_tmp_carry__13_n_6,cal_tmp_carry__13_n_7}),
        .S({cal_tmp_carry__13_i_1_n_0,cal_tmp_carry__13_i_2_n_0,cal_tmp_carry__13_i_3_n_0,cal_tmp_carry__13_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__13_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[58]),
        .O(cal_tmp_carry__13_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__13_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[57]),
        .O(cal_tmp_carry__13_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__13_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[56]),
        .O(cal_tmp_carry__13_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__13_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[55]),
        .O(cal_tmp_carry__13_i_4_n_0));
  CARRY4 cal_tmp_carry__14
       (.CI(cal_tmp_carry__13_n_0),
        .CO({cal_tmp_carry__14_n_0,cal_tmp_carry__14_n_1,cal_tmp_carry__14_n_2,cal_tmp_carry__14_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__14_n_4,cal_tmp_carry__14_n_5,cal_tmp_carry__14_n_6,cal_tmp_carry__14_n_7}),
        .S({cal_tmp_carry__14_i_1_n_0,cal_tmp_carry__14_i_2_n_0,cal_tmp_carry__14_i_3_n_0,cal_tmp_carry__14_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__14_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[62]),
        .O(cal_tmp_carry__14_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__14_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[61]),
        .O(cal_tmp_carry__14_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__14_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[60]),
        .O(cal_tmp_carry__14_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__14_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[59]),
        .O(cal_tmp_carry__14_i_4_n_0));
  CARRY4 cal_tmp_carry__15
       (.CI(cal_tmp_carry__14_n_0),
        .CO({cal_tmp_carry__15_n_0,cal_tmp_carry__15_n_1,cal_tmp_carry__15_n_2,cal_tmp_carry__15_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__15_n_4,cal_tmp_carry__15_n_5,cal_tmp_carry__15_n_6,cal_tmp_carry__15_n_7}),
        .S({cal_tmp_carry__15_i_1_n_0,cal_tmp_carry__15_i_2_n_0,cal_tmp_carry__15_i_3_n_0,cal_tmp_carry__15_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__15_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[66]),
        .O(cal_tmp_carry__15_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__15_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[65]),
        .O(cal_tmp_carry__15_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__15_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[64]),
        .O(cal_tmp_carry__15_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__15_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[63]),
        .O(cal_tmp_carry__15_i_4_n_0));
  CARRY4 cal_tmp_carry__16
       (.CI(cal_tmp_carry__15_n_0),
        .CO(p_2_out),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }),
        .O({p_0_in,NLW_cal_tmp_carry__16_O_UNCONNECTED[0]}),
        .S({\<const0> ,\<const0> ,\<const1> ,cal_tmp_carry__16_i_1_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__16_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[67]),
        .O(cal_tmp_carry__16_i_1_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__1_i_1
       (.I0(remd_tmp[10]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[10]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__1_i_2
       (.I0(remd_tmp[9]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[9]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__1_i_3
       (.I0(remd_tmp[8]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[8]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__1_i_4
       (.I0(remd_tmp[7]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[7]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__1_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[10]),
        .I2(divisor0[11]),
        .O(cal_tmp_carry__1_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__1_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[9]),
        .I2(divisor0[10]),
        .O(cal_tmp_carry__1_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__1_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[8]),
        .I2(divisor0[9]),
        .O(cal_tmp_carry__1_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__1_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[7]),
        .I2(divisor0[8]),
        .O(cal_tmp_carry__1_i_8_n_0));
  CARRY4 cal_tmp_carry__2
       (.CI(cal_tmp_carry__1_n_0),
        .CO({cal_tmp_carry__2_n_0,cal_tmp_carry__2_n_1,cal_tmp_carry__2_n_2,cal_tmp_carry__2_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[14:11]),
        .O({cal_tmp_carry__2_n_4,cal_tmp_carry__2_n_5,cal_tmp_carry__2_n_6,cal_tmp_carry__2_n_7}),
        .S({cal_tmp_carry__2_i_5_n_0,cal_tmp_carry__2_i_6_n_0,cal_tmp_carry__2_i_7_n_0,cal_tmp_carry__2_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__2_i_1
       (.I0(remd_tmp[14]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[14]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__2_i_2
       (.I0(remd_tmp[13]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[13]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__2_i_3
       (.I0(remd_tmp[12]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[12]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__2_i_4
       (.I0(remd_tmp[11]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[11]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__2_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[14]),
        .I2(divisor0[15]),
        .O(cal_tmp_carry__2_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__2_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[13]),
        .I2(divisor0[14]),
        .O(cal_tmp_carry__2_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__2_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[12]),
        .I2(divisor0[13]),
        .O(cal_tmp_carry__2_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__2_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[11]),
        .I2(divisor0[12]),
        .O(cal_tmp_carry__2_i_8_n_0));
  CARRY4 cal_tmp_carry__3
       (.CI(cal_tmp_carry__2_n_0),
        .CO({cal_tmp_carry__3_n_0,cal_tmp_carry__3_n_1,cal_tmp_carry__3_n_2,cal_tmp_carry__3_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[18:15]),
        .O({cal_tmp_carry__3_n_4,cal_tmp_carry__3_n_5,cal_tmp_carry__3_n_6,cal_tmp_carry__3_n_7}),
        .S({cal_tmp_carry__3_i_5_n_0,cal_tmp_carry__3_i_6_n_0,cal_tmp_carry__3_i_7_n_0,cal_tmp_carry__3_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__3_i_1
       (.I0(remd_tmp[18]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[18]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__3_i_2
       (.I0(remd_tmp[17]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[17]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__3_i_3
       (.I0(remd_tmp[16]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[16]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__3_i_4
       (.I0(remd_tmp[15]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[15]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__3_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[18]),
        .I2(divisor0[19]),
        .O(cal_tmp_carry__3_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__3_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[17]),
        .I2(divisor0[18]),
        .O(cal_tmp_carry__3_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__3_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[16]),
        .I2(divisor0[17]),
        .O(cal_tmp_carry__3_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__3_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[15]),
        .I2(divisor0[16]),
        .O(cal_tmp_carry__3_i_8_n_0));
  CARRY4 cal_tmp_carry__4
       (.CI(cal_tmp_carry__3_n_0),
        .CO({cal_tmp_carry__4_n_0,cal_tmp_carry__4_n_1,cal_tmp_carry__4_n_2,cal_tmp_carry__4_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[22:19]),
        .O({cal_tmp_carry__4_n_4,cal_tmp_carry__4_n_5,cal_tmp_carry__4_n_6,cal_tmp_carry__4_n_7}),
        .S({cal_tmp_carry__4_i_5_n_0,cal_tmp_carry__4_i_6_n_0,cal_tmp_carry__4_i_7_n_0,cal_tmp_carry__4_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__4_i_1
       (.I0(remd_tmp[22]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[22]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__4_i_2
       (.I0(remd_tmp[21]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[21]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__4_i_3
       (.I0(remd_tmp[20]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[20]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__4_i_4
       (.I0(remd_tmp[19]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[19]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__4_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[22]),
        .I2(divisor0[23]),
        .O(cal_tmp_carry__4_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__4_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[21]),
        .I2(divisor0[22]),
        .O(cal_tmp_carry__4_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__4_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[20]),
        .I2(divisor0[21]),
        .O(cal_tmp_carry__4_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__4_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[19]),
        .I2(divisor0[20]),
        .O(cal_tmp_carry__4_i_8_n_0));
  CARRY4 cal_tmp_carry__5
       (.CI(cal_tmp_carry__4_n_0),
        .CO({cal_tmp_carry__5_n_0,cal_tmp_carry__5_n_1,cal_tmp_carry__5_n_2,cal_tmp_carry__5_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[26:23]),
        .O({cal_tmp_carry__5_n_4,cal_tmp_carry__5_n_5,cal_tmp_carry__5_n_6,cal_tmp_carry__5_n_7}),
        .S({cal_tmp_carry__5_i_5_n_0,cal_tmp_carry__5_i_6_n_0,cal_tmp_carry__5_i_7_n_0,cal_tmp_carry__5_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__5_i_1
       (.I0(remd_tmp[26]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[26]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__5_i_2
       (.I0(remd_tmp[25]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[25]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__5_i_3
       (.I0(remd_tmp[24]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[24]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__5_i_4
       (.I0(remd_tmp[23]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[23]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__5_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[26]),
        .I2(divisor0[27]),
        .O(cal_tmp_carry__5_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__5_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[25]),
        .I2(divisor0[26]),
        .O(cal_tmp_carry__5_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__5_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[24]),
        .I2(divisor0[25]),
        .O(cal_tmp_carry__5_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__5_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[23]),
        .I2(divisor0[24]),
        .O(cal_tmp_carry__5_i_8_n_0));
  CARRY4 cal_tmp_carry__6
       (.CI(cal_tmp_carry__5_n_0),
        .CO({cal_tmp_carry__6_n_0,cal_tmp_carry__6_n_1,cal_tmp_carry__6_n_2,cal_tmp_carry__6_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[30:27]),
        .O({cal_tmp_carry__6_n_4,cal_tmp_carry__6_n_5,cal_tmp_carry__6_n_6,cal_tmp_carry__6_n_7}),
        .S({cal_tmp_carry__6_i_5_n_0,cal_tmp_carry__6_i_6_n_0,cal_tmp_carry__6_i_7_n_0,cal_tmp_carry__6_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__6_i_1
       (.I0(remd_tmp[30]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[30]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__6_i_2
       (.I0(remd_tmp[29]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[29]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__6_i_3
       (.I0(remd_tmp[28]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[28]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__6_i_4
       (.I0(remd_tmp[27]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[27]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__6_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[30]),
        .I2(divisor0[31]),
        .O(cal_tmp_carry__6_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__6_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[29]),
        .I2(divisor0[30]),
        .O(cal_tmp_carry__6_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__6_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[28]),
        .I2(divisor0[29]),
        .O(cal_tmp_carry__6_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__6_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[27]),
        .I2(divisor0[28]),
        .O(cal_tmp_carry__6_i_8_n_0));
  CARRY4 cal_tmp_carry__7
       (.CI(cal_tmp_carry__6_n_0),
        .CO({cal_tmp_carry__7_n_0,cal_tmp_carry__7_n_1,cal_tmp_carry__7_n_2,cal_tmp_carry__7_n_3}),
        .CYINIT(\<const0> ),
        .DI(remd_tmp_mux[34:31]),
        .O({cal_tmp_carry__7_n_4,cal_tmp_carry__7_n_5,cal_tmp_carry__7_n_6,cal_tmp_carry__7_n_7}),
        .S({cal_tmp_carry__7_i_5_n_0,cal_tmp_carry__7_i_6_n_0,cal_tmp_carry__7_i_7_n_0,cal_tmp_carry__7_i_8_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__7_i_1
       (.I0(remd_tmp[34]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[34]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__7_i_2
       (.I0(remd_tmp[33]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[33]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__7_i_3
       (.I0(remd_tmp[32]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[32]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__7_i_4
       (.I0(remd_tmp[31]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[31]));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__7_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[34]),
        .I2(divisor0[35]),
        .O(cal_tmp_carry__7_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__7_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[33]),
        .I2(divisor0[34]),
        .O(cal_tmp_carry__7_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__7_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[32]),
        .I2(divisor0[33]),
        .O(cal_tmp_carry__7_i_7_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__7_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[31]),
        .I2(divisor0[32]),
        .O(cal_tmp_carry__7_i_8_n_0));
  CARRY4 cal_tmp_carry__8
       (.CI(cal_tmp_carry__7_n_0),
        .CO({cal_tmp_carry__8_n_0,cal_tmp_carry__8_n_1,cal_tmp_carry__8_n_2,cal_tmp_carry__8_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,remd_tmp_mux[35]}),
        .O({cal_tmp_carry__8_n_4,cal_tmp_carry__8_n_5,cal_tmp_carry__8_n_6,cal_tmp_carry__8_n_7}),
        .S({cal_tmp_carry__8_i_2_n_0,cal_tmp_carry__8_i_3_n_0,cal_tmp_carry__8_i_4_n_0,cal_tmp_carry__8_i_5_n_0}));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry__8_i_1
       (.I0(remd_tmp[35]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[35]));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__8_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[38]),
        .O(cal_tmp_carry__8_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__8_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[37]),
        .O(cal_tmp_carry__8_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__8_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[36]),
        .O(cal_tmp_carry__8_i_4_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry__8_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[35]),
        .I2(divisor0[36]),
        .O(cal_tmp_carry__8_i_5_n_0));
  CARRY4 cal_tmp_carry__9
       (.CI(cal_tmp_carry__8_n_0),
        .CO({cal_tmp_carry__9_n_0,cal_tmp_carry__9_n_1,cal_tmp_carry__9_n_2,cal_tmp_carry__9_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O({cal_tmp_carry__9_n_4,cal_tmp_carry__9_n_5,cal_tmp_carry__9_n_6,cal_tmp_carry__9_n_7}),
        .S({cal_tmp_carry__9_i_1_n_0,cal_tmp_carry__9_i_2_n_0,cal_tmp_carry__9_i_3_n_0,cal_tmp_carry__9_i_4_n_0}));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__9_i_1
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[42]),
        .O(cal_tmp_carry__9_i_1_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__9_i_2
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[41]),
        .O(cal_tmp_carry__9_i_2_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__9_i_3
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[40]),
        .O(cal_tmp_carry__9_i_3_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    cal_tmp_carry__9_i_4
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[39]),
        .O(cal_tmp_carry__9_i_4_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry_i_1
       (.I0(remd_tmp[2]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[2]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry_i_2
       (.I0(remd_tmp[1]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[1]));
  LUT2 #(
    .INIT(4'h2)) 
    cal_tmp_carry_i_3
       (.I0(remd_tmp[0]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(remd_tmp_mux[0]));
  LUT2 #(
    .INIT(4'hE)) 
    cal_tmp_carry_i_4
       (.I0(dividend_tmp[68]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(cal_tmp_carry_i_4_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry_i_5
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[2]),
        .I2(divisor0[3]),
        .O(cal_tmp_carry_i_5_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry_i_6
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[1]),
        .I2(divisor0[2]),
        .O(cal_tmp_carry_i_6_n_0));
  LUT3 #(
    .INIT(8'h4B)) 
    cal_tmp_carry_i_7
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(remd_tmp[0]),
        .I2(divisor0[1]),
        .O(cal_tmp_carry_i_7_n_0));
  LUT3 #(
    .INIT(8'hE1)) 
    cal_tmp_carry_i_8
       (.I0(\r_stage_reg_n_0_[0] ),
        .I1(dividend_tmp[68]),
        .I2(divisor0[0]),
        .O(cal_tmp_carry_i_8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[10]_i_1 
       (.I0(\quot_reg[31] [9]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[11]_i_1 
       (.I0(\quot_reg[31] [10]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[12]_i_1 
       (.I0(\quot_reg[31] [11]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[13]_i_1 
       (.I0(\quot_reg[31] [12]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[14]_i_1 
       (.I0(\quot_reg[31] [13]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[15]_i_1 
       (.I0(\quot_reg[31] [14]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[16]_i_1 
       (.I0(\quot_reg[31] [15]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[17]_i_1 
       (.I0(\quot_reg[31] [16]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[18]_i_1 
       (.I0(\quot_reg[31] [17]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[19]_i_1 
       (.I0(\quot_reg[31] [18]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[1]_i_1 
       (.I0(\quot_reg[31] [0]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[20]_i_1 
       (.I0(\quot_reg[31] [19]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[21]_i_1 
       (.I0(\quot_reg[31] [20]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[22]_i_1 
       (.I0(\quot_reg[31] [21]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[23]_i_1 
       (.I0(\quot_reg[31] [22]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[24]_i_1 
       (.I0(\quot_reg[31] [23]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[25]_i_1 
       (.I0(\quot_reg[31] [24]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[26]_i_1 
       (.I0(\quot_reg[31] [25]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[27]_i_1 
       (.I0(\quot_reg[31] [26]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[28]_i_1 
       (.I0(\quot_reg[31] [27]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[29]_i_1 
       (.I0(\quot_reg[31] [28]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[2]_i_1 
       (.I0(\quot_reg[31] [1]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[30]_i_1 
       (.I0(\quot_reg[31] [29]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[31]_i_1 
       (.I0(\quot_reg[31] [30]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[31]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[32]_i_1 
       (.I0(\quot_reg[31] [31]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[33]_i_1 
       (.I0(dividend_tmp[32]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[34]_i_1 
       (.I0(dividend_tmp[33]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[35]_i_1 
       (.I0(dividend_tmp[34]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[36]_i_1 
       (.I0(dividend_tmp[35]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[37]_i_1 
       (.I0(dividend_tmp[36]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[38]_i_1 
       (.I0(dividend_tmp[37]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[39]_i_1 
       (.I0(dividend_tmp[38]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[3]_i_1 
       (.I0(\quot_reg[31] [2]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[40]_i_1 
       (.I0(dividend_tmp[39]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[41]_i_1 
       (.I0(dividend_tmp[40]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[42]_i_1 
       (.I0(dividend_tmp[41]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[43]_i_1 
       (.I0(dividend_tmp[42]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[44]_i_1 
       (.I0(dividend_tmp[43]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[45]_i_1 
       (.I0(dividend_tmp[44]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[46]_i_1 
       (.I0(dividend_tmp[45]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[47]_i_1 
       (.I0(dividend_tmp[46]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[48]_i_1 
       (.I0(dividend_tmp[47]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[48]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[49]_i_1 
       (.I0(dividend_tmp[48]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[49]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[4]_i_1 
       (.I0(\quot_reg[31] [3]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[50]_i_1 
       (.I0(dividend_tmp[49]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[50]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[51]_i_1 
       (.I0(dividend_tmp[50]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[51]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[52]_i_1 
       (.I0(dividend_tmp[51]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[52]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[53]_i_1 
       (.I0(dividend_tmp[52]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[53]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[54]_i_1 
       (.I0(dividend_tmp[53]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[54]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[55]_i_1 
       (.I0(dividend_tmp[54]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[55]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[56]_i_1 
       (.I0(dividend_tmp[55]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[56]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[57]_i_1 
       (.I0(dividend_tmp[56]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[57]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[58]_i_1 
       (.I0(dividend_tmp[57]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[58]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[59]_i_1 
       (.I0(dividend_tmp[58]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[59]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[5]_i_1 
       (.I0(\quot_reg[31] [4]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[60]_i_1 
       (.I0(dividend_tmp[59]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[60]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[61]_i_1 
       (.I0(dividend_tmp[60]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[61]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[62]_i_1 
       (.I0(dividend_tmp[61]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[62]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[63]_i_1 
       (.I0(dividend_tmp[62]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[63]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[64]_i_1 
       (.I0(dividend_tmp[63]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[64]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[65]_i_1 
       (.I0(dividend_tmp[64]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[65]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[66]_i_1 
       (.I0(dividend_tmp[65]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[66]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[67]_i_1 
       (.I0(dividend_tmp[66]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[67]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[68]_i_1 
       (.I0(dividend_tmp[67]),
        .I1(\r_stage_reg_n_0_[0] ),
        .O(\dividend_tmp[68]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[6]_i_1 
       (.I0(\quot_reg[31] [5]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[7]_i_1 
       (.I0(\quot_reg[31] [6]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[8]_i_1 
       (.I0(\quot_reg[31] [7]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \dividend_tmp[9]_i_1 
       (.I0(\quot_reg[31] [8]),
        .I1(\r_stage_reg[0]_rep_n_0 ),
        .O(\dividend_tmp[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[0] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(p_2_out),
        .Q(\quot_reg[31] [0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[10] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[10]_i_1_n_0 ),
        .Q(\quot_reg[31] [10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[11] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[11]_i_1_n_0 ),
        .Q(\quot_reg[31] [11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[12] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[12]_i_1_n_0 ),
        .Q(\quot_reg[31] [12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[13] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[13]_i_1_n_0 ),
        .Q(\quot_reg[31] [13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[14] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[14]_i_1_n_0 ),
        .Q(\quot_reg[31] [14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[15] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[15]_i_1_n_0 ),
        .Q(\quot_reg[31] [15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[16] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[16]_i_1_n_0 ),
        .Q(\quot_reg[31] [16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[17] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[17]_i_1_n_0 ),
        .Q(\quot_reg[31] [17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[18] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[18]_i_1_n_0 ),
        .Q(\quot_reg[31] [18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[19] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[19]_i_1_n_0 ),
        .Q(\quot_reg[31] [19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[1] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[1]_i_1_n_0 ),
        .Q(\quot_reg[31] [1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[20] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[20]_i_1_n_0 ),
        .Q(\quot_reg[31] [20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[21] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[21]_i_1_n_0 ),
        .Q(\quot_reg[31] [21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[22] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[22]_i_1_n_0 ),
        .Q(\quot_reg[31] [22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[23] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[23]_i_1_n_0 ),
        .Q(\quot_reg[31] [23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[24] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[24]_i_1_n_0 ),
        .Q(\quot_reg[31] [24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[25] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[25]_i_1_n_0 ),
        .Q(\quot_reg[31] [25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[26] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[26]_i_1_n_0 ),
        .Q(\quot_reg[31] [26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[27] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[27]_i_1_n_0 ),
        .Q(\quot_reg[31] [27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[28] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[28]_i_1_n_0 ),
        .Q(\quot_reg[31] [28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[29] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[29]_i_1_n_0 ),
        .Q(\quot_reg[31] [29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[2] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[2]_i_1_n_0 ),
        .Q(\quot_reg[31] [2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[30] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[30]_i_1_n_0 ),
        .Q(\quot_reg[31] [30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[31] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[31]_i_1_n_0 ),
        .Q(\quot_reg[31] [31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[32] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[32]_i_1_n_0 ),
        .Q(dividend_tmp[32]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[33] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[33]_i_1_n_0 ),
        .Q(dividend_tmp[33]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[34] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[34]_i_1_n_0 ),
        .Q(dividend_tmp[34]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[35] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[35]_i_1_n_0 ),
        .Q(dividend_tmp[35]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[36] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[36]_i_1_n_0 ),
        .Q(dividend_tmp[36]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[37] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[37]_i_1_n_0 ),
        .Q(dividend_tmp[37]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[38] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[38]_i_1_n_0 ),
        .Q(dividend_tmp[38]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[39] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[39]_i_1_n_0 ),
        .Q(dividend_tmp[39]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[3] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[3]_i_1_n_0 ),
        .Q(\quot_reg[31] [3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[40] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[40]_i_1_n_0 ),
        .Q(dividend_tmp[40]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[41] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[41]_i_1_n_0 ),
        .Q(dividend_tmp[41]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[42] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[42]_i_1_n_0 ),
        .Q(dividend_tmp[42]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[43] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[43]_i_1_n_0 ),
        .Q(dividend_tmp[43]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[44] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[44]_i_1_n_0 ),
        .Q(dividend_tmp[44]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[45] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[45]_i_1_n_0 ),
        .Q(dividend_tmp[45]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[46] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[46]_i_1_n_0 ),
        .Q(dividend_tmp[46]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[47] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[47]_i_1_n_0 ),
        .Q(dividend_tmp[47]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[48] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[48]_i_1_n_0 ),
        .Q(dividend_tmp[48]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[49] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[49]_i_1_n_0 ),
        .Q(dividend_tmp[49]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[4] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[4]_i_1_n_0 ),
        .Q(\quot_reg[31] [4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[50] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[50]_i_1_n_0 ),
        .Q(dividend_tmp[50]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[51] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[51]_i_1_n_0 ),
        .Q(dividend_tmp[51]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[52] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[52]_i_1_n_0 ),
        .Q(dividend_tmp[52]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[53] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[53]_i_1_n_0 ),
        .Q(dividend_tmp[53]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[54] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[54]_i_1_n_0 ),
        .Q(dividend_tmp[54]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[55] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[55]_i_1_n_0 ),
        .Q(dividend_tmp[55]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[56] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[56]_i_1_n_0 ),
        .Q(dividend_tmp[56]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[57] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[57]_i_1_n_0 ),
        .Q(dividend_tmp[57]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[58] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[58]_i_1_n_0 ),
        .Q(dividend_tmp[58]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[59] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[59]_i_1_n_0 ),
        .Q(dividend_tmp[59]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[5] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[5]_i_1_n_0 ),
        .Q(\quot_reg[31] [5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[60] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[60]_i_1_n_0 ),
        .Q(dividend_tmp[60]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[61] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[61]_i_1_n_0 ),
        .Q(dividend_tmp[61]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[62] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[62]_i_1_n_0 ),
        .Q(dividend_tmp[62]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[63] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[63]_i_1_n_0 ),
        .Q(dividend_tmp[63]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[64] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[64]_i_1_n_0 ),
        .Q(dividend_tmp[64]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[65] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[65]_i_1_n_0 ),
        .Q(dividend_tmp[65]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[66] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[66]_i_1_n_0 ),
        .Q(dividend_tmp[66]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[67] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[67]_i_1_n_0 ),
        .Q(dividend_tmp[67]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[68] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[68]_i_1_n_0 ),
        .Q(dividend_tmp[68]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[6] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[6]_i_1_n_0 ),
        .Q(\quot_reg[31] [6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[7] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[7]_i_1_n_0 ),
        .Q(\quot_reg[31] [7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[8] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[8]_i_1_n_0 ),
        .Q(\quot_reg[31] [8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \dividend_tmp_reg[9] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\dividend_tmp[9]_i_1_n_0 ),
        .Q(\quot_reg[31] [9]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[0] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [0]),
        .Q(divisor0[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[10] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [10]),
        .Q(divisor0[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[11] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [11]),
        .Q(divisor0[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[12] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [12]),
        .Q(divisor0[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[13] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [13]),
        .Q(divisor0[13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[14] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [14]),
        .Q(divisor0[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[15] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [15]),
        .Q(divisor0[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[16] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [16]),
        .Q(divisor0[16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[17] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [17]),
        .Q(divisor0[17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[18] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [18]),
        .Q(divisor0[18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[19] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [19]),
        .Q(divisor0[19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[1] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [1]),
        .Q(divisor0[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[20] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [20]),
        .Q(divisor0[20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[21] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [21]),
        .Q(divisor0[21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[22] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [22]),
        .Q(divisor0[22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[23] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [23]),
        .Q(divisor0[23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[24] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [24]),
        .Q(divisor0[24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[25] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [25]),
        .Q(divisor0[25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[26] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [26]),
        .Q(divisor0[26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[27] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [27]),
        .Q(divisor0[27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[28] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [28]),
        .Q(divisor0[28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[29] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [29]),
        .Q(divisor0[29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[2] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [2]),
        .Q(divisor0[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[30] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [30]),
        .Q(divisor0[30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[31] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [31]),
        .Q(divisor0[31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[32] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [32]),
        .Q(divisor0[32]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[33] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [33]),
        .Q(divisor0[33]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[34] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [34]),
        .Q(divisor0[34]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[35] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [35]),
        .Q(divisor0[35]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[36] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [36]),
        .Q(divisor0[36]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[3] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [3]),
        .Q(divisor0[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[4] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [4]),
        .Q(divisor0[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[5] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [5]),
        .Q(divisor0[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[6] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [6]),
        .Q(divisor0[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[7] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [7]),
        .Q(divisor0[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[8] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [8]),
        .Q(divisor0[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \divisor0_reg[9] 
       (.C(ap_clk),
        .CE(E),
        .D(\divisor0_reg[36]_0 [9]),
        .Q(divisor0[9]),
        .R(\<const0> ));
  (* ORIG_CELL_NAME = "r_stage_reg[0]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \r_stage_reg[0] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(E),
        .Q(\r_stage_reg_n_0_[0] ),
        .R(ap_rst));
  (* ORIG_CELL_NAME = "r_stage_reg[0]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \r_stage_reg[0]_rep 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(E),
        .Q(\r_stage_reg[0]_rep_n_0 ),
        .R(ap_rst));
  (* srl_bus_name = "U0/\RFNCO_Divider_HLSbkb_U1/RFNCO_Divider_HLSbkb_div_U/RFNCO_Divider_HLSbkb_div_u_0/r_stage_reg " *) 
  (* srl_name = "U0/\RFNCO_Divider_HLSbkb_U1/RFNCO_Divider_HLSbkb_div_U/RFNCO_Divider_HLSbkb_div_u_0/r_stage_reg[32]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_30 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \r_stage_reg[32]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_30 
       (.A({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .CE(\r_stage_reg[0]_0 ),
        .CLK(ap_clk),
        .D(\r_stage_reg[0]_rep_n_0 ),
        .Q31(\r_stage_reg[32]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_30_n_1 ));
  (* srl_bus_name = "U0/\RFNCO_Divider_HLSbkb_U1/RFNCO_Divider_HLSbkb_div_U/RFNCO_Divider_HLSbkb_div_u_0/r_stage_reg " *) 
  (* srl_name = "U0/\RFNCO_Divider_HLSbkb_U1/RFNCO_Divider_HLSbkb_div_U/RFNCO_Divider_HLSbkb_div_u_0/r_stage_reg[64]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_62 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \r_stage_reg[64]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_62 
       (.A({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .CE(\r_stage_reg[0]_0 ),
        .CLK(ap_clk),
        .D(\r_stage_reg[32]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_30_n_1 ),
        .Q31(\r_stage_reg[64]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_62_n_1 ));
  (* srl_bus_name = "U0/\RFNCO_Divider_HLSbkb_U1/RFNCO_Divider_HLSbkb_div_U/RFNCO_Divider_HLSbkb_div_u_0/r_stage_reg " *) 
  (* srl_name = "U0/\RFNCO_Divider_HLSbkb_U1/RFNCO_Divider_HLSbkb_div_U/RFNCO_Divider_HLSbkb_div_u_0/r_stage_reg[67]_srl3___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_65 " *) 
  SRLC32E #(
    .INIT(32'h00000000)) 
    \r_stage_reg[67]_srl3___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_65 
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> }),
        .CE(\r_stage_reg[0]_0 ),
        .CLK(ap_clk),
        .D(\r_stage_reg[64]_srl32___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_62_n_1 ),
        .Q(\r_stage_reg[67]_srl3___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_65_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \r_stage_reg[68]_RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_66 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\r_stage_reg[67]_srl3___RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_65_n_0 ),
        .Q(\r_stage_reg[68]_RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_66_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \r_stage_reg[69] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_gate_n_0),
        .Q(\quot_reg[0] ),
        .R(ap_rst));
  LUT2 #(
    .INIT(4'h8)) 
    r_stage_reg_gate
       (.I0(\r_stage_reg[68]_RFNCO_Divider_HLSbkb_U1_RFNCO_Divider_HLSbkb_div_U_RFNCO_Divider_HLSbkb_div_u_0_r_stage_reg_r_66_n_0 ),
        .I1(r_stage_reg_r_66_n_0),
        .O(r_stage_reg_gate_n_0));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\<const1> ),
        .Q(r_stage_reg_r_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_0
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_n_0),
        .Q(r_stage_reg_r_0_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_1
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_0_n_0),
        .Q(r_stage_reg_r_1_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_10
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_9_n_0),
        .Q(r_stage_reg_r_10_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_11
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_10_n_0),
        .Q(r_stage_reg_r_11_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_12
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_11_n_0),
        .Q(r_stage_reg_r_12_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_13
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_12_n_0),
        .Q(r_stage_reg_r_13_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_14
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_13_n_0),
        .Q(r_stage_reg_r_14_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_15
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_14_n_0),
        .Q(r_stage_reg_r_15_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_16
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_15_n_0),
        .Q(r_stage_reg_r_16_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_17
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_16_n_0),
        .Q(r_stage_reg_r_17_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_18
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_17_n_0),
        .Q(r_stage_reg_r_18_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_19
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_18_n_0),
        .Q(r_stage_reg_r_19_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_2
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_1_n_0),
        .Q(r_stage_reg_r_2_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_20
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_19_n_0),
        .Q(r_stage_reg_r_20_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_21
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_20_n_0),
        .Q(r_stage_reg_r_21_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_22
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_21_n_0),
        .Q(r_stage_reg_r_22_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_23
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_22_n_0),
        .Q(r_stage_reg_r_23_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_24
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_23_n_0),
        .Q(r_stage_reg_r_24_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_25
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_24_n_0),
        .Q(r_stage_reg_r_25_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_26
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_25_n_0),
        .Q(r_stage_reg_r_26_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_27
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_26_n_0),
        .Q(r_stage_reg_r_27_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_28
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_27_n_0),
        .Q(r_stage_reg_r_28_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_29
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_28_n_0),
        .Q(r_stage_reg_r_29_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_3
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_2_n_0),
        .Q(r_stage_reg_r_3_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_30
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_29_n_0),
        .Q(r_stage_reg_r_30_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_31
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_30_n_0),
        .Q(r_stage_reg_r_31_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_32
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_31_n_0),
        .Q(r_stage_reg_r_32_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_33
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_32_n_0),
        .Q(r_stage_reg_r_33_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_34
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_33_n_0),
        .Q(r_stage_reg_r_34_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_35
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_34_n_0),
        .Q(r_stage_reg_r_35_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_36
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_35_n_0),
        .Q(r_stage_reg_r_36_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_37
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_36_n_0),
        .Q(r_stage_reg_r_37_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_38
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_37_n_0),
        .Q(r_stage_reg_r_38_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_39
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_38_n_0),
        .Q(r_stage_reg_r_39_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_4
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_3_n_0),
        .Q(r_stage_reg_r_4_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_40
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_39_n_0),
        .Q(r_stage_reg_r_40_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_41
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_40_n_0),
        .Q(r_stage_reg_r_41_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_42
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_41_n_0),
        .Q(r_stage_reg_r_42_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_43
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_42_n_0),
        .Q(r_stage_reg_r_43_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_44
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_43_n_0),
        .Q(r_stage_reg_r_44_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_45
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_44_n_0),
        .Q(r_stage_reg_r_45_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_46
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_45_n_0),
        .Q(r_stage_reg_r_46_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_47
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_46_n_0),
        .Q(r_stage_reg_r_47_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_48
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_47_n_0),
        .Q(r_stage_reg_r_48_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_49
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_48_n_0),
        .Q(r_stage_reg_r_49_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_5
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_4_n_0),
        .Q(r_stage_reg_r_5_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_50
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_49_n_0),
        .Q(r_stage_reg_r_50_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_51
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_50_n_0),
        .Q(r_stage_reg_r_51_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_52
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_51_n_0),
        .Q(r_stage_reg_r_52_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_53
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_52_n_0),
        .Q(r_stage_reg_r_53_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_54
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_53_n_0),
        .Q(r_stage_reg_r_54_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_55
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_54_n_0),
        .Q(r_stage_reg_r_55_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_56
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_55_n_0),
        .Q(r_stage_reg_r_56_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_57
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_56_n_0),
        .Q(r_stage_reg_r_57_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_58
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_57_n_0),
        .Q(r_stage_reg_r_58_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_59
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_58_n_0),
        .Q(r_stage_reg_r_59_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_6
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_5_n_0),
        .Q(r_stage_reg_r_6_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_60
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_59_n_0),
        .Q(r_stage_reg_r_60_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_61
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_60_n_0),
        .Q(r_stage_reg_r_61_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_62
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_61_n_0),
        .Q(r_stage_reg_r_62_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_63
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_62_n_0),
        .Q(r_stage_reg_r_63_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_64
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_63_n_0),
        .Q(r_stage_reg_r_64_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_65
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_64_n_0),
        .Q(r_stage_reg_r_65_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_66
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_65_n_0),
        .Q(r_stage_reg_r_66_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_7
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_6_n_0),
        .Q(r_stage_reg_r_7_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_8
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_7_n_0),
        .Q(r_stage_reg_r_8_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    r_stage_reg_r_9
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(r_stage_reg_r_8_n_0),
        .Q(r_stage_reg_r_9_n_0),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'hEFE0)) 
    \remd_tmp[0]_i_1 
       (.I0(dividend_tmp[68]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry_n_7),
        .O(\remd_tmp[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[10]_i_1 
       (.I0(remd_tmp[9]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__1_n_5),
        .O(\remd_tmp[10]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[11]_i_1 
       (.I0(remd_tmp[10]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__1_n_4),
        .O(\remd_tmp[11]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[12]_i_1 
       (.I0(remd_tmp[11]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__2_n_7),
        .O(\remd_tmp[12]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[13]_i_1 
       (.I0(remd_tmp[12]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__2_n_6),
        .O(\remd_tmp[13]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[14]_i_1 
       (.I0(remd_tmp[13]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__2_n_5),
        .O(\remd_tmp[14]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[15]_i_1 
       (.I0(remd_tmp[14]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__2_n_4),
        .O(\remd_tmp[15]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[16]_i_1 
       (.I0(remd_tmp[15]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__3_n_7),
        .O(\remd_tmp[16]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[17]_i_1 
       (.I0(remd_tmp[16]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__3_n_6),
        .O(\remd_tmp[17]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[18]_i_1 
       (.I0(remd_tmp[17]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__3_n_5),
        .O(\remd_tmp[18]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[19]_i_1 
       (.I0(remd_tmp[18]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__3_n_4),
        .O(\remd_tmp[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[1]_i_1 
       (.I0(remd_tmp[0]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry_n_6),
        .O(\remd_tmp[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[20]_i_1 
       (.I0(remd_tmp[19]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__4_n_7),
        .O(\remd_tmp[20]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[21]_i_1 
       (.I0(remd_tmp[20]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__4_n_6),
        .O(\remd_tmp[21]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[22]_i_1 
       (.I0(remd_tmp[21]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__4_n_5),
        .O(\remd_tmp[22]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[23]_i_1 
       (.I0(remd_tmp[22]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__4_n_4),
        .O(\remd_tmp[23]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[24]_i_1 
       (.I0(remd_tmp[23]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__5_n_7),
        .O(\remd_tmp[24]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[25]_i_1 
       (.I0(remd_tmp[24]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__5_n_6),
        .O(\remd_tmp[25]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[26]_i_1 
       (.I0(remd_tmp[25]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__5_n_5),
        .O(\remd_tmp[26]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[27]_i_1 
       (.I0(remd_tmp[26]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__5_n_4),
        .O(\remd_tmp[27]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[28]_i_1 
       (.I0(remd_tmp[27]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__6_n_7),
        .O(\remd_tmp[28]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[29]_i_1 
       (.I0(remd_tmp[28]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__6_n_6),
        .O(\remd_tmp[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[2]_i_1 
       (.I0(remd_tmp[1]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry_n_5),
        .O(\remd_tmp[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[30]_i_1 
       (.I0(remd_tmp[29]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__6_n_5),
        .O(\remd_tmp[30]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[31]_i_1 
       (.I0(remd_tmp[30]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__6_n_4),
        .O(\remd_tmp[31]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[32]_i_1 
       (.I0(remd_tmp[31]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__7_n_7),
        .O(\remd_tmp[32]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[33]_i_1 
       (.I0(remd_tmp[32]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__7_n_6),
        .O(\remd_tmp[33]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[34]_i_1 
       (.I0(remd_tmp[33]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__7_n_5),
        .O(\remd_tmp[34]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[35]_i_1 
       (.I0(remd_tmp[34]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__7_n_4),
        .O(\remd_tmp[35]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[36]_i_1 
       (.I0(remd_tmp[35]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__8_n_7),
        .O(\remd_tmp[36]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[37]_i_1 
       (.I0(remd_tmp[36]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__8_n_6),
        .O(\remd_tmp[37]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[38]_i_1 
       (.I0(remd_tmp[37]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__8_n_5),
        .O(\remd_tmp[38]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[39]_i_1 
       (.I0(remd_tmp[38]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__8_n_4),
        .O(\remd_tmp[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[3]_i_1 
       (.I0(remd_tmp[2]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry_n_4),
        .O(\remd_tmp[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[40]_i_1 
       (.I0(remd_tmp[39]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__9_n_7),
        .O(\remd_tmp[40]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[41]_i_1 
       (.I0(remd_tmp[40]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__9_n_6),
        .O(\remd_tmp[41]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[42]_i_1 
       (.I0(remd_tmp[41]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__9_n_5),
        .O(\remd_tmp[42]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[43]_i_1 
       (.I0(remd_tmp[42]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__9_n_4),
        .O(\remd_tmp[43]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[44]_i_1 
       (.I0(remd_tmp[43]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__10_n_7),
        .O(\remd_tmp[44]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[45]_i_1 
       (.I0(remd_tmp[44]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__10_n_6),
        .O(\remd_tmp[45]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[46]_i_1 
       (.I0(remd_tmp[45]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__10_n_5),
        .O(\remd_tmp[46]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[47]_i_1 
       (.I0(remd_tmp[46]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__10_n_4),
        .O(\remd_tmp[47]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[48]_i_1 
       (.I0(remd_tmp[47]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__11_n_7),
        .O(\remd_tmp[48]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[49]_i_1 
       (.I0(remd_tmp[48]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__11_n_6),
        .O(\remd_tmp[49]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[4]_i_1 
       (.I0(remd_tmp[3]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__0_n_7),
        .O(\remd_tmp[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[50]_i_1 
       (.I0(remd_tmp[49]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__11_n_5),
        .O(\remd_tmp[50]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[51]_i_1 
       (.I0(remd_tmp[50]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__11_n_4),
        .O(\remd_tmp[51]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[52]_i_1 
       (.I0(remd_tmp[51]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__12_n_7),
        .O(\remd_tmp[52]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[53]_i_1 
       (.I0(remd_tmp[52]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__12_n_6),
        .O(\remd_tmp[53]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[54]_i_1 
       (.I0(remd_tmp[53]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__12_n_5),
        .O(\remd_tmp[54]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[55]_i_1 
       (.I0(remd_tmp[54]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__12_n_4),
        .O(\remd_tmp[55]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[56]_i_1 
       (.I0(remd_tmp[55]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__13_n_7),
        .O(\remd_tmp[56]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[57]_i_1 
       (.I0(remd_tmp[56]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__13_n_6),
        .O(\remd_tmp[57]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[58]_i_1 
       (.I0(remd_tmp[57]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__13_n_5),
        .O(\remd_tmp[58]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[59]_i_1 
       (.I0(remd_tmp[58]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__13_n_4),
        .O(\remd_tmp[59]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[5]_i_1 
       (.I0(remd_tmp[4]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__0_n_6),
        .O(\remd_tmp[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[60]_i_1 
       (.I0(remd_tmp[59]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__14_n_7),
        .O(\remd_tmp[60]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[61]_i_1 
       (.I0(remd_tmp[60]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__14_n_6),
        .O(\remd_tmp[61]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[62]_i_1 
       (.I0(remd_tmp[61]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__14_n_5),
        .O(\remd_tmp[62]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[63]_i_1 
       (.I0(remd_tmp[62]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__14_n_4),
        .O(\remd_tmp[63]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[64]_i_1 
       (.I0(remd_tmp[63]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__15_n_7),
        .O(\remd_tmp[64]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[65]_i_1 
       (.I0(remd_tmp[64]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__15_n_6),
        .O(\remd_tmp[65]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[66]_i_1 
       (.I0(remd_tmp[65]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__15_n_5),
        .O(\remd_tmp[66]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[67]_i_1 
       (.I0(remd_tmp[66]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__15_n_4),
        .O(\remd_tmp[67]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[6]_i_1 
       (.I0(remd_tmp[5]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__0_n_5),
        .O(\remd_tmp[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[7]_i_1 
       (.I0(remd_tmp[6]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__0_n_4),
        .O(\remd_tmp[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[8]_i_1 
       (.I0(remd_tmp[7]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__1_n_7),
        .O(\remd_tmp[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \remd_tmp[9]_i_1 
       (.I0(remd_tmp[8]),
        .I1(\r_stage_reg_n_0_[0] ),
        .I2(p_0_in),
        .I3(cal_tmp_carry__1_n_6),
        .O(\remd_tmp[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[0] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[0]_i_1_n_0 ),
        .Q(remd_tmp[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[10] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[10]_i_1_n_0 ),
        .Q(remd_tmp[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[11] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[11]_i_1_n_0 ),
        .Q(remd_tmp[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[12] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[12]_i_1_n_0 ),
        .Q(remd_tmp[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[13] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[13]_i_1_n_0 ),
        .Q(remd_tmp[13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[14] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[14]_i_1_n_0 ),
        .Q(remd_tmp[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[15] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[15]_i_1_n_0 ),
        .Q(remd_tmp[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[16] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[16]_i_1_n_0 ),
        .Q(remd_tmp[16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[17] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[17]_i_1_n_0 ),
        .Q(remd_tmp[17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[18] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[18]_i_1_n_0 ),
        .Q(remd_tmp[18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[19] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[19]_i_1_n_0 ),
        .Q(remd_tmp[19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[1] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[1]_i_1_n_0 ),
        .Q(remd_tmp[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[20] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[20]_i_1_n_0 ),
        .Q(remd_tmp[20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[21] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[21]_i_1_n_0 ),
        .Q(remd_tmp[21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[22] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[22]_i_1_n_0 ),
        .Q(remd_tmp[22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[23] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[23]_i_1_n_0 ),
        .Q(remd_tmp[23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[24] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[24]_i_1_n_0 ),
        .Q(remd_tmp[24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[25] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[25]_i_1_n_0 ),
        .Q(remd_tmp[25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[26] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[26]_i_1_n_0 ),
        .Q(remd_tmp[26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[27] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[27]_i_1_n_0 ),
        .Q(remd_tmp[27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[28] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[28]_i_1_n_0 ),
        .Q(remd_tmp[28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[29] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[29]_i_1_n_0 ),
        .Q(remd_tmp[29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[2] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[2]_i_1_n_0 ),
        .Q(remd_tmp[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[30] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[30]_i_1_n_0 ),
        .Q(remd_tmp[30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[31] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[31]_i_1_n_0 ),
        .Q(remd_tmp[31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[32] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[32]_i_1_n_0 ),
        .Q(remd_tmp[32]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[33] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[33]_i_1_n_0 ),
        .Q(remd_tmp[33]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[34] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[34]_i_1_n_0 ),
        .Q(remd_tmp[34]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[35] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[35]_i_1_n_0 ),
        .Q(remd_tmp[35]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[36] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[36]_i_1_n_0 ),
        .Q(remd_tmp[36]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[37] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[37]_i_1_n_0 ),
        .Q(remd_tmp[37]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[38] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[38]_i_1_n_0 ),
        .Q(remd_tmp[38]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[39] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[39]_i_1_n_0 ),
        .Q(remd_tmp[39]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[3] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[3]_i_1_n_0 ),
        .Q(remd_tmp[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[40] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[40]_i_1_n_0 ),
        .Q(remd_tmp[40]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[41] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[41]_i_1_n_0 ),
        .Q(remd_tmp[41]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[42] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[42]_i_1_n_0 ),
        .Q(remd_tmp[42]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[43] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[43]_i_1_n_0 ),
        .Q(remd_tmp[43]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[44] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[44]_i_1_n_0 ),
        .Q(remd_tmp[44]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[45] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[45]_i_1_n_0 ),
        .Q(remd_tmp[45]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[46] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[46]_i_1_n_0 ),
        .Q(remd_tmp[46]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[47] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[47]_i_1_n_0 ),
        .Q(remd_tmp[47]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[48] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[48]_i_1_n_0 ),
        .Q(remd_tmp[48]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[49] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[49]_i_1_n_0 ),
        .Q(remd_tmp[49]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[4] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[4]_i_1_n_0 ),
        .Q(remd_tmp[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[50] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[50]_i_1_n_0 ),
        .Q(remd_tmp[50]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[51] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[51]_i_1_n_0 ),
        .Q(remd_tmp[51]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[52] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[52]_i_1_n_0 ),
        .Q(remd_tmp[52]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[53] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[53]_i_1_n_0 ),
        .Q(remd_tmp[53]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[54] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[54]_i_1_n_0 ),
        .Q(remd_tmp[54]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[55] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[55]_i_1_n_0 ),
        .Q(remd_tmp[55]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[56] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[56]_i_1_n_0 ),
        .Q(remd_tmp[56]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[57] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[57]_i_1_n_0 ),
        .Q(remd_tmp[57]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[58] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[58]_i_1_n_0 ),
        .Q(remd_tmp[58]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[59] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[59]_i_1_n_0 ),
        .Q(remd_tmp[59]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[5] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[5]_i_1_n_0 ),
        .Q(remd_tmp[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[60] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[60]_i_1_n_0 ),
        .Q(remd_tmp[60]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[61] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[61]_i_1_n_0 ),
        .Q(remd_tmp[61]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[62] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[62]_i_1_n_0 ),
        .Q(remd_tmp[62]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[63] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[63]_i_1_n_0 ),
        .Q(remd_tmp[63]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[64] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[64]_i_1_n_0 ),
        .Q(remd_tmp[64]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[65] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[65]_i_1_n_0 ),
        .Q(remd_tmp[65]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[66] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[66]_i_1_n_0 ),
        .Q(remd_tmp[66]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[67] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[67]_i_1_n_0 ),
        .Q(remd_tmp[67]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[6] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[6]_i_1_n_0 ),
        .Q(remd_tmp[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[7] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[7]_i_1_n_0 ),
        .Q(remd_tmp[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[8] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[8]_i_1_n_0 ),
        .Q(remd_tmp[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \remd_tmp_reg[9] 
       (.C(ap_clk),
        .CE(\r_stage_reg[0]_0 ),
        .D(\remd_tmp[9]_i_1_n_0 ),
        .Q(remd_tmp[9]),
        .R(\<const0> ));
  LUT5 #(
    .INIT(32'h00000001)) 
    start0_i_1
       (.I0(Q[1]),
        .I1(Q[2]),
        .I2(Q[3]),
        .I3(Q[0]),
        .I4(Q[4]),
        .O(\r_stage_reg[0]_0 ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_RFNCO_HLS_0,RFNCO_HLS,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_RFNCO_HLS_0,RFNCO_HLS,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=RFNCO_HLS,x_ipVersion=1.0,x_ipCoreRevision=2113025637,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "RFNCO_HLS,Vivado 2018.2" *) (* ip_definition_source = "HLS" *) 
module RFNCO_cmp_RFNCO_HLS_0
   (inputs_H_V_ap_vld,
    inputs_ftw_H1_V_ap_vld,
    inputs_ftw_H1_prog_V_ap_vld,
    inputs_ftw_LO_0_V_ap_vld,
    inputs_ftw_LO_1_V_ap_vld,
    inputs_ftw_H1_on_V_ap_vld,
    inputs_dftw_H1_slip_V_ap_vld,
    inputs_coef_V_ap_vld,
    inputs_offset_V_ap_vld,
    inputs_offset_FSK_V_ap_vld,
    inputs_offset_AM_on_V_ap_vld,
    inputs_offset_AM_off_V_ap_vld,
    inputs_phase_H1_comp_V_ap_vld,
    inputs_rate_V_ap_vld,
    inputs_valid_ap_vld,
    inputs_enable_FSK_ap_vld,
    inputs_reset_FSK_ap_vld,
    inputs_slip_sign_ap_vld,
    inputs_enable_slip_ap_vld,
    inputs_reset_slip_ap_vld,
    inputs_reset_NCO_ap_vld,
    inputs_force_AM_ap_vld,
    outputs_phase_IF_0_V_ap_vld,
    outputs_phase_IF_1_V_ap_vld,
    outputs_phase_H1_V_ap_vld,
    outputs_phase_H1_offset_V_ap_vld,
    outputs_phase_H1_prog_offset_V_ap_vld,
    outputs_phase_H1_main_V_ap_vld,
    outputs_phase_H1_slip_V_ap_vld,
    outputs_ftw_H1_muxed_V_ap_vld,
    outputs_coef_muxed_V_ap_vld,
    outputs_AM_ap_vld,
    outputs_frev_ap_vld,
    outputs_frev_main_ap_vld,
    outputs_AM_auto_on_ap_vld,
    outputs_valid_ap_vld,
    ap_clk,
    ap_rst,
    inputs_H_V,
    inputs_ftw_H1_V,
    inputs_ftw_H1_prog_V,
    inputs_ftw_LO_0_V,
    inputs_ftw_LO_1_V,
    inputs_ftw_H1_on_V,
    inputs_dftw_H1_slip_V,
    inputs_coef_V,
    inputs_offset_V,
    inputs_offset_FSK_V,
    inputs_offset_AM_on_V,
    inputs_offset_AM_off_V,
    inputs_phase_H1_comp_V,
    inputs_rate_V,
    inputs_valid,
    inputs_enable_FSK,
    inputs_reset_FSK,
    inputs_slip_sign,
    inputs_enable_slip,
    inputs_reset_slip,
    inputs_reset_NCO,
    inputs_force_AM,
    outputs_phase_IF_0_V,
    outputs_phase_IF_1_V,
    outputs_phase_H1_V,
    outputs_phase_H1_offset_V,
    outputs_phase_H1_prog_offset_V,
    outputs_phase_H1_main_V,
    outputs_phase_H1_slip_V,
    outputs_ftw_H1_muxed_V,
    outputs_coef_muxed_V,
    outputs_AM,
    outputs_frev,
    outputs_frev_main,
    outputs_AM_auto_on,
    outputs_valid);
  input inputs_H_V_ap_vld;
  input inputs_ftw_H1_V_ap_vld;
  input inputs_ftw_H1_prog_V_ap_vld;
  input inputs_ftw_LO_0_V_ap_vld;
  input inputs_ftw_LO_1_V_ap_vld;
  input inputs_ftw_H1_on_V_ap_vld;
  input inputs_dftw_H1_slip_V_ap_vld;
  input inputs_coef_V_ap_vld;
  input inputs_offset_V_ap_vld;
  input inputs_offset_FSK_V_ap_vld;
  input inputs_offset_AM_on_V_ap_vld;
  input inputs_offset_AM_off_V_ap_vld;
  input inputs_phase_H1_comp_V_ap_vld;
  input inputs_rate_V_ap_vld;
  input inputs_valid_ap_vld;
  input inputs_enable_FSK_ap_vld;
  input inputs_reset_FSK_ap_vld;
  input inputs_slip_sign_ap_vld;
  input inputs_enable_slip_ap_vld;
  input inputs_reset_slip_ap_vld;
  input inputs_reset_NCO_ap_vld;
  input inputs_force_AM_ap_vld;
  output outputs_phase_IF_0_V_ap_vld;
  output outputs_phase_IF_1_V_ap_vld;
  output outputs_phase_H1_V_ap_vld;
  output outputs_phase_H1_offset_V_ap_vld;
  output outputs_phase_H1_prog_offset_V_ap_vld;
  output outputs_phase_H1_main_V_ap_vld;
  output outputs_phase_H1_slip_V_ap_vld;
  output outputs_ftw_H1_muxed_V_ap_vld;
  output outputs_coef_muxed_V_ap_vld;
  output outputs_AM_ap_vld;
  output outputs_frev_ap_vld;
  output outputs_frev_main_ap_vld;
  output outputs_AM_auto_on_ap_vld;
  output outputs_valid_ap_vld;
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_clk, ASSOCIATED_RESET ap_rst, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {CLK {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input ap_clk;
  (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME ap_rst, POLARITY ACTIVE_HIGH, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {RST {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input ap_rst;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_H_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_H_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [15:0]inputs_H_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_H1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_H1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_H1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_H1_prog_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_H1_prog_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_H1_prog_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_LO_0_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_LO_0_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_LO_0_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_LO_1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_LO_1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_LO_1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_ftw_H1_on_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_ftw_H1_on_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_ftw_H1_on_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_dftw_H1_slip_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_dftw_H1_slip_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}" *) input [31:0]inputs_dftw_H1_slip_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_coef_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_coef_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value -4294967258} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [31:0]inputs_coef_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_offset_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_offset_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_offset_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_offset_FSK_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_offset_FSK_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_offset_FSK_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_offset_AM_on_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_offset_AM_on_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_offset_AM_on_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_offset_AM_off_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_offset_AM_off_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}" *) input [47:0]inputs_offset_AM_off_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_phase_H1_comp_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_phase_H1_comp_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [47:0]inputs_phase_H1_comp_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_rate_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_rate_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 3} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) input [2:0]inputs_rate_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_valid DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_valid, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_valid;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_enable_FSK DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_enable_FSK, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_enable_FSK;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_reset_FSK DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_reset_FSK, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_reset_FSK;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_slip_sign DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_slip_sign, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_slip_sign;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_enable_slip DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_enable_slip, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_enable_slip;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_reset_slip DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_reset_slip, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_reset_slip;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_reset_NCO DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_reset_NCO, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_reset_NCO;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 inputs_force_AM DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME inputs_force_AM, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) input [0:0]inputs_force_AM;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_IF_0_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_IF_0_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_IF_0_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_IF_1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_IF_1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_IF_1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_H1_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_H1_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_H1_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_H1_offset_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_H1_offset_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_H1_offset_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_H1_prog_offset_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_H1_prog_offset_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_H1_prog_offset_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_H1_main_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_H1_main_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_H1_main_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_phase_H1_slip_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_phase_H1_slip_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_phase_H1_slip_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_ftw_H1_muxed_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_ftw_H1_muxed_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 48} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [47:0]outputs_ftw_H1_muxed_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_coef_muxed_V DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_coef_muxed_V, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value -4294967258} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}}" *) output [31:0]outputs_coef_muxed_V;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_AM DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_AM, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) output outputs_AM;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_frev DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_frev, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) output outputs_frev;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_frev_main DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_frev_main, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) output outputs_frev_main;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_AM_auto_on DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_AM_auto_on, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) output outputs_AM_auto_on;
  (* X_INTERFACE_INFO = "xilinx.com:signal:data:1.0 outputs_valid DATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME outputs_valid, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}}}" *) output outputs_valid;

  wire ap_clk;
  wire ap_rst;
  wire [15:0]inputs_H_V;
  wire inputs_H_V_ap_vld;
  wire [31:0]inputs_coef_V;
  wire inputs_coef_V_ap_vld;
  wire [31:0]inputs_dftw_H1_slip_V;
  wire inputs_dftw_H1_slip_V_ap_vld;
  wire [0:0]inputs_enable_FSK;
  wire inputs_enable_FSK_ap_vld;
  wire [0:0]inputs_enable_slip;
  wire inputs_enable_slip_ap_vld;
  wire [0:0]inputs_force_AM;
  wire inputs_force_AM_ap_vld;
  wire [47:0]inputs_ftw_H1_V;
  wire inputs_ftw_H1_V_ap_vld;
  wire [47:0]inputs_ftw_H1_on_V;
  wire inputs_ftw_H1_on_V_ap_vld;
  wire [47:0]inputs_ftw_H1_prog_V;
  wire inputs_ftw_H1_prog_V_ap_vld;
  wire [47:0]inputs_ftw_LO_0_V;
  wire inputs_ftw_LO_0_V_ap_vld;
  wire [47:0]inputs_ftw_LO_1_V;
  wire inputs_ftw_LO_1_V_ap_vld;
  wire [47:0]inputs_offset_AM_off_V;
  wire inputs_offset_AM_off_V_ap_vld;
  wire [47:0]inputs_offset_AM_on_V;
  wire inputs_offset_AM_on_V_ap_vld;
  wire [47:0]inputs_offset_FSK_V;
  wire inputs_offset_FSK_V_ap_vld;
  wire [47:0]inputs_offset_V;
  wire inputs_offset_V_ap_vld;
  wire [47:0]inputs_phase_H1_comp_V;
  wire inputs_phase_H1_comp_V_ap_vld;
  wire [2:0]inputs_rate_V;
  wire inputs_rate_V_ap_vld;
  wire [0:0]inputs_reset_FSK;
  wire inputs_reset_FSK_ap_vld;
  wire [0:0]inputs_reset_NCO;
  wire inputs_reset_NCO_ap_vld;
  wire [0:0]inputs_reset_slip;
  wire inputs_reset_slip_ap_vld;
  wire [0:0]inputs_slip_sign;
  wire inputs_slip_sign_ap_vld;
  wire [0:0]inputs_valid;
  wire inputs_valid_ap_vld;
  wire outputs_AM;
  wire outputs_AM_ap_vld;
  wire outputs_AM_auto_on;
  wire outputs_AM_auto_on_ap_vld;
  wire [31:0]outputs_coef_muxed_V;
  wire outputs_coef_muxed_V_ap_vld;
  wire outputs_frev;
  wire outputs_frev_ap_vld;
  wire outputs_frev_main;
  wire outputs_frev_main_ap_vld;
  wire [47:0]outputs_ftw_H1_muxed_V;
  wire outputs_ftw_H1_muxed_V_ap_vld;
  wire [47:0]outputs_phase_H1_V;
  wire outputs_phase_H1_V_ap_vld;
  wire [47:0]outputs_phase_H1_main_V;
  wire outputs_phase_H1_main_V_ap_vld;
  wire [47:0]outputs_phase_H1_offset_V;
  wire outputs_phase_H1_offset_V_ap_vld;
  wire [47:0]outputs_phase_H1_prog_offset_V;
  wire outputs_phase_H1_prog_offset_V_ap_vld;
  wire [47:0]outputs_phase_H1_slip_V;
  wire outputs_phase_H1_slip_V_ap_vld;
  wire [47:0]outputs_phase_IF_0_V;
  wire outputs_phase_IF_0_V_ap_vld;
  wire [47:0]outputs_phase_IF_1_V;
  wire outputs_phase_IF_1_V_ap_vld;
  wire outputs_valid;
  wire outputs_valid_ap_vld;

  (* core_generation_info = "RFNCO_HLS,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg676-2,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=6.908000,HLS_SYN_LAT=8,HLS_SYN_TPT=1,HLS_SYN_MEM=18,HLS_SYN_DSP=18,HLS_SYN_FF=4447,HLS_SYN_LUT=3229,HLS_VERSION=2018_2}" *) 
  RFNCO_cmp_RFNCO_HLS_0_RFNCO_HLS U0
       (.ap_clk(ap_clk),
        .ap_rst(ap_rst),
        .inputs_H_V(inputs_H_V),
        .inputs_H_V_ap_vld(inputs_H_V_ap_vld),
        .inputs_coef_V(inputs_coef_V),
        .inputs_coef_V_ap_vld(inputs_coef_V_ap_vld),
        .inputs_dftw_H1_slip_V(inputs_dftw_H1_slip_V),
        .inputs_dftw_H1_slip_V_ap_vld(inputs_dftw_H1_slip_V_ap_vld),
        .inputs_enable_FSK(inputs_enable_FSK),
        .inputs_enable_FSK_ap_vld(inputs_enable_FSK_ap_vld),
        .inputs_enable_slip(inputs_enable_slip),
        .inputs_enable_slip_ap_vld(inputs_enable_slip_ap_vld),
        .inputs_force_AM(inputs_force_AM),
        .inputs_force_AM_ap_vld(inputs_force_AM_ap_vld),
        .inputs_ftw_H1_V(inputs_ftw_H1_V),
        .inputs_ftw_H1_V_ap_vld(inputs_ftw_H1_V_ap_vld),
        .inputs_ftw_H1_on_V(inputs_ftw_H1_on_V),
        .inputs_ftw_H1_on_V_ap_vld(inputs_ftw_H1_on_V_ap_vld),
        .inputs_ftw_H1_prog_V(inputs_ftw_H1_prog_V),
        .inputs_ftw_H1_prog_V_ap_vld(inputs_ftw_H1_prog_V_ap_vld),
        .inputs_ftw_LO_0_V(inputs_ftw_LO_0_V),
        .inputs_ftw_LO_0_V_ap_vld(inputs_ftw_LO_0_V_ap_vld),
        .inputs_ftw_LO_1_V(inputs_ftw_LO_1_V),
        .inputs_ftw_LO_1_V_ap_vld(inputs_ftw_LO_1_V_ap_vld),
        .inputs_offset_AM_off_V(inputs_offset_AM_off_V),
        .inputs_offset_AM_off_V_ap_vld(inputs_offset_AM_off_V_ap_vld),
        .inputs_offset_AM_on_V(inputs_offset_AM_on_V),
        .inputs_offset_AM_on_V_ap_vld(inputs_offset_AM_on_V_ap_vld),
        .inputs_offset_FSK_V(inputs_offset_FSK_V),
        .inputs_offset_FSK_V_ap_vld(inputs_offset_FSK_V_ap_vld),
        .inputs_offset_V(inputs_offset_V),
        .inputs_offset_V_ap_vld(inputs_offset_V_ap_vld),
        .inputs_phase_H1_comp_V(inputs_phase_H1_comp_V),
        .inputs_phase_H1_comp_V_ap_vld(inputs_phase_H1_comp_V_ap_vld),
        .inputs_rate_V(inputs_rate_V),
        .inputs_rate_V_ap_vld(inputs_rate_V_ap_vld),
        .inputs_reset_FSK(inputs_reset_FSK),
        .inputs_reset_FSK_ap_vld(inputs_reset_FSK_ap_vld),
        .inputs_reset_NCO(inputs_reset_NCO),
        .inputs_reset_NCO_ap_vld(inputs_reset_NCO_ap_vld),
        .inputs_reset_slip(inputs_reset_slip),
        .inputs_reset_slip_ap_vld(inputs_reset_slip_ap_vld),
        .inputs_slip_sign(inputs_slip_sign),
        .inputs_slip_sign_ap_vld(inputs_slip_sign_ap_vld),
        .inputs_valid(inputs_valid),
        .inputs_valid_ap_vld(inputs_valid_ap_vld),
        .outputs_AM(outputs_AM),
        .outputs_AM_ap_vld(outputs_AM_ap_vld),
        .outputs_AM_auto_on(outputs_AM_auto_on),
        .outputs_AM_auto_on_ap_vld(outputs_AM_auto_on_ap_vld),
        .outputs_coef_muxed_V(outputs_coef_muxed_V),
        .outputs_coef_muxed_V_ap_vld(outputs_coef_muxed_V_ap_vld),
        .outputs_frev(outputs_frev),
        .outputs_frev_ap_vld(outputs_frev_ap_vld),
        .outputs_frev_main(outputs_frev_main),
        .outputs_frev_main_ap_vld(outputs_frev_main_ap_vld),
        .outputs_ftw_H1_muxed_V(outputs_ftw_H1_muxed_V),
        .outputs_ftw_H1_muxed_V_ap_vld(outputs_ftw_H1_muxed_V_ap_vld),
        .outputs_phase_H1_V(outputs_phase_H1_V),
        .outputs_phase_H1_V_ap_vld(outputs_phase_H1_V_ap_vld),
        .outputs_phase_H1_main_V(outputs_phase_H1_main_V),
        .outputs_phase_H1_main_V_ap_vld(outputs_phase_H1_main_V_ap_vld),
        .outputs_phase_H1_offset_V(outputs_phase_H1_offset_V),
        .outputs_phase_H1_offset_V_ap_vld(outputs_phase_H1_offset_V_ap_vld),
        .outputs_phase_H1_prog_offset_V(outputs_phase_H1_prog_offset_V),
        .outputs_phase_H1_prog_offset_V_ap_vld(outputs_phase_H1_prog_offset_V_ap_vld),
        .outputs_phase_H1_slip_V(outputs_phase_H1_slip_V),
        .outputs_phase_H1_slip_V_ap_vld(outputs_phase_H1_slip_V_ap_vld),
        .outputs_phase_IF_0_V(outputs_phase_IF_0_V),
        .outputs_phase_IF_0_V_ap_vld(outputs_phase_IF_0_V_ap_vld),
        .outputs_phase_IF_1_V(outputs_phase_IF_1_V),
        .outputs_phase_IF_1_V_ap_vld(outputs_phase_IF_1_V_ap_vld),
        .outputs_valid(outputs_valid),
        .outputs_valid_ap_vld(outputs_valid_ap_vld));
endmodule

(* CORE_GENERATION_INFO = "RFNCO_HLS,hls_ip_2018_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg676-2,HLS_INPUT_CLOCK=8.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=6.908000,HLS_SYN_LAT=8,HLS_SYN_TPT=1,HLS_SYN_MEM=18,HLS_SYN_DSP=18,HLS_SYN_FF=4447,HLS_SYN_LUT=3229,HLS_VERSION=2018_2}" *) (* ORIG_REF_NAME = "RFNCO_HLS" *) 
module RFNCO_cmp_RFNCO_HLS_0_RFNCO_HLS
   (ap_clk,
    ap_rst,
    inputs_H_V,
    inputs_H_V_ap_vld,
    inputs_ftw_H1_V,
    inputs_ftw_H1_V_ap_vld,
    inputs_ftw_H1_prog_V,
    inputs_ftw_H1_prog_V_ap_vld,
    inputs_ftw_LO_0_V,
    inputs_ftw_LO_0_V_ap_vld,
    inputs_ftw_LO_1_V,
    inputs_ftw_LO_1_V_ap_vld,
    inputs_ftw_H1_on_V,
    inputs_ftw_H1_on_V_ap_vld,
    inputs_dftw_H1_slip_V,
    inputs_dftw_H1_slip_V_ap_vld,
    inputs_coef_V,
    inputs_coef_V_ap_vld,
    inputs_offset_V,
    inputs_offset_V_ap_vld,
    inputs_offset_FSK_V,
    inputs_offset_FSK_V_ap_vld,
    inputs_offset_AM_on_V,
    inputs_offset_AM_on_V_ap_vld,
    inputs_offset_AM_off_V,
    inputs_offset_AM_off_V_ap_vld,
    inputs_phase_H1_comp_V,
    inputs_phase_H1_comp_V_ap_vld,
    inputs_rate_V,
    inputs_rate_V_ap_vld,
    inputs_valid,
    inputs_valid_ap_vld,
    inputs_enable_FSK,
    inputs_enable_FSK_ap_vld,
    inputs_reset_FSK,
    inputs_reset_FSK_ap_vld,
    inputs_slip_sign,
    inputs_slip_sign_ap_vld,
    inputs_enable_slip,
    inputs_enable_slip_ap_vld,
    inputs_reset_slip,
    inputs_reset_slip_ap_vld,
    inputs_reset_NCO,
    inputs_reset_NCO_ap_vld,
    inputs_force_AM,
    inputs_force_AM_ap_vld,
    outputs_phase_IF_0_V,
    outputs_phase_IF_0_V_ap_vld,
    outputs_phase_IF_1_V,
    outputs_phase_IF_1_V_ap_vld,
    outputs_phase_H1_V,
    outputs_phase_H1_V_ap_vld,
    outputs_phase_H1_offset_V,
    outputs_phase_H1_offset_V_ap_vld,
    outputs_phase_H1_prog_offset_V,
    outputs_phase_H1_prog_offset_V_ap_vld,
    outputs_phase_H1_main_V,
    outputs_phase_H1_main_V_ap_vld,
    outputs_phase_H1_slip_V,
    outputs_phase_H1_slip_V_ap_vld,
    outputs_ftw_H1_muxed_V,
    outputs_ftw_H1_muxed_V_ap_vld,
    outputs_coef_muxed_V,
    outputs_coef_muxed_V_ap_vld,
    outputs_AM,
    outputs_AM_ap_vld,
    outputs_frev,
    outputs_frev_ap_vld,
    outputs_frev_main,
    outputs_frev_main_ap_vld,
    outputs_AM_auto_on,
    outputs_AM_auto_on_ap_vld,
    outputs_valid,
    outputs_valid_ap_vld);
  input ap_clk;
  input ap_rst;
  input [15:0]inputs_H_V;
  input inputs_H_V_ap_vld;
  input [47:0]inputs_ftw_H1_V;
  input inputs_ftw_H1_V_ap_vld;
  input [47:0]inputs_ftw_H1_prog_V;
  input inputs_ftw_H1_prog_V_ap_vld;
  input [47:0]inputs_ftw_LO_0_V;
  input inputs_ftw_LO_0_V_ap_vld;
  input [47:0]inputs_ftw_LO_1_V;
  input inputs_ftw_LO_1_V_ap_vld;
  input [47:0]inputs_ftw_H1_on_V;
  input inputs_ftw_H1_on_V_ap_vld;
  input [31:0]inputs_dftw_H1_slip_V;
  input inputs_dftw_H1_slip_V_ap_vld;
  input [31:0]inputs_coef_V;
  input inputs_coef_V_ap_vld;
  input [47:0]inputs_offset_V;
  input inputs_offset_V_ap_vld;
  input [47:0]inputs_offset_FSK_V;
  input inputs_offset_FSK_V_ap_vld;
  input [47:0]inputs_offset_AM_on_V;
  input inputs_offset_AM_on_V_ap_vld;
  input [47:0]inputs_offset_AM_off_V;
  input inputs_offset_AM_off_V_ap_vld;
  input [47:0]inputs_phase_H1_comp_V;
  input inputs_phase_H1_comp_V_ap_vld;
  input [2:0]inputs_rate_V;
  input inputs_rate_V_ap_vld;
  input [0:0]inputs_valid;
  input inputs_valid_ap_vld;
  input [0:0]inputs_enable_FSK;
  input inputs_enable_FSK_ap_vld;
  input [0:0]inputs_reset_FSK;
  input inputs_reset_FSK_ap_vld;
  input [0:0]inputs_slip_sign;
  input inputs_slip_sign_ap_vld;
  input [0:0]inputs_enable_slip;
  input inputs_enable_slip_ap_vld;
  input [0:0]inputs_reset_slip;
  input inputs_reset_slip_ap_vld;
  input [0:0]inputs_reset_NCO;
  input inputs_reset_NCO_ap_vld;
  input [0:0]inputs_force_AM;
  input inputs_force_AM_ap_vld;
  output [47:0]outputs_phase_IF_0_V;
  output outputs_phase_IF_0_V_ap_vld;
  output [47:0]outputs_phase_IF_1_V;
  output outputs_phase_IF_1_V_ap_vld;
  output [47:0]outputs_phase_H1_V;
  output outputs_phase_H1_V_ap_vld;
  output [47:0]outputs_phase_H1_offset_V;
  output outputs_phase_H1_offset_V_ap_vld;
  output [47:0]outputs_phase_H1_prog_offset_V;
  output outputs_phase_H1_prog_offset_V_ap_vld;
  output [47:0]outputs_phase_H1_main_V;
  output outputs_phase_H1_main_V_ap_vld;
  output [47:0]outputs_phase_H1_slip_V;
  output outputs_phase_H1_slip_V_ap_vld;
  output [47:0]outputs_ftw_H1_muxed_V;
  output outputs_ftw_H1_muxed_V_ap_vld;
  output [31:0]outputs_coef_muxed_V;
  output outputs_coef_muxed_V_ap_vld;
  output outputs_AM;
  output outputs_AM_ap_vld;
  output outputs_frev;
  output outputs_frev_ap_vld;
  output outputs_frev_main;
  output outputs_frev_main_ap_vld;
  output outputs_AM_auto_on;
  output outputs_AM_auto_on_ap_vld;
  output outputs_valid;
  output outputs_valid_ap_vld;

  wire \<const0> ;
  wire \<const1> ;
  wire \AM_auto_on_3_reg_1571_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \AM_auto_on_3_reg_1571_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire AM_auto_on_3_reg_1571_pp0_iter5_reg_reg_gate_n_0;
  wire AM_auto_on_3_reg_1571_pp0_iter6_reg;
  wire GND_2;
  wire VCC_2;
  wire [47:0]acc_H1_FSK_V;
  wire acc_H1_FSK_V0;
  wire \acc_H1_FSK_V[0]_i_2_n_0 ;
  wire \acc_H1_FSK_V[10]_i_2_n_0 ;
  wire \acc_H1_FSK_V[11]_i_10_n_0 ;
  wire \acc_H1_FSK_V[11]_i_11_n_0 ;
  wire \acc_H1_FSK_V[11]_i_12_n_0 ;
  wire \acc_H1_FSK_V[11]_i_2_n_0 ;
  wire \acc_H1_FSK_V[11]_i_5_n_0 ;
  wire \acc_H1_FSK_V[11]_i_6_n_0 ;
  wire \acc_H1_FSK_V[11]_i_7_n_0 ;
  wire \acc_H1_FSK_V[11]_i_8_n_0 ;
  wire \acc_H1_FSK_V[11]_i_9_n_0 ;
  wire \acc_H1_FSK_V[12]_i_2_n_0 ;
  wire \acc_H1_FSK_V[13]_i_10_n_0 ;
  wire \acc_H1_FSK_V[13]_i_11_n_0 ;
  wire \acc_H1_FSK_V[13]_i_2_n_0 ;
  wire \acc_H1_FSK_V[13]_i_4_n_0 ;
  wire \acc_H1_FSK_V[13]_i_5_n_0 ;
  wire \acc_H1_FSK_V[13]_i_6_n_0 ;
  wire \acc_H1_FSK_V[13]_i_7_n_0 ;
  wire \acc_H1_FSK_V[13]_i_8_n_0 ;
  wire \acc_H1_FSK_V[13]_i_9_n_0 ;
  wire \acc_H1_FSK_V[14]_i_2_n_0 ;
  wire \acc_H1_FSK_V[15]_i_10_n_0 ;
  wire \acc_H1_FSK_V[15]_i_11_n_0 ;
  wire \acc_H1_FSK_V[15]_i_12_n_0 ;
  wire \acc_H1_FSK_V[15]_i_2_n_0 ;
  wire \acc_H1_FSK_V[15]_i_5_n_0 ;
  wire \acc_H1_FSK_V[15]_i_6_n_0 ;
  wire \acc_H1_FSK_V[15]_i_7_n_0 ;
  wire \acc_H1_FSK_V[15]_i_8_n_0 ;
  wire \acc_H1_FSK_V[15]_i_9_n_0 ;
  wire \acc_H1_FSK_V[16]_i_2_n_0 ;
  wire \acc_H1_FSK_V[17]_i_10_n_0 ;
  wire \acc_H1_FSK_V[17]_i_11_n_0 ;
  wire \acc_H1_FSK_V[17]_i_2_n_0 ;
  wire \acc_H1_FSK_V[17]_i_4_n_0 ;
  wire \acc_H1_FSK_V[17]_i_5_n_0 ;
  wire \acc_H1_FSK_V[17]_i_6_n_0 ;
  wire \acc_H1_FSK_V[17]_i_7_n_0 ;
  wire \acc_H1_FSK_V[17]_i_8_n_0 ;
  wire \acc_H1_FSK_V[17]_i_9_n_0 ;
  wire \acc_H1_FSK_V[18]_i_2_n_0 ;
  wire \acc_H1_FSK_V[19]_i_10_n_0 ;
  wire \acc_H1_FSK_V[19]_i_11_n_0 ;
  wire \acc_H1_FSK_V[19]_i_12_n_0 ;
  wire \acc_H1_FSK_V[19]_i_2_n_0 ;
  wire \acc_H1_FSK_V[19]_i_5_n_0 ;
  wire \acc_H1_FSK_V[19]_i_6_n_0 ;
  wire \acc_H1_FSK_V[19]_i_7_n_0 ;
  wire \acc_H1_FSK_V[19]_i_8_n_0 ;
  wire \acc_H1_FSK_V[19]_i_9_n_0 ;
  wire \acc_H1_FSK_V[1]_i_10_n_0 ;
  wire \acc_H1_FSK_V[1]_i_11_n_0 ;
  wire \acc_H1_FSK_V[1]_i_12_n_0 ;
  wire \acc_H1_FSK_V[1]_i_14_n_0 ;
  wire \acc_H1_FSK_V[1]_i_15_n_0 ;
  wire \acc_H1_FSK_V[1]_i_16_n_0 ;
  wire \acc_H1_FSK_V[1]_i_17_n_0 ;
  wire \acc_H1_FSK_V[1]_i_18_n_0 ;
  wire \acc_H1_FSK_V[1]_i_20_n_0 ;
  wire \acc_H1_FSK_V[1]_i_21_n_0 ;
  wire \acc_H1_FSK_V[1]_i_22_n_0 ;
  wire \acc_H1_FSK_V[1]_i_23_n_0 ;
  wire \acc_H1_FSK_V[1]_i_25_n_0 ;
  wire \acc_H1_FSK_V[1]_i_26_n_0 ;
  wire \acc_H1_FSK_V[1]_i_27_n_0 ;
  wire \acc_H1_FSK_V[1]_i_28_n_0 ;
  wire \acc_H1_FSK_V[1]_i_2_n_0 ;
  wire \acc_H1_FSK_V[1]_i_30_n_0 ;
  wire \acc_H1_FSK_V[1]_i_31_n_0 ;
  wire \acc_H1_FSK_V[1]_i_32_n_0 ;
  wire \acc_H1_FSK_V[1]_i_33_n_0 ;
  wire \acc_H1_FSK_V[1]_i_34_n_0 ;
  wire \acc_H1_FSK_V[1]_i_35_n_0 ;
  wire \acc_H1_FSK_V[1]_i_36_n_0 ;
  wire \acc_H1_FSK_V[1]_i_5_n_0 ;
  wire \acc_H1_FSK_V[1]_i_6_n_0 ;
  wire \acc_H1_FSK_V[1]_i_7_n_0 ;
  wire \acc_H1_FSK_V[1]_i_8_n_0 ;
  wire \acc_H1_FSK_V[1]_i_9_n_0 ;
  wire \acc_H1_FSK_V[20]_i_2_n_0 ;
  wire \acc_H1_FSK_V[21]_i_10_n_0 ;
  wire \acc_H1_FSK_V[21]_i_11_n_0 ;
  wire \acc_H1_FSK_V[21]_i_2_n_0 ;
  wire \acc_H1_FSK_V[21]_i_4_n_0 ;
  wire \acc_H1_FSK_V[21]_i_5_n_0 ;
  wire \acc_H1_FSK_V[21]_i_6_n_0 ;
  wire \acc_H1_FSK_V[21]_i_7_n_0 ;
  wire \acc_H1_FSK_V[21]_i_8_n_0 ;
  wire \acc_H1_FSK_V[21]_i_9_n_0 ;
  wire \acc_H1_FSK_V[22]_i_2_n_0 ;
  wire \acc_H1_FSK_V[23]_i_10_n_0 ;
  wire \acc_H1_FSK_V[23]_i_11_n_0 ;
  wire \acc_H1_FSK_V[23]_i_12_n_0 ;
  wire \acc_H1_FSK_V[23]_i_2_n_0 ;
  wire \acc_H1_FSK_V[23]_i_5_n_0 ;
  wire \acc_H1_FSK_V[23]_i_6_n_0 ;
  wire \acc_H1_FSK_V[23]_i_7_n_0 ;
  wire \acc_H1_FSK_V[23]_i_8_n_0 ;
  wire \acc_H1_FSK_V[23]_i_9_n_0 ;
  wire \acc_H1_FSK_V[24]_i_2_n_0 ;
  wire \acc_H1_FSK_V[25]_i_10_n_0 ;
  wire \acc_H1_FSK_V[25]_i_11_n_0 ;
  wire \acc_H1_FSK_V[25]_i_2_n_0 ;
  wire \acc_H1_FSK_V[25]_i_4_n_0 ;
  wire \acc_H1_FSK_V[25]_i_5_n_0 ;
  wire \acc_H1_FSK_V[25]_i_6_n_0 ;
  wire \acc_H1_FSK_V[25]_i_7_n_0 ;
  wire \acc_H1_FSK_V[25]_i_8_n_0 ;
  wire \acc_H1_FSK_V[25]_i_9_n_0 ;
  wire \acc_H1_FSK_V[26]_i_2_n_0 ;
  wire \acc_H1_FSK_V[27]_i_10_n_0 ;
  wire \acc_H1_FSK_V[27]_i_11_n_0 ;
  wire \acc_H1_FSK_V[27]_i_12_n_0 ;
  wire \acc_H1_FSK_V[27]_i_2_n_0 ;
  wire \acc_H1_FSK_V[27]_i_5_n_0 ;
  wire \acc_H1_FSK_V[27]_i_6_n_0 ;
  wire \acc_H1_FSK_V[27]_i_7_n_0 ;
  wire \acc_H1_FSK_V[27]_i_8_n_0 ;
  wire \acc_H1_FSK_V[27]_i_9_n_0 ;
  wire \acc_H1_FSK_V[28]_i_2_n_0 ;
  wire \acc_H1_FSK_V[29]_i_10_n_0 ;
  wire \acc_H1_FSK_V[29]_i_11_n_0 ;
  wire \acc_H1_FSK_V[29]_i_2_n_0 ;
  wire \acc_H1_FSK_V[29]_i_4_n_0 ;
  wire \acc_H1_FSK_V[29]_i_5_n_0 ;
  wire \acc_H1_FSK_V[29]_i_6_n_0 ;
  wire \acc_H1_FSK_V[29]_i_7_n_0 ;
  wire \acc_H1_FSK_V[29]_i_8_n_0 ;
  wire \acc_H1_FSK_V[29]_i_9_n_0 ;
  wire \acc_H1_FSK_V[2]_i_2_n_0 ;
  wire \acc_H1_FSK_V[30]_i_2_n_0 ;
  wire \acc_H1_FSK_V[31]_i_10_n_0 ;
  wire \acc_H1_FSK_V[31]_i_11_n_0 ;
  wire \acc_H1_FSK_V[31]_i_12_n_0 ;
  wire \acc_H1_FSK_V[31]_i_2_n_0 ;
  wire \acc_H1_FSK_V[31]_i_5_n_0 ;
  wire \acc_H1_FSK_V[31]_i_6_n_0 ;
  wire \acc_H1_FSK_V[31]_i_7_n_0 ;
  wire \acc_H1_FSK_V[31]_i_8_n_0 ;
  wire \acc_H1_FSK_V[31]_i_9_n_0 ;
  wire \acc_H1_FSK_V[32]_i_2_n_0 ;
  wire \acc_H1_FSK_V[33]_i_10_n_0 ;
  wire \acc_H1_FSK_V[33]_i_11_n_0 ;
  wire \acc_H1_FSK_V[33]_i_2_n_0 ;
  wire \acc_H1_FSK_V[33]_i_4_n_0 ;
  wire \acc_H1_FSK_V[33]_i_5_n_0 ;
  wire \acc_H1_FSK_V[33]_i_6_n_0 ;
  wire \acc_H1_FSK_V[33]_i_7_n_0 ;
  wire \acc_H1_FSK_V[33]_i_8_n_0 ;
  wire \acc_H1_FSK_V[33]_i_9_n_0 ;
  wire \acc_H1_FSK_V[34]_i_2_n_0 ;
  wire \acc_H1_FSK_V[35]_i_10_n_0 ;
  wire \acc_H1_FSK_V[35]_i_11_n_0 ;
  wire \acc_H1_FSK_V[35]_i_12_n_0 ;
  wire \acc_H1_FSK_V[35]_i_2_n_0 ;
  wire \acc_H1_FSK_V[35]_i_5_n_0 ;
  wire \acc_H1_FSK_V[35]_i_6_n_0 ;
  wire \acc_H1_FSK_V[35]_i_7_n_0 ;
  wire \acc_H1_FSK_V[35]_i_8_n_0 ;
  wire \acc_H1_FSK_V[35]_i_9_n_0 ;
  wire \acc_H1_FSK_V[36]_i_2_n_0 ;
  wire \acc_H1_FSK_V[37]_i_10_n_0 ;
  wire \acc_H1_FSK_V[37]_i_11_n_0 ;
  wire \acc_H1_FSK_V[37]_i_2_n_0 ;
  wire \acc_H1_FSK_V[37]_i_4_n_0 ;
  wire \acc_H1_FSK_V[37]_i_5_n_0 ;
  wire \acc_H1_FSK_V[37]_i_6_n_0 ;
  wire \acc_H1_FSK_V[37]_i_7_n_0 ;
  wire \acc_H1_FSK_V[37]_i_8_n_0 ;
  wire \acc_H1_FSK_V[37]_i_9_n_0 ;
  wire \acc_H1_FSK_V[38]_i_2_n_0 ;
  wire \acc_H1_FSK_V[39]_i_10_n_0 ;
  wire \acc_H1_FSK_V[39]_i_11_n_0 ;
  wire \acc_H1_FSK_V[39]_i_12_n_0 ;
  wire \acc_H1_FSK_V[39]_i_2_n_0 ;
  wire \acc_H1_FSK_V[39]_i_5_n_0 ;
  wire \acc_H1_FSK_V[39]_i_6_n_0 ;
  wire \acc_H1_FSK_V[39]_i_7_n_0 ;
  wire \acc_H1_FSK_V[39]_i_8_n_0 ;
  wire \acc_H1_FSK_V[39]_i_9_n_0 ;
  wire \acc_H1_FSK_V[3]_i_10_n_0 ;
  wire \acc_H1_FSK_V[3]_i_11_n_0 ;
  wire \acc_H1_FSK_V[3]_i_12_n_0 ;
  wire \acc_H1_FSK_V[3]_i_2_n_0 ;
  wire \acc_H1_FSK_V[3]_i_5_n_0 ;
  wire \acc_H1_FSK_V[3]_i_6_n_0 ;
  wire \acc_H1_FSK_V[3]_i_7_n_0 ;
  wire \acc_H1_FSK_V[3]_i_8_n_0 ;
  wire \acc_H1_FSK_V[3]_i_9_n_0 ;
  wire \acc_H1_FSK_V[40]_i_2_n_0 ;
  wire \acc_H1_FSK_V[41]_i_10_n_0 ;
  wire \acc_H1_FSK_V[41]_i_11_n_0 ;
  wire \acc_H1_FSK_V[41]_i_12_n_0 ;
  wire \acc_H1_FSK_V[41]_i_13_n_0 ;
  wire \acc_H1_FSK_V[41]_i_14_n_0 ;
  wire \acc_H1_FSK_V[41]_i_15_n_0 ;
  wire \acc_H1_FSK_V[41]_i_16_n_0 ;
  wire \acc_H1_FSK_V[41]_i_17_n_0 ;
  wire \acc_H1_FSK_V[41]_i_18_n_0 ;
  wire \acc_H1_FSK_V[41]_i_19_n_0 ;
  wire \acc_H1_FSK_V[41]_i_20_n_0 ;
  wire \acc_H1_FSK_V[41]_i_22_n_0 ;
  wire \acc_H1_FSK_V[41]_i_23_n_0 ;
  wire \acc_H1_FSK_V[41]_i_24_n_0 ;
  wire \acc_H1_FSK_V[41]_i_25_n_0 ;
  wire \acc_H1_FSK_V[41]_i_26_n_0 ;
  wire \acc_H1_FSK_V[41]_i_27_n_0 ;
  wire \acc_H1_FSK_V[41]_i_28_n_0 ;
  wire \acc_H1_FSK_V[41]_i_29_n_0 ;
  wire \acc_H1_FSK_V[41]_i_2_n_0 ;
  wire \acc_H1_FSK_V[41]_i_31_n_0 ;
  wire \acc_H1_FSK_V[41]_i_32_n_0 ;
  wire \acc_H1_FSK_V[41]_i_33_n_0 ;
  wire \acc_H1_FSK_V[41]_i_34_n_0 ;
  wire \acc_H1_FSK_V[41]_i_35_n_0 ;
  wire \acc_H1_FSK_V[41]_i_36_n_0 ;
  wire \acc_H1_FSK_V[41]_i_37_n_0 ;
  wire \acc_H1_FSK_V[41]_i_38_n_0 ;
  wire \acc_H1_FSK_V[41]_i_39_n_0 ;
  wire \acc_H1_FSK_V[41]_i_40_n_0 ;
  wire \acc_H1_FSK_V[41]_i_41_n_0 ;
  wire \acc_H1_FSK_V[41]_i_42_n_0 ;
  wire \acc_H1_FSK_V[41]_i_43_n_0 ;
  wire \acc_H1_FSK_V[41]_i_44_n_0 ;
  wire \acc_H1_FSK_V[41]_i_45_n_0 ;
  wire \acc_H1_FSK_V[41]_i_46_n_0 ;
  wire \acc_H1_FSK_V[41]_i_6_n_0 ;
  wire \acc_H1_FSK_V[41]_i_7_n_0 ;
  wire \acc_H1_FSK_V[41]_i_8_n_0 ;
  wire \acc_H1_FSK_V[41]_i_9_n_0 ;
  wire \acc_H1_FSK_V[42]_i_1_n_0 ;
  wire \acc_H1_FSK_V[42]_i_2_n_0 ;
  wire \acc_H1_FSK_V[43]_i_10_n_0 ;
  wire \acc_H1_FSK_V[43]_i_1_n_0 ;
  wire \acc_H1_FSK_V[43]_i_2_n_0 ;
  wire \acc_H1_FSK_V[43]_i_5_n_0 ;
  wire \acc_H1_FSK_V[43]_i_6_n_0 ;
  wire \acc_H1_FSK_V[43]_i_7_n_0 ;
  wire \acc_H1_FSK_V[43]_i_8_n_0 ;
  wire \acc_H1_FSK_V[43]_i_9_n_0 ;
  wire \acc_H1_FSK_V[44]_i_1_n_0 ;
  wire \acc_H1_FSK_V[44]_i_2_n_0 ;
  wire \acc_H1_FSK_V[45]_i_1_n_0 ;
  wire \acc_H1_FSK_V[45]_i_2_n_0 ;
  wire \acc_H1_FSK_V[46]_i_1_n_0 ;
  wire \acc_H1_FSK_V[46]_i_2_n_0 ;
  wire \acc_H1_FSK_V[47]_i_10_n_0 ;
  wire \acc_H1_FSK_V[47]_i_11_n_0 ;
  wire \acc_H1_FSK_V[47]_i_1_n_0 ;
  wire \acc_H1_FSK_V[47]_i_3_n_0 ;
  wire \acc_H1_FSK_V[47]_i_4_n_0 ;
  wire \acc_H1_FSK_V[47]_i_5_n_0 ;
  wire \acc_H1_FSK_V[47]_i_8_n_0 ;
  wire \acc_H1_FSK_V[47]_i_9_n_0 ;
  wire \acc_H1_FSK_V[4]_i_2_n_0 ;
  wire \acc_H1_FSK_V[5]_i_10_n_0 ;
  wire \acc_H1_FSK_V[5]_i_11_n_0 ;
  wire \acc_H1_FSK_V[5]_i_2_n_0 ;
  wire \acc_H1_FSK_V[5]_i_4_n_0 ;
  wire \acc_H1_FSK_V[5]_i_5_n_0 ;
  wire \acc_H1_FSK_V[5]_i_6_n_0 ;
  wire \acc_H1_FSK_V[5]_i_7_n_0 ;
  wire \acc_H1_FSK_V[5]_i_8_n_0 ;
  wire \acc_H1_FSK_V[5]_i_9_n_0 ;
  wire \acc_H1_FSK_V[6]_i_2_n_0 ;
  wire \acc_H1_FSK_V[7]_i_10_n_0 ;
  wire \acc_H1_FSK_V[7]_i_11_n_0 ;
  wire \acc_H1_FSK_V[7]_i_12_n_0 ;
  wire \acc_H1_FSK_V[7]_i_2_n_0 ;
  wire \acc_H1_FSK_V[7]_i_5_n_0 ;
  wire \acc_H1_FSK_V[7]_i_6_n_0 ;
  wire \acc_H1_FSK_V[7]_i_7_n_0 ;
  wire \acc_H1_FSK_V[7]_i_8_n_0 ;
  wire \acc_H1_FSK_V[7]_i_9_n_0 ;
  wire \acc_H1_FSK_V[8]_i_2_n_0 ;
  wire \acc_H1_FSK_V[9]_i_10_n_0 ;
  wire \acc_H1_FSK_V[9]_i_11_n_0 ;
  wire \acc_H1_FSK_V[9]_i_2_n_0 ;
  wire \acc_H1_FSK_V[9]_i_4_n_0 ;
  wire \acc_H1_FSK_V[9]_i_5_n_0 ;
  wire \acc_H1_FSK_V[9]_i_6_n_0 ;
  wire \acc_H1_FSK_V[9]_i_7_n_0 ;
  wire \acc_H1_FSK_V[9]_i_8_n_0 ;
  wire \acc_H1_FSK_V[9]_i_9_n_0 ;
  wire \acc_H1_FSK_V_reg[11]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[11]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[11]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[11]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[11]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[11]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[11]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[11]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[13]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[13]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[13]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[13]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[15]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[15]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[15]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[15]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[15]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[15]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[15]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[15]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[17]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[17]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[17]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[17]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[19]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[19]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[19]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[19]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[19]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[19]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[19]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[19]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[1]_i_13_n_0 ;
  wire \acc_H1_FSK_V_reg[1]_i_13_n_1 ;
  wire \acc_H1_FSK_V_reg[1]_i_13_n_2 ;
  wire \acc_H1_FSK_V_reg[1]_i_13_n_3 ;
  wire \acc_H1_FSK_V_reg[1]_i_19_n_0 ;
  wire \acc_H1_FSK_V_reg[1]_i_19_n_1 ;
  wire \acc_H1_FSK_V_reg[1]_i_19_n_2 ;
  wire \acc_H1_FSK_V_reg[1]_i_19_n_3 ;
  wire \acc_H1_FSK_V_reg[1]_i_24_n_0 ;
  wire \acc_H1_FSK_V_reg[1]_i_24_n_1 ;
  wire \acc_H1_FSK_V_reg[1]_i_24_n_2 ;
  wire \acc_H1_FSK_V_reg[1]_i_24_n_3 ;
  wire \acc_H1_FSK_V_reg[1]_i_29_n_0 ;
  wire \acc_H1_FSK_V_reg[1]_i_29_n_1 ;
  wire \acc_H1_FSK_V_reg[1]_i_29_n_2 ;
  wire \acc_H1_FSK_V_reg[1]_i_29_n_3 ;
  wire \acc_H1_FSK_V_reg[1]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[1]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[1]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[1]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[1]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[1]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[1]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[1]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[21]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[21]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[21]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[21]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[23]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[23]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[23]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[23]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[23]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[23]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[23]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[23]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[25]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[25]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[25]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[25]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[27]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[27]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[27]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[27]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[27]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[27]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[27]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[27]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[29]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[29]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[29]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[29]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[31]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[31]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[31]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[31]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[31]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[31]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[31]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[31]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[33]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[33]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[33]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[33]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[35]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[35]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[35]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[35]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[35]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[35]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[35]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[35]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[37]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[37]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[37]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[37]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[39]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[39]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[39]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[39]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[39]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[39]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[39]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[39]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[3]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[3]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[3]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[3]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[3]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[3]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[3]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[3]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[41]_i_21_n_0 ;
  wire \acc_H1_FSK_V_reg[41]_i_21_n_1 ;
  wire \acc_H1_FSK_V_reg[41]_i_21_n_2 ;
  wire \acc_H1_FSK_V_reg[41]_i_21_n_3 ;
  wire \acc_H1_FSK_V_reg[41]_i_30_n_0 ;
  wire \acc_H1_FSK_V_reg[41]_i_30_n_1 ;
  wire \acc_H1_FSK_V_reg[41]_i_30_n_2 ;
  wire \acc_H1_FSK_V_reg[41]_i_30_n_3 ;
  wire \acc_H1_FSK_V_reg[41]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[41]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[41]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[41]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[41]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[41]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[41]_i_5_n_0 ;
  wire \acc_H1_FSK_V_reg[41]_i_5_n_1 ;
  wire \acc_H1_FSK_V_reg[41]_i_5_n_2 ;
  wire \acc_H1_FSK_V_reg[41]_i_5_n_3 ;
  wire \acc_H1_FSK_V_reg[43]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[43]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[43]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[43]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[43]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[43]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[43]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[43]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[47]_i_6_n_1 ;
  wire \acc_H1_FSK_V_reg[47]_i_6_n_2 ;
  wire \acc_H1_FSK_V_reg[47]_i_6_n_3 ;
  wire \acc_H1_FSK_V_reg[47]_i_7_n_1 ;
  wire \acc_H1_FSK_V_reg[47]_i_7_n_2 ;
  wire \acc_H1_FSK_V_reg[47]_i_7_n_3 ;
  wire \acc_H1_FSK_V_reg[5]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[5]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[5]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[5]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[7]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[7]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[7]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[7]_i_3_n_3 ;
  wire \acc_H1_FSK_V_reg[7]_i_4_n_0 ;
  wire \acc_H1_FSK_V_reg[7]_i_4_n_1 ;
  wire \acc_H1_FSK_V_reg[7]_i_4_n_2 ;
  wire \acc_H1_FSK_V_reg[7]_i_4_n_3 ;
  wire \acc_H1_FSK_V_reg[9]_i_3_n_0 ;
  wire \acc_H1_FSK_V_reg[9]_i_3_n_1 ;
  wire \acc_H1_FSK_V_reg[9]_i_3_n_2 ;
  wire \acc_H1_FSK_V_reg[9]_i_3_n_3 ;
  wire acc_H1_V0;
  wire \acc_H1_V[0]_i_4_n_0 ;
  wire \acc_H1_V[0]_i_5_n_0 ;
  wire \acc_H1_V[0]_i_6_n_0 ;
  wire \acc_H1_V[0]_i_7_n_0 ;
  wire \acc_H1_V[12]_i_2_n_0 ;
  wire \acc_H1_V[12]_i_3_n_0 ;
  wire \acc_H1_V[12]_i_4_n_0 ;
  wire \acc_H1_V[12]_i_5_n_0 ;
  wire \acc_H1_V[16]_i_2_n_0 ;
  wire \acc_H1_V[16]_i_3_n_0 ;
  wire \acc_H1_V[16]_i_4_n_0 ;
  wire \acc_H1_V[16]_i_5_n_0 ;
  wire \acc_H1_V[20]_i_2_n_0 ;
  wire \acc_H1_V[20]_i_3_n_0 ;
  wire \acc_H1_V[20]_i_4_n_0 ;
  wire \acc_H1_V[20]_i_5_n_0 ;
  wire \acc_H1_V[24]_i_2_n_0 ;
  wire \acc_H1_V[24]_i_3_n_0 ;
  wire \acc_H1_V[24]_i_4_n_0 ;
  wire \acc_H1_V[24]_i_5_n_0 ;
  wire \acc_H1_V[28]_i_2_n_0 ;
  wire \acc_H1_V[28]_i_3_n_0 ;
  wire \acc_H1_V[28]_i_4_n_0 ;
  wire \acc_H1_V[28]_i_5_n_0 ;
  wire \acc_H1_V[32]_i_2_n_0 ;
  wire \acc_H1_V[32]_i_3_n_0 ;
  wire \acc_H1_V[32]_i_4_n_0 ;
  wire \acc_H1_V[32]_i_5_n_0 ;
  wire \acc_H1_V[36]_i_2_n_0 ;
  wire \acc_H1_V[36]_i_3_n_0 ;
  wire \acc_H1_V[36]_i_4_n_0 ;
  wire \acc_H1_V[36]_i_5_n_0 ;
  wire \acc_H1_V[40]_i_2_n_0 ;
  wire \acc_H1_V[40]_i_3_n_0 ;
  wire \acc_H1_V[40]_i_4_n_0 ;
  wire \acc_H1_V[40]_i_5_n_0 ;
  wire \acc_H1_V[44]_i_2_n_0 ;
  wire \acc_H1_V[44]_i_3_n_0 ;
  wire \acc_H1_V[44]_i_4_n_0 ;
  wire \acc_H1_V[44]_i_5_n_0 ;
  wire \acc_H1_V[4]_i_2_n_0 ;
  wire \acc_H1_V[4]_i_3_n_0 ;
  wire \acc_H1_V[4]_i_4_n_0 ;
  wire \acc_H1_V[4]_i_5_n_0 ;
  wire \acc_H1_V[8]_i_2_n_0 ;
  wire \acc_H1_V[8]_i_3_n_0 ;
  wire \acc_H1_V[8]_i_4_n_0 ;
  wire \acc_H1_V[8]_i_5_n_0 ;
  wire [47:0]acc_H1_V_reg;
  wire \acc_H1_V_reg[0]_i_3_n_0 ;
  wire \acc_H1_V_reg[0]_i_3_n_1 ;
  wire \acc_H1_V_reg[0]_i_3_n_2 ;
  wire \acc_H1_V_reg[0]_i_3_n_3 ;
  wire \acc_H1_V_reg[0]_i_3_n_4 ;
  wire \acc_H1_V_reg[0]_i_3_n_5 ;
  wire \acc_H1_V_reg[0]_i_3_n_6 ;
  wire \acc_H1_V_reg[0]_i_3_n_7 ;
  wire \acc_H1_V_reg[12]_i_1_n_0 ;
  wire \acc_H1_V_reg[12]_i_1_n_1 ;
  wire \acc_H1_V_reg[12]_i_1_n_2 ;
  wire \acc_H1_V_reg[12]_i_1_n_3 ;
  wire \acc_H1_V_reg[12]_i_1_n_4 ;
  wire \acc_H1_V_reg[12]_i_1_n_5 ;
  wire \acc_H1_V_reg[12]_i_1_n_6 ;
  wire \acc_H1_V_reg[12]_i_1_n_7 ;
  wire \acc_H1_V_reg[16]_i_1_n_0 ;
  wire \acc_H1_V_reg[16]_i_1_n_1 ;
  wire \acc_H1_V_reg[16]_i_1_n_2 ;
  wire \acc_H1_V_reg[16]_i_1_n_3 ;
  wire \acc_H1_V_reg[16]_i_1_n_4 ;
  wire \acc_H1_V_reg[16]_i_1_n_5 ;
  wire \acc_H1_V_reg[16]_i_1_n_6 ;
  wire \acc_H1_V_reg[16]_i_1_n_7 ;
  wire \acc_H1_V_reg[20]_i_1_n_0 ;
  wire \acc_H1_V_reg[20]_i_1_n_1 ;
  wire \acc_H1_V_reg[20]_i_1_n_2 ;
  wire \acc_H1_V_reg[20]_i_1_n_3 ;
  wire \acc_H1_V_reg[20]_i_1_n_4 ;
  wire \acc_H1_V_reg[20]_i_1_n_5 ;
  wire \acc_H1_V_reg[20]_i_1_n_6 ;
  wire \acc_H1_V_reg[20]_i_1_n_7 ;
  wire \acc_H1_V_reg[24]_i_1_n_0 ;
  wire \acc_H1_V_reg[24]_i_1_n_1 ;
  wire \acc_H1_V_reg[24]_i_1_n_2 ;
  wire \acc_H1_V_reg[24]_i_1_n_3 ;
  wire \acc_H1_V_reg[24]_i_1_n_4 ;
  wire \acc_H1_V_reg[24]_i_1_n_5 ;
  wire \acc_H1_V_reg[24]_i_1_n_6 ;
  wire \acc_H1_V_reg[24]_i_1_n_7 ;
  wire \acc_H1_V_reg[28]_i_1_n_0 ;
  wire \acc_H1_V_reg[28]_i_1_n_1 ;
  wire \acc_H1_V_reg[28]_i_1_n_2 ;
  wire \acc_H1_V_reg[28]_i_1_n_3 ;
  wire \acc_H1_V_reg[28]_i_1_n_4 ;
  wire \acc_H1_V_reg[28]_i_1_n_5 ;
  wire \acc_H1_V_reg[28]_i_1_n_6 ;
  wire \acc_H1_V_reg[28]_i_1_n_7 ;
  wire \acc_H1_V_reg[32]_i_1_n_0 ;
  wire \acc_H1_V_reg[32]_i_1_n_1 ;
  wire \acc_H1_V_reg[32]_i_1_n_2 ;
  wire \acc_H1_V_reg[32]_i_1_n_3 ;
  wire \acc_H1_V_reg[32]_i_1_n_4 ;
  wire \acc_H1_V_reg[32]_i_1_n_5 ;
  wire \acc_H1_V_reg[32]_i_1_n_6 ;
  wire \acc_H1_V_reg[32]_i_1_n_7 ;
  wire \acc_H1_V_reg[36]_i_1_n_0 ;
  wire \acc_H1_V_reg[36]_i_1_n_1 ;
  wire \acc_H1_V_reg[36]_i_1_n_2 ;
  wire \acc_H1_V_reg[36]_i_1_n_3 ;
  wire \acc_H1_V_reg[36]_i_1_n_4 ;
  wire \acc_H1_V_reg[36]_i_1_n_5 ;
  wire \acc_H1_V_reg[36]_i_1_n_6 ;
  wire \acc_H1_V_reg[36]_i_1_n_7 ;
  wire \acc_H1_V_reg[40]_i_1_n_0 ;
  wire \acc_H1_V_reg[40]_i_1_n_1 ;
  wire \acc_H1_V_reg[40]_i_1_n_2 ;
  wire \acc_H1_V_reg[40]_i_1_n_3 ;
  wire \acc_H1_V_reg[40]_i_1_n_4 ;
  wire \acc_H1_V_reg[40]_i_1_n_5 ;
  wire \acc_H1_V_reg[40]_i_1_n_6 ;
  wire \acc_H1_V_reg[40]_i_1_n_7 ;
  wire \acc_H1_V_reg[44]_i_1_n_1 ;
  wire \acc_H1_V_reg[44]_i_1_n_2 ;
  wire \acc_H1_V_reg[44]_i_1_n_3 ;
  wire \acc_H1_V_reg[44]_i_1_n_4 ;
  wire \acc_H1_V_reg[44]_i_1_n_5 ;
  wire \acc_H1_V_reg[44]_i_1_n_6 ;
  wire \acc_H1_V_reg[44]_i_1_n_7 ;
  wire \acc_H1_V_reg[4]_i_1_n_0 ;
  wire \acc_H1_V_reg[4]_i_1_n_1 ;
  wire \acc_H1_V_reg[4]_i_1_n_2 ;
  wire \acc_H1_V_reg[4]_i_1_n_3 ;
  wire \acc_H1_V_reg[4]_i_1_n_4 ;
  wire \acc_H1_V_reg[4]_i_1_n_5 ;
  wire \acc_H1_V_reg[4]_i_1_n_6 ;
  wire \acc_H1_V_reg[4]_i_1_n_7 ;
  wire \acc_H1_V_reg[8]_i_1_n_0 ;
  wire \acc_H1_V_reg[8]_i_1_n_1 ;
  wire \acc_H1_V_reg[8]_i_1_n_2 ;
  wire \acc_H1_V_reg[8]_i_1_n_3 ;
  wire \acc_H1_V_reg[8]_i_1_n_4 ;
  wire \acc_H1_V_reg[8]_i_1_n_5 ;
  wire \acc_H1_V_reg[8]_i_1_n_6 ;
  wire \acc_H1_V_reg[8]_i_1_n_7 ;
  wire acc_H1_prog_V;
  wire \acc_H1_prog_V[0]_i_2_n_0 ;
  wire \acc_H1_prog_V[0]_i_3_n_0 ;
  wire \acc_H1_prog_V[0]_i_4_n_0 ;
  wire \acc_H1_prog_V[0]_i_5_n_0 ;
  wire \acc_H1_prog_V[12]_i_2_n_0 ;
  wire \acc_H1_prog_V[12]_i_3_n_0 ;
  wire \acc_H1_prog_V[12]_i_4_n_0 ;
  wire \acc_H1_prog_V[12]_i_5_n_0 ;
  wire \acc_H1_prog_V[16]_i_2_n_0 ;
  wire \acc_H1_prog_V[16]_i_3_n_0 ;
  wire \acc_H1_prog_V[16]_i_4_n_0 ;
  wire \acc_H1_prog_V[16]_i_5_n_0 ;
  wire \acc_H1_prog_V[20]_i_2_n_0 ;
  wire \acc_H1_prog_V[20]_i_3_n_0 ;
  wire \acc_H1_prog_V[20]_i_4_n_0 ;
  wire \acc_H1_prog_V[20]_i_5_n_0 ;
  wire \acc_H1_prog_V[24]_i_2_n_0 ;
  wire \acc_H1_prog_V[24]_i_3_n_0 ;
  wire \acc_H1_prog_V[24]_i_4_n_0 ;
  wire \acc_H1_prog_V[24]_i_5_n_0 ;
  wire \acc_H1_prog_V[28]_i_2_n_0 ;
  wire \acc_H1_prog_V[28]_i_3_n_0 ;
  wire \acc_H1_prog_V[28]_i_4_n_0 ;
  wire \acc_H1_prog_V[28]_i_5_n_0 ;
  wire \acc_H1_prog_V[32]_i_2_n_0 ;
  wire \acc_H1_prog_V[32]_i_3_n_0 ;
  wire \acc_H1_prog_V[32]_i_4_n_0 ;
  wire \acc_H1_prog_V[32]_i_5_n_0 ;
  wire \acc_H1_prog_V[36]_i_2_n_0 ;
  wire \acc_H1_prog_V[36]_i_3_n_0 ;
  wire \acc_H1_prog_V[36]_i_4_n_0 ;
  wire \acc_H1_prog_V[36]_i_5_n_0 ;
  wire \acc_H1_prog_V[40]_i_2_n_0 ;
  wire \acc_H1_prog_V[40]_i_3_n_0 ;
  wire \acc_H1_prog_V[40]_i_4_n_0 ;
  wire \acc_H1_prog_V[40]_i_5_n_0 ;
  wire \acc_H1_prog_V[44]_i_2_n_0 ;
  wire \acc_H1_prog_V[44]_i_3_n_0 ;
  wire \acc_H1_prog_V[44]_i_4_n_0 ;
  wire \acc_H1_prog_V[44]_i_5_n_0 ;
  wire \acc_H1_prog_V[4]_i_2_n_0 ;
  wire \acc_H1_prog_V[4]_i_3_n_0 ;
  wire \acc_H1_prog_V[4]_i_4_n_0 ;
  wire \acc_H1_prog_V[4]_i_5_n_0 ;
  wire \acc_H1_prog_V[8]_i_2_n_0 ;
  wire \acc_H1_prog_V[8]_i_3_n_0 ;
  wire \acc_H1_prog_V[8]_i_4_n_0 ;
  wire \acc_H1_prog_V[8]_i_5_n_0 ;
  wire [47:0]acc_H1_prog_V_reg;
  wire \acc_H1_prog_V_reg[0]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[0]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[12]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[16]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[20]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[24]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[28]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[32]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[36]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[40]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[44]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[4]_i_1_n_7 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_0 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_1 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_2 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_3 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_4 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_5 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_6 ;
  wire \acc_H1_prog_V_reg[8]_i_1_n_7 ;
  wire [47:0]acc_H1_slip_V;
  wire acc_H1_slip_V0;
  wire \acc_H1_slip_V[11]_i_10_n_0 ;
  wire \acc_H1_slip_V[11]_i_3_n_0 ;
  wire \acc_H1_slip_V[11]_i_4_n_0 ;
  wire \acc_H1_slip_V[11]_i_5_n_0 ;
  wire \acc_H1_slip_V[11]_i_6_n_0 ;
  wire \acc_H1_slip_V[11]_i_7_n_0 ;
  wire \acc_H1_slip_V[11]_i_8_n_0 ;
  wire \acc_H1_slip_V[11]_i_9_n_0 ;
  wire \acc_H1_slip_V[15]_i_10_n_0 ;
  wire \acc_H1_slip_V[15]_i_3_n_0 ;
  wire \acc_H1_slip_V[15]_i_4_n_0 ;
  wire \acc_H1_slip_V[15]_i_5_n_0 ;
  wire \acc_H1_slip_V[15]_i_6_n_0 ;
  wire \acc_H1_slip_V[15]_i_7_n_0 ;
  wire \acc_H1_slip_V[15]_i_8_n_0 ;
  wire \acc_H1_slip_V[15]_i_9_n_0 ;
  wire \acc_H1_slip_V[19]_i_10_n_0 ;
  wire \acc_H1_slip_V[19]_i_3_n_0 ;
  wire \acc_H1_slip_V[19]_i_4_n_0 ;
  wire \acc_H1_slip_V[19]_i_5_n_0 ;
  wire \acc_H1_slip_V[19]_i_6_n_0 ;
  wire \acc_H1_slip_V[19]_i_7_n_0 ;
  wire \acc_H1_slip_V[19]_i_8_n_0 ;
  wire \acc_H1_slip_V[19]_i_9_n_0 ;
  wire \acc_H1_slip_V[23]_i_10_n_0 ;
  wire \acc_H1_slip_V[23]_i_3_n_0 ;
  wire \acc_H1_slip_V[23]_i_4_n_0 ;
  wire \acc_H1_slip_V[23]_i_5_n_0 ;
  wire \acc_H1_slip_V[23]_i_6_n_0 ;
  wire \acc_H1_slip_V[23]_i_7_n_0 ;
  wire \acc_H1_slip_V[23]_i_8_n_0 ;
  wire \acc_H1_slip_V[23]_i_9_n_0 ;
  wire \acc_H1_slip_V[27]_i_10_n_0 ;
  wire \acc_H1_slip_V[27]_i_3_n_0 ;
  wire \acc_H1_slip_V[27]_i_4_n_0 ;
  wire \acc_H1_slip_V[27]_i_5_n_0 ;
  wire \acc_H1_slip_V[27]_i_6_n_0 ;
  wire \acc_H1_slip_V[27]_i_7_n_0 ;
  wire \acc_H1_slip_V[27]_i_8_n_0 ;
  wire \acc_H1_slip_V[27]_i_9_n_0 ;
  wire \acc_H1_slip_V[31]_i_10_n_0 ;
  wire \acc_H1_slip_V[31]_i_3_n_0 ;
  wire \acc_H1_slip_V[31]_i_4_n_0 ;
  wire \acc_H1_slip_V[31]_i_5_n_0 ;
  wire \acc_H1_slip_V[31]_i_6_n_0 ;
  wire \acc_H1_slip_V[31]_i_7_n_0 ;
  wire \acc_H1_slip_V[31]_i_8_n_0 ;
  wire \acc_H1_slip_V[31]_i_9_n_0 ;
  wire \acc_H1_slip_V[35]_i_10_n_0 ;
  wire \acc_H1_slip_V[35]_i_3_n_0 ;
  wire \acc_H1_slip_V[35]_i_4_n_0 ;
  wire \acc_H1_slip_V[35]_i_5_n_0 ;
  wire \acc_H1_slip_V[35]_i_6_n_0 ;
  wire \acc_H1_slip_V[35]_i_7_n_0 ;
  wire \acc_H1_slip_V[35]_i_8_n_0 ;
  wire \acc_H1_slip_V[35]_i_9_n_0 ;
  wire \acc_H1_slip_V[39]_i_10_n_0 ;
  wire \acc_H1_slip_V[39]_i_3_n_0 ;
  wire \acc_H1_slip_V[39]_i_4_n_0 ;
  wire \acc_H1_slip_V[39]_i_5_n_0 ;
  wire \acc_H1_slip_V[39]_i_6_n_0 ;
  wire \acc_H1_slip_V[39]_i_7_n_0 ;
  wire \acc_H1_slip_V[39]_i_8_n_0 ;
  wire \acc_H1_slip_V[39]_i_9_n_0 ;
  wire \acc_H1_slip_V[3]_i_3_n_0 ;
  wire \acc_H1_slip_V[3]_i_4_n_0 ;
  wire \acc_H1_slip_V[3]_i_5_n_0 ;
  wire \acc_H1_slip_V[3]_i_6_n_0 ;
  wire \acc_H1_slip_V[3]_i_7_n_0 ;
  wire \acc_H1_slip_V[3]_i_8_n_0 ;
  wire \acc_H1_slip_V[3]_i_9_n_0 ;
  wire \acc_H1_slip_V[43]_i_10_n_0 ;
  wire \acc_H1_slip_V[43]_i_3_n_0 ;
  wire \acc_H1_slip_V[43]_i_4_n_0 ;
  wire \acc_H1_slip_V[43]_i_5_n_0 ;
  wire \acc_H1_slip_V[43]_i_6_n_0 ;
  wire \acc_H1_slip_V[43]_i_7_n_0 ;
  wire \acc_H1_slip_V[43]_i_8_n_0 ;
  wire \acc_H1_slip_V[43]_i_9_n_0 ;
  wire \acc_H1_slip_V[47]_i_10_n_0 ;
  wire \acc_H1_slip_V[47]_i_1_n_0 ;
  wire \acc_H1_slip_V[47]_i_4_n_0 ;
  wire \acc_H1_slip_V[47]_i_5_n_0 ;
  wire \acc_H1_slip_V[47]_i_6_n_0 ;
  wire \acc_H1_slip_V[47]_i_7_n_0 ;
  wire \acc_H1_slip_V[47]_i_8_n_0 ;
  wire \acc_H1_slip_V[47]_i_9_n_0 ;
  wire \acc_H1_slip_V[7]_i_10_n_0 ;
  wire \acc_H1_slip_V[7]_i_3_n_0 ;
  wire \acc_H1_slip_V[7]_i_4_n_0 ;
  wire \acc_H1_slip_V[7]_i_5_n_0 ;
  wire \acc_H1_slip_V[7]_i_6_n_0 ;
  wire \acc_H1_slip_V[7]_i_7_n_0 ;
  wire \acc_H1_slip_V[7]_i_8_n_0 ;
  wire \acc_H1_slip_V[7]_i_9_n_0 ;
  wire \acc_H1_slip_V_reg[11]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[11]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[11]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[11]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[15]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[15]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[15]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[15]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[19]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[19]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[19]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[19]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[23]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[23]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[23]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[23]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[27]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[27]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[27]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[27]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[31]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[31]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[31]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[31]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[35]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[35]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[35]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[35]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[39]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[39]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[39]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[39]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[3]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[3]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[3]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[3]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[43]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[43]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[43]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[43]_i_2_n_3 ;
  wire \acc_H1_slip_V_reg[47]_i_3_n_1 ;
  wire \acc_H1_slip_V_reg[47]_i_3_n_2 ;
  wire \acc_H1_slip_V_reg[47]_i_3_n_3 ;
  wire \acc_H1_slip_V_reg[7]_i_2_n_0 ;
  wire \acc_H1_slip_V_reg[7]_i_2_n_1 ;
  wire \acc_H1_slip_V_reg[7]_i_2_n_2 ;
  wire \acc_H1_slip_V_reg[7]_i_2_n_3 ;
  wire acc_LO_0_V0;
  wire \acc_LO_0_V[0]_i_3_n_0 ;
  wire \acc_LO_0_V[0]_i_4_n_0 ;
  wire \acc_LO_0_V[0]_i_5_n_0 ;
  wire \acc_LO_0_V[0]_i_6_n_0 ;
  wire \acc_LO_0_V[12]_i_2_n_0 ;
  wire \acc_LO_0_V[12]_i_3_n_0 ;
  wire \acc_LO_0_V[12]_i_4_n_0 ;
  wire \acc_LO_0_V[12]_i_5_n_0 ;
  wire \acc_LO_0_V[16]_i_2_n_0 ;
  wire \acc_LO_0_V[16]_i_3_n_0 ;
  wire \acc_LO_0_V[16]_i_4_n_0 ;
  wire \acc_LO_0_V[16]_i_5_n_0 ;
  wire \acc_LO_0_V[20]_i_2_n_0 ;
  wire \acc_LO_0_V[20]_i_3_n_0 ;
  wire \acc_LO_0_V[20]_i_4_n_0 ;
  wire \acc_LO_0_V[20]_i_5_n_0 ;
  wire \acc_LO_0_V[24]_i_2_n_0 ;
  wire \acc_LO_0_V[24]_i_3_n_0 ;
  wire \acc_LO_0_V[24]_i_4_n_0 ;
  wire \acc_LO_0_V[24]_i_5_n_0 ;
  wire \acc_LO_0_V[28]_i_2_n_0 ;
  wire \acc_LO_0_V[28]_i_3_n_0 ;
  wire \acc_LO_0_V[28]_i_4_n_0 ;
  wire \acc_LO_0_V[28]_i_5_n_0 ;
  wire \acc_LO_0_V[32]_i_2_n_0 ;
  wire \acc_LO_0_V[32]_i_3_n_0 ;
  wire \acc_LO_0_V[32]_i_4_n_0 ;
  wire \acc_LO_0_V[32]_i_5_n_0 ;
  wire \acc_LO_0_V[36]_i_2_n_0 ;
  wire \acc_LO_0_V[36]_i_3_n_0 ;
  wire \acc_LO_0_V[36]_i_4_n_0 ;
  wire \acc_LO_0_V[36]_i_5_n_0 ;
  wire \acc_LO_0_V[40]_i_2_n_0 ;
  wire \acc_LO_0_V[40]_i_3_n_0 ;
  wire \acc_LO_0_V[40]_i_4_n_0 ;
  wire \acc_LO_0_V[40]_i_5_n_0 ;
  wire \acc_LO_0_V[44]_i_2_n_0 ;
  wire \acc_LO_0_V[44]_i_3_n_0 ;
  wire \acc_LO_0_V[44]_i_4_n_0 ;
  wire \acc_LO_0_V[44]_i_5_n_0 ;
  wire \acc_LO_0_V[4]_i_2_n_0 ;
  wire \acc_LO_0_V[4]_i_3_n_0 ;
  wire \acc_LO_0_V[4]_i_4_n_0 ;
  wire \acc_LO_0_V[4]_i_5_n_0 ;
  wire \acc_LO_0_V[8]_i_2_n_0 ;
  wire \acc_LO_0_V[8]_i_3_n_0 ;
  wire \acc_LO_0_V[8]_i_4_n_0 ;
  wire \acc_LO_0_V[8]_i_5_n_0 ;
  wire [47:0]acc_LO_0_V_reg;
  wire \acc_LO_0_V_reg[0]_i_2_n_0 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_1 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_2 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_3 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_4 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_5 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_6 ;
  wire \acc_LO_0_V_reg[0]_i_2_n_7 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[12]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[16]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[20]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[24]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[28]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[32]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[36]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[40]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[44]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[4]_i_1_n_7 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_0 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_1 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_2 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_3 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_4 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_5 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_6 ;
  wire \acc_LO_0_V_reg[8]_i_1_n_7 ;
  wire \acc_LO_1_V[0]_i_2_n_0 ;
  wire \acc_LO_1_V[0]_i_3_n_0 ;
  wire \acc_LO_1_V[0]_i_4_n_0 ;
  wire \acc_LO_1_V[0]_i_5_n_0 ;
  wire \acc_LO_1_V[12]_i_2_n_0 ;
  wire \acc_LO_1_V[12]_i_3_n_0 ;
  wire \acc_LO_1_V[12]_i_4_n_0 ;
  wire \acc_LO_1_V[12]_i_5_n_0 ;
  wire \acc_LO_1_V[16]_i_2_n_0 ;
  wire \acc_LO_1_V[16]_i_3_n_0 ;
  wire \acc_LO_1_V[16]_i_4_n_0 ;
  wire \acc_LO_1_V[16]_i_5_n_0 ;
  wire \acc_LO_1_V[20]_i_2_n_0 ;
  wire \acc_LO_1_V[20]_i_3_n_0 ;
  wire \acc_LO_1_V[20]_i_4_n_0 ;
  wire \acc_LO_1_V[20]_i_5_n_0 ;
  wire \acc_LO_1_V[24]_i_2_n_0 ;
  wire \acc_LO_1_V[24]_i_3_n_0 ;
  wire \acc_LO_1_V[24]_i_4_n_0 ;
  wire \acc_LO_1_V[24]_i_5_n_0 ;
  wire \acc_LO_1_V[28]_i_2_n_0 ;
  wire \acc_LO_1_V[28]_i_3_n_0 ;
  wire \acc_LO_1_V[28]_i_4_n_0 ;
  wire \acc_LO_1_V[28]_i_5_n_0 ;
  wire \acc_LO_1_V[32]_i_2_n_0 ;
  wire \acc_LO_1_V[32]_i_3_n_0 ;
  wire \acc_LO_1_V[32]_i_4_n_0 ;
  wire \acc_LO_1_V[32]_i_5_n_0 ;
  wire \acc_LO_1_V[36]_i_2_n_0 ;
  wire \acc_LO_1_V[36]_i_3_n_0 ;
  wire \acc_LO_1_V[36]_i_4_n_0 ;
  wire \acc_LO_1_V[36]_i_5_n_0 ;
  wire \acc_LO_1_V[40]_i_2_n_0 ;
  wire \acc_LO_1_V[40]_i_3_n_0 ;
  wire \acc_LO_1_V[40]_i_4_n_0 ;
  wire \acc_LO_1_V[40]_i_5_n_0 ;
  wire \acc_LO_1_V[44]_i_2_n_0 ;
  wire \acc_LO_1_V[44]_i_3_n_0 ;
  wire \acc_LO_1_V[44]_i_4_n_0 ;
  wire \acc_LO_1_V[44]_i_5_n_0 ;
  wire \acc_LO_1_V[4]_i_2_n_0 ;
  wire \acc_LO_1_V[4]_i_3_n_0 ;
  wire \acc_LO_1_V[4]_i_4_n_0 ;
  wire \acc_LO_1_V[4]_i_5_n_0 ;
  wire \acc_LO_1_V[8]_i_2_n_0 ;
  wire \acc_LO_1_V[8]_i_3_n_0 ;
  wire \acc_LO_1_V[8]_i_4_n_0 ;
  wire \acc_LO_1_V[8]_i_5_n_0 ;
  wire [47:0]acc_LO_1_V_reg;
  wire \acc_LO_1_V_reg[0]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[0]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[12]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[16]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[20]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[24]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[28]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[32]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[36]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[40]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[44]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[4]_i_1_n_7 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_0 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_1 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_2 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_3 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_4 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_5 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_6 ;
  wire \acc_LO_1_V_reg[8]_i_1_n_7 ;
  wire ap_clk;
  wire ap_enable_reg_pp0_iter1;
  wire ap_enable_reg_pp0_iter1_i_2_n_0;
  wire ap_enable_reg_pp0_iter1_i_3_n_0;
  wire ap_enable_reg_pp0_iter1_i_4_n_0;
  wire ap_enable_reg_pp0_iter1_i_5_n_0;
  wire ap_enable_reg_pp0_iter1_i_6_n_0;
  wire ap_enable_reg_pp0_iter2;
  wire ap_enable_reg_pp0_iter3;
  wire ap_enable_reg_pp0_iter4;
  wire ap_enable_reg_pp0_iter5;
  wire ap_enable_reg_pp0_iter6;
  wire ap_enable_reg_pp0_iter7;
  wire ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428[0]_i_1_n_0 ;
  wire [31:0]ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[10]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[11]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[12]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[13]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[14]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[15]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[16]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[17]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[18]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[19]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[20]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[21]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[22]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[23]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[24]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[25]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[26]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[27]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[28]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[29]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[2]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[30]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[31]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[3]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[4]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[5]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[6]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[7]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[8]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[9]_i_1_n_0 ;
  wire ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450;
  wire \ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_2_n_0 ;
  wire ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468;
  wire \ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468[0]_i_1_n_0 ;
  wire ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459;
  wire \ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459[0]_i_1_n_0 ;
  wire [2:0]ap_phi_reg_pp0_iter2_p_Val2_3_reg_440;
  wire \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]_i_1_n_0 ;
  wire [47:0]ap_phi_reg_pp0_iter2_p_Val2_7_reg_487;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[10]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[11]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[12]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[13]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[14]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[15]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[16]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[17]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[18]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[19]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[20]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[21]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[22]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[23]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[24]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[25]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[26]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[27]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[28]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[29]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[2]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[30]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[31]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[32]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[33]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[34]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[35]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[36]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[37]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[38]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[39]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[3]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[40]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[41]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[42]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[43]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[44]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[45]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[46]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[47]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[4]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[5]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[6]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[7]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[8]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[9]_i_1_n_0 ;
  wire [47:0]ap_phi_reg_pp0_iter2_p_Val2_8_reg_478;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[10]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[11]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[12]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[13]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[14]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[15]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[16]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[17]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[18]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[19]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[20]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[21]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[22]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[23]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[24]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[25]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[26]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[27]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[28]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[29]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[2]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[30]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[31]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[32]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[33]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[34]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[35]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[36]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[37]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[38]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[39]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[3]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[40]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[41]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[42]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[43]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[44]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[45]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[46]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[47]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[4]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[5]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[6]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[7]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[8]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[9]_i_1_n_0 ;
  wire [31:0]ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]_i_1_n_0 ;
  wire [47:0]ap_phi_reg_pp0_iter3_p_Val2_7_reg_487;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]_i_1_n_0 ;
  wire [47:0]ap_phi_reg_pp0_iter3_p_Val2_8_reg_478;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]_i_1_n_0 ;
  wire \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]_i_1_n_0 ;
  wire ap_rst;
  wire clk_off;
  wire \clk_off[0]_i_3_n_0 ;
  wire [31:0]clk_off_reg;
  wire \clk_off_reg[0]_i_2_n_0 ;
  wire \clk_off_reg[0]_i_2_n_1 ;
  wire \clk_off_reg[0]_i_2_n_2 ;
  wire \clk_off_reg[0]_i_2_n_3 ;
  wire \clk_off_reg[0]_i_2_n_4 ;
  wire \clk_off_reg[0]_i_2_n_5 ;
  wire \clk_off_reg[0]_i_2_n_6 ;
  wire \clk_off_reg[0]_i_2_n_7 ;
  wire \clk_off_reg[12]_i_1_n_0 ;
  wire \clk_off_reg[12]_i_1_n_1 ;
  wire \clk_off_reg[12]_i_1_n_2 ;
  wire \clk_off_reg[12]_i_1_n_3 ;
  wire \clk_off_reg[12]_i_1_n_4 ;
  wire \clk_off_reg[12]_i_1_n_5 ;
  wire \clk_off_reg[12]_i_1_n_6 ;
  wire \clk_off_reg[12]_i_1_n_7 ;
  wire \clk_off_reg[16]_i_1_n_0 ;
  wire \clk_off_reg[16]_i_1_n_1 ;
  wire \clk_off_reg[16]_i_1_n_2 ;
  wire \clk_off_reg[16]_i_1_n_3 ;
  wire \clk_off_reg[16]_i_1_n_4 ;
  wire \clk_off_reg[16]_i_1_n_5 ;
  wire \clk_off_reg[16]_i_1_n_6 ;
  wire \clk_off_reg[16]_i_1_n_7 ;
  wire \clk_off_reg[20]_i_1_n_0 ;
  wire \clk_off_reg[20]_i_1_n_1 ;
  wire \clk_off_reg[20]_i_1_n_2 ;
  wire \clk_off_reg[20]_i_1_n_3 ;
  wire \clk_off_reg[20]_i_1_n_4 ;
  wire \clk_off_reg[20]_i_1_n_5 ;
  wire \clk_off_reg[20]_i_1_n_6 ;
  wire \clk_off_reg[20]_i_1_n_7 ;
  wire \clk_off_reg[24]_i_1_n_0 ;
  wire \clk_off_reg[24]_i_1_n_1 ;
  wire \clk_off_reg[24]_i_1_n_2 ;
  wire \clk_off_reg[24]_i_1_n_3 ;
  wire \clk_off_reg[24]_i_1_n_4 ;
  wire \clk_off_reg[24]_i_1_n_5 ;
  wire \clk_off_reg[24]_i_1_n_6 ;
  wire \clk_off_reg[24]_i_1_n_7 ;
  wire \clk_off_reg[28]_i_1_n_1 ;
  wire \clk_off_reg[28]_i_1_n_2 ;
  wire \clk_off_reg[28]_i_1_n_3 ;
  wire \clk_off_reg[28]_i_1_n_4 ;
  wire \clk_off_reg[28]_i_1_n_5 ;
  wire \clk_off_reg[28]_i_1_n_6 ;
  wire \clk_off_reg[28]_i_1_n_7 ;
  wire \clk_off_reg[4]_i_1_n_0 ;
  wire \clk_off_reg[4]_i_1_n_1 ;
  wire \clk_off_reg[4]_i_1_n_2 ;
  wire \clk_off_reg[4]_i_1_n_3 ;
  wire \clk_off_reg[4]_i_1_n_4 ;
  wire \clk_off_reg[4]_i_1_n_5 ;
  wire \clk_off_reg[4]_i_1_n_6 ;
  wire \clk_off_reg[4]_i_1_n_7 ;
  wire \clk_off_reg[8]_i_1_n_0 ;
  wire \clk_off_reg[8]_i_1_n_1 ;
  wire \clk_off_reg[8]_i_1_n_2 ;
  wire \clk_off_reg[8]_i_1_n_3 ;
  wire \clk_off_reg[8]_i_1_n_4 ;
  wire \clk_off_reg[8]_i_1_n_5 ;
  wire \clk_off_reg[8]_i_1_n_6 ;
  wire \clk_off_reg[8]_i_1_n_7 ;
  wire clk_on;
  wire \clk_on[0]_i_2_n_0 ;
  wire \clk_on[0]_i_4_n_0 ;
  wire [31:0]clk_on_reg;
  wire \clk_on_reg[0]_i_3_n_0 ;
  wire \clk_on_reg[0]_i_3_n_1 ;
  wire \clk_on_reg[0]_i_3_n_2 ;
  wire \clk_on_reg[0]_i_3_n_3 ;
  wire \clk_on_reg[0]_i_3_n_4 ;
  wire \clk_on_reg[0]_i_3_n_5 ;
  wire \clk_on_reg[0]_i_3_n_6 ;
  wire \clk_on_reg[0]_i_3_n_7 ;
  wire \clk_on_reg[12]_i_1_n_0 ;
  wire \clk_on_reg[12]_i_1_n_1 ;
  wire \clk_on_reg[12]_i_1_n_2 ;
  wire \clk_on_reg[12]_i_1_n_3 ;
  wire \clk_on_reg[12]_i_1_n_4 ;
  wire \clk_on_reg[12]_i_1_n_5 ;
  wire \clk_on_reg[12]_i_1_n_6 ;
  wire \clk_on_reg[12]_i_1_n_7 ;
  wire \clk_on_reg[16]_i_1_n_0 ;
  wire \clk_on_reg[16]_i_1_n_1 ;
  wire \clk_on_reg[16]_i_1_n_2 ;
  wire \clk_on_reg[16]_i_1_n_3 ;
  wire \clk_on_reg[16]_i_1_n_4 ;
  wire \clk_on_reg[16]_i_1_n_5 ;
  wire \clk_on_reg[16]_i_1_n_6 ;
  wire \clk_on_reg[16]_i_1_n_7 ;
  wire \clk_on_reg[20]_i_1_n_0 ;
  wire \clk_on_reg[20]_i_1_n_1 ;
  wire \clk_on_reg[20]_i_1_n_2 ;
  wire \clk_on_reg[20]_i_1_n_3 ;
  wire \clk_on_reg[20]_i_1_n_4 ;
  wire \clk_on_reg[20]_i_1_n_5 ;
  wire \clk_on_reg[20]_i_1_n_6 ;
  wire \clk_on_reg[20]_i_1_n_7 ;
  wire \clk_on_reg[24]_i_1_n_0 ;
  wire \clk_on_reg[24]_i_1_n_1 ;
  wire \clk_on_reg[24]_i_1_n_2 ;
  wire \clk_on_reg[24]_i_1_n_3 ;
  wire \clk_on_reg[24]_i_1_n_4 ;
  wire \clk_on_reg[24]_i_1_n_5 ;
  wire \clk_on_reg[24]_i_1_n_6 ;
  wire \clk_on_reg[24]_i_1_n_7 ;
  wire \clk_on_reg[28]_i_1_n_1 ;
  wire \clk_on_reg[28]_i_1_n_2 ;
  wire \clk_on_reg[28]_i_1_n_3 ;
  wire \clk_on_reg[28]_i_1_n_4 ;
  wire \clk_on_reg[28]_i_1_n_5 ;
  wire \clk_on_reg[28]_i_1_n_6 ;
  wire \clk_on_reg[28]_i_1_n_7 ;
  wire \clk_on_reg[4]_i_1_n_0 ;
  wire \clk_on_reg[4]_i_1_n_1 ;
  wire \clk_on_reg[4]_i_1_n_2 ;
  wire \clk_on_reg[4]_i_1_n_3 ;
  wire \clk_on_reg[4]_i_1_n_4 ;
  wire \clk_on_reg[4]_i_1_n_5 ;
  wire \clk_on_reg[4]_i_1_n_6 ;
  wire \clk_on_reg[4]_i_1_n_7 ;
  wire \clk_on_reg[8]_i_1_n_0 ;
  wire \clk_on_reg[8]_i_1_n_1 ;
  wire \clk_on_reg[8]_i_1_n_2 ;
  wire \clk_on_reg[8]_i_1_n_3 ;
  wire \clk_on_reg[8]_i_1_n_4 ;
  wire \clk_on_reg[8]_i_1_n_5 ;
  wire \clk_on_reg[8]_i_1_n_6 ;
  wire \clk_on_reg[8]_i_1_n_7 ;
  wire [47:0]in;
  wire [15:0]inputs_H_V;
  wire inputs_H_V_ap_vld;
  wire inputs_H_V_ap_vld_preg;
  wire inputs_H_V_ap_vld_preg_i_1_n_0;
  wire [15:0]inputs_H_V_preg;
  wire [15:0]inputs_H_V_read_reg_1490;
  wire [15:0]inputs_H_V_read_reg_1490_pp0_iter2_reg;
  wire [15:0]inputs_H_V_read_reg_1490_pp0_iter3_reg;
  wire [31:0]inputs_coef_V;
  wire inputs_coef_V_ap_vld;
  wire inputs_coef_V_ap_vld_preg;
  wire inputs_coef_V_ap_vld_preg_i_1_n_0;
  wire [31:0]inputs_coef_V_preg;
  wire [31:0]inputs_coef_V_read_reg_1457;
  wire [31:0]inputs_current_coef_6_reg_1554;
  wire [31:0]inputs_current_coef_6_reg_1554_pp0_iter4_reg;
  wire [31:0]inputs_current_coef_6_reg_1554_pp0_iter5_reg;
  wire [31:0]inputs_current_coef_6_reg_1554_pp0_iter6_reg;
  wire [31:0]inputs_current_coef_s;
  wire inputs_current_coef_s0;
  wire \inputs_current_coef_s[31]_i_1_n_0 ;
  wire [31:0]inputs_current_dftw_s;
  wire inputs_current_dftw_s0;
  wire inputs_current_enabl;
  wire inputs_current_enabl_1;
  wire inputs_current_enabl_10;
  wire inputs_current_force;
  wire inputs_current_force_2_reg_468;
  wire \inputs_current_force_2_reg_468[0]_i_1_n_0 ;
  wire [47:0]inputs_current_ftw_H_1;
  wire [47:0]inputs_current_ftw_H_2;
  wire \inputs_current_ftw_H_reg_n_0_[0] ;
  wire \inputs_current_ftw_H_reg_n_0_[10] ;
  wire \inputs_current_ftw_H_reg_n_0_[11] ;
  wire \inputs_current_ftw_H_reg_n_0_[12] ;
  wire \inputs_current_ftw_H_reg_n_0_[13] ;
  wire \inputs_current_ftw_H_reg_n_0_[14] ;
  wire \inputs_current_ftw_H_reg_n_0_[15] ;
  wire \inputs_current_ftw_H_reg_n_0_[16] ;
  wire \inputs_current_ftw_H_reg_n_0_[17] ;
  wire \inputs_current_ftw_H_reg_n_0_[18] ;
  wire \inputs_current_ftw_H_reg_n_0_[19] ;
  wire \inputs_current_ftw_H_reg_n_0_[1] ;
  wire \inputs_current_ftw_H_reg_n_0_[20] ;
  wire \inputs_current_ftw_H_reg_n_0_[21] ;
  wire \inputs_current_ftw_H_reg_n_0_[22] ;
  wire \inputs_current_ftw_H_reg_n_0_[23] ;
  wire \inputs_current_ftw_H_reg_n_0_[24] ;
  wire \inputs_current_ftw_H_reg_n_0_[25] ;
  wire \inputs_current_ftw_H_reg_n_0_[26] ;
  wire \inputs_current_ftw_H_reg_n_0_[27] ;
  wire \inputs_current_ftw_H_reg_n_0_[28] ;
  wire \inputs_current_ftw_H_reg_n_0_[29] ;
  wire \inputs_current_ftw_H_reg_n_0_[2] ;
  wire \inputs_current_ftw_H_reg_n_0_[30] ;
  wire \inputs_current_ftw_H_reg_n_0_[31] ;
  wire \inputs_current_ftw_H_reg_n_0_[32] ;
  wire \inputs_current_ftw_H_reg_n_0_[33] ;
  wire \inputs_current_ftw_H_reg_n_0_[34] ;
  wire \inputs_current_ftw_H_reg_n_0_[35] ;
  wire \inputs_current_ftw_H_reg_n_0_[36] ;
  wire \inputs_current_ftw_H_reg_n_0_[37] ;
  wire \inputs_current_ftw_H_reg_n_0_[38] ;
  wire \inputs_current_ftw_H_reg_n_0_[39] ;
  wire \inputs_current_ftw_H_reg_n_0_[3] ;
  wire \inputs_current_ftw_H_reg_n_0_[40] ;
  wire \inputs_current_ftw_H_reg_n_0_[41] ;
  wire \inputs_current_ftw_H_reg_n_0_[42] ;
  wire \inputs_current_ftw_H_reg_n_0_[43] ;
  wire \inputs_current_ftw_H_reg_n_0_[44] ;
  wire \inputs_current_ftw_H_reg_n_0_[45] ;
  wire \inputs_current_ftw_H_reg_n_0_[46] ;
  wire \inputs_current_ftw_H_reg_n_0_[47] ;
  wire \inputs_current_ftw_H_reg_n_0_[4] ;
  wire \inputs_current_ftw_H_reg_n_0_[5] ;
  wire \inputs_current_ftw_H_reg_n_0_[6] ;
  wire \inputs_current_ftw_H_reg_n_0_[7] ;
  wire \inputs_current_ftw_H_reg_n_0_[8] ;
  wire \inputs_current_ftw_H_reg_n_0_[9] ;
  wire inputs_current_ftw_L0;
  wire \inputs_current_ftw_L_reg_n_0_[0] ;
  wire \inputs_current_ftw_L_reg_n_0_[10] ;
  wire \inputs_current_ftw_L_reg_n_0_[11] ;
  wire \inputs_current_ftw_L_reg_n_0_[12] ;
  wire \inputs_current_ftw_L_reg_n_0_[13] ;
  wire \inputs_current_ftw_L_reg_n_0_[14] ;
  wire \inputs_current_ftw_L_reg_n_0_[15] ;
  wire \inputs_current_ftw_L_reg_n_0_[16] ;
  wire \inputs_current_ftw_L_reg_n_0_[17] ;
  wire \inputs_current_ftw_L_reg_n_0_[18] ;
  wire \inputs_current_ftw_L_reg_n_0_[19] ;
  wire \inputs_current_ftw_L_reg_n_0_[1] ;
  wire \inputs_current_ftw_L_reg_n_0_[20] ;
  wire \inputs_current_ftw_L_reg_n_0_[21] ;
  wire \inputs_current_ftw_L_reg_n_0_[22] ;
  wire \inputs_current_ftw_L_reg_n_0_[23] ;
  wire \inputs_current_ftw_L_reg_n_0_[24] ;
  wire \inputs_current_ftw_L_reg_n_0_[25] ;
  wire \inputs_current_ftw_L_reg_n_0_[26] ;
  wire \inputs_current_ftw_L_reg_n_0_[27] ;
  wire \inputs_current_ftw_L_reg_n_0_[28] ;
  wire \inputs_current_ftw_L_reg_n_0_[29] ;
  wire \inputs_current_ftw_L_reg_n_0_[2] ;
  wire \inputs_current_ftw_L_reg_n_0_[30] ;
  wire \inputs_current_ftw_L_reg_n_0_[31] ;
  wire \inputs_current_ftw_L_reg_n_0_[32] ;
  wire \inputs_current_ftw_L_reg_n_0_[33] ;
  wire \inputs_current_ftw_L_reg_n_0_[34] ;
  wire \inputs_current_ftw_L_reg_n_0_[35] ;
  wire \inputs_current_ftw_L_reg_n_0_[36] ;
  wire \inputs_current_ftw_L_reg_n_0_[37] ;
  wire \inputs_current_ftw_L_reg_n_0_[38] ;
  wire \inputs_current_ftw_L_reg_n_0_[39] ;
  wire \inputs_current_ftw_L_reg_n_0_[3] ;
  wire \inputs_current_ftw_L_reg_n_0_[40] ;
  wire \inputs_current_ftw_L_reg_n_0_[41] ;
  wire \inputs_current_ftw_L_reg_n_0_[42] ;
  wire \inputs_current_ftw_L_reg_n_0_[43] ;
  wire \inputs_current_ftw_L_reg_n_0_[44] ;
  wire \inputs_current_ftw_L_reg_n_0_[45] ;
  wire \inputs_current_ftw_L_reg_n_0_[46] ;
  wire \inputs_current_ftw_L_reg_n_0_[47] ;
  wire \inputs_current_ftw_L_reg_n_0_[4] ;
  wire \inputs_current_ftw_L_reg_n_0_[5] ;
  wire \inputs_current_ftw_L_reg_n_0_[6] ;
  wire \inputs_current_ftw_L_reg_n_0_[7] ;
  wire \inputs_current_ftw_L_reg_n_0_[8] ;
  wire \inputs_current_ftw_L_reg_n_0_[9] ;
  wire [47:0]inputs_current_offse;
  wire [47:0]inputs_current_offse_1;
  wire [47:0]inputs_current_offse_3;
  wire [47:0]inputs_current_offse_4;
  wire [47:0]inputs_current_phase;
  wire [2:0]inputs_current_rate_s;
  wire inputs_current_reset;
  wire inputs_current_reset_1;
  wire inputs_current_reset_3_reg_1615;
  wire inputs_current_reset_3_reg_1615_pp0_iter4_reg;
  wire inputs_current_slip_s;
  wire [31:0]inputs_dftw_H1_slip_V;
  wire inputs_dftw_H1_slip_V_ap_vld;
  wire inputs_dftw_H1_slip_V_ap_vld_preg;
  wire inputs_dftw_H1_slip_V_ap_vld_preg_i_1_n_0;
  wire [31:0]inputs_dftw_H1_slip_V_preg;
  wire [0:0]inputs_enable_FSK;
  wire inputs_enable_FSK_ap_vld;
  wire inputs_enable_FSK_ap_vld_preg;
  wire inputs_enable_FSK_ap_vld_preg_i_1_n_0;
  wire inputs_enable_FSK_preg;
  wire \inputs_enable_FSK_preg[0]_i_1_n_0 ;
  wire inputs_enable_FSK_re_reg_1414;
  wire [0:0]inputs_enable_slip;
  wire inputs_enable_slip_ap_vld;
  wire inputs_enable_slip_ap_vld_preg;
  wire inputs_enable_slip_ap_vld_preg_i_1_n_0;
  wire inputs_enable_slip_preg;
  wire \inputs_enable_slip_preg[0]_i_1_n_0 ;
  wire [0:0]inputs_force_AM;
  wire inputs_force_AM_ap_vld;
  wire inputs_force_AM_ap_vld_preg;
  wire inputs_force_AM_ap_vld_preg_i_1_n_0;
  wire inputs_force_AM_preg;
  wire \inputs_force_AM_preg[0]_i_1_n_0 ;
  wire inputs_force_AM_read_reg_1392;
  wire [47:0]inputs_ftw_H1_V;
  wire inputs_ftw_H1_V_ap_vld;
  wire inputs_ftw_H1_V_ap_vld_preg;
  wire inputs_ftw_H1_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_ftw_H1_V_preg;
  wire [47:0]inputs_ftw_H1_V_read_reg_1484;
  wire [47:0]inputs_ftw_H1_on_V;
  wire inputs_ftw_H1_on_V_ap_vld;
  wire inputs_ftw_H1_on_V_ap_vld_preg;
  wire inputs_ftw_H1_on_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_ftw_H1_on_V_preg;
  wire [47:0]inputs_ftw_H1_on_V_r_reg_1463;
  wire [47:0]inputs_ftw_H1_prog_V;
  wire [47:0]inputs_ftw_H1_prog_V_1_reg_1479;
  wire inputs_ftw_H1_prog_V_ap_vld;
  wire inputs_ftw_H1_prog_V_ap_vld_preg;
  wire inputs_ftw_H1_prog_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_ftw_H1_prog_V_preg;
  wire [47:0]inputs_ftw_LO_0_V;
  wire inputs_ftw_LO_0_V_ap_vld;
  wire inputs_ftw_LO_0_V_ap_vld_preg;
  wire inputs_ftw_LO_0_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_ftw_LO_0_V_preg;
  wire [47:0]inputs_ftw_LO_0_V_re_reg_1474;
  wire [47:0]inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg;
  wire [47:0]inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg;
  wire [47:0]inputs_ftw_LO_1_V;
  wire inputs_ftw_LO_1_V_ap_vld;
  wire inputs_ftw_LO_1_V_ap_vld_preg;
  wire inputs_ftw_LO_1_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_ftw_LO_1_V_preg;
  wire [47:0]inputs_ftw_LO_1_V_re_reg_1469;
  wire [47:0]inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg;
  wire [47:0]inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg;
  wire [47:0]inputs_offset_AM_off_V;
  wire inputs_offset_AM_off_V_ap_vld;
  wire inputs_offset_AM_off_V_ap_vld_preg;
  wire inputs_offset_AM_off_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_offset_AM_off_V_preg;
  wire [47:0]inputs_offset_AM_off_reg_1437;
  wire [47:0]inputs_offset_AM_on_V;
  wire inputs_offset_AM_on_V_ap_vld;
  wire inputs_offset_AM_on_V_ap_vld_preg;
  wire inputs_offset_AM_on_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_offset_AM_on_V_preg;
  wire [47:0]inputs_offset_AM_on_s_reg_1442;
  wire [47:0]inputs_offset_FSK_V;
  wire inputs_offset_FSK_V_ap_vld;
  wire inputs_offset_FSK_V_ap_vld_preg;
  wire inputs_offset_FSK_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_offset_FSK_V_preg;
  wire [47:0]inputs_offset_FSK_V_s_reg_1447;
  wire [47:0]inputs_offset_V;
  wire inputs_offset_V_ap_vld;
  wire inputs_offset_V_ap_vld_preg;
  wire inputs_offset_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_offset_V_preg;
  wire [47:0]inputs_offset_V_read_reg_1452;
  wire [47:0]inputs_phase_H1_comp_V;
  wire inputs_phase_H1_comp_V_ap_vld;
  wire inputs_phase_H1_comp_V_ap_vld_preg;
  wire inputs_phase_H1_comp_V_ap_vld_preg_i_1_n_0;
  wire [47:0]inputs_phase_H1_comp_V_preg;
  wire [47:0]inputs_phase_H1_comp_reg_1432;
  wire [47:0]inputs_phase_H1_comp_reg_1432_pp0_iter2_reg;
  wire [47:0]inputs_phase_H1_comp_reg_1432_pp0_iter3_reg;
  wire [2:0]inputs_rate_V;
  wire inputs_rate_V_ap_vld;
  wire inputs_rate_V_ap_vld_preg;
  wire inputs_rate_V_ap_vld_preg_i_1_n_0;
  wire [2:0]inputs_rate_V_preg;
  wire \inputs_rate_V_preg[0]_i_1_n_0 ;
  wire \inputs_rate_V_preg[1]_i_1_n_0 ;
  wire \inputs_rate_V_preg[2]_i_1_n_0 ;
  wire [2:0]inputs_rate_V_read_reg_1426;
  wire [0:0]inputs_reset_FSK;
  wire inputs_reset_FSK_ap_vld;
  wire inputs_reset_FSK_ap_vld_preg;
  wire inputs_reset_FSK_ap_vld_preg_i_1_n_0;
  wire inputs_reset_FSK_preg;
  wire \inputs_reset_FSK_preg[0]_i_1_n_0 ;
  wire inputs_reset_FSK_rea_reg_1409;
  wire [0:0]inputs_reset_NCO;
  wire inputs_reset_NCO_ap_vld;
  wire inputs_reset_NCO_ap_vld_preg;
  wire inputs_reset_NCO_ap_vld_preg_i_1_n_0;
  wire inputs_reset_NCO_preg;
  wire \inputs_reset_NCO_preg[0]_i_1_n_0 ;
  wire inputs_reset_NCO_rea_reg_1398;
  wire [0:0]inputs_reset_slip;
  wire inputs_reset_slip_ap_vld;
  wire inputs_reset_slip_ap_vld_preg;
  wire inputs_reset_slip_ap_vld_preg_i_1_n_0;
  wire inputs_reset_slip_preg;
  wire \inputs_reset_slip_preg[0]_i_1_n_0 ;
  wire inputs_reset_slip_re_reg_1403;
  wire [0:0]inputs_slip_sign;
  wire inputs_slip_sign_ap_vld;
  wire inputs_slip_sign_ap_vld_preg;
  wire inputs_slip_sign_ap_vld_preg_i_1_n_0;
  wire inputs_slip_sign_preg;
  wire \inputs_slip_sign_preg[0]_i_1_n_0 ;
  wire [0:0]inputs_valid;
  wire inputs_valid_ap_vld;
  wire inputs_valid_ap_vld_preg;
  wire inputs_valid_ap_vld_preg_i_1_n_0;
  wire inputs_valid_preg;
  wire \inputs_valid_preg[0]_i_1_n_0 ;
  wire inputs_valid_read_reg_1420;
  wire inputs_valid_read_reg_1420_pp0_iter2_reg;
  wire inputs_valid_read_reg_1420_pp0_iter3_reg;
  wire inputs_valid_read_reg_1420_pp0_iter4_reg;
  wire inputs_valid_read_reg_1420_pp0_iter5_reg;
  wire inputs_valid_read_reg_1420_pp0_iter6_reg;
  wire or_cond_reg_1520;
  wire \or_cond_reg_1520[0]_i_2_n_0 ;
  wire \or_cond_reg_1520[0]_i_3_n_0 ;
  wire \or_cond_reg_1520[0]_i_4_n_0 ;
  wire outputs_AM;
  wire outputs_AM_auto_on;
  wire [31:0]outputs_coef_muxed_V;
  wire outputs_frev;
  wire outputs_frev_main;
  wire [47:0]outputs_ftw_H1_muxed_V;
  wire [47:0]outputs_phase_H1_V;
  wire [47:0]outputs_phase_H1_main_V;
  wire [47:0]outputs_phase_H1_offset_V;
  wire [47:0]outputs_phase_H1_prog_offset_V;
  wire [47:0]outputs_phase_H1_slip_V;
  wire [47:0]outputs_phase_IF_0_V;
  wire outputs_phase_IF_0_V_1_data_reg0;
  wire \outputs_phase_IF_0_V_1_data_reg[11]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[11]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[11]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[11]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[15]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[15]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[15]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[15]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[19]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[19]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[19]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[19]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[23]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[23]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[23]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[23]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[27]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[27]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[27]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[27]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[31]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[31]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[31]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[31]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[35]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[35]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[35]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[35]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_6_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_7_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_8_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[39]_i_9_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[3]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[3]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[3]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[3]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_10_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_6_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_7_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_8_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[43]_i_9_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_10_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_11_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_12_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_13_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_14_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_15_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_6_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_7_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_8_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[47]_i_9_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[7]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[7]_i_3_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[7]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg[7]_i_5_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_3_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_3_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_3 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_0 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_1 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_2 ;
  wire \outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_3 ;
  wire outputs_phase_IF_0_V_1_vld_reg_i_1_n_0;
  wire [47:0]outputs_phase_IF_1_V;
  wire \outputs_phase_IF_1_V_1_data_reg[11]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[11]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[11]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[11]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[15]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[15]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[15]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[15]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[19]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[19]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[19]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[19]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[23]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[23]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[23]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[23]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[27]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[27]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[27]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[27]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[31]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[31]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[31]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[31]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[35]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[35]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[35]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[35]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_7_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_8_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[39]_i_9_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[3]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[3]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[3]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[3]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_10_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_7_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_8_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[43]_i_9_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_10_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_11_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_12_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_13_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_14_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_8_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[47]_i_9_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[7]_i_2_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[7]_i_3_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[7]_i_4_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg[7]_i_5_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_6_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_6_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_3 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_0 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_1 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_2 ;
  wire \outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_3 ;
  wire outputs_phase_IF_1_V_ap_vld;
  wire outputs_valid;
  wire p_0_in47_out;
  wire p_0_in55_out;
  wire \p_0_out[0]__0_n_0 ;
  wire \p_0_out[10]__0_n_0 ;
  wire \p_0_out[11]__0_n_0 ;
  wire \p_0_out[12]__0_n_0 ;
  wire \p_0_out[13]__0_n_0 ;
  wire \p_0_out[14]__0_n_0 ;
  wire \p_0_out[15]__0_n_0 ;
  wire \p_0_out[16]__0_n_0 ;
  wire \p_0_out[16]__1_n_0 ;
  wire \p_0_out[1]__0_n_0 ;
  wire \p_0_out[2]__0_n_0 ;
  wire \p_0_out[3]__0_n_0 ;
  wire \p_0_out[4]__0_n_0 ;
  wire \p_0_out[5]__0_n_0 ;
  wire \p_0_out[6]__0_n_0 ;
  wire \p_0_out[7]__0_n_0 ;
  wire \p_0_out[8]__0_n_0 ;
  wire \p_0_out[9]__0_n_0 ;
  wire p_0_out__0_i_10_n_0;
  wire p_0_out__0_i_11_n_0;
  wire p_0_out__0_i_12_n_0;
  wire p_0_out__0_i_13_n_0;
  wire p_0_out__0_i_14_n_0;
  wire p_0_out__0_i_15_n_0;
  wire p_0_out__0_i_1_n_0;
  wire p_0_out__0_i_2_n_0;
  wire p_0_out__0_i_3_n_0;
  wire p_0_out__0_i_4_n_0;
  wire p_0_out__0_i_5_n_0;
  wire p_0_out__0_i_6_n_0;
  wire p_0_out__0_i_7_n_0;
  wire p_0_out__0_i_8_n_0;
  wire p_0_out__0_i_9_n_0;
  wire p_0_out__0_n_100;
  wire p_0_out__0_n_101;
  wire p_0_out__0_n_102;
  wire p_0_out__0_n_103;
  wire p_0_out__0_n_104;
  wire p_0_out__0_n_105;
  wire p_0_out__0_n_58;
  wire p_0_out__0_n_59;
  wire p_0_out__0_n_60;
  wire p_0_out__0_n_61;
  wire p_0_out__0_n_62;
  wire p_0_out__0_n_63;
  wire p_0_out__0_n_64;
  wire p_0_out__0_n_65;
  wire p_0_out__0_n_66;
  wire p_0_out__0_n_67;
  wire p_0_out__0_n_68;
  wire p_0_out__0_n_69;
  wire p_0_out__0_n_70;
  wire p_0_out__0_n_71;
  wire p_0_out__0_n_72;
  wire p_0_out__0_n_73;
  wire p_0_out__0_n_74;
  wire p_0_out__0_n_75;
  wire p_0_out__0_n_76;
  wire p_0_out__0_n_77;
  wire p_0_out__0_n_78;
  wire p_0_out__0_n_79;
  wire p_0_out__0_n_80;
  wire p_0_out__0_n_81;
  wire p_0_out__0_n_82;
  wire p_0_out__0_n_83;
  wire p_0_out__0_n_84;
  wire p_0_out__0_n_85;
  wire p_0_out__0_n_86;
  wire p_0_out__0_n_87;
  wire p_0_out__0_n_88;
  wire p_0_out__0_n_89;
  wire p_0_out__0_n_90;
  wire p_0_out__0_n_91;
  wire p_0_out__0_n_92;
  wire p_0_out__0_n_93;
  wire p_0_out__0_n_94;
  wire p_0_out__0_n_95;
  wire p_0_out__0_n_96;
  wire p_0_out__0_n_97;
  wire p_0_out__0_n_98;
  wire p_0_out__0_n_99;
  wire p_0_out__2_n_100;
  wire p_0_out__2_n_101;
  wire p_0_out__2_n_102;
  wire p_0_out__2_n_103;
  wire p_0_out__2_n_104;
  wire p_0_out__2_n_105;
  wire p_0_out__2_n_58;
  wire p_0_out__2_n_59;
  wire p_0_out__2_n_60;
  wire p_0_out__2_n_61;
  wire p_0_out__2_n_62;
  wire p_0_out__2_n_63;
  wire p_0_out__2_n_64;
  wire p_0_out__2_n_65;
  wire p_0_out__2_n_66;
  wire p_0_out__2_n_67;
  wire p_0_out__2_n_68;
  wire p_0_out__2_n_69;
  wire p_0_out__2_n_70;
  wire p_0_out__2_n_71;
  wire p_0_out__2_n_72;
  wire p_0_out__2_n_73;
  wire p_0_out__2_n_74;
  wire p_0_out__2_n_75;
  wire p_0_out__2_n_76;
  wire p_0_out__2_n_77;
  wire p_0_out__2_n_78;
  wire p_0_out__2_n_79;
  wire p_0_out__2_n_80;
  wire p_0_out__2_n_81;
  wire p_0_out__2_n_82;
  wire p_0_out__2_n_83;
  wire p_0_out__2_n_84;
  wire p_0_out__2_n_85;
  wire p_0_out__2_n_86;
  wire p_0_out__2_n_87;
  wire p_0_out__2_n_88;
  wire p_0_out__2_n_89;
  wire p_0_out__2_n_90;
  wire p_0_out__2_n_91;
  wire p_0_out__2_n_92;
  wire p_0_out__2_n_93;
  wire p_0_out__2_n_94;
  wire p_0_out__2_n_95;
  wire p_0_out__2_n_96;
  wire p_0_out__2_n_97;
  wire p_0_out__2_n_98;
  wire p_0_out__2_n_99;
  wire p_0_out__3_n_100;
  wire p_0_out__3_n_101;
  wire p_0_out__3_n_102;
  wire p_0_out__3_n_103;
  wire p_0_out__3_n_104;
  wire p_0_out__3_n_105;
  wire p_0_out__3_n_58;
  wire p_0_out__3_n_59;
  wire p_0_out__3_n_60;
  wire p_0_out__3_n_61;
  wire p_0_out__3_n_62;
  wire p_0_out__3_n_63;
  wire p_0_out__3_n_64;
  wire p_0_out__3_n_65;
  wire p_0_out__3_n_66;
  wire p_0_out__3_n_67;
  wire p_0_out__3_n_68;
  wire p_0_out__3_n_69;
  wire p_0_out__3_n_70;
  wire p_0_out__3_n_71;
  wire p_0_out__3_n_72;
  wire p_0_out__3_n_73;
  wire p_0_out__3_n_74;
  wire p_0_out__3_n_75;
  wire p_0_out__3_n_76;
  wire p_0_out__3_n_77;
  wire p_0_out__3_n_78;
  wire p_0_out__3_n_79;
  wire p_0_out__3_n_80;
  wire p_0_out__3_n_81;
  wire p_0_out__3_n_82;
  wire p_0_out__3_n_83;
  wire p_0_out__3_n_84;
  wire p_0_out__3_n_85;
  wire p_0_out__3_n_86;
  wire p_0_out__3_n_87;
  wire p_0_out__3_n_88;
  wire p_0_out__3_n_89;
  wire p_0_out__3_n_90;
  wire p_0_out__3_n_91;
  wire p_0_out__3_n_92;
  wire p_0_out__3_n_93;
  wire p_0_out__3_n_94;
  wire p_0_out__3_n_95;
  wire p_0_out__3_n_96;
  wire p_0_out__3_n_97;
  wire p_0_out__3_n_98;
  wire p_0_out__3_n_99;
  wire [79:38]p_0_out__4;
  wire \p_0_out_n_0_[0] ;
  wire \p_0_out_n_0_[10] ;
  wire \p_0_out_n_0_[11] ;
  wire \p_0_out_n_0_[12] ;
  wire \p_0_out_n_0_[13] ;
  wire \p_0_out_n_0_[14] ;
  wire \p_0_out_n_0_[15] ;
  wire \p_0_out_n_0_[16] ;
  wire \p_0_out_n_0_[1] ;
  wire \p_0_out_n_0_[2] ;
  wire \p_0_out_n_0_[3] ;
  wire \p_0_out_n_0_[4] ;
  wire \p_0_out_n_0_[5] ;
  wire \p_0_out_n_0_[6] ;
  wire \p_0_out_n_0_[7] ;
  wire \p_0_out_n_0_[8] ;
  wire \p_0_out_n_0_[9] ;
  wire [41:0]p_1_in;
  wire p_1_in48_out;
  wire p_1_in49_out;
  wire [40:0]p_5_in;
  wire [47:41]p_5_in__0;
  wire [41:0]p_Val2_12_reg_1560;
  wire \p_Val2_12_reg_1560[0]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[10]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[11]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[11]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[11]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[11]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[11]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[12]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[13]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[14]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[15]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[15]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[15]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[15]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[15]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[16]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[17]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[18]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[19]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[19]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[19]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[19]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[19]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[1]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[20]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[21]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[22]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[23]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[23]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[23]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[23]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[23]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[24]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[24]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[24]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[24]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[24]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[24]_i_7_n_0 ;
  wire \p_Val2_12_reg_1560[25]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[26]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[27]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[27]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[27]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[27]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[27]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[28]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[29]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[2]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[30]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[31]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[31]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[31]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[31]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[31]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[32]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[33]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[34]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[35]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[35]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[35]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[35]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[35]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[36]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[37]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[38]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[39]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[39]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[39]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[39]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[39]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[3]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[3]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[3]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[3]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[3]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[40]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[41]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[41]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[41]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[41]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[41]_i_7_n_0 ;
  wire \p_Val2_12_reg_1560[41]_i_8_n_0 ;
  wire \p_Val2_12_reg_1560[4]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[5]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[6]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[7]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[7]_i_3_n_0 ;
  wire \p_Val2_12_reg_1560[7]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560[7]_i_5_n_0 ;
  wire \p_Val2_12_reg_1560[7]_i_6_n_0 ;
  wire \p_Val2_12_reg_1560[8]_i_1_n_0 ;
  wire \p_Val2_12_reg_1560[9]_i_1_n_0 ;
  wire [41:0]p_Val2_12_reg_1560_pp0_iter4_reg;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[11]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[15]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[19]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[23]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[24]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[24]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[24]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[24]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[27]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[31]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[35]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[39]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[3]_i_2_n_7 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_4_n_0 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_4_n_1 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_4_n_2 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_4_n_3 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_4_n_6 ;
  wire \p_Val2_12_reg_1560_reg[41]_i_4_n_7 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_0 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_1 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_2 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_3 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_4 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_5 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_6 ;
  wire \p_Val2_12_reg_1560_reg[7]_i_2_n_7 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_13_reg_1576_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__0_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__10_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__11_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__12_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__13_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__14_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__15_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__16_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__17_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__18_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__19_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__1_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__20_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__21_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__22_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__23_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__24_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__25_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__26_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__27_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__28_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__29_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__2_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__30_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__31_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__32_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__33_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__34_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__35_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__36_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__37_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__38_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__39_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__3_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__40_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__41_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__42_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__43_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__44_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__45_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__46_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__4_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__5_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__6_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__7_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__8_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__9_n_0;
  wire p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate_n_0;
  wire [47:0]p_Val2_13_reg_1576_pp0_iter6_reg;
  wire [47:0]p_Val2_15_fu_962_p2;
  wire [47:0]p_Val2_15_reg_1581;
  wire \p_Val2_15_reg_1581[11]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[11]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[15]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[19]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[23]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[27]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[31]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[35]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[39]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[3]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[43]_i_9_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[47]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_2_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_3_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_4_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_5_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_6_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_7_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_8_n_0 ;
  wire \p_Val2_15_reg_1581[7]_i_9_n_0 ;
  wire [47:0]p_Val2_15_reg_1581_pp0_iter4_reg;
  wire [47:0]p_Val2_15_reg_1581_pp0_iter5_reg;
  wire [47:0]p_Val2_15_reg_1581_pp0_iter6_reg;
  wire \p_Val2_15_reg_1581_reg[11]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[11]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[11]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[11]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[15]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[15]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[15]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[15]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[19]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[19]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[19]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[19]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[23]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[23]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[23]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[23]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[27]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[27]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[27]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[27]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[31]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[31]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[31]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[31]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[35]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[35]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[35]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[35]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[39]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[39]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[39]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[39]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[3]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[3]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[3]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[3]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[43]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[43]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[43]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[43]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[47]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[47]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[47]_i_1_n_3 ;
  wire \p_Val2_15_reg_1581_reg[7]_i_1_n_0 ;
  wire \p_Val2_15_reg_1581_reg[7]_i_1_n_1 ;
  wire \p_Val2_15_reg_1581_reg[7]_i_1_n_2 ;
  wire \p_Val2_15_reg_1581_reg[7]_i_1_n_3 ;
  wire p_Val2_19_fu_1151_p2__0_i_10_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_11_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_12_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_13_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_14_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_15_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_16_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_17_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_18_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_19_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_1_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_1_n_1;
  wire p_Val2_19_fu_1151_p2__0_i_1_n_2;
  wire p_Val2_19_fu_1151_p2__0_i_1_n_3;
  wire p_Val2_19_fu_1151_p2__0_i_20_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_2_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_2_n_1;
  wire p_Val2_19_fu_1151_p2__0_i_2_n_2;
  wire p_Val2_19_fu_1151_p2__0_i_2_n_3;
  wire p_Val2_19_fu_1151_p2__0_i_3_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_3_n_1;
  wire p_Val2_19_fu_1151_p2__0_i_3_n_2;
  wire p_Val2_19_fu_1151_p2__0_i_3_n_3;
  wire p_Val2_19_fu_1151_p2__0_i_4_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_4_n_1;
  wire p_Val2_19_fu_1151_p2__0_i_4_n_2;
  wire p_Val2_19_fu_1151_p2__0_i_4_n_3;
  wire p_Val2_19_fu_1151_p2__0_i_5_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_6_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_7_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_8_n_0;
  wire p_Val2_19_fu_1151_p2__0_i_9_n_0;
  wire p_Val2_19_fu_1151_p2__0_n_100;
  wire p_Val2_19_fu_1151_p2__0_n_101;
  wire p_Val2_19_fu_1151_p2__0_n_102;
  wire p_Val2_19_fu_1151_p2__0_n_103;
  wire p_Val2_19_fu_1151_p2__0_n_104;
  wire p_Val2_19_fu_1151_p2__0_n_105;
  wire p_Val2_19_fu_1151_p2__0_n_106;
  wire p_Val2_19_fu_1151_p2__0_n_107;
  wire p_Val2_19_fu_1151_p2__0_n_108;
  wire p_Val2_19_fu_1151_p2__0_n_109;
  wire p_Val2_19_fu_1151_p2__0_n_110;
  wire p_Val2_19_fu_1151_p2__0_n_111;
  wire p_Val2_19_fu_1151_p2__0_n_112;
  wire p_Val2_19_fu_1151_p2__0_n_113;
  wire p_Val2_19_fu_1151_p2__0_n_114;
  wire p_Val2_19_fu_1151_p2__0_n_115;
  wire p_Val2_19_fu_1151_p2__0_n_116;
  wire p_Val2_19_fu_1151_p2__0_n_117;
  wire p_Val2_19_fu_1151_p2__0_n_118;
  wire p_Val2_19_fu_1151_p2__0_n_119;
  wire p_Val2_19_fu_1151_p2__0_n_120;
  wire p_Val2_19_fu_1151_p2__0_n_121;
  wire p_Val2_19_fu_1151_p2__0_n_122;
  wire p_Val2_19_fu_1151_p2__0_n_123;
  wire p_Val2_19_fu_1151_p2__0_n_124;
  wire p_Val2_19_fu_1151_p2__0_n_125;
  wire p_Val2_19_fu_1151_p2__0_n_126;
  wire p_Val2_19_fu_1151_p2__0_n_127;
  wire p_Val2_19_fu_1151_p2__0_n_128;
  wire p_Val2_19_fu_1151_p2__0_n_129;
  wire p_Val2_19_fu_1151_p2__0_n_130;
  wire p_Val2_19_fu_1151_p2__0_n_131;
  wire p_Val2_19_fu_1151_p2__0_n_132;
  wire p_Val2_19_fu_1151_p2__0_n_133;
  wire p_Val2_19_fu_1151_p2__0_n_134;
  wire p_Val2_19_fu_1151_p2__0_n_135;
  wire p_Val2_19_fu_1151_p2__0_n_136;
  wire p_Val2_19_fu_1151_p2__0_n_137;
  wire p_Val2_19_fu_1151_p2__0_n_138;
  wire p_Val2_19_fu_1151_p2__0_n_139;
  wire p_Val2_19_fu_1151_p2__0_n_140;
  wire p_Val2_19_fu_1151_p2__0_n_141;
  wire p_Val2_19_fu_1151_p2__0_n_142;
  wire p_Val2_19_fu_1151_p2__0_n_143;
  wire p_Val2_19_fu_1151_p2__0_n_144;
  wire p_Val2_19_fu_1151_p2__0_n_145;
  wire p_Val2_19_fu_1151_p2__0_n_146;
  wire p_Val2_19_fu_1151_p2__0_n_147;
  wire p_Val2_19_fu_1151_p2__0_n_148;
  wire p_Val2_19_fu_1151_p2__0_n_149;
  wire p_Val2_19_fu_1151_p2__0_n_150;
  wire p_Val2_19_fu_1151_p2__0_n_151;
  wire p_Val2_19_fu_1151_p2__0_n_152;
  wire p_Val2_19_fu_1151_p2__0_n_153;
  wire p_Val2_19_fu_1151_p2__0_n_58;
  wire p_Val2_19_fu_1151_p2__0_n_59;
  wire p_Val2_19_fu_1151_p2__0_n_60;
  wire p_Val2_19_fu_1151_p2__0_n_61;
  wire p_Val2_19_fu_1151_p2__0_n_62;
  wire p_Val2_19_fu_1151_p2__0_n_63;
  wire p_Val2_19_fu_1151_p2__0_n_64;
  wire p_Val2_19_fu_1151_p2__0_n_65;
  wire p_Val2_19_fu_1151_p2__0_n_66;
  wire p_Val2_19_fu_1151_p2__0_n_67;
  wire p_Val2_19_fu_1151_p2__0_n_68;
  wire p_Val2_19_fu_1151_p2__0_n_69;
  wire p_Val2_19_fu_1151_p2__0_n_70;
  wire p_Val2_19_fu_1151_p2__0_n_71;
  wire p_Val2_19_fu_1151_p2__0_n_72;
  wire p_Val2_19_fu_1151_p2__0_n_73;
  wire p_Val2_19_fu_1151_p2__0_n_74;
  wire p_Val2_19_fu_1151_p2__0_n_75;
  wire p_Val2_19_fu_1151_p2__0_n_76;
  wire p_Val2_19_fu_1151_p2__0_n_77;
  wire p_Val2_19_fu_1151_p2__0_n_78;
  wire p_Val2_19_fu_1151_p2__0_n_79;
  wire p_Val2_19_fu_1151_p2__0_n_80;
  wire p_Val2_19_fu_1151_p2__0_n_81;
  wire p_Val2_19_fu_1151_p2__0_n_82;
  wire p_Val2_19_fu_1151_p2__0_n_83;
  wire p_Val2_19_fu_1151_p2__0_n_84;
  wire p_Val2_19_fu_1151_p2__0_n_85;
  wire p_Val2_19_fu_1151_p2__0_n_86;
  wire p_Val2_19_fu_1151_p2__0_n_87;
  wire p_Val2_19_fu_1151_p2__0_n_88;
  wire p_Val2_19_fu_1151_p2__0_n_89;
  wire p_Val2_19_fu_1151_p2__0_n_90;
  wire p_Val2_19_fu_1151_p2__0_n_91;
  wire p_Val2_19_fu_1151_p2__0_n_92;
  wire p_Val2_19_fu_1151_p2__0_n_93;
  wire p_Val2_19_fu_1151_p2__0_n_94;
  wire p_Val2_19_fu_1151_p2__0_n_95;
  wire p_Val2_19_fu_1151_p2__0_n_96;
  wire p_Val2_19_fu_1151_p2__0_n_97;
  wire p_Val2_19_fu_1151_p2__0_n_98;
  wire p_Val2_19_fu_1151_p2__0_n_99;
  wire p_Val2_19_fu_1151_p2__1_i_10_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_11_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_12_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_13_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_14_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_15_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_16_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_17_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_18_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_19_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_1_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_1_n_1;
  wire p_Val2_19_fu_1151_p2__1_i_1_n_2;
  wire p_Val2_19_fu_1151_p2__1_i_1_n_3;
  wire p_Val2_19_fu_1151_p2__1_i_20_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_2_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_2_n_1;
  wire p_Val2_19_fu_1151_p2__1_i_2_n_2;
  wire p_Val2_19_fu_1151_p2__1_i_2_n_3;
  wire p_Val2_19_fu_1151_p2__1_i_3_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_3_n_1;
  wire p_Val2_19_fu_1151_p2__1_i_3_n_2;
  wire p_Val2_19_fu_1151_p2__1_i_3_n_3;
  wire p_Val2_19_fu_1151_p2__1_i_4_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_4_n_1;
  wire p_Val2_19_fu_1151_p2__1_i_4_n_2;
  wire p_Val2_19_fu_1151_p2__1_i_4_n_3;
  wire p_Val2_19_fu_1151_p2__1_i_5_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_6_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_7_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_8_n_0;
  wire p_Val2_19_fu_1151_p2__1_i_9_n_0;
  wire p_Val2_19_fu_1151_p2__1_n_100;
  wire p_Val2_19_fu_1151_p2__1_n_101;
  wire p_Val2_19_fu_1151_p2__1_n_102;
  wire p_Val2_19_fu_1151_p2__1_n_103;
  wire p_Val2_19_fu_1151_p2__1_n_104;
  wire p_Val2_19_fu_1151_p2__1_n_105;
  wire p_Val2_19_fu_1151_p2__1_n_106;
  wire p_Val2_19_fu_1151_p2__1_n_107;
  wire p_Val2_19_fu_1151_p2__1_n_108;
  wire p_Val2_19_fu_1151_p2__1_n_109;
  wire p_Val2_19_fu_1151_p2__1_n_110;
  wire p_Val2_19_fu_1151_p2__1_n_111;
  wire p_Val2_19_fu_1151_p2__1_n_112;
  wire p_Val2_19_fu_1151_p2__1_n_113;
  wire p_Val2_19_fu_1151_p2__1_n_114;
  wire p_Val2_19_fu_1151_p2__1_n_115;
  wire p_Val2_19_fu_1151_p2__1_n_116;
  wire p_Val2_19_fu_1151_p2__1_n_117;
  wire p_Val2_19_fu_1151_p2__1_n_118;
  wire p_Val2_19_fu_1151_p2__1_n_119;
  wire p_Val2_19_fu_1151_p2__1_n_120;
  wire p_Val2_19_fu_1151_p2__1_n_121;
  wire p_Val2_19_fu_1151_p2__1_n_122;
  wire p_Val2_19_fu_1151_p2__1_n_123;
  wire p_Val2_19_fu_1151_p2__1_n_124;
  wire p_Val2_19_fu_1151_p2__1_n_125;
  wire p_Val2_19_fu_1151_p2__1_n_126;
  wire p_Val2_19_fu_1151_p2__1_n_127;
  wire p_Val2_19_fu_1151_p2__1_n_128;
  wire p_Val2_19_fu_1151_p2__1_n_129;
  wire p_Val2_19_fu_1151_p2__1_n_130;
  wire p_Val2_19_fu_1151_p2__1_n_131;
  wire p_Val2_19_fu_1151_p2__1_n_132;
  wire p_Val2_19_fu_1151_p2__1_n_133;
  wire p_Val2_19_fu_1151_p2__1_n_134;
  wire p_Val2_19_fu_1151_p2__1_n_135;
  wire p_Val2_19_fu_1151_p2__1_n_136;
  wire p_Val2_19_fu_1151_p2__1_n_137;
  wire p_Val2_19_fu_1151_p2__1_n_138;
  wire p_Val2_19_fu_1151_p2__1_n_139;
  wire p_Val2_19_fu_1151_p2__1_n_140;
  wire p_Val2_19_fu_1151_p2__1_n_141;
  wire p_Val2_19_fu_1151_p2__1_n_142;
  wire p_Val2_19_fu_1151_p2__1_n_143;
  wire p_Val2_19_fu_1151_p2__1_n_144;
  wire p_Val2_19_fu_1151_p2__1_n_145;
  wire p_Val2_19_fu_1151_p2__1_n_146;
  wire p_Val2_19_fu_1151_p2__1_n_147;
  wire p_Val2_19_fu_1151_p2__1_n_148;
  wire p_Val2_19_fu_1151_p2__1_n_149;
  wire p_Val2_19_fu_1151_p2__1_n_150;
  wire p_Val2_19_fu_1151_p2__1_n_151;
  wire p_Val2_19_fu_1151_p2__1_n_152;
  wire p_Val2_19_fu_1151_p2__1_n_153;
  wire p_Val2_19_fu_1151_p2__1_n_58;
  wire p_Val2_19_fu_1151_p2__1_n_59;
  wire p_Val2_19_fu_1151_p2__1_n_60;
  wire p_Val2_19_fu_1151_p2__1_n_61;
  wire p_Val2_19_fu_1151_p2__1_n_62;
  wire p_Val2_19_fu_1151_p2__1_n_63;
  wire p_Val2_19_fu_1151_p2__1_n_64;
  wire p_Val2_19_fu_1151_p2__1_n_65;
  wire p_Val2_19_fu_1151_p2__1_n_66;
  wire p_Val2_19_fu_1151_p2__1_n_67;
  wire p_Val2_19_fu_1151_p2__1_n_68;
  wire p_Val2_19_fu_1151_p2__1_n_69;
  wire p_Val2_19_fu_1151_p2__1_n_70;
  wire p_Val2_19_fu_1151_p2__1_n_71;
  wire p_Val2_19_fu_1151_p2__1_n_72;
  wire p_Val2_19_fu_1151_p2__1_n_73;
  wire p_Val2_19_fu_1151_p2__1_n_74;
  wire p_Val2_19_fu_1151_p2__1_n_75;
  wire p_Val2_19_fu_1151_p2__1_n_76;
  wire p_Val2_19_fu_1151_p2__1_n_77;
  wire p_Val2_19_fu_1151_p2__1_n_78;
  wire p_Val2_19_fu_1151_p2__1_n_79;
  wire p_Val2_19_fu_1151_p2__1_n_80;
  wire p_Val2_19_fu_1151_p2__1_n_81;
  wire p_Val2_19_fu_1151_p2__1_n_82;
  wire p_Val2_19_fu_1151_p2__1_n_83;
  wire p_Val2_19_fu_1151_p2__1_n_84;
  wire p_Val2_19_fu_1151_p2__1_n_85;
  wire p_Val2_19_fu_1151_p2__1_n_86;
  wire p_Val2_19_fu_1151_p2__1_n_87;
  wire p_Val2_19_fu_1151_p2__1_n_88;
  wire p_Val2_19_fu_1151_p2__1_n_89;
  wire p_Val2_19_fu_1151_p2__1_n_90;
  wire p_Val2_19_fu_1151_p2__1_n_91;
  wire p_Val2_19_fu_1151_p2__1_n_92;
  wire p_Val2_19_fu_1151_p2__1_n_93;
  wire p_Val2_19_fu_1151_p2__1_n_94;
  wire p_Val2_19_fu_1151_p2__1_n_95;
  wire p_Val2_19_fu_1151_p2__1_n_96;
  wire p_Val2_19_fu_1151_p2__1_n_97;
  wire p_Val2_19_fu_1151_p2__1_n_98;
  wire p_Val2_19_fu_1151_p2__1_n_99;
  wire p_Val2_19_fu_1151_p2_i_10_n_0;
  wire p_Val2_19_fu_1151_p2_i_10_n_1;
  wire p_Val2_19_fu_1151_p2_i_10_n_2;
  wire p_Val2_19_fu_1151_p2_i_10_n_3;
  wire p_Val2_19_fu_1151_p2_i_11_n_0;
  wire p_Val2_19_fu_1151_p2_i_11_n_1;
  wire p_Val2_19_fu_1151_p2_i_11_n_2;
  wire p_Val2_19_fu_1151_p2_i_11_n_3;
  wire p_Val2_19_fu_1151_p2_i_12_n_0;
  wire p_Val2_19_fu_1151_p2_i_13_n_0;
  wire p_Val2_19_fu_1151_p2_i_14_n_0;
  wire p_Val2_19_fu_1151_p2_i_15_n_0;
  wire p_Val2_19_fu_1151_p2_i_16_n_0;
  wire p_Val2_19_fu_1151_p2_i_17_n_0;
  wire p_Val2_19_fu_1151_p2_i_18_n_0;
  wire p_Val2_19_fu_1151_p2_i_19_n_0;
  wire p_Val2_19_fu_1151_p2_i_1_n_0;
  wire p_Val2_19_fu_1151_p2_i_20_n_0;
  wire p_Val2_19_fu_1151_p2_i_21_n_0;
  wire p_Val2_19_fu_1151_p2_i_22_n_0;
  wire p_Val2_19_fu_1151_p2_i_23_n_0;
  wire p_Val2_19_fu_1151_p2_i_24_n_0;
  wire p_Val2_19_fu_1151_p2_i_25_n_0;
  wire p_Val2_19_fu_1151_p2_i_26_n_0;
  wire p_Val2_19_fu_1151_p2_i_27_n_0;
  wire p_Val2_19_fu_1151_p2_i_28_n_0;
  wire p_Val2_19_fu_1151_p2_i_29_n_1;
  wire p_Val2_19_fu_1151_p2_i_29_n_2;
  wire p_Val2_19_fu_1151_p2_i_29_n_3;
  wire p_Val2_19_fu_1151_p2_i_30_n_0;
  wire p_Val2_19_fu_1151_p2_i_31_n_0;
  wire p_Val2_19_fu_1151_p2_i_32_n_0;
  wire p_Val2_19_fu_1151_p2_i_33_n_0;
  wire p_Val2_19_fu_1151_p2_i_34_n_0;
  wire p_Val2_19_fu_1151_p2_i_35_n_0;
  wire p_Val2_19_fu_1151_p2_i_36_n_0;
  wire p_Val2_19_fu_1151_p2_i_37_n_0;
  wire p_Val2_19_fu_1151_p2_i_38_n_0;
  wire p_Val2_19_fu_1151_p2_i_39_n_0;
  wire p_Val2_19_fu_1151_p2_i_40_n_0;
  wire p_Val2_19_fu_1151_p2_i_41_n_0;
  wire p_Val2_19_fu_1151_p2_i_42_n_0;
  wire p_Val2_19_fu_1151_p2_i_43_n_0;
  wire p_Val2_19_fu_1151_p2_i_44_n_0;
  wire p_Val2_19_fu_1151_p2_i_45_n_0;
  wire p_Val2_19_fu_1151_p2_i_5_n_0;
  wire p_Val2_19_fu_1151_p2_i_9_n_0;
  wire p_Val2_19_fu_1151_p2_i_9_n_1;
  wire p_Val2_19_fu_1151_p2_i_9_n_2;
  wire p_Val2_19_fu_1151_p2_i_9_n_3;
  wire p_Val2_19_fu_1151_p2_n_100;
  wire p_Val2_19_fu_1151_p2_n_101;
  wire p_Val2_19_fu_1151_p2_n_102;
  wire p_Val2_19_fu_1151_p2_n_103;
  wire p_Val2_19_fu_1151_p2_n_104;
  wire p_Val2_19_fu_1151_p2_n_105;
  wire p_Val2_19_fu_1151_p2_n_106;
  wire p_Val2_19_fu_1151_p2_n_107;
  wire p_Val2_19_fu_1151_p2_n_108;
  wire p_Val2_19_fu_1151_p2_n_109;
  wire p_Val2_19_fu_1151_p2_n_110;
  wire p_Val2_19_fu_1151_p2_n_111;
  wire p_Val2_19_fu_1151_p2_n_112;
  wire p_Val2_19_fu_1151_p2_n_113;
  wire p_Val2_19_fu_1151_p2_n_114;
  wire p_Val2_19_fu_1151_p2_n_115;
  wire p_Val2_19_fu_1151_p2_n_116;
  wire p_Val2_19_fu_1151_p2_n_117;
  wire p_Val2_19_fu_1151_p2_n_118;
  wire p_Val2_19_fu_1151_p2_n_119;
  wire p_Val2_19_fu_1151_p2_n_120;
  wire p_Val2_19_fu_1151_p2_n_121;
  wire p_Val2_19_fu_1151_p2_n_122;
  wire p_Val2_19_fu_1151_p2_n_123;
  wire p_Val2_19_fu_1151_p2_n_124;
  wire p_Val2_19_fu_1151_p2_n_125;
  wire p_Val2_19_fu_1151_p2_n_126;
  wire p_Val2_19_fu_1151_p2_n_127;
  wire p_Val2_19_fu_1151_p2_n_128;
  wire p_Val2_19_fu_1151_p2_n_129;
  wire p_Val2_19_fu_1151_p2_n_130;
  wire p_Val2_19_fu_1151_p2_n_131;
  wire p_Val2_19_fu_1151_p2_n_132;
  wire p_Val2_19_fu_1151_p2_n_133;
  wire p_Val2_19_fu_1151_p2_n_134;
  wire p_Val2_19_fu_1151_p2_n_135;
  wire p_Val2_19_fu_1151_p2_n_136;
  wire p_Val2_19_fu_1151_p2_n_137;
  wire p_Val2_19_fu_1151_p2_n_138;
  wire p_Val2_19_fu_1151_p2_n_139;
  wire p_Val2_19_fu_1151_p2_n_140;
  wire p_Val2_19_fu_1151_p2_n_141;
  wire p_Val2_19_fu_1151_p2_n_142;
  wire p_Val2_19_fu_1151_p2_n_143;
  wire p_Val2_19_fu_1151_p2_n_144;
  wire p_Val2_19_fu_1151_p2_n_145;
  wire p_Val2_19_fu_1151_p2_n_146;
  wire p_Val2_19_fu_1151_p2_n_147;
  wire p_Val2_19_fu_1151_p2_n_148;
  wire p_Val2_19_fu_1151_p2_n_149;
  wire p_Val2_19_fu_1151_p2_n_150;
  wire p_Val2_19_fu_1151_p2_n_151;
  wire p_Val2_19_fu_1151_p2_n_152;
  wire p_Val2_19_fu_1151_p2_n_153;
  wire p_Val2_19_fu_1151_p2_n_58;
  wire p_Val2_19_fu_1151_p2_n_59;
  wire p_Val2_19_fu_1151_p2_n_60;
  wire p_Val2_19_fu_1151_p2_n_61;
  wire p_Val2_19_fu_1151_p2_n_62;
  wire p_Val2_19_fu_1151_p2_n_63;
  wire p_Val2_19_fu_1151_p2_n_64;
  wire p_Val2_19_fu_1151_p2_n_65;
  wire p_Val2_19_fu_1151_p2_n_66;
  wire p_Val2_19_fu_1151_p2_n_67;
  wire p_Val2_19_fu_1151_p2_n_68;
  wire p_Val2_19_fu_1151_p2_n_69;
  wire p_Val2_19_fu_1151_p2_n_70;
  wire p_Val2_19_fu_1151_p2_n_71;
  wire p_Val2_19_fu_1151_p2_n_72;
  wire p_Val2_19_fu_1151_p2_n_73;
  wire p_Val2_19_fu_1151_p2_n_74;
  wire p_Val2_19_fu_1151_p2_n_75;
  wire p_Val2_19_fu_1151_p2_n_76;
  wire p_Val2_19_fu_1151_p2_n_77;
  wire p_Val2_19_fu_1151_p2_n_78;
  wire p_Val2_19_fu_1151_p2_n_79;
  wire p_Val2_19_fu_1151_p2_n_80;
  wire p_Val2_19_fu_1151_p2_n_81;
  wire p_Val2_19_fu_1151_p2_n_82;
  wire p_Val2_19_fu_1151_p2_n_83;
  wire p_Val2_19_fu_1151_p2_n_84;
  wire p_Val2_19_fu_1151_p2_n_85;
  wire p_Val2_19_fu_1151_p2_n_86;
  wire p_Val2_19_fu_1151_p2_n_87;
  wire p_Val2_19_fu_1151_p2_n_88;
  wire p_Val2_19_fu_1151_p2_n_89;
  wire p_Val2_19_fu_1151_p2_n_90;
  wire p_Val2_19_fu_1151_p2_n_91;
  wire p_Val2_19_fu_1151_p2_n_92;
  wire p_Val2_19_fu_1151_p2_n_93;
  wire p_Val2_19_fu_1151_p2_n_94;
  wire p_Val2_19_fu_1151_p2_n_95;
  wire p_Val2_19_fu_1151_p2_n_96;
  wire p_Val2_19_fu_1151_p2_n_97;
  wire p_Val2_19_fu_1151_p2_n_98;
  wire p_Val2_19_fu_1151_p2_n_99;
  wire [47:0]p_Val2_21_fu_1207_p2;
  wire [45:42]p_Val2_22_fu_1036_p4;
  wire [47:0]p_Val2_23_fu_1286_p21_out;
  wire p_Val2_26_fu_1377_p2_i_10_n_0;
  wire p_Val2_26_fu_1377_p2_i_11_n_0;
  wire p_Val2_26_fu_1377_p2_i_12_n_0;
  wire p_Val2_26_fu_1377_p2_i_13_n_0;
  wire p_Val2_26_fu_1377_p2_i_14_n_0;
  wire p_Val2_26_fu_1377_p2_i_15_n_0;
  wire p_Val2_26_fu_1377_p2_i_16_n_0;
  wire p_Val2_26_fu_1377_p2_i_17_n_0;
  wire p_Val2_26_fu_1377_p2_i_18_n_0;
  wire p_Val2_26_fu_1377_p2_i_19_n_0;
  wire p_Val2_26_fu_1377_p2_i_1_n_0;
  wire p_Val2_26_fu_1377_p2_i_1_n_1;
  wire p_Val2_26_fu_1377_p2_i_1_n_2;
  wire p_Val2_26_fu_1377_p2_i_1_n_3;
  wire p_Val2_26_fu_1377_p2_i_20_n_0;
  wire p_Val2_26_fu_1377_p2_i_21_n_0;
  wire p_Val2_26_fu_1377_p2_i_22_n_0;
  wire p_Val2_26_fu_1377_p2_i_23_n_0;
  wire p_Val2_26_fu_1377_p2_i_24_n_0;
  wire p_Val2_26_fu_1377_p2_i_25_n_0;
  wire p_Val2_26_fu_1377_p2_i_2_n_0;
  wire p_Val2_26_fu_1377_p2_i_2_n_1;
  wire p_Val2_26_fu_1377_p2_i_2_n_2;
  wire p_Val2_26_fu_1377_p2_i_2_n_3;
  wire p_Val2_26_fu_1377_p2_i_3_n_0;
  wire p_Val2_26_fu_1377_p2_i_3_n_1;
  wire p_Val2_26_fu_1377_p2_i_3_n_2;
  wire p_Val2_26_fu_1377_p2_i_3_n_3;
  wire p_Val2_26_fu_1377_p2_i_4_n_0;
  wire p_Val2_26_fu_1377_p2_i_4_n_1;
  wire p_Val2_26_fu_1377_p2_i_4_n_2;
  wire p_Val2_26_fu_1377_p2_i_4_n_3;
  wire p_Val2_26_fu_1377_p2_i_5_n_0;
  wire p_Val2_26_fu_1377_p2_i_5_n_1;
  wire p_Val2_26_fu_1377_p2_i_5_n_2;
  wire p_Val2_26_fu_1377_p2_i_5_n_3;
  wire p_Val2_26_fu_1377_p2_i_6_n_0;
  wire p_Val2_26_fu_1377_p2_i_7_n_0;
  wire p_Val2_26_fu_1377_p2_i_8_n_0;
  wire p_Val2_26_fu_1377_p2_i_9_n_0;
  wire p_Val2_26_fu_1377_p2_n_100;
  wire p_Val2_26_fu_1377_p2_n_101;
  wire p_Val2_26_fu_1377_p2_n_102;
  wire p_Val2_26_fu_1377_p2_n_103;
  wire p_Val2_26_fu_1377_p2_n_104;
  wire p_Val2_26_fu_1377_p2_n_105;
  wire p_Val2_26_fu_1377_p2_n_106;
  wire p_Val2_26_fu_1377_p2_n_107;
  wire p_Val2_26_fu_1377_p2_n_108;
  wire p_Val2_26_fu_1377_p2_n_109;
  wire p_Val2_26_fu_1377_p2_n_110;
  wire p_Val2_26_fu_1377_p2_n_111;
  wire p_Val2_26_fu_1377_p2_n_112;
  wire p_Val2_26_fu_1377_p2_n_113;
  wire p_Val2_26_fu_1377_p2_n_114;
  wire p_Val2_26_fu_1377_p2_n_115;
  wire p_Val2_26_fu_1377_p2_n_116;
  wire p_Val2_26_fu_1377_p2_n_117;
  wire p_Val2_26_fu_1377_p2_n_118;
  wire p_Val2_26_fu_1377_p2_n_119;
  wire p_Val2_26_fu_1377_p2_n_120;
  wire p_Val2_26_fu_1377_p2_n_121;
  wire p_Val2_26_fu_1377_p2_n_122;
  wire p_Val2_26_fu_1377_p2_n_123;
  wire p_Val2_26_fu_1377_p2_n_124;
  wire p_Val2_26_fu_1377_p2_n_125;
  wire p_Val2_26_fu_1377_p2_n_126;
  wire p_Val2_26_fu_1377_p2_n_127;
  wire p_Val2_26_fu_1377_p2_n_128;
  wire p_Val2_26_fu_1377_p2_n_129;
  wire p_Val2_26_fu_1377_p2_n_130;
  wire p_Val2_26_fu_1377_p2_n_131;
  wire p_Val2_26_fu_1377_p2_n_132;
  wire p_Val2_26_fu_1377_p2_n_133;
  wire p_Val2_26_fu_1377_p2_n_134;
  wire p_Val2_26_fu_1377_p2_n_135;
  wire p_Val2_26_fu_1377_p2_n_136;
  wire p_Val2_26_fu_1377_p2_n_137;
  wire p_Val2_26_fu_1377_p2_n_138;
  wire p_Val2_26_fu_1377_p2_n_139;
  wire p_Val2_26_fu_1377_p2_n_140;
  wire p_Val2_26_fu_1377_p2_n_141;
  wire p_Val2_26_fu_1377_p2_n_142;
  wire p_Val2_26_fu_1377_p2_n_143;
  wire p_Val2_26_fu_1377_p2_n_144;
  wire p_Val2_26_fu_1377_p2_n_145;
  wire p_Val2_26_fu_1377_p2_n_146;
  wire p_Val2_26_fu_1377_p2_n_147;
  wire p_Val2_26_fu_1377_p2_n_148;
  wire p_Val2_26_fu_1377_p2_n_149;
  wire p_Val2_26_fu_1377_p2_n_150;
  wire p_Val2_26_fu_1377_p2_n_151;
  wire p_Val2_26_fu_1377_p2_n_152;
  wire p_Val2_26_fu_1377_p2_n_153;
  wire p_Val2_26_fu_1377_p2_n_58;
  wire p_Val2_26_fu_1377_p2_n_59;
  wire p_Val2_26_fu_1377_p2_n_60;
  wire p_Val2_26_fu_1377_p2_n_61;
  wire p_Val2_26_fu_1377_p2_n_62;
  wire p_Val2_26_fu_1377_p2_n_63;
  wire p_Val2_26_fu_1377_p2_n_64;
  wire p_Val2_26_fu_1377_p2_n_65;
  wire p_Val2_26_fu_1377_p2_n_66;
  wire p_Val2_26_fu_1377_p2_n_67;
  wire p_Val2_26_fu_1377_p2_n_68;
  wire p_Val2_26_fu_1377_p2_n_69;
  wire p_Val2_26_fu_1377_p2_n_70;
  wire p_Val2_26_fu_1377_p2_n_71;
  wire p_Val2_26_fu_1377_p2_n_72;
  wire p_Val2_26_fu_1377_p2_n_73;
  wire p_Val2_26_fu_1377_p2_n_74;
  wire p_Val2_26_fu_1377_p2_n_75;
  wire p_Val2_26_fu_1377_p2_n_76;
  wire p_Val2_26_fu_1377_p2_n_77;
  wire p_Val2_26_fu_1377_p2_n_78;
  wire p_Val2_26_fu_1377_p2_n_79;
  wire p_Val2_26_fu_1377_p2_n_80;
  wire p_Val2_26_fu_1377_p2_n_81;
  wire p_Val2_26_fu_1377_p2_n_82;
  wire p_Val2_26_fu_1377_p2_n_83;
  wire p_Val2_26_fu_1377_p2_n_84;
  wire p_Val2_26_fu_1377_p2_n_85;
  wire p_Val2_26_fu_1377_p2_n_86;
  wire p_Val2_26_fu_1377_p2_n_87;
  wire p_Val2_26_fu_1377_p2_n_88;
  wire p_Val2_26_fu_1377_p2_n_89;
  wire p_Val2_26_fu_1377_p2_n_90;
  wire p_Val2_26_fu_1377_p2_n_91;
  wire p_Val2_26_fu_1377_p2_n_92;
  wire p_Val2_26_fu_1377_p2_n_93;
  wire p_Val2_26_fu_1377_p2_n_94;
  wire p_Val2_26_fu_1377_p2_n_95;
  wire p_Val2_26_fu_1377_p2_n_96;
  wire p_Val2_26_fu_1377_p2_n_97;
  wire p_Val2_26_fu_1377_p2_n_98;
  wire p_Val2_26_fu_1377_p2_n_99;
  wire p_Val2_26_reg_1683_reg__1_i_10_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_11_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_12_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_13_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_14_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_15_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_1_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_1_n_1;
  wire p_Val2_26_reg_1683_reg__1_i_1_n_2;
  wire p_Val2_26_reg_1683_reg__1_i_1_n_3;
  wire p_Val2_26_reg_1683_reg__1_i_2_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_2_n_1;
  wire p_Val2_26_reg_1683_reg__1_i_2_n_2;
  wire p_Val2_26_reg_1683_reg__1_i_2_n_3;
  wire p_Val2_26_reg_1683_reg__1_i_3_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_3_n_1;
  wire p_Val2_26_reg_1683_reg__1_i_3_n_2;
  wire p_Val2_26_reg_1683_reg__1_i_3_n_3;
  wire p_Val2_26_reg_1683_reg__1_i_4_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_5_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_6_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_7_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_8_n_0;
  wire p_Val2_26_reg_1683_reg__1_i_9_n_0;
  wire p_Val2_26_reg_1683_reg__1_n_100;
  wire p_Val2_26_reg_1683_reg__1_n_101;
  wire p_Val2_26_reg_1683_reg__1_n_102;
  wire p_Val2_26_reg_1683_reg__1_n_103;
  wire p_Val2_26_reg_1683_reg__1_n_104;
  wire p_Val2_26_reg_1683_reg__1_n_105;
  wire p_Val2_26_reg_1683_reg__1_n_58;
  wire p_Val2_26_reg_1683_reg__1_n_59;
  wire p_Val2_26_reg_1683_reg__1_n_60;
  wire p_Val2_26_reg_1683_reg__1_n_61;
  wire p_Val2_26_reg_1683_reg__1_n_62;
  wire p_Val2_26_reg_1683_reg__1_n_63;
  wire p_Val2_26_reg_1683_reg__1_n_64;
  wire p_Val2_26_reg_1683_reg__1_n_65;
  wire p_Val2_26_reg_1683_reg__1_n_66;
  wire p_Val2_26_reg_1683_reg__1_n_67;
  wire p_Val2_26_reg_1683_reg__1_n_68;
  wire p_Val2_26_reg_1683_reg__1_n_69;
  wire p_Val2_26_reg_1683_reg__1_n_70;
  wire p_Val2_26_reg_1683_reg__1_n_71;
  wire p_Val2_26_reg_1683_reg__1_n_72;
  wire p_Val2_26_reg_1683_reg__1_n_73;
  wire p_Val2_26_reg_1683_reg__1_n_74;
  wire p_Val2_26_reg_1683_reg__1_n_75;
  wire p_Val2_26_reg_1683_reg__1_n_76;
  wire p_Val2_26_reg_1683_reg__1_n_77;
  wire p_Val2_26_reg_1683_reg__1_n_78;
  wire p_Val2_26_reg_1683_reg__1_n_79;
  wire p_Val2_26_reg_1683_reg__1_n_80;
  wire p_Val2_26_reg_1683_reg__1_n_81;
  wire p_Val2_26_reg_1683_reg__1_n_82;
  wire p_Val2_26_reg_1683_reg__1_n_83;
  wire p_Val2_26_reg_1683_reg__1_n_84;
  wire p_Val2_26_reg_1683_reg__1_n_85;
  wire p_Val2_26_reg_1683_reg__1_n_86;
  wire p_Val2_26_reg_1683_reg__1_n_87;
  wire p_Val2_26_reg_1683_reg__1_n_88;
  wire p_Val2_26_reg_1683_reg__1_n_89;
  wire p_Val2_26_reg_1683_reg__1_n_90;
  wire p_Val2_26_reg_1683_reg__1_n_91;
  wire p_Val2_26_reg_1683_reg__1_n_92;
  wire p_Val2_26_reg_1683_reg__1_n_93;
  wire p_Val2_26_reg_1683_reg__1_n_94;
  wire p_Val2_26_reg_1683_reg__1_n_95;
  wire p_Val2_26_reg_1683_reg__1_n_96;
  wire p_Val2_26_reg_1683_reg__1_n_97;
  wire p_Val2_26_reg_1683_reg__1_n_98;
  wire p_Val2_26_reg_1683_reg__1_n_99;
  wire [47:33]p_Val2_26_reg_1683_reg__2;
  wire p_Val2_26_reg_1683_reg_i_10_n_0;
  wire p_Val2_26_reg_1683_reg_i_11_n_0;
  wire p_Val2_26_reg_1683_reg_i_12_n_0;
  wire p_Val2_26_reg_1683_reg_i_13_n_0;
  wire p_Val2_26_reg_1683_reg_i_14_n_0;
  wire p_Val2_26_reg_1683_reg_i_15_n_0;
  wire p_Val2_26_reg_1683_reg_i_16_n_0;
  wire p_Val2_26_reg_1683_reg_i_17_n_0;
  wire p_Val2_26_reg_1683_reg_i_18_n_0;
  wire p_Val2_26_reg_1683_reg_i_19_n_0;
  wire p_Val2_26_reg_1683_reg_i_1_n_1;
  wire p_Val2_26_reg_1683_reg_i_1_n_2;
  wire p_Val2_26_reg_1683_reg_i_1_n_3;
  wire p_Val2_26_reg_1683_reg_i_20_n_0;
  wire p_Val2_26_reg_1683_reg_i_2_n_0;
  wire p_Val2_26_reg_1683_reg_i_2_n_1;
  wire p_Val2_26_reg_1683_reg_i_2_n_2;
  wire p_Val2_26_reg_1683_reg_i_2_n_3;
  wire p_Val2_26_reg_1683_reg_i_3_n_0;
  wire p_Val2_26_reg_1683_reg_i_3_n_1;
  wire p_Val2_26_reg_1683_reg_i_3_n_2;
  wire p_Val2_26_reg_1683_reg_i_3_n_3;
  wire p_Val2_26_reg_1683_reg_i_4_n_0;
  wire p_Val2_26_reg_1683_reg_i_4_n_1;
  wire p_Val2_26_reg_1683_reg_i_4_n_2;
  wire p_Val2_26_reg_1683_reg_i_4_n_3;
  wire p_Val2_26_reg_1683_reg_i_5_n_0;
  wire p_Val2_26_reg_1683_reg_i_6_n_0;
  wire p_Val2_26_reg_1683_reg_i_7_n_0;
  wire p_Val2_26_reg_1683_reg_i_8_n_0;
  wire p_Val2_26_reg_1683_reg_i_9_n_0;
  wire \p_Val2_26_reg_1683_reg_n_0_[0] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[10] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[11] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[12] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[13] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[14] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[15] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[16] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[1] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[2] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[3] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[4] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[5] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[6] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[7] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[8] ;
  wire \p_Val2_26_reg_1683_reg_n_0_[9] ;
  wire p_Val2_26_reg_1683_reg_n_100;
  wire p_Val2_26_reg_1683_reg_n_101;
  wire p_Val2_26_reg_1683_reg_n_102;
  wire p_Val2_26_reg_1683_reg_n_103;
  wire p_Val2_26_reg_1683_reg_n_104;
  wire p_Val2_26_reg_1683_reg_n_105;
  wire p_Val2_26_reg_1683_reg_n_58;
  wire p_Val2_26_reg_1683_reg_n_59;
  wire p_Val2_26_reg_1683_reg_n_60;
  wire p_Val2_26_reg_1683_reg_n_61;
  wire p_Val2_26_reg_1683_reg_n_62;
  wire p_Val2_26_reg_1683_reg_n_63;
  wire p_Val2_26_reg_1683_reg_n_64;
  wire p_Val2_26_reg_1683_reg_n_65;
  wire p_Val2_26_reg_1683_reg_n_66;
  wire p_Val2_26_reg_1683_reg_n_67;
  wire p_Val2_26_reg_1683_reg_n_68;
  wire p_Val2_26_reg_1683_reg_n_69;
  wire p_Val2_26_reg_1683_reg_n_70;
  wire p_Val2_26_reg_1683_reg_n_71;
  wire p_Val2_26_reg_1683_reg_n_72;
  wire p_Val2_26_reg_1683_reg_n_73;
  wire p_Val2_26_reg_1683_reg_n_74;
  wire p_Val2_26_reg_1683_reg_n_75;
  wire p_Val2_26_reg_1683_reg_n_76;
  wire p_Val2_26_reg_1683_reg_n_77;
  wire p_Val2_26_reg_1683_reg_n_78;
  wire p_Val2_26_reg_1683_reg_n_79;
  wire p_Val2_26_reg_1683_reg_n_80;
  wire p_Val2_26_reg_1683_reg_n_81;
  wire p_Val2_26_reg_1683_reg_n_82;
  wire p_Val2_26_reg_1683_reg_n_83;
  wire p_Val2_26_reg_1683_reg_n_84;
  wire p_Val2_26_reg_1683_reg_n_85;
  wire p_Val2_26_reg_1683_reg_n_86;
  wire p_Val2_26_reg_1683_reg_n_87;
  wire p_Val2_26_reg_1683_reg_n_88;
  wire p_Val2_26_reg_1683_reg_n_89;
  wire p_Val2_26_reg_1683_reg_n_90;
  wire p_Val2_26_reg_1683_reg_n_91;
  wire p_Val2_26_reg_1683_reg_n_92;
  wire p_Val2_26_reg_1683_reg_n_93;
  wire p_Val2_26_reg_1683_reg_n_94;
  wire p_Val2_26_reg_1683_reg_n_95;
  wire p_Val2_26_reg_1683_reg_n_96;
  wire p_Val2_26_reg_1683_reg_n_97;
  wire p_Val2_26_reg_1683_reg_n_98;
  wire p_Val2_26_reg_1683_reg_n_99;
  wire [47:0]p_Val2_27_fu_1271_p2;
  wire [47:0]p_Val2_27_reg_1649;
  wire \p_Val2_27_reg_1649[11]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[11]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[11]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[11]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[15]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[15]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[15]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[15]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[19]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[19]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[19]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[19]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[23]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[23]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[23]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[23]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[27]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[27]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[27]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[27]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[31]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[31]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[31]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[31]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[35]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[35]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[35]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[35]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[39]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[39]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[39]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[39]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[3]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[3]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[3]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[3]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[43]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[43]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[43]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[43]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[47]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[47]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[47]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[47]_i_5_n_0 ;
  wire \p_Val2_27_reg_1649[7]_i_2_n_0 ;
  wire \p_Val2_27_reg_1649[7]_i_3_n_0 ;
  wire \p_Val2_27_reg_1649[7]_i_4_n_0 ;
  wire \p_Val2_27_reg_1649[7]_i_5_n_0 ;
  wire [47:0]p_Val2_27_reg_1649_pp0_iter6_reg;
  wire \p_Val2_27_reg_1649_reg[11]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[11]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[11]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[11]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[15]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[15]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[15]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[15]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[19]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[19]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[19]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[19]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[23]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[23]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[23]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[23]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[27]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[27]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[27]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[27]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[31]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[31]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[31]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[31]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[35]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[35]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[35]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[35]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[39]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[39]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[39]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[39]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[3]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[3]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[3]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[3]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[43]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[43]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[43]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[43]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[47]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[47]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[47]_i_1_n_3 ;
  wire \p_Val2_27_reg_1649_reg[7]_i_1_n_0 ;
  wire \p_Val2_27_reg_1649_reg[7]_i_1_n_1 ;
  wire \p_Val2_27_reg_1649_reg[7]_i_1_n_2 ;
  wire \p_Val2_27_reg_1649_reg[7]_i_1_n_3 ;
  wire [47:0]p_Val2_29_fu_1280_p2;
  wire p_Val2_30_fu_1372_p2_i_10_n_0;
  wire p_Val2_30_fu_1372_p2_i_11_n_0;
  wire p_Val2_30_fu_1372_p2_i_12_n_0;
  wire p_Val2_30_fu_1372_p2_i_13_n_0;
  wire p_Val2_30_fu_1372_p2_i_14_n_0;
  wire p_Val2_30_fu_1372_p2_i_15_n_0;
  wire p_Val2_30_fu_1372_p2_i_16_n_0;
  wire p_Val2_30_fu_1372_p2_i_17_n_0;
  wire p_Val2_30_fu_1372_p2_i_18_n_0;
  wire p_Val2_30_fu_1372_p2_i_19_n_0;
  wire p_Val2_30_fu_1372_p2_i_1_n_0;
  wire p_Val2_30_fu_1372_p2_i_1_n_1;
  wire p_Val2_30_fu_1372_p2_i_1_n_2;
  wire p_Val2_30_fu_1372_p2_i_1_n_3;
  wire p_Val2_30_fu_1372_p2_i_20_n_0;
  wire p_Val2_30_fu_1372_p2_i_21_n_0;
  wire p_Val2_30_fu_1372_p2_i_22_n_0;
  wire p_Val2_30_fu_1372_p2_i_23_n_0;
  wire p_Val2_30_fu_1372_p2_i_24_n_0;
  wire p_Val2_30_fu_1372_p2_i_25_n_0;
  wire p_Val2_30_fu_1372_p2_i_2_n_0;
  wire p_Val2_30_fu_1372_p2_i_2_n_1;
  wire p_Val2_30_fu_1372_p2_i_2_n_2;
  wire p_Val2_30_fu_1372_p2_i_2_n_3;
  wire p_Val2_30_fu_1372_p2_i_3_n_0;
  wire p_Val2_30_fu_1372_p2_i_3_n_1;
  wire p_Val2_30_fu_1372_p2_i_3_n_2;
  wire p_Val2_30_fu_1372_p2_i_3_n_3;
  wire p_Val2_30_fu_1372_p2_i_4_n_0;
  wire p_Val2_30_fu_1372_p2_i_4_n_1;
  wire p_Val2_30_fu_1372_p2_i_4_n_2;
  wire p_Val2_30_fu_1372_p2_i_4_n_3;
  wire p_Val2_30_fu_1372_p2_i_5_n_0;
  wire p_Val2_30_fu_1372_p2_i_5_n_1;
  wire p_Val2_30_fu_1372_p2_i_5_n_2;
  wire p_Val2_30_fu_1372_p2_i_5_n_3;
  wire p_Val2_30_fu_1372_p2_i_6_n_0;
  wire p_Val2_30_fu_1372_p2_i_7_n_0;
  wire p_Val2_30_fu_1372_p2_i_8_n_0;
  wire p_Val2_30_fu_1372_p2_i_9_n_0;
  wire p_Val2_30_fu_1372_p2_n_100;
  wire p_Val2_30_fu_1372_p2_n_101;
  wire p_Val2_30_fu_1372_p2_n_102;
  wire p_Val2_30_fu_1372_p2_n_103;
  wire p_Val2_30_fu_1372_p2_n_104;
  wire p_Val2_30_fu_1372_p2_n_105;
  wire p_Val2_30_fu_1372_p2_n_106;
  wire p_Val2_30_fu_1372_p2_n_107;
  wire p_Val2_30_fu_1372_p2_n_108;
  wire p_Val2_30_fu_1372_p2_n_109;
  wire p_Val2_30_fu_1372_p2_n_110;
  wire p_Val2_30_fu_1372_p2_n_111;
  wire p_Val2_30_fu_1372_p2_n_112;
  wire p_Val2_30_fu_1372_p2_n_113;
  wire p_Val2_30_fu_1372_p2_n_114;
  wire p_Val2_30_fu_1372_p2_n_115;
  wire p_Val2_30_fu_1372_p2_n_116;
  wire p_Val2_30_fu_1372_p2_n_117;
  wire p_Val2_30_fu_1372_p2_n_118;
  wire p_Val2_30_fu_1372_p2_n_119;
  wire p_Val2_30_fu_1372_p2_n_120;
  wire p_Val2_30_fu_1372_p2_n_121;
  wire p_Val2_30_fu_1372_p2_n_122;
  wire p_Val2_30_fu_1372_p2_n_123;
  wire p_Val2_30_fu_1372_p2_n_124;
  wire p_Val2_30_fu_1372_p2_n_125;
  wire p_Val2_30_fu_1372_p2_n_126;
  wire p_Val2_30_fu_1372_p2_n_127;
  wire p_Val2_30_fu_1372_p2_n_128;
  wire p_Val2_30_fu_1372_p2_n_129;
  wire p_Val2_30_fu_1372_p2_n_130;
  wire p_Val2_30_fu_1372_p2_n_131;
  wire p_Val2_30_fu_1372_p2_n_132;
  wire p_Val2_30_fu_1372_p2_n_133;
  wire p_Val2_30_fu_1372_p2_n_134;
  wire p_Val2_30_fu_1372_p2_n_135;
  wire p_Val2_30_fu_1372_p2_n_136;
  wire p_Val2_30_fu_1372_p2_n_137;
  wire p_Val2_30_fu_1372_p2_n_138;
  wire p_Val2_30_fu_1372_p2_n_139;
  wire p_Val2_30_fu_1372_p2_n_140;
  wire p_Val2_30_fu_1372_p2_n_141;
  wire p_Val2_30_fu_1372_p2_n_142;
  wire p_Val2_30_fu_1372_p2_n_143;
  wire p_Val2_30_fu_1372_p2_n_144;
  wire p_Val2_30_fu_1372_p2_n_145;
  wire p_Val2_30_fu_1372_p2_n_146;
  wire p_Val2_30_fu_1372_p2_n_147;
  wire p_Val2_30_fu_1372_p2_n_148;
  wire p_Val2_30_fu_1372_p2_n_149;
  wire p_Val2_30_fu_1372_p2_n_150;
  wire p_Val2_30_fu_1372_p2_n_151;
  wire p_Val2_30_fu_1372_p2_n_152;
  wire p_Val2_30_fu_1372_p2_n_153;
  wire p_Val2_30_fu_1372_p2_n_58;
  wire p_Val2_30_fu_1372_p2_n_59;
  wire p_Val2_30_fu_1372_p2_n_60;
  wire p_Val2_30_fu_1372_p2_n_61;
  wire p_Val2_30_fu_1372_p2_n_62;
  wire p_Val2_30_fu_1372_p2_n_63;
  wire p_Val2_30_fu_1372_p2_n_64;
  wire p_Val2_30_fu_1372_p2_n_65;
  wire p_Val2_30_fu_1372_p2_n_66;
  wire p_Val2_30_fu_1372_p2_n_67;
  wire p_Val2_30_fu_1372_p2_n_68;
  wire p_Val2_30_fu_1372_p2_n_69;
  wire p_Val2_30_fu_1372_p2_n_70;
  wire p_Val2_30_fu_1372_p2_n_71;
  wire p_Val2_30_fu_1372_p2_n_72;
  wire p_Val2_30_fu_1372_p2_n_73;
  wire p_Val2_30_fu_1372_p2_n_74;
  wire p_Val2_30_fu_1372_p2_n_75;
  wire p_Val2_30_fu_1372_p2_n_76;
  wire p_Val2_30_fu_1372_p2_n_77;
  wire p_Val2_30_fu_1372_p2_n_78;
  wire p_Val2_30_fu_1372_p2_n_79;
  wire p_Val2_30_fu_1372_p2_n_80;
  wire p_Val2_30_fu_1372_p2_n_81;
  wire p_Val2_30_fu_1372_p2_n_82;
  wire p_Val2_30_fu_1372_p2_n_83;
  wire p_Val2_30_fu_1372_p2_n_84;
  wire p_Val2_30_fu_1372_p2_n_85;
  wire p_Val2_30_fu_1372_p2_n_86;
  wire p_Val2_30_fu_1372_p2_n_87;
  wire p_Val2_30_fu_1372_p2_n_88;
  wire p_Val2_30_fu_1372_p2_n_89;
  wire p_Val2_30_fu_1372_p2_n_90;
  wire p_Val2_30_fu_1372_p2_n_91;
  wire p_Val2_30_fu_1372_p2_n_92;
  wire p_Val2_30_fu_1372_p2_n_93;
  wire p_Val2_30_fu_1372_p2_n_94;
  wire p_Val2_30_fu_1372_p2_n_95;
  wire p_Val2_30_fu_1372_p2_n_96;
  wire p_Val2_30_fu_1372_p2_n_97;
  wire p_Val2_30_fu_1372_p2_n_98;
  wire p_Val2_30_fu_1372_p2_n_99;
  wire p_Val2_30_reg_1678_reg__1_i_10_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_11_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_12_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_13_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_14_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_15_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_1_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_1_n_1;
  wire p_Val2_30_reg_1678_reg__1_i_1_n_2;
  wire p_Val2_30_reg_1678_reg__1_i_1_n_3;
  wire p_Val2_30_reg_1678_reg__1_i_2_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_2_n_1;
  wire p_Val2_30_reg_1678_reg__1_i_2_n_2;
  wire p_Val2_30_reg_1678_reg__1_i_2_n_3;
  wire p_Val2_30_reg_1678_reg__1_i_3_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_3_n_1;
  wire p_Val2_30_reg_1678_reg__1_i_3_n_2;
  wire p_Val2_30_reg_1678_reg__1_i_3_n_3;
  wire p_Val2_30_reg_1678_reg__1_i_4_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_5_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_6_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_7_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_8_n_0;
  wire p_Val2_30_reg_1678_reg__1_i_9_n_0;
  wire p_Val2_30_reg_1678_reg__1_n_100;
  wire p_Val2_30_reg_1678_reg__1_n_101;
  wire p_Val2_30_reg_1678_reg__1_n_102;
  wire p_Val2_30_reg_1678_reg__1_n_103;
  wire p_Val2_30_reg_1678_reg__1_n_104;
  wire p_Val2_30_reg_1678_reg__1_n_105;
  wire p_Val2_30_reg_1678_reg__1_n_58;
  wire p_Val2_30_reg_1678_reg__1_n_59;
  wire p_Val2_30_reg_1678_reg__1_n_60;
  wire p_Val2_30_reg_1678_reg__1_n_61;
  wire p_Val2_30_reg_1678_reg__1_n_62;
  wire p_Val2_30_reg_1678_reg__1_n_63;
  wire p_Val2_30_reg_1678_reg__1_n_64;
  wire p_Val2_30_reg_1678_reg__1_n_65;
  wire p_Val2_30_reg_1678_reg__1_n_66;
  wire p_Val2_30_reg_1678_reg__1_n_67;
  wire p_Val2_30_reg_1678_reg__1_n_68;
  wire p_Val2_30_reg_1678_reg__1_n_69;
  wire p_Val2_30_reg_1678_reg__1_n_70;
  wire p_Val2_30_reg_1678_reg__1_n_71;
  wire p_Val2_30_reg_1678_reg__1_n_72;
  wire p_Val2_30_reg_1678_reg__1_n_73;
  wire p_Val2_30_reg_1678_reg__1_n_74;
  wire p_Val2_30_reg_1678_reg__1_n_75;
  wire p_Val2_30_reg_1678_reg__1_n_76;
  wire p_Val2_30_reg_1678_reg__1_n_77;
  wire p_Val2_30_reg_1678_reg__1_n_78;
  wire p_Val2_30_reg_1678_reg__1_n_79;
  wire p_Val2_30_reg_1678_reg__1_n_80;
  wire p_Val2_30_reg_1678_reg__1_n_81;
  wire p_Val2_30_reg_1678_reg__1_n_82;
  wire p_Val2_30_reg_1678_reg__1_n_83;
  wire p_Val2_30_reg_1678_reg__1_n_84;
  wire p_Val2_30_reg_1678_reg__1_n_85;
  wire p_Val2_30_reg_1678_reg__1_n_86;
  wire p_Val2_30_reg_1678_reg__1_n_87;
  wire p_Val2_30_reg_1678_reg__1_n_88;
  wire p_Val2_30_reg_1678_reg__1_n_89;
  wire p_Val2_30_reg_1678_reg__1_n_90;
  wire p_Val2_30_reg_1678_reg__1_n_91;
  wire p_Val2_30_reg_1678_reg__1_n_92;
  wire p_Val2_30_reg_1678_reg__1_n_93;
  wire p_Val2_30_reg_1678_reg__1_n_94;
  wire p_Val2_30_reg_1678_reg__1_n_95;
  wire p_Val2_30_reg_1678_reg__1_n_96;
  wire p_Val2_30_reg_1678_reg__1_n_97;
  wire p_Val2_30_reg_1678_reg__1_n_98;
  wire p_Val2_30_reg_1678_reg__1_n_99;
  wire [47:33]p_Val2_30_reg_1678_reg__2;
  wire p_Val2_30_reg_1678_reg_i_10_n_0;
  wire p_Val2_30_reg_1678_reg_i_11_n_0;
  wire p_Val2_30_reg_1678_reg_i_12_n_0;
  wire p_Val2_30_reg_1678_reg_i_13_n_0;
  wire p_Val2_30_reg_1678_reg_i_14_n_0;
  wire p_Val2_30_reg_1678_reg_i_15_n_0;
  wire p_Val2_30_reg_1678_reg_i_16_n_0;
  wire p_Val2_30_reg_1678_reg_i_17_n_0;
  wire p_Val2_30_reg_1678_reg_i_18_n_0;
  wire p_Val2_30_reg_1678_reg_i_19_n_0;
  wire p_Val2_30_reg_1678_reg_i_1_n_1;
  wire p_Val2_30_reg_1678_reg_i_1_n_2;
  wire p_Val2_30_reg_1678_reg_i_1_n_3;
  wire p_Val2_30_reg_1678_reg_i_20_n_0;
  wire p_Val2_30_reg_1678_reg_i_2_n_0;
  wire p_Val2_30_reg_1678_reg_i_2_n_1;
  wire p_Val2_30_reg_1678_reg_i_2_n_2;
  wire p_Val2_30_reg_1678_reg_i_2_n_3;
  wire p_Val2_30_reg_1678_reg_i_3_n_0;
  wire p_Val2_30_reg_1678_reg_i_3_n_1;
  wire p_Val2_30_reg_1678_reg_i_3_n_2;
  wire p_Val2_30_reg_1678_reg_i_3_n_3;
  wire p_Val2_30_reg_1678_reg_i_4_n_0;
  wire p_Val2_30_reg_1678_reg_i_4_n_1;
  wire p_Val2_30_reg_1678_reg_i_4_n_2;
  wire p_Val2_30_reg_1678_reg_i_4_n_3;
  wire p_Val2_30_reg_1678_reg_i_5_n_0;
  wire p_Val2_30_reg_1678_reg_i_6_n_0;
  wire p_Val2_30_reg_1678_reg_i_7_n_0;
  wire p_Val2_30_reg_1678_reg_i_8_n_0;
  wire p_Val2_30_reg_1678_reg_i_9_n_0;
  wire \p_Val2_30_reg_1678_reg_n_0_[0] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[10] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[11] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[12] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[13] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[14] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[15] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[16] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[1] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[2] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[3] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[4] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[5] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[6] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[7] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[8] ;
  wire \p_Val2_30_reg_1678_reg_n_0_[9] ;
  wire p_Val2_30_reg_1678_reg_n_100;
  wire p_Val2_30_reg_1678_reg_n_101;
  wire p_Val2_30_reg_1678_reg_n_102;
  wire p_Val2_30_reg_1678_reg_n_103;
  wire p_Val2_30_reg_1678_reg_n_104;
  wire p_Val2_30_reg_1678_reg_n_105;
  wire p_Val2_30_reg_1678_reg_n_58;
  wire p_Val2_30_reg_1678_reg_n_59;
  wire p_Val2_30_reg_1678_reg_n_60;
  wire p_Val2_30_reg_1678_reg_n_61;
  wire p_Val2_30_reg_1678_reg_n_62;
  wire p_Val2_30_reg_1678_reg_n_63;
  wire p_Val2_30_reg_1678_reg_n_64;
  wire p_Val2_30_reg_1678_reg_n_65;
  wire p_Val2_30_reg_1678_reg_n_66;
  wire p_Val2_30_reg_1678_reg_n_67;
  wire p_Val2_30_reg_1678_reg_n_68;
  wire p_Val2_30_reg_1678_reg_n_69;
  wire p_Val2_30_reg_1678_reg_n_70;
  wire p_Val2_30_reg_1678_reg_n_71;
  wire p_Val2_30_reg_1678_reg_n_72;
  wire p_Val2_30_reg_1678_reg_n_73;
  wire p_Val2_30_reg_1678_reg_n_74;
  wire p_Val2_30_reg_1678_reg_n_75;
  wire p_Val2_30_reg_1678_reg_n_76;
  wire p_Val2_30_reg_1678_reg_n_77;
  wire p_Val2_30_reg_1678_reg_n_78;
  wire p_Val2_30_reg_1678_reg_n_79;
  wire p_Val2_30_reg_1678_reg_n_80;
  wire p_Val2_30_reg_1678_reg_n_81;
  wire p_Val2_30_reg_1678_reg_n_82;
  wire p_Val2_30_reg_1678_reg_n_83;
  wire p_Val2_30_reg_1678_reg_n_84;
  wire p_Val2_30_reg_1678_reg_n_85;
  wire p_Val2_30_reg_1678_reg_n_86;
  wire p_Val2_30_reg_1678_reg_n_87;
  wire p_Val2_30_reg_1678_reg_n_88;
  wire p_Val2_30_reg_1678_reg_n_89;
  wire p_Val2_30_reg_1678_reg_n_90;
  wire p_Val2_30_reg_1678_reg_n_91;
  wire p_Val2_30_reg_1678_reg_n_92;
  wire p_Val2_30_reg_1678_reg_n_93;
  wire p_Val2_30_reg_1678_reg_n_94;
  wire p_Val2_30_reg_1678_reg_n_95;
  wire p_Val2_30_reg_1678_reg_n_96;
  wire p_Val2_30_reg_1678_reg_n_97;
  wire p_Val2_30_reg_1678_reg_n_98;
  wire p_Val2_30_reg_1678_reg_n_99;
  wire [47:0]p_Val2_31_fu_1382_p23_out;
  wire [47:0]p_Val2_32_fu_1387_p22_out;
  wire [47:0]p_Val2_33_fu_1080_p3;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_Val2_33_reg_1631_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__0_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__10_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__11_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__12_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__13_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__14_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__15_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__16_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__17_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__18_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__19_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__1_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__20_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__21_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__22_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__23_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__24_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__25_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__26_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__27_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__28_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__29_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__2_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__30_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__31_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__32_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__33_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__34_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__35_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__36_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__37_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__38_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__39_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__3_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__40_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__41_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__42_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__43_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__44_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__45_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__46_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__4_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__5_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__6_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__7_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__8_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__9_n_0;
  wire p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate_n_0;
  wire [47:0]p_Val2_33_reg_1631_pp0_iter6_reg;
  wire [47:0]p_Val2_38_reg_1664;
  wire [47:0]p_Val2_38_reg_1664_pp0_iter6_reg;
  wire [47:0]p_Val2_39_reg_1669;
  wire [47:0]p_Val2_39_reg_1669_pp0_iter6_reg;
  wire \p_Val2_3_reg_440[0]_i_1_n_0 ;
  wire \p_Val2_3_reg_440[1]_i_1_n_0 ;
  wire \p_Val2_3_reg_440[2]_i_2_n_0 ;
  wire \p_Val2_3_reg_440_reg_n_0_[0] ;
  wire \p_Val2_3_reg_440_reg_n_0_[1] ;
  wire \p_Val2_3_reg_440_reg_n_0_[2] ;
  wire p_Val2_4_reg_1510;
  wire \p_Val2_4_reg_1510[0]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[10]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[11]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[12]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[13]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[14]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[15]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[16]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[17]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[18]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[19]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[1]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[20]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[21]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[22]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[23]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[24]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[25]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[26]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[27]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[28]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[29]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[2]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[30]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[31]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[32]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[33]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[34]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[35]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[36]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[37]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[38]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[39]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[3]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[40]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[41]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[42]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[43]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[44]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[45]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[46]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[47]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[4]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[5]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[6]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[7]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[8]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510[9]_i_1_n_0 ;
  wire \p_Val2_4_reg_1510_reg_n_0_[0] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[10] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[11] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[12] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[13] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[14] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[15] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[16] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[17] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[18] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[19] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[1] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[20] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[21] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[22] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[23] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[24] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[25] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[26] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[27] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[28] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[29] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[2] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[30] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[31] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[32] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[33] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[34] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[35] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[36] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[37] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[38] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[39] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[3] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[40] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[41] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[42] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[43] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[44] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[45] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[46] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[47] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[4] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[5] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[6] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[7] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[8] ;
  wire \p_Val2_4_reg_1510_reg_n_0_[9] ;
  wire [47:0]p_Val2_s_14_fu_1229_p2;
  wire [47:0]p_tmp_8_fu_693_p3;
  wire p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[0]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[10]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[11]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[12]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[13]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[14]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[15]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[16]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[17]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[18]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[19]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[1]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[20]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[21]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[22]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[23]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[24]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[25]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[26]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[27]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[28]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[29]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[2]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[30]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[31]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[32]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[33]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[34]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[35]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[36]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[37]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[38]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[39]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[3]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[40]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[41]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[42]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[43]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[44]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[45]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[46]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[47]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[4]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[5]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[6]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[7]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[8]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter4_reg_reg[9]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire \p_tmp_8_reg_1515_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__0_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__10_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__11_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__12_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__13_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__14_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__15_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__16_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__17_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__18_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__19_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__1_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__20_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__21_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__22_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__23_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__24_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__25_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__26_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__27_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__28_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__29_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__2_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__30_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__31_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__32_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__33_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__34_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__35_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__36_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__37_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__38_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__39_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__3_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__40_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__41_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__42_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__43_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__44_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__45_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__46_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__4_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__5_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__6_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__7_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__8_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__9_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate_n_0;
  wire p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0;
  wire [47:0]p_tmp_8_reg_1515_pp0_iter6_reg;
  wire p_tmp_8_reg_1515_reg_r_n_0;
  wire [47:0]phase_H1_prog_offset_fu_972_p2;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__0_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__10_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__11_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__12_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__13_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__14_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__15_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__16_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__17_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__18_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__19_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__1_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__20_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__21_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__22_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__23_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__24_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__25_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__26_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__27_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__28_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__29_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__2_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__30_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__31_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__32_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__33_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__34_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__35_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__36_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__37_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__38_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__39_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__3_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__40_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__41_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__42_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__43_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__44_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__45_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__46_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__4_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__5_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__6_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__7_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__8_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__9_n_0;
  wire phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate_n_0;
  wire [47:0]phase_H1_prog_offset_reg_1587_pp0_iter6_reg;
  wire [47:41]phase_H1_trunc_AM_on_fu_1004_p2;
  wire [47:0]phase_H1_trunc_AM_on_reg_1597;
  wire \phase_H1_trunc_AM_on_reg_1597[11]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[11]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[11]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[11]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[15]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[15]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[15]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[15]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[19]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[19]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[19]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[19]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[23]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[23]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[23]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[23]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[27]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[27]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[27]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[27]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[31]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[31]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[31]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[31]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[35]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[35]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[35]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[35]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[39]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[39]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[39]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[39]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[3]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[3]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[3]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[3]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[40]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[40]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[40]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[40]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[47]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[47]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[47]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[47]_i_6_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[7]_i_2_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[7]_i_3_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[7]_i_4_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597[7]_i_5_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2_n_3 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_0 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_1 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_2 ;
  wire \phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_3 ;
  wire [47:41]phase_H1_trunc_V_fu_988_p2;
  wire [40:0]r_V_6_fu_998_p2;
  wire [47:41]r_V_6_fu_998_p2__0;
  wire [48:0]r_V_fu_1058_p2;
  wire [48:0]r_V_reg_1610;
  wire \r_V_reg_1610[12]_i_2_n_0 ;
  wire \r_V_reg_1610[12]_i_3_n_0 ;
  wire \r_V_reg_1610[12]_i_4_n_0 ;
  wire \r_V_reg_1610[12]_i_5_n_0 ;
  wire \r_V_reg_1610[16]_i_2_n_0 ;
  wire \r_V_reg_1610[16]_i_3_n_0 ;
  wire \r_V_reg_1610[16]_i_4_n_0 ;
  wire \r_V_reg_1610[16]_i_5_n_0 ;
  wire \r_V_reg_1610[20]_i_2_n_0 ;
  wire \r_V_reg_1610[20]_i_3_n_0 ;
  wire \r_V_reg_1610[20]_i_4_n_0 ;
  wire \r_V_reg_1610[20]_i_5_n_0 ;
  wire \r_V_reg_1610[24]_i_2_n_0 ;
  wire \r_V_reg_1610[24]_i_3_n_0 ;
  wire \r_V_reg_1610[24]_i_4_n_0 ;
  wire \r_V_reg_1610[24]_i_5_n_0 ;
  wire \r_V_reg_1610[28]_i_2_n_0 ;
  wire \r_V_reg_1610[28]_i_3_n_0 ;
  wire \r_V_reg_1610[28]_i_4_n_0 ;
  wire \r_V_reg_1610[28]_i_5_n_0 ;
  wire \r_V_reg_1610[32]_i_2_n_0 ;
  wire \r_V_reg_1610[32]_i_3_n_0 ;
  wire \r_V_reg_1610[32]_i_4_n_0 ;
  wire \r_V_reg_1610[32]_i_5_n_0 ;
  wire \r_V_reg_1610[36]_i_2_n_0 ;
  wire \r_V_reg_1610[36]_i_3_n_0 ;
  wire \r_V_reg_1610[36]_i_4_n_0 ;
  wire \r_V_reg_1610[36]_i_5_n_0 ;
  wire \r_V_reg_1610[40]_i_2_n_0 ;
  wire \r_V_reg_1610[40]_i_3_n_0 ;
  wire \r_V_reg_1610[40]_i_4_n_0 ;
  wire \r_V_reg_1610[40]_i_5_n_0 ;
  wire \r_V_reg_1610[44]_i_3_n_0 ;
  wire \r_V_reg_1610[44]_i_4_n_0 ;
  wire \r_V_reg_1610[44]_i_5_n_0 ;
  wire \r_V_reg_1610[44]_i_6_n_0 ;
  wire \r_V_reg_1610[44]_i_7_n_0 ;
  wire \r_V_reg_1610[48]_i_3_n_0 ;
  wire \r_V_reg_1610[48]_i_4_n_0 ;
  wire \r_V_reg_1610[4]_i_2_n_0 ;
  wire \r_V_reg_1610[4]_i_3_n_0 ;
  wire \r_V_reg_1610[4]_i_4_n_0 ;
  wire \r_V_reg_1610[4]_i_5_n_0 ;
  wire \r_V_reg_1610[8]_i_2_n_0 ;
  wire \r_V_reg_1610[8]_i_3_n_0 ;
  wire \r_V_reg_1610[8]_i_4_n_0 ;
  wire \r_V_reg_1610[8]_i_5_n_0 ;
  wire \r_V_reg_1610_reg[12]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[12]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[12]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[12]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[16]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[16]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[16]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[16]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[20]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[20]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[20]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[20]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[24]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[24]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[24]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[24]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[28]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[28]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[28]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[28]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[32]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[32]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[32]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[32]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[36]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[36]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[36]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[36]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[40]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[40]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[40]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[40]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[44]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[44]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[44]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[44]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[48]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[48]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[48]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[4]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[4]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[4]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[4]_i_1_n_3 ;
  wire \r_V_reg_1610_reg[8]_i_1_n_0 ;
  wire \r_V_reg_1610_reg[8]_i_1_n_1 ;
  wire \r_V_reg_1610_reg[8]_i_1_n_2 ;
  wire \r_V_reg_1610_reg[8]_i_1_n_3 ;
  wire [5:0]sel0;
  wire sel_tmp2_fu_731_p2;
  wire sel_tmp2_reg_1535;
  wire sel_tmp2_reg_1535_pp0_iter3_reg;
  wire sel_tmp3_fu_938_p2;
  wire sel_tmp3_reg_1566;
  wire \sel_tmp3_reg_1566[0]_i_10_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_11_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_12_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_13_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_14_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_2_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_3_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_4_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_5_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_6_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_7_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_8_n_0 ;
  wire \sel_tmp3_reg_1566[0]_i_9_n_0 ;
  wire sel_tmp_reg_1527;
  wire storemerge_fu_1180_p2;
  wire storemerge_reg_1641;
  wire \storemerge_reg_1641[0]_i_10_n_0 ;
  wire \storemerge_reg_1641[0]_i_11_n_0 ;
  wire \storemerge_reg_1641[0]_i_12_n_0 ;
  wire \storemerge_reg_1641[0]_i_13_n_0 ;
  wire \storemerge_reg_1641[0]_i_15_n_0 ;
  wire \storemerge_reg_1641[0]_i_16_n_0 ;
  wire \storemerge_reg_1641[0]_i_17_n_0 ;
  wire \storemerge_reg_1641[0]_i_18_n_0 ;
  wire \storemerge_reg_1641[0]_i_19_n_0 ;
  wire \storemerge_reg_1641[0]_i_20_n_0 ;
  wire \storemerge_reg_1641[0]_i_21_n_0 ;
  wire \storemerge_reg_1641[0]_i_22_n_0 ;
  wire \storemerge_reg_1641[0]_i_24_n_0 ;
  wire \storemerge_reg_1641[0]_i_25_n_0 ;
  wire \storemerge_reg_1641[0]_i_26_n_0 ;
  wire \storemerge_reg_1641[0]_i_27_n_0 ;
  wire \storemerge_reg_1641[0]_i_28_n_0 ;
  wire \storemerge_reg_1641[0]_i_29_n_0 ;
  wire \storemerge_reg_1641[0]_i_30_n_0 ;
  wire \storemerge_reg_1641[0]_i_31_n_0 ;
  wire \storemerge_reg_1641[0]_i_33_n_0 ;
  wire \storemerge_reg_1641[0]_i_34_n_0 ;
  wire \storemerge_reg_1641[0]_i_35_n_0 ;
  wire \storemerge_reg_1641[0]_i_36_n_0 ;
  wire \storemerge_reg_1641[0]_i_37_n_0 ;
  wire \storemerge_reg_1641[0]_i_38_n_0 ;
  wire \storemerge_reg_1641[0]_i_39_n_0 ;
  wire \storemerge_reg_1641[0]_i_40_n_0 ;
  wire \storemerge_reg_1641[0]_i_42_n_0 ;
  wire \storemerge_reg_1641[0]_i_43_n_0 ;
  wire \storemerge_reg_1641[0]_i_44_n_0 ;
  wire \storemerge_reg_1641[0]_i_45_n_0 ;
  wire \storemerge_reg_1641[0]_i_46_n_0 ;
  wire \storemerge_reg_1641[0]_i_47_n_0 ;
  wire \storemerge_reg_1641[0]_i_48_n_0 ;
  wire \storemerge_reg_1641[0]_i_49_n_0 ;
  wire \storemerge_reg_1641[0]_i_4_n_0 ;
  wire \storemerge_reg_1641[0]_i_50_n_0 ;
  wire \storemerge_reg_1641[0]_i_51_n_0 ;
  wire \storemerge_reg_1641[0]_i_52_n_0 ;
  wire \storemerge_reg_1641[0]_i_53_n_0 ;
  wire \storemerge_reg_1641[0]_i_54_n_0 ;
  wire \storemerge_reg_1641[0]_i_55_n_0 ;
  wire \storemerge_reg_1641[0]_i_56_n_0 ;
  wire \storemerge_reg_1641[0]_i_57_n_0 ;
  wire \storemerge_reg_1641[0]_i_6_n_0 ;
  wire \storemerge_reg_1641[0]_i_7_n_0 ;
  wire \storemerge_reg_1641[0]_i_8_n_0 ;
  wire \storemerge_reg_1641[0]_i_9_n_0 ;
  wire storemerge_reg_1641_pp0_iter5_reg;
  wire storemerge_reg_1641_pp0_iter6_reg;
  wire \storemerge_reg_1641_reg[0]_i_14_n_0 ;
  wire \storemerge_reg_1641_reg[0]_i_14_n_1 ;
  wire \storemerge_reg_1641_reg[0]_i_14_n_2 ;
  wire \storemerge_reg_1641_reg[0]_i_14_n_3 ;
  wire \storemerge_reg_1641_reg[0]_i_23_n_0 ;
  wire \storemerge_reg_1641_reg[0]_i_23_n_1 ;
  wire \storemerge_reg_1641_reg[0]_i_23_n_2 ;
  wire \storemerge_reg_1641_reg[0]_i_23_n_3 ;
  wire \storemerge_reg_1641_reg[0]_i_32_n_0 ;
  wire \storemerge_reg_1641_reg[0]_i_32_n_1 ;
  wire \storemerge_reg_1641_reg[0]_i_32_n_2 ;
  wire \storemerge_reg_1641_reg[0]_i_32_n_3 ;
  wire \storemerge_reg_1641_reg[0]_i_3_n_0 ;
  wire \storemerge_reg_1641_reg[0]_i_3_n_1 ;
  wire \storemerge_reg_1641_reg[0]_i_3_n_2 ;
  wire \storemerge_reg_1641_reg[0]_i_3_n_3 ;
  wire \storemerge_reg_1641_reg[0]_i_41_n_0 ;
  wire \storemerge_reg_1641_reg[0]_i_41_n_1 ;
  wire \storemerge_reg_1641_reg[0]_i_41_n_2 ;
  wire \storemerge_reg_1641_reg[0]_i_41_n_3 ;
  wire \storemerge_reg_1641_reg[0]_i_5_n_0 ;
  wire \storemerge_reg_1641_reg[0]_i_5_n_1 ;
  wire \storemerge_reg_1641_reg[0]_i_5_n_2 ;
  wire \storemerge_reg_1641_reg[0]_i_5_n_3 ;
  wire tmp_12_fu_1030_p2;
  wire tmp_12_reg_1606;
  wire \tmp_12_reg_1606[0]_i_10_n_0 ;
  wire \tmp_12_reg_1606[0]_i_11_n_0 ;
  wire \tmp_12_reg_1606[0]_i_13_n_0 ;
  wire \tmp_12_reg_1606[0]_i_14_n_0 ;
  wire \tmp_12_reg_1606[0]_i_15_n_0 ;
  wire \tmp_12_reg_1606[0]_i_16_n_0 ;
  wire \tmp_12_reg_1606[0]_i_17_n_0 ;
  wire \tmp_12_reg_1606[0]_i_18_n_0 ;
  wire \tmp_12_reg_1606[0]_i_19_n_0 ;
  wire \tmp_12_reg_1606[0]_i_1_n_0 ;
  wire \tmp_12_reg_1606[0]_i_20_n_0 ;
  wire \tmp_12_reg_1606[0]_i_22_n_0 ;
  wire \tmp_12_reg_1606[0]_i_23_n_0 ;
  wire \tmp_12_reg_1606[0]_i_24_n_0 ;
  wire \tmp_12_reg_1606[0]_i_25_n_0 ;
  wire \tmp_12_reg_1606[0]_i_26_n_0 ;
  wire \tmp_12_reg_1606[0]_i_27_n_0 ;
  wire \tmp_12_reg_1606[0]_i_28_n_0 ;
  wire \tmp_12_reg_1606[0]_i_29_n_0 ;
  wire \tmp_12_reg_1606[0]_i_31_n_0 ;
  wire \tmp_12_reg_1606[0]_i_32_n_0 ;
  wire \tmp_12_reg_1606[0]_i_33_n_0 ;
  wire \tmp_12_reg_1606[0]_i_34_n_0 ;
  wire \tmp_12_reg_1606[0]_i_35_n_0 ;
  wire \tmp_12_reg_1606[0]_i_36_n_0 ;
  wire \tmp_12_reg_1606[0]_i_37_n_0 ;
  wire \tmp_12_reg_1606[0]_i_38_n_0 ;
  wire \tmp_12_reg_1606[0]_i_40_n_0 ;
  wire \tmp_12_reg_1606[0]_i_41_n_0 ;
  wire \tmp_12_reg_1606[0]_i_42_n_0 ;
  wire \tmp_12_reg_1606[0]_i_43_n_0 ;
  wire \tmp_12_reg_1606[0]_i_44_n_0 ;
  wire \tmp_12_reg_1606[0]_i_45_n_0 ;
  wire \tmp_12_reg_1606[0]_i_46_n_0 ;
  wire \tmp_12_reg_1606[0]_i_47_n_0 ;
  wire \tmp_12_reg_1606[0]_i_48_n_0 ;
  wire \tmp_12_reg_1606[0]_i_49_n_0 ;
  wire \tmp_12_reg_1606[0]_i_4_n_0 ;
  wire \tmp_12_reg_1606[0]_i_50_n_0 ;
  wire \tmp_12_reg_1606[0]_i_51_n_0 ;
  wire \tmp_12_reg_1606[0]_i_52_n_0 ;
  wire \tmp_12_reg_1606[0]_i_53_n_0 ;
  wire \tmp_12_reg_1606[0]_i_54_n_0 ;
  wire \tmp_12_reg_1606[0]_i_55_n_0 ;
  wire \tmp_12_reg_1606[0]_i_5_n_0 ;
  wire \tmp_12_reg_1606[0]_i_6_n_0 ;
  wire \tmp_12_reg_1606[0]_i_7_n_0 ;
  wire \tmp_12_reg_1606[0]_i_8_n_0 ;
  wire \tmp_12_reg_1606[0]_i_9_n_0 ;
  wire tmp_12_reg_1606_pp0_iter4_reg;
  wire \tmp_12_reg_1606_reg[0]_i_12_n_0 ;
  wire \tmp_12_reg_1606_reg[0]_i_12_n_1 ;
  wire \tmp_12_reg_1606_reg[0]_i_12_n_2 ;
  wire \tmp_12_reg_1606_reg[0]_i_12_n_3 ;
  wire \tmp_12_reg_1606_reg[0]_i_21_n_0 ;
  wire \tmp_12_reg_1606_reg[0]_i_21_n_1 ;
  wire \tmp_12_reg_1606_reg[0]_i_21_n_2 ;
  wire \tmp_12_reg_1606_reg[0]_i_21_n_3 ;
  wire \tmp_12_reg_1606_reg[0]_i_2_n_1 ;
  wire \tmp_12_reg_1606_reg[0]_i_2_n_2 ;
  wire \tmp_12_reg_1606_reg[0]_i_2_n_3 ;
  wire \tmp_12_reg_1606_reg[0]_i_30_n_0 ;
  wire \tmp_12_reg_1606_reg[0]_i_30_n_1 ;
  wire \tmp_12_reg_1606_reg[0]_i_30_n_2 ;
  wire \tmp_12_reg_1606_reg[0]_i_30_n_3 ;
  wire \tmp_12_reg_1606_reg[0]_i_39_n_0 ;
  wire \tmp_12_reg_1606_reg[0]_i_39_n_1 ;
  wire \tmp_12_reg_1606_reg[0]_i_39_n_2 ;
  wire \tmp_12_reg_1606_reg[0]_i_39_n_3 ;
  wire \tmp_12_reg_1606_reg[0]_i_3_n_0 ;
  wire \tmp_12_reg_1606_reg[0]_i_3_n_1 ;
  wire \tmp_12_reg_1606_reg[0]_i_3_n_2 ;
  wire \tmp_12_reg_1606_reg[0]_i_3_n_3 ;
  wire tmp_15_fu_1198_p2;
  wire tmp_18_fu_1170_p2;
  wire tmp_19_fu_1068_p2;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_1 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_2 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_3 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_1 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_2 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_3 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_1 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_2 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_3 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_1 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_2 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_3 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_1 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_2 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_3 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \tmp_19_reg_1621_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire tmp_19_reg_1621_pp0_iter5_reg_reg_gate_n_0;
  wire tmp_19_reg_1621_pp0_iter6_reg;
  wire tmp_20_fu_1074_p2;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_1 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_2 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_3 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_1 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_2 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_3 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_1 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_2 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_3 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_1 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_2 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_3 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_1 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_2 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_3 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ;
  wire \tmp_20_reg_1626_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ;
  wire tmp_20_reg_1626_pp0_iter5_reg_reg_gate_n_0;
  wire tmp_20_reg_1626_pp0_iter6_reg;
  wire tmp_22_reg_1544;
  wire tmp_22_reg_1544_pp0_iter3_reg;
  wire tmp_22_reg_1544_pp0_iter4_reg;
  wire tmp_3_fu_1010_p2;
  wire tmp_3_reg_1602;
  wire \tmp_3_reg_1602[0]_i_10_n_0 ;
  wire \tmp_3_reg_1602[0]_i_12_n_0 ;
  wire \tmp_3_reg_1602[0]_i_13_n_0 ;
  wire \tmp_3_reg_1602[0]_i_14_n_0 ;
  wire \tmp_3_reg_1602[0]_i_15_n_0 ;
  wire \tmp_3_reg_1602[0]_i_16_n_0 ;
  wire \tmp_3_reg_1602[0]_i_17_n_0 ;
  wire \tmp_3_reg_1602[0]_i_18_n_0 ;
  wire \tmp_3_reg_1602[0]_i_19_n_0 ;
  wire \tmp_3_reg_1602[0]_i_20_n_0 ;
  wire \tmp_3_reg_1602[0]_i_21_n_0 ;
  wire \tmp_3_reg_1602[0]_i_22_n_0 ;
  wire \tmp_3_reg_1602[0]_i_25_n_0 ;
  wire \tmp_3_reg_1602[0]_i_26_n_0 ;
  wire \tmp_3_reg_1602[0]_i_28_n_0 ;
  wire \tmp_3_reg_1602[0]_i_29_n_0 ;
  wire \tmp_3_reg_1602[0]_i_30_n_0 ;
  wire \tmp_3_reg_1602[0]_i_31_n_0 ;
  wire \tmp_3_reg_1602[0]_i_32_n_0 ;
  wire \tmp_3_reg_1602[0]_i_33_n_0 ;
  wire \tmp_3_reg_1602[0]_i_34_n_0 ;
  wire \tmp_3_reg_1602[0]_i_35_n_0 ;
  wire \tmp_3_reg_1602[0]_i_37_n_0 ;
  wire \tmp_3_reg_1602[0]_i_38_n_0 ;
  wire \tmp_3_reg_1602[0]_i_39_n_0 ;
  wire \tmp_3_reg_1602[0]_i_3_n_0 ;
  wire \tmp_3_reg_1602[0]_i_40_n_0 ;
  wire \tmp_3_reg_1602[0]_i_41_n_0 ;
  wire \tmp_3_reg_1602[0]_i_42_n_0 ;
  wire \tmp_3_reg_1602[0]_i_43_n_0 ;
  wire \tmp_3_reg_1602[0]_i_44_n_0 ;
  wire \tmp_3_reg_1602[0]_i_46_n_0 ;
  wire \tmp_3_reg_1602[0]_i_47_n_0 ;
  wire \tmp_3_reg_1602[0]_i_48_n_0 ;
  wire \tmp_3_reg_1602[0]_i_49_n_0 ;
  wire \tmp_3_reg_1602[0]_i_4_n_0 ;
  wire \tmp_3_reg_1602[0]_i_50_n_0 ;
  wire \tmp_3_reg_1602[0]_i_51_n_0 ;
  wire \tmp_3_reg_1602[0]_i_52_n_0 ;
  wire \tmp_3_reg_1602[0]_i_53_n_0 ;
  wire \tmp_3_reg_1602[0]_i_54_n_0 ;
  wire \tmp_3_reg_1602[0]_i_55_n_0 ;
  wire \tmp_3_reg_1602[0]_i_56_n_0 ;
  wire \tmp_3_reg_1602[0]_i_57_n_0 ;
  wire \tmp_3_reg_1602[0]_i_58_n_0 ;
  wire \tmp_3_reg_1602[0]_i_59_n_0 ;
  wire \tmp_3_reg_1602[0]_i_5_n_0 ;
  wire \tmp_3_reg_1602[0]_i_60_n_0 ;
  wire \tmp_3_reg_1602[0]_i_61_n_0 ;
  wire \tmp_3_reg_1602[0]_i_6_n_0 ;
  wire \tmp_3_reg_1602[0]_i_7_n_0 ;
  wire \tmp_3_reg_1602[0]_i_8_n_0 ;
  wire \tmp_3_reg_1602[0]_i_9_n_0 ;
  wire tmp_3_reg_1602_pp0_iter4_reg;
  wire \tmp_3_reg_1602_reg[0]_i_11_n_0 ;
  wire \tmp_3_reg_1602_reg[0]_i_11_n_1 ;
  wire \tmp_3_reg_1602_reg[0]_i_11_n_2 ;
  wire \tmp_3_reg_1602_reg[0]_i_11_n_3 ;
  wire \tmp_3_reg_1602_reg[0]_i_1_n_1 ;
  wire \tmp_3_reg_1602_reg[0]_i_1_n_2 ;
  wire \tmp_3_reg_1602_reg[0]_i_1_n_3 ;
  wire \tmp_3_reg_1602_reg[0]_i_27_n_0 ;
  wire \tmp_3_reg_1602_reg[0]_i_27_n_1 ;
  wire \tmp_3_reg_1602_reg[0]_i_27_n_2 ;
  wire \tmp_3_reg_1602_reg[0]_i_27_n_3 ;
  wire \tmp_3_reg_1602_reg[0]_i_2_n_0 ;
  wire \tmp_3_reg_1602_reg[0]_i_2_n_1 ;
  wire \tmp_3_reg_1602_reg[0]_i_2_n_2 ;
  wire \tmp_3_reg_1602_reg[0]_i_2_n_3 ;
  wire \tmp_3_reg_1602_reg[0]_i_36_n_0 ;
  wire \tmp_3_reg_1602_reg[0]_i_36_n_1 ;
  wire \tmp_3_reg_1602_reg[0]_i_36_n_2 ;
  wire \tmp_3_reg_1602_reg[0]_i_36_n_3 ;
  wire \tmp_3_reg_1602_reg[0]_i_45_n_0 ;
  wire \tmp_3_reg_1602_reg[0]_i_45_n_1 ;
  wire \tmp_3_reg_1602_reg[0]_i_45_n_2 ;
  wire \tmp_3_reg_1602_reg[0]_i_45_n_3 ;
  wire tmp_6_reg_16360;
  wire [47:0]tmp_8_fu_673_p3;
  wire [3:0]\NLW_acc_H1_FSK_V_reg[1]_i_3_O_UNCONNECTED ;

  assign outputs_AM_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_AM_auto_on_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_coef_muxed_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_frev_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_frev_main_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_ftw_H1_muxed_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_phase_H1_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_phase_H1_main_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_phase_H1_offset_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_phase_H1_prog_offset_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_phase_H1_slip_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_phase_IF_0_V_ap_vld = outputs_phase_IF_1_V_ap_vld;
  assign outputs_valid_ap_vld = outputs_phase_IF_1_V_ap_vld;
  (* srl_bus_name = "U0/\AM_auto_on_3_reg_1571_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\AM_auto_on_3_reg_1571_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \AM_auto_on_3_reg_1571_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_0_in55_out),
        .Q(\AM_auto_on_3_reg_1571_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAA8A)) 
    \AM_auto_on_3_reg_1571_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(sel_tmp_reg_1527),
        .I1(\sel_tmp3_reg_1566[0]_i_6_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_5_n_0 ),
        .I3(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_3_n_0 ),
        .I5(\sel_tmp3_reg_1566[0]_i_2_n_0 ),
        .O(p_0_in55_out));
  FDRE #(
    .INIT(1'b0)) 
    \AM_auto_on_3_reg_1571_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\AM_auto_on_3_reg_1571_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\AM_auto_on_3_reg_1571_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  LUT2 #(
    .INIT(4'h8)) 
    AM_auto_on_3_reg_1571_pp0_iter5_reg_reg_gate
       (.I0(\AM_auto_on_3_reg_1571_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(AM_auto_on_3_reg_1571_pp0_iter5_reg_reg_gate_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \AM_auto_on_3_reg_1571_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(AM_auto_on_3_reg_1571_pp0_iter5_reg_reg_gate_n_0),
        .Q(AM_auto_on_3_reg_1571_pp0_iter6_reg),
        .R(ap_rst));
  GND GND
       (.G(\<const0> ));
  GND GND_1
       (.G(GND_2));
  VCC VCC
       (.P(\<const1> ));
  VCC VCC_1
       (.P(VCC_2));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[0]_i_1 
       (.I0(\acc_H1_FSK_V[0]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[0]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[0]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[0]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[0]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[0]),
        .I5(p_0_out__4[38]),
        .O(\acc_H1_FSK_V[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[10]_i_1 
       (.I0(\acc_H1_FSK_V[10]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[10]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[10]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[10]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[10]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[10]),
        .I5(p_0_out__4[48]),
        .O(\acc_H1_FSK_V[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[11]_i_1 
       (.I0(\acc_H1_FSK_V[11]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[11]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[11]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[11]_i_10 
       (.I0(acc_H1_FSK_V[10]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[10]),
        .O(\acc_H1_FSK_V[11]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[11]_i_11 
       (.I0(acc_H1_FSK_V[9]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[9]),
        .O(\acc_H1_FSK_V[11]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[11]_i_12 
       (.I0(acc_H1_FSK_V[8]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[8]),
        .O(\acc_H1_FSK_V[11]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[11]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[11]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[11]),
        .I5(p_0_out__4[49]),
        .O(\acc_H1_FSK_V[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[11]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[11]),
        .I1(acc_H1_FSK_V[11]),
        .O(\acc_H1_FSK_V[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[11]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[10]),
        .I1(acc_H1_FSK_V[10]),
        .O(\acc_H1_FSK_V[11]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[11]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[9]),
        .I1(acc_H1_FSK_V[9]),
        .O(\acc_H1_FSK_V[11]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[11]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[8]),
        .I1(acc_H1_FSK_V[8]),
        .O(\acc_H1_FSK_V[11]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[11]_i_9 
       (.I0(acc_H1_FSK_V[11]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[11]),
        .O(\acc_H1_FSK_V[11]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[12]_i_1 
       (.I0(\acc_H1_FSK_V[12]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[12]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[12]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[12]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[12]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[12]),
        .I5(p_0_out__4[50]),
        .O(\acc_H1_FSK_V[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[13]_i_1 
       (.I0(\acc_H1_FSK_V[13]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[13]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[13]));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[13]_i_10 
       (.I0(p_0_out__2_n_90),
        .I1(p_0_out__3_n_73),
        .I2(\p_0_out_n_0_[15] ),
        .I3(\acc_H1_FSK_V[13]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[13]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[13]_i_11 
       (.I0(p_0_out__2_n_91),
        .I1(p_0_out__3_n_74),
        .I2(\p_0_out_n_0_[14] ),
        .I3(\acc_H1_FSK_V[13]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[13]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[13]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[13]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[13]),
        .I5(p_0_out__4[51]),
        .O(\acc_H1_FSK_V[13]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[13]_i_4 
       (.I0(p_0_out__2_n_89),
        .I1(p_0_out__3_n_72),
        .I2(\p_0_out_n_0_[16] ),
        .O(\acc_H1_FSK_V[13]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[13]_i_5 
       (.I0(p_0_out__2_n_90),
        .I1(p_0_out__3_n_73),
        .I2(\p_0_out_n_0_[15] ),
        .O(\acc_H1_FSK_V[13]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[13]_i_6 
       (.I0(p_0_out__2_n_91),
        .I1(p_0_out__3_n_74),
        .I2(\p_0_out_n_0_[14] ),
        .O(\acc_H1_FSK_V[13]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[13]_i_7 
       (.I0(p_0_out__2_n_92),
        .I1(p_0_out__3_n_75),
        .I2(\p_0_out_n_0_[13] ),
        .O(\acc_H1_FSK_V[13]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[13]_i_8 
       (.I0(p_0_out__2_n_88),
        .I1(p_0_out__3_n_71),
        .I2(p_0_out__0_n_105),
        .I3(\acc_H1_FSK_V[13]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[13]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[13]_i_9 
       (.I0(p_0_out__2_n_89),
        .I1(p_0_out__3_n_72),
        .I2(\p_0_out_n_0_[16] ),
        .I3(\acc_H1_FSK_V[13]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[13]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[14]_i_1 
       (.I0(\acc_H1_FSK_V[14]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[14]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[14]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[14]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[14]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[14]),
        .I5(p_0_out__4[52]),
        .O(\acc_H1_FSK_V[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[15]_i_1 
       (.I0(\acc_H1_FSK_V[15]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[15]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[15]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[15]_i_10 
       (.I0(acc_H1_FSK_V[14]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[14]),
        .O(\acc_H1_FSK_V[15]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[15]_i_11 
       (.I0(acc_H1_FSK_V[13]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[13]),
        .O(\acc_H1_FSK_V[15]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[15]_i_12 
       (.I0(acc_H1_FSK_V[12]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[12]),
        .O(\acc_H1_FSK_V[15]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[15]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[15]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[15]),
        .I5(p_0_out__4[53]),
        .O(\acc_H1_FSK_V[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[15]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[15]),
        .I1(acc_H1_FSK_V[15]),
        .O(\acc_H1_FSK_V[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[15]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[14]),
        .I1(acc_H1_FSK_V[14]),
        .O(\acc_H1_FSK_V[15]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[15]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[13]),
        .I1(acc_H1_FSK_V[13]),
        .O(\acc_H1_FSK_V[15]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[15]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[12]),
        .I1(acc_H1_FSK_V[12]),
        .O(\acc_H1_FSK_V[15]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[15]_i_9 
       (.I0(acc_H1_FSK_V[15]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[15]),
        .O(\acc_H1_FSK_V[15]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[16]_i_1 
       (.I0(\acc_H1_FSK_V[16]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[16]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[16]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[16]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[16]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[16]),
        .I5(p_0_out__4[54]),
        .O(\acc_H1_FSK_V[16]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[17]_i_1 
       (.I0(\acc_H1_FSK_V[17]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[17]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[17]));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[17]_i_10 
       (.I0(p_0_out__2_n_86),
        .I1(p_0_out__3_n_69),
        .I2(p_0_out__0_n_103),
        .I3(\acc_H1_FSK_V[17]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[17]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[17]_i_11 
       (.I0(p_0_out__2_n_87),
        .I1(p_0_out__3_n_70),
        .I2(p_0_out__0_n_104),
        .I3(\acc_H1_FSK_V[17]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[17]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[17]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[17]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[17]),
        .I5(p_0_out__4[55]),
        .O(\acc_H1_FSK_V[17]_i_2_n_0 ));
  (* HLUTNM = "lutpair92" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[17]_i_4 
       (.I0(p_0_out__2_n_85),
        .I1(p_0_out__3_n_68),
        .I2(p_0_out__0_n_102),
        .O(\acc_H1_FSK_V[17]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[17]_i_5 
       (.I0(p_0_out__2_n_86),
        .I1(p_0_out__3_n_69),
        .I2(p_0_out__0_n_103),
        .O(\acc_H1_FSK_V[17]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[17]_i_6 
       (.I0(p_0_out__2_n_87),
        .I1(p_0_out__3_n_70),
        .I2(p_0_out__0_n_104),
        .O(\acc_H1_FSK_V[17]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[17]_i_7 
       (.I0(p_0_out__2_n_88),
        .I1(p_0_out__3_n_71),
        .I2(p_0_out__0_n_105),
        .O(\acc_H1_FSK_V[17]_i_7_n_0 ));
  (* HLUTNM = "lutpair93" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[17]_i_8 
       (.I0(p_0_out__2_n_84),
        .I1(p_0_out__3_n_67),
        .I2(p_0_out__0_n_101),
        .I3(\acc_H1_FSK_V[17]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[17]_i_8_n_0 ));
  (* HLUTNM = "lutpair92" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[17]_i_9 
       (.I0(p_0_out__2_n_85),
        .I1(p_0_out__3_n_68),
        .I2(p_0_out__0_n_102),
        .I3(\acc_H1_FSK_V[17]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[17]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[18]_i_1 
       (.I0(\acc_H1_FSK_V[18]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[18]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[18]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[18]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[18]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[18]),
        .I5(p_0_out__4[56]),
        .O(\acc_H1_FSK_V[18]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[19]_i_1 
       (.I0(\acc_H1_FSK_V[19]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[19]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[19]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[19]_i_10 
       (.I0(acc_H1_FSK_V[18]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[18]),
        .O(\acc_H1_FSK_V[19]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[19]_i_11 
       (.I0(acc_H1_FSK_V[17]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[17]),
        .O(\acc_H1_FSK_V[19]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[19]_i_12 
       (.I0(acc_H1_FSK_V[16]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[16]),
        .O(\acc_H1_FSK_V[19]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[19]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[19]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[19]),
        .I5(p_0_out__4[57]),
        .O(\acc_H1_FSK_V[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[19]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[19]),
        .I1(acc_H1_FSK_V[19]),
        .O(\acc_H1_FSK_V[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[19]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[18]),
        .I1(acc_H1_FSK_V[18]),
        .O(\acc_H1_FSK_V[19]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[19]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[17]),
        .I1(acc_H1_FSK_V[17]),
        .O(\acc_H1_FSK_V[19]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[19]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[16]),
        .I1(acc_H1_FSK_V[16]),
        .O(\acc_H1_FSK_V[19]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[19]_i_9 
       (.I0(acc_H1_FSK_V[19]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[19]),
        .O(\acc_H1_FSK_V[19]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[1]_i_1 
       (.I0(\acc_H1_FSK_V[1]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[1]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[1]));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[1]_i_10 
       (.I0(p_0_out__2_n_101),
        .I1(p_0_out__3_n_84),
        .I2(\p_0_out_n_0_[4] ),
        .I3(\acc_H1_FSK_V[1]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[1]_i_11 
       (.I0(p_0_out__2_n_102),
        .I1(p_0_out__3_n_85),
        .I2(\p_0_out_n_0_[3] ),
        .I3(\acc_H1_FSK_V[1]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[1]_i_12 
       (.I0(p_0_out__2_n_103),
        .I1(p_0_out__3_n_86),
        .I2(\p_0_out_n_0_[2] ),
        .I3(\acc_H1_FSK_V[1]_i_8_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_12_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \acc_H1_FSK_V[1]_i_14 
       (.I0(p_0_out__3_n_87),
        .I1(\p_0_out_n_0_[1] ),
        .I2(p_0_out__2_n_104),
        .O(\acc_H1_FSK_V[1]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h69969696)) 
    \acc_H1_FSK_V[1]_i_15 
       (.I0(p_0_out__3_n_87),
        .I1(p_0_out__2_n_104),
        .I2(\p_0_out_n_0_[1] ),
        .I3(p_0_out__2_n_105),
        .I4(\p_0_out_n_0_[0] ),
        .O(\acc_H1_FSK_V[1]_i_15_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \acc_H1_FSK_V[1]_i_16 
       (.I0(p_0_out__2_n_105),
        .I1(\p_0_out_n_0_[0] ),
        .I2(p_0_out__3_n_88),
        .O(\acc_H1_FSK_V[1]_i_16_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_17 
       (.I0(p_0_out__3_n_89),
        .I1(\p_0_out[16]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_17_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_18 
       (.I0(p_0_out__3_n_90),
        .I1(\p_0_out[15]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[1]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[1]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[1]),
        .I5(p_0_out__4[39]),
        .O(\acc_H1_FSK_V[1]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_20 
       (.I0(p_0_out__3_n_91),
        .I1(\p_0_out[14]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_20_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_21 
       (.I0(p_0_out__3_n_92),
        .I1(\p_0_out[13]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_21_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_22 
       (.I0(p_0_out__3_n_93),
        .I1(\p_0_out[12]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_22_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_23 
       (.I0(p_0_out__3_n_94),
        .I1(\p_0_out[11]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_23_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_25 
       (.I0(p_0_out__3_n_95),
        .I1(\p_0_out[10]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_25_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_26 
       (.I0(p_0_out__3_n_96),
        .I1(\p_0_out[9]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_26_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_27 
       (.I0(p_0_out__3_n_97),
        .I1(\p_0_out[8]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_27_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_28 
       (.I0(p_0_out__3_n_98),
        .I1(\p_0_out[7]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_28_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_30 
       (.I0(p_0_out__3_n_99),
        .I1(\p_0_out[6]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_30_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_31 
       (.I0(p_0_out__3_n_100),
        .I1(\p_0_out[5]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_31_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_32 
       (.I0(p_0_out__3_n_101),
        .I1(\p_0_out[4]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_32_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_33 
       (.I0(p_0_out__3_n_102),
        .I1(\p_0_out[3]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_33_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_34 
       (.I0(p_0_out__3_n_103),
        .I1(\p_0_out[2]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_34_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_35 
       (.I0(p_0_out__3_n_104),
        .I1(\p_0_out[1]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_35_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[1]_i_36 
       (.I0(p_0_out__3_n_105),
        .I1(\p_0_out[0]__0_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_36_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[1]_i_5 
       (.I0(p_0_out__2_n_101),
        .I1(p_0_out__3_n_84),
        .I2(\p_0_out_n_0_[4] ),
        .O(\acc_H1_FSK_V[1]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[1]_i_6 
       (.I0(p_0_out__2_n_102),
        .I1(p_0_out__3_n_85),
        .I2(\p_0_out_n_0_[3] ),
        .O(\acc_H1_FSK_V[1]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[1]_i_7 
       (.I0(p_0_out__2_n_103),
        .I1(p_0_out__3_n_86),
        .I2(\p_0_out_n_0_[2] ),
        .O(\acc_H1_FSK_V[1]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[1]_i_8 
       (.I0(p_0_out__3_n_87),
        .I1(p_0_out__2_n_104),
        .I2(\p_0_out_n_0_[1] ),
        .O(\acc_H1_FSK_V[1]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[1]_i_9 
       (.I0(p_0_out__2_n_100),
        .I1(p_0_out__3_n_83),
        .I2(\p_0_out_n_0_[5] ),
        .I3(\acc_H1_FSK_V[1]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[20]_i_1 
       (.I0(\acc_H1_FSK_V[20]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[20]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[20]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[20]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[20]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[20]),
        .I5(p_0_out__4[58]),
        .O(\acc_H1_FSK_V[20]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[21]_i_1 
       (.I0(\acc_H1_FSK_V[21]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[21]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[21]));
  (* HLUTNM = "lutpair95" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[21]_i_10 
       (.I0(p_0_out__2_n_82),
        .I1(p_0_out__3_n_65),
        .I2(p_0_out__0_n_99),
        .I3(\acc_H1_FSK_V[21]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[21]_i_10_n_0 ));
  (* HLUTNM = "lutpair94" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[21]_i_11 
       (.I0(p_0_out__2_n_83),
        .I1(p_0_out__3_n_66),
        .I2(p_0_out__0_n_100),
        .I3(\acc_H1_FSK_V[21]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[21]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[21]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[21]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[21]),
        .I5(p_0_out__4[59]),
        .O(\acc_H1_FSK_V[21]_i_2_n_0 ));
  (* HLUTNM = "lutpair96" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[21]_i_4 
       (.I0(p_0_out__2_n_81),
        .I1(p_0_out__3_n_64),
        .I2(p_0_out__0_n_98),
        .O(\acc_H1_FSK_V[21]_i_4_n_0 ));
  (* HLUTNM = "lutpair95" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[21]_i_5 
       (.I0(p_0_out__2_n_82),
        .I1(p_0_out__3_n_65),
        .I2(p_0_out__0_n_99),
        .O(\acc_H1_FSK_V[21]_i_5_n_0 ));
  (* HLUTNM = "lutpair94" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[21]_i_6 
       (.I0(p_0_out__2_n_83),
        .I1(p_0_out__3_n_66),
        .I2(p_0_out__0_n_100),
        .O(\acc_H1_FSK_V[21]_i_6_n_0 ));
  (* HLUTNM = "lutpair93" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[21]_i_7 
       (.I0(p_0_out__2_n_84),
        .I1(p_0_out__3_n_67),
        .I2(p_0_out__0_n_101),
        .O(\acc_H1_FSK_V[21]_i_7_n_0 ));
  (* HLUTNM = "lutpair97" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[21]_i_8 
       (.I0(p_0_out__2_n_80),
        .I1(p_0_out__3_n_63),
        .I2(p_0_out__0_n_97),
        .I3(\acc_H1_FSK_V[21]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[21]_i_8_n_0 ));
  (* HLUTNM = "lutpair96" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[21]_i_9 
       (.I0(p_0_out__2_n_81),
        .I1(p_0_out__3_n_64),
        .I2(p_0_out__0_n_98),
        .I3(\acc_H1_FSK_V[21]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[21]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[22]_i_1 
       (.I0(\acc_H1_FSK_V[22]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[22]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[22]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[22]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[22]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[22]),
        .I5(p_0_out__4[60]),
        .O(\acc_H1_FSK_V[22]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[23]_i_1 
       (.I0(\acc_H1_FSK_V[23]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[23]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[23]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[23]_i_10 
       (.I0(acc_H1_FSK_V[22]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[22]),
        .O(\acc_H1_FSK_V[23]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[23]_i_11 
       (.I0(acc_H1_FSK_V[21]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[21]),
        .O(\acc_H1_FSK_V[23]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[23]_i_12 
       (.I0(acc_H1_FSK_V[20]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[20]),
        .O(\acc_H1_FSK_V[23]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[23]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[23]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[23]),
        .I5(p_0_out__4[61]),
        .O(\acc_H1_FSK_V[23]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[23]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[23]),
        .I1(acc_H1_FSK_V[23]),
        .O(\acc_H1_FSK_V[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[23]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[22]),
        .I1(acc_H1_FSK_V[22]),
        .O(\acc_H1_FSK_V[23]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[23]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[21]),
        .I1(acc_H1_FSK_V[21]),
        .O(\acc_H1_FSK_V[23]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[23]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[20]),
        .I1(acc_H1_FSK_V[20]),
        .O(\acc_H1_FSK_V[23]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[23]_i_9 
       (.I0(acc_H1_FSK_V[23]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[23]),
        .O(\acc_H1_FSK_V[23]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[24]_i_1 
       (.I0(\acc_H1_FSK_V[24]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[24]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[24]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[24]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[24]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[24]),
        .I5(p_0_out__4[62]),
        .O(\acc_H1_FSK_V[24]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[25]_i_1 
       (.I0(\acc_H1_FSK_V[25]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[25]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[25]));
  (* HLUTNM = "lutpair99" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[25]_i_10 
       (.I0(p_0_out__2_n_78),
        .I1(p_0_out__3_n_61),
        .I2(p_0_out__0_n_95),
        .I3(\acc_H1_FSK_V[25]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[25]_i_10_n_0 ));
  (* HLUTNM = "lutpair98" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[25]_i_11 
       (.I0(p_0_out__2_n_79),
        .I1(p_0_out__3_n_62),
        .I2(p_0_out__0_n_96),
        .I3(\acc_H1_FSK_V[25]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[25]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[25]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[25]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[25]),
        .I5(p_0_out__4[63]),
        .O(\acc_H1_FSK_V[25]_i_2_n_0 ));
  (* HLUTNM = "lutpair100" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[25]_i_4 
       (.I0(p_0_out__2_n_77),
        .I1(p_0_out__3_n_60),
        .I2(p_0_out__0_n_94),
        .O(\acc_H1_FSK_V[25]_i_4_n_0 ));
  (* HLUTNM = "lutpair99" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[25]_i_5 
       (.I0(p_0_out__2_n_78),
        .I1(p_0_out__3_n_61),
        .I2(p_0_out__0_n_95),
        .O(\acc_H1_FSK_V[25]_i_5_n_0 ));
  (* HLUTNM = "lutpair98" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[25]_i_6 
       (.I0(p_0_out__2_n_79),
        .I1(p_0_out__3_n_62),
        .I2(p_0_out__0_n_96),
        .O(\acc_H1_FSK_V[25]_i_6_n_0 ));
  (* HLUTNM = "lutpair97" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[25]_i_7 
       (.I0(p_0_out__2_n_80),
        .I1(p_0_out__3_n_63),
        .I2(p_0_out__0_n_97),
        .O(\acc_H1_FSK_V[25]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[25]_i_8 
       (.I0(\acc_H1_FSK_V[25]_i_4_n_0 ),
        .I1(p_0_out__3_n_59),
        .I2(p_0_out__0_n_93),
        .I3(p_0_out__2_n_76),
        .O(\acc_H1_FSK_V[25]_i_8_n_0 ));
  (* HLUTNM = "lutpair100" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[25]_i_9 
       (.I0(p_0_out__2_n_77),
        .I1(p_0_out__3_n_60),
        .I2(p_0_out__0_n_94),
        .I3(\acc_H1_FSK_V[25]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[25]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[26]_i_1 
       (.I0(\acc_H1_FSK_V[26]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[26]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[26]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[26]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[26]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[26]),
        .I5(p_0_out__4[64]),
        .O(\acc_H1_FSK_V[26]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[27]_i_1 
       (.I0(\acc_H1_FSK_V[27]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[27]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[27]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[27]_i_10 
       (.I0(acc_H1_FSK_V[26]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[26]),
        .O(\acc_H1_FSK_V[27]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[27]_i_11 
       (.I0(acc_H1_FSK_V[25]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[25]),
        .O(\acc_H1_FSK_V[27]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[27]_i_12 
       (.I0(acc_H1_FSK_V[24]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[24]),
        .O(\acc_H1_FSK_V[27]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[27]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[27]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[27]),
        .I5(p_0_out__4[65]),
        .O(\acc_H1_FSK_V[27]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[27]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[27]),
        .I1(acc_H1_FSK_V[27]),
        .O(\acc_H1_FSK_V[27]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[27]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[26]),
        .I1(acc_H1_FSK_V[26]),
        .O(\acc_H1_FSK_V[27]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[27]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[25]),
        .I1(acc_H1_FSK_V[25]),
        .O(\acc_H1_FSK_V[27]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[27]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[24]),
        .I1(acc_H1_FSK_V[24]),
        .O(\acc_H1_FSK_V[27]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[27]_i_9 
       (.I0(acc_H1_FSK_V[27]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[27]),
        .O(\acc_H1_FSK_V[27]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[28]_i_1 
       (.I0(\acc_H1_FSK_V[28]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[28]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[28]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[28]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[28]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[28]),
        .I5(p_0_out__4[66]),
        .O(\acc_H1_FSK_V[28]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[29]_i_1 
       (.I0(\acc_H1_FSK_V[29]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[29]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[29]));
  (* HLUTNM = "lutpair101" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[29]_i_10 
       (.I0(p_0_out__0_n_92),
        .I1(p_0_out__2_n_75),
        .I2(p_0_out__0_n_91),
        .I3(p_0_out__2_n_74),
        .I4(\acc_H1_FSK_V[29]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[29]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h6969699669969696)) 
    \acc_H1_FSK_V[29]_i_11 
       (.I0(p_0_out__2_n_75),
        .I1(p_0_out__0_n_92),
        .I2(p_0_out__3_n_58),
        .I3(p_0_out__0_n_93),
        .I4(p_0_out__3_n_59),
        .I5(p_0_out__2_n_76),
        .O(\acc_H1_FSK_V[29]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[29]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[29]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[29]),
        .I5(p_0_out__4[67]),
        .O(\acc_H1_FSK_V[29]_i_2_n_0 ));
  (* HLUTNM = "lutpair102" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[29]_i_4 
       (.I0(p_0_out__0_n_91),
        .I1(p_0_out__2_n_74),
        .I2(p_0_out__0_n_90),
        .I3(p_0_out__2_n_73),
        .O(\acc_H1_FSK_V[29]_i_4_n_0 ));
  (* HLUTNM = "lutpair101" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[29]_i_5 
       (.I0(p_0_out__0_n_92),
        .I1(p_0_out__2_n_75),
        .I2(p_0_out__0_n_91),
        .I3(p_0_out__2_n_74),
        .O(\acc_H1_FSK_V[29]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h41)) 
    \acc_H1_FSK_V[29]_i_6 
       (.I0(p_0_out__3_n_58),
        .I1(p_0_out__0_n_92),
        .I2(p_0_out__2_n_75),
        .O(\acc_H1_FSK_V[29]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'h96)) 
    \acc_H1_FSK_V[29]_i_7 
       (.I0(p_0_out__3_n_58),
        .I1(p_0_out__0_n_92),
        .I2(p_0_out__2_n_75),
        .O(\acc_H1_FSK_V[29]_i_7_n_0 ));
  (* HLUTNM = "lutpair103" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[29]_i_8 
       (.I0(p_0_out__0_n_90),
        .I1(p_0_out__2_n_73),
        .I2(p_0_out__0_n_89),
        .I3(p_0_out__2_n_72),
        .I4(\acc_H1_FSK_V[29]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[29]_i_8_n_0 ));
  (* HLUTNM = "lutpair102" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[29]_i_9 
       (.I0(p_0_out__0_n_91),
        .I1(p_0_out__2_n_74),
        .I2(p_0_out__0_n_90),
        .I3(p_0_out__2_n_73),
        .I4(\acc_H1_FSK_V[29]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[29]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[2]_i_1 
       (.I0(\acc_H1_FSK_V[2]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[2]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[2]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[2]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[2]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[2]),
        .I5(p_0_out__4[40]),
        .O(\acc_H1_FSK_V[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[30]_i_1 
       (.I0(\acc_H1_FSK_V[30]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[30]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[30]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[30]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[30]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[30]),
        .I5(p_0_out__4[68]),
        .O(\acc_H1_FSK_V[30]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[31]_i_1 
       (.I0(\acc_H1_FSK_V[31]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[31]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[31]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[31]_i_10 
       (.I0(acc_H1_FSK_V[30]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[30]),
        .O(\acc_H1_FSK_V[31]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[31]_i_11 
       (.I0(acc_H1_FSK_V[29]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[29]),
        .O(\acc_H1_FSK_V[31]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[31]_i_12 
       (.I0(acc_H1_FSK_V[28]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[28]),
        .O(\acc_H1_FSK_V[31]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[31]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[31]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[31]),
        .I5(p_0_out__4[69]),
        .O(\acc_H1_FSK_V[31]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[31]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[31]),
        .I1(acc_H1_FSK_V[31]),
        .O(\acc_H1_FSK_V[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[31]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[30]),
        .I1(acc_H1_FSK_V[30]),
        .O(\acc_H1_FSK_V[31]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[31]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[29]),
        .I1(acc_H1_FSK_V[29]),
        .O(\acc_H1_FSK_V[31]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[31]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[28]),
        .I1(acc_H1_FSK_V[28]),
        .O(\acc_H1_FSK_V[31]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[31]_i_9 
       (.I0(acc_H1_FSK_V[31]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[31]),
        .O(\acc_H1_FSK_V[31]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[32]_i_1 
       (.I0(\acc_H1_FSK_V[32]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[32]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[32]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[32]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[32]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[32]),
        .I5(p_0_out__4[70]),
        .O(\acc_H1_FSK_V[32]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[33]_i_1 
       (.I0(\acc_H1_FSK_V[33]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[33]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[33]));
  (* HLUTNM = "lutpair105" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[33]_i_10 
       (.I0(p_0_out__0_n_88),
        .I1(p_0_out__2_n_71),
        .I2(p_0_out__0_n_87),
        .I3(p_0_out__2_n_70),
        .I4(\acc_H1_FSK_V[33]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[33]_i_10_n_0 ));
  (* HLUTNM = "lutpair104" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[33]_i_11 
       (.I0(p_0_out__0_n_89),
        .I1(p_0_out__2_n_72),
        .I2(p_0_out__0_n_88),
        .I3(p_0_out__2_n_71),
        .I4(\acc_H1_FSK_V[33]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[33]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[33]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[33]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[33]),
        .I5(p_0_out__4[71]),
        .O(\acc_H1_FSK_V[33]_i_2_n_0 ));
  (* HLUTNM = "lutpair106" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[33]_i_4 
       (.I0(p_0_out__0_n_87),
        .I1(p_0_out__2_n_70),
        .I2(p_0_out__0_n_86),
        .I3(p_0_out__2_n_69),
        .O(\acc_H1_FSK_V[33]_i_4_n_0 ));
  (* HLUTNM = "lutpair105" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[33]_i_5 
       (.I0(p_0_out__0_n_88),
        .I1(p_0_out__2_n_71),
        .I2(p_0_out__0_n_87),
        .I3(p_0_out__2_n_70),
        .O(\acc_H1_FSK_V[33]_i_5_n_0 ));
  (* HLUTNM = "lutpair104" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[33]_i_6 
       (.I0(p_0_out__0_n_89),
        .I1(p_0_out__2_n_72),
        .I2(p_0_out__0_n_88),
        .I3(p_0_out__2_n_71),
        .O(\acc_H1_FSK_V[33]_i_6_n_0 ));
  (* HLUTNM = "lutpair103" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[33]_i_7 
       (.I0(p_0_out__0_n_90),
        .I1(p_0_out__2_n_73),
        .I2(p_0_out__0_n_89),
        .I3(p_0_out__2_n_72),
        .O(\acc_H1_FSK_V[33]_i_7_n_0 ));
  (* HLUTNM = "lutpair107" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[33]_i_8 
       (.I0(p_0_out__0_n_86),
        .I1(p_0_out__2_n_69),
        .I2(p_0_out__0_n_85),
        .I3(p_0_out__2_n_68),
        .I4(\acc_H1_FSK_V[33]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[33]_i_8_n_0 ));
  (* HLUTNM = "lutpair106" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[33]_i_9 
       (.I0(p_0_out__0_n_87),
        .I1(p_0_out__2_n_70),
        .I2(p_0_out__0_n_86),
        .I3(p_0_out__2_n_69),
        .I4(\acc_H1_FSK_V[33]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[33]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[34]_i_1 
       (.I0(\acc_H1_FSK_V[34]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[34]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[34]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[34]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[34]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[34]),
        .I5(p_0_out__4[72]),
        .O(\acc_H1_FSK_V[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[35]_i_1 
       (.I0(\acc_H1_FSK_V[35]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[35]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[35]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[35]_i_10 
       (.I0(acc_H1_FSK_V[34]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[34]),
        .O(\acc_H1_FSK_V[35]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[35]_i_11 
       (.I0(acc_H1_FSK_V[33]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[33]),
        .O(\acc_H1_FSK_V[35]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[35]_i_12 
       (.I0(acc_H1_FSK_V[32]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[32]),
        .O(\acc_H1_FSK_V[35]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[35]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[35]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[35]),
        .I5(p_0_out__4[73]),
        .O(\acc_H1_FSK_V[35]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[35]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[35]),
        .I1(acc_H1_FSK_V[35]),
        .O(\acc_H1_FSK_V[35]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[35]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[34]),
        .I1(acc_H1_FSK_V[34]),
        .O(\acc_H1_FSK_V[35]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[35]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[33]),
        .I1(acc_H1_FSK_V[33]),
        .O(\acc_H1_FSK_V[35]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[35]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[32]),
        .I1(acc_H1_FSK_V[32]),
        .O(\acc_H1_FSK_V[35]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[35]_i_9 
       (.I0(acc_H1_FSK_V[35]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[35]),
        .O(\acc_H1_FSK_V[35]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[36]_i_1 
       (.I0(\acc_H1_FSK_V[36]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[36]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[36]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[36]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[36]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[36]),
        .I5(p_0_out__4[74]),
        .O(\acc_H1_FSK_V[36]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[37]_i_1 
       (.I0(\acc_H1_FSK_V[37]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[37]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[37]));
  (* HLUTNM = "lutpair109" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[37]_i_10 
       (.I0(p_0_out__0_n_84),
        .I1(p_0_out__2_n_67),
        .I2(p_0_out__0_n_83),
        .I3(p_0_out__2_n_66),
        .I4(\acc_H1_FSK_V[37]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[37]_i_10_n_0 ));
  (* HLUTNM = "lutpair108" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[37]_i_11 
       (.I0(p_0_out__0_n_85),
        .I1(p_0_out__2_n_68),
        .I2(p_0_out__0_n_84),
        .I3(p_0_out__2_n_67),
        .I4(\acc_H1_FSK_V[37]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[37]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[37]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[37]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[37]),
        .I5(p_0_out__4[75]),
        .O(\acc_H1_FSK_V[37]_i_2_n_0 ));
  (* HLUTNM = "lutpair110" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[37]_i_4 
       (.I0(p_0_out__0_n_83),
        .I1(p_0_out__2_n_66),
        .I2(p_0_out__0_n_82),
        .I3(p_0_out__2_n_65),
        .O(\acc_H1_FSK_V[37]_i_4_n_0 ));
  (* HLUTNM = "lutpair109" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[37]_i_5 
       (.I0(p_0_out__0_n_84),
        .I1(p_0_out__2_n_67),
        .I2(p_0_out__0_n_83),
        .I3(p_0_out__2_n_66),
        .O(\acc_H1_FSK_V[37]_i_5_n_0 ));
  (* HLUTNM = "lutpair108" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[37]_i_6 
       (.I0(p_0_out__0_n_85),
        .I1(p_0_out__2_n_68),
        .I2(p_0_out__0_n_84),
        .I3(p_0_out__2_n_67),
        .O(\acc_H1_FSK_V[37]_i_6_n_0 ));
  (* HLUTNM = "lutpair107" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[37]_i_7 
       (.I0(p_0_out__0_n_86),
        .I1(p_0_out__2_n_69),
        .I2(p_0_out__0_n_85),
        .I3(p_0_out__2_n_68),
        .O(\acc_H1_FSK_V[37]_i_7_n_0 ));
  (* HLUTNM = "lutpair111" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[37]_i_8 
       (.I0(p_0_out__0_n_82),
        .I1(p_0_out__2_n_65),
        .I2(p_0_out__0_n_81),
        .I3(p_0_out__2_n_64),
        .I4(\acc_H1_FSK_V[37]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[37]_i_8_n_0 ));
  (* HLUTNM = "lutpair110" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[37]_i_9 
       (.I0(p_0_out__0_n_83),
        .I1(p_0_out__2_n_66),
        .I2(p_0_out__0_n_82),
        .I3(p_0_out__2_n_65),
        .I4(\acc_H1_FSK_V[37]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[37]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[38]_i_1 
       (.I0(\acc_H1_FSK_V[38]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[38]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[38]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[38]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[38]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[38]),
        .I5(p_0_out__4[76]),
        .O(\acc_H1_FSK_V[38]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[39]_i_1 
       (.I0(\acc_H1_FSK_V[39]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[39]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[39]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[39]_i_10 
       (.I0(acc_H1_FSK_V[38]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[38]),
        .O(\acc_H1_FSK_V[39]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[39]_i_11 
       (.I0(acc_H1_FSK_V[37]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[37]),
        .O(\acc_H1_FSK_V[39]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[39]_i_12 
       (.I0(acc_H1_FSK_V[36]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[36]),
        .O(\acc_H1_FSK_V[39]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[39]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[39]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[39]),
        .I5(p_0_out__4[77]),
        .O(\acc_H1_FSK_V[39]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[39]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[39]),
        .I1(acc_H1_FSK_V[39]),
        .O(\acc_H1_FSK_V[39]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[39]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[38]),
        .I1(acc_H1_FSK_V[38]),
        .O(\acc_H1_FSK_V[39]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[39]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[37]),
        .I1(acc_H1_FSK_V[37]),
        .O(\acc_H1_FSK_V[39]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[39]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[36]),
        .I1(acc_H1_FSK_V[36]),
        .O(\acc_H1_FSK_V[39]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[39]_i_9 
       (.I0(acc_H1_FSK_V[39]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[39]),
        .O(\acc_H1_FSK_V[39]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[3]_i_1 
       (.I0(\acc_H1_FSK_V[3]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[3]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[3]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[3]_i_10 
       (.I0(acc_H1_FSK_V[2]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[2]),
        .O(\acc_H1_FSK_V[3]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[3]_i_11 
       (.I0(acc_H1_FSK_V[1]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[1]),
        .O(\acc_H1_FSK_V[3]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[3]_i_12 
       (.I0(acc_H1_FSK_V[0]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[0]),
        .O(\acc_H1_FSK_V[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[3]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[3]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[3]),
        .I5(p_0_out__4[41]),
        .O(\acc_H1_FSK_V[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[3]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[3]),
        .I1(acc_H1_FSK_V[3]),
        .O(\acc_H1_FSK_V[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[3]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[2]),
        .I1(acc_H1_FSK_V[2]),
        .O(\acc_H1_FSK_V[3]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[3]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[1]),
        .I1(acc_H1_FSK_V[1]),
        .O(\acc_H1_FSK_V[3]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[3]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[0]),
        .I1(acc_H1_FSK_V[0]),
        .O(\acc_H1_FSK_V[3]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[3]_i_9 
       (.I0(acc_H1_FSK_V[3]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[3]),
        .O(\acc_H1_FSK_V[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[40]_i_1 
       (.I0(\acc_H1_FSK_V[40]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[40]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[40]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[40]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[40]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[40]),
        .I5(p_0_out__4[78]),
        .O(\acc_H1_FSK_V[40]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[41]_i_1 
       (.I0(\acc_H1_FSK_V[41]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[41]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[41]));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_10 
       (.I0(clk_off_reg[31]),
        .I1(clk_on_reg[31]),
        .I2(clk_on_reg[30]),
        .I3(clk_off_reg[30]),
        .O(\acc_H1_FSK_V[41]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_11 
       (.I0(clk_on_reg[29]),
        .I1(clk_off_reg[29]),
        .I2(clk_on_reg[28]),
        .I3(clk_off_reg[28]),
        .O(\acc_H1_FSK_V[41]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_12 
       (.I0(clk_on_reg[27]),
        .I1(clk_off_reg[27]),
        .I2(clk_on_reg[26]),
        .I3(clk_off_reg[26]),
        .O(\acc_H1_FSK_V[41]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_13 
       (.I0(clk_on_reg[25]),
        .I1(clk_off_reg[25]),
        .I2(clk_on_reg[24]),
        .I3(clk_off_reg[24]),
        .O(\acc_H1_FSK_V[41]_i_13_n_0 ));
  (* HLUTNM = "lutpair113" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[41]_i_14 
       (.I0(p_0_out__0_n_80),
        .I1(p_0_out__2_n_63),
        .I2(p_0_out__0_n_79),
        .I3(p_0_out__2_n_62),
        .O(\acc_H1_FSK_V[41]_i_14_n_0 ));
  (* HLUTNM = "lutpair112" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[41]_i_15 
       (.I0(p_0_out__0_n_81),
        .I1(p_0_out__2_n_64),
        .I2(p_0_out__0_n_80),
        .I3(p_0_out__2_n_63),
        .O(\acc_H1_FSK_V[41]_i_15_n_0 ));
  (* HLUTNM = "lutpair111" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \acc_H1_FSK_V[41]_i_16 
       (.I0(p_0_out__0_n_82),
        .I1(p_0_out__2_n_65),
        .I2(p_0_out__0_n_81),
        .I3(p_0_out__2_n_64),
        .O(\acc_H1_FSK_V[41]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hE11E0FF00FF01EE1)) 
    \acc_H1_FSK_V[41]_i_17 
       (.I0(p_0_out__2_n_62),
        .I1(p_0_out__0_n_79),
        .I2(p_0_out__2_n_60),
        .I3(p_0_out__0_n_77),
        .I4(p_0_out__2_n_61),
        .I5(p_0_out__0_n_78),
        .O(\acc_H1_FSK_V[41]_i_17_n_0 ));
  LUT5 #(
    .INIT(32'h96969669)) 
    \acc_H1_FSK_V[41]_i_18 
       (.I0(\acc_H1_FSK_V[41]_i_14_n_0 ),
        .I1(p_0_out__2_n_61),
        .I2(p_0_out__0_n_78),
        .I3(p_0_out__2_n_62),
        .I4(p_0_out__0_n_79),
        .O(\acc_H1_FSK_V[41]_i_18_n_0 ));
  (* HLUTNM = "lutpair113" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[41]_i_19 
       (.I0(p_0_out__0_n_80),
        .I1(p_0_out__2_n_63),
        .I2(p_0_out__0_n_79),
        .I3(p_0_out__2_n_62),
        .I4(\acc_H1_FSK_V[41]_i_15_n_0 ),
        .O(\acc_H1_FSK_V[41]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[41]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[41]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[41]),
        .I5(p_0_out__4[79]),
        .O(\acc_H1_FSK_V[41]_i_2_n_0 ));
  (* HLUTNM = "lutpair112" *) 
  LUT5 #(
    .INIT(32'hE11E1EE1)) 
    \acc_H1_FSK_V[41]_i_20 
       (.I0(p_0_out__0_n_81),
        .I1(p_0_out__2_n_64),
        .I2(p_0_out__0_n_80),
        .I3(p_0_out__2_n_63),
        .I4(\acc_H1_FSK_V[41]_i_16_n_0 ),
        .O(\acc_H1_FSK_V[41]_i_20_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_22 
       (.I0(clk_off_reg[23]),
        .I1(clk_on_reg[23]),
        .I2(clk_on_reg[22]),
        .I3(clk_off_reg[22]),
        .O(\acc_H1_FSK_V[41]_i_22_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_23 
       (.I0(clk_off_reg[21]),
        .I1(clk_on_reg[21]),
        .I2(clk_on_reg[20]),
        .I3(clk_off_reg[20]),
        .O(\acc_H1_FSK_V[41]_i_23_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_24 
       (.I0(clk_off_reg[19]),
        .I1(clk_on_reg[19]),
        .I2(clk_on_reg[18]),
        .I3(clk_off_reg[18]),
        .O(\acc_H1_FSK_V[41]_i_24_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_25 
       (.I0(clk_off_reg[17]),
        .I1(clk_on_reg[17]),
        .I2(clk_on_reg[16]),
        .I3(clk_off_reg[16]),
        .O(\acc_H1_FSK_V[41]_i_25_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_26 
       (.I0(clk_on_reg[23]),
        .I1(clk_off_reg[23]),
        .I2(clk_on_reg[22]),
        .I3(clk_off_reg[22]),
        .O(\acc_H1_FSK_V[41]_i_26_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_27 
       (.I0(clk_on_reg[21]),
        .I1(clk_off_reg[21]),
        .I2(clk_on_reg[20]),
        .I3(clk_off_reg[20]),
        .O(\acc_H1_FSK_V[41]_i_27_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_28 
       (.I0(clk_on_reg[19]),
        .I1(clk_off_reg[19]),
        .I2(clk_on_reg[18]),
        .I3(clk_off_reg[18]),
        .O(\acc_H1_FSK_V[41]_i_28_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_29 
       (.I0(clk_on_reg[17]),
        .I1(clk_off_reg[17]),
        .I2(clk_on_reg[16]),
        .I3(clk_off_reg[16]),
        .O(\acc_H1_FSK_V[41]_i_29_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_31 
       (.I0(clk_off_reg[15]),
        .I1(clk_on_reg[15]),
        .I2(clk_on_reg[14]),
        .I3(clk_off_reg[14]),
        .O(\acc_H1_FSK_V[41]_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_32 
       (.I0(clk_off_reg[13]),
        .I1(clk_on_reg[13]),
        .I2(clk_on_reg[12]),
        .I3(clk_off_reg[12]),
        .O(\acc_H1_FSK_V[41]_i_32_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_33 
       (.I0(clk_off_reg[11]),
        .I1(clk_on_reg[11]),
        .I2(clk_on_reg[10]),
        .I3(clk_off_reg[10]),
        .O(\acc_H1_FSK_V[41]_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_34 
       (.I0(clk_off_reg[9]),
        .I1(clk_on_reg[9]),
        .I2(clk_on_reg[8]),
        .I3(clk_off_reg[8]),
        .O(\acc_H1_FSK_V[41]_i_34_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_35 
       (.I0(clk_on_reg[15]),
        .I1(clk_off_reg[15]),
        .I2(clk_on_reg[14]),
        .I3(clk_off_reg[14]),
        .O(\acc_H1_FSK_V[41]_i_35_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_36 
       (.I0(clk_on_reg[13]),
        .I1(clk_off_reg[13]),
        .I2(clk_on_reg[12]),
        .I3(clk_off_reg[12]),
        .O(\acc_H1_FSK_V[41]_i_36_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_37 
       (.I0(clk_on_reg[11]),
        .I1(clk_off_reg[11]),
        .I2(clk_on_reg[10]),
        .I3(clk_off_reg[10]),
        .O(\acc_H1_FSK_V[41]_i_37_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_38 
       (.I0(clk_on_reg[9]),
        .I1(clk_off_reg[9]),
        .I2(clk_on_reg[8]),
        .I3(clk_off_reg[8]),
        .O(\acc_H1_FSK_V[41]_i_38_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_39 
       (.I0(clk_off_reg[7]),
        .I1(clk_on_reg[7]),
        .I2(clk_on_reg[6]),
        .I3(clk_off_reg[6]),
        .O(\acc_H1_FSK_V[41]_i_39_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_40 
       (.I0(clk_off_reg[5]),
        .I1(clk_on_reg[5]),
        .I2(clk_on_reg[4]),
        .I3(clk_off_reg[4]),
        .O(\acc_H1_FSK_V[41]_i_40_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_41 
       (.I0(clk_off_reg[3]),
        .I1(clk_on_reg[3]),
        .I2(clk_on_reg[2]),
        .I3(clk_off_reg[2]),
        .O(\acc_H1_FSK_V[41]_i_41_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_42 
       (.I0(clk_off_reg[1]),
        .I1(clk_on_reg[1]),
        .I2(clk_on_reg[0]),
        .I3(clk_off_reg[0]),
        .O(\acc_H1_FSK_V[41]_i_42_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_43 
       (.I0(clk_on_reg[7]),
        .I1(clk_off_reg[7]),
        .I2(clk_on_reg[6]),
        .I3(clk_off_reg[6]),
        .O(\acc_H1_FSK_V[41]_i_43_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_44 
       (.I0(clk_on_reg[5]),
        .I1(clk_off_reg[5]),
        .I2(clk_on_reg[4]),
        .I3(clk_off_reg[4]),
        .O(\acc_H1_FSK_V[41]_i_44_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_45 
       (.I0(clk_on_reg[3]),
        .I1(clk_off_reg[3]),
        .I2(clk_on_reg[2]),
        .I3(clk_off_reg[2]),
        .O(\acc_H1_FSK_V[41]_i_45_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \acc_H1_FSK_V[41]_i_46 
       (.I0(clk_on_reg[1]),
        .I1(clk_off_reg[1]),
        .I2(clk_off_reg[0]),
        .I3(clk_on_reg[0]),
        .O(\acc_H1_FSK_V[41]_i_46_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_6 
       (.I0(clk_on_reg[31]),
        .I1(clk_off_reg[31]),
        .I2(clk_on_reg[30]),
        .I3(clk_off_reg[30]),
        .O(\acc_H1_FSK_V[41]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_7 
       (.I0(clk_off_reg[29]),
        .I1(clk_on_reg[29]),
        .I2(clk_on_reg[28]),
        .I3(clk_off_reg[28]),
        .O(\acc_H1_FSK_V[41]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_8 
       (.I0(clk_off_reg[27]),
        .I1(clk_on_reg[27]),
        .I2(clk_on_reg[26]),
        .I3(clk_off_reg[26]),
        .O(\acc_H1_FSK_V[41]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \acc_H1_FSK_V[41]_i_9 
       (.I0(clk_off_reg[25]),
        .I1(clk_on_reg[25]),
        .I2(clk_on_reg[24]),
        .I3(clk_off_reg[24]),
        .O(\acc_H1_FSK_V[41]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \acc_H1_FSK_V[42]_i_1 
       (.I0(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I1(\acc_H1_FSK_V[42]_i_2_n_0 ),
        .O(\acc_H1_FSK_V[42]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF3F5F3F0F3F5F3FF)) 
    \acc_H1_FSK_V[42]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[42]),
        .I1(p_Val2_s_14_fu_1229_p2[42]),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(tmp_15_fu_1198_p2),
        .I5(acc_H1_FSK_V[42]),
        .O(\acc_H1_FSK_V[42]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \acc_H1_FSK_V[43]_i_1 
       (.I0(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I1(\acc_H1_FSK_V[43]_i_2_n_0 ),
        .O(\acc_H1_FSK_V[43]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[43]_i_10 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[40]),
        .I1(acc_H1_FSK_V[40]),
        .O(\acc_H1_FSK_V[43]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFF03FF05FFF3FFF5)) 
    \acc_H1_FSK_V[43]_i_2 
       (.I0(acc_H1_FSK_V[43]),
        .I1(p_Val2_21_fu_1207_p2[43]),
        .I2(tmp_12_reg_1606_pp0_iter4_reg),
        .I3(tmp_3_reg_1602_pp0_iter4_reg),
        .I4(tmp_15_fu_1198_p2),
        .I5(p_Val2_s_14_fu_1229_p2[43]),
        .O(\acc_H1_FSK_V[43]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \acc_H1_FSK_V[43]_i_5 
       (.I0(acc_H1_FSK_V[43]),
        .O(\acc_H1_FSK_V[43]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \acc_H1_FSK_V[43]_i_6 
       (.I0(acc_H1_FSK_V[42]),
        .O(\acc_H1_FSK_V[43]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[43]_i_7 
       (.I0(acc_H1_FSK_V[41]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[41]),
        .O(\acc_H1_FSK_V[43]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[43]_i_8 
       (.I0(acc_H1_FSK_V[40]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[40]),
        .O(\acc_H1_FSK_V[43]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[43]_i_9 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[41]),
        .I1(acc_H1_FSK_V[41]),
        .O(\acc_H1_FSK_V[43]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \acc_H1_FSK_V[44]_i_1 
       (.I0(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I1(\acc_H1_FSK_V[44]_i_2_n_0 ),
        .O(\acc_H1_FSK_V[44]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF03FF05FFF3FFF5)) 
    \acc_H1_FSK_V[44]_i_2 
       (.I0(acc_H1_FSK_V[44]),
        .I1(p_Val2_21_fu_1207_p2[44]),
        .I2(tmp_12_reg_1606_pp0_iter4_reg),
        .I3(tmp_3_reg_1602_pp0_iter4_reg),
        .I4(tmp_15_fu_1198_p2),
        .I5(p_Val2_s_14_fu_1229_p2[44]),
        .O(\acc_H1_FSK_V[44]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \acc_H1_FSK_V[45]_i_1 
       (.I0(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I1(\acc_H1_FSK_V[45]_i_2_n_0 ),
        .O(\acc_H1_FSK_V[45]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF3F5F3F0F3F5F3FF)) 
    \acc_H1_FSK_V[45]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[45]),
        .I1(p_Val2_s_14_fu_1229_p2[45]),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(tmp_15_fu_1198_p2),
        .I5(acc_H1_FSK_V[45]),
        .O(\acc_H1_FSK_V[45]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \acc_H1_FSK_V[46]_i_1 
       (.I0(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I1(\acc_H1_FSK_V[46]_i_2_n_0 ),
        .O(\acc_H1_FSK_V[46]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF3F5F3F0F3F5F3FF)) 
    \acc_H1_FSK_V[46]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[46]),
        .I1(p_Val2_s_14_fu_1229_p2[46]),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(tmp_15_fu_1198_p2),
        .I5(acc_H1_FSK_V[46]),
        .O(\acc_H1_FSK_V[46]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \acc_H1_FSK_V[47]_i_1 
       (.I0(ap_rst),
        .I1(ap_enable_reg_pp0_iter5),
        .I2(p_Val2_4_reg_1510),
        .I3(tmp_22_reg_1544_pp0_iter4_reg),
        .O(\acc_H1_FSK_V[47]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \acc_H1_FSK_V[47]_i_10 
       (.I0(acc_H1_FSK_V[45]),
        .O(\acc_H1_FSK_V[47]_i_10_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \acc_H1_FSK_V[47]_i_11 
       (.I0(acc_H1_FSK_V[44]),
        .O(\acc_H1_FSK_V[47]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hFD000000)) 
    \acc_H1_FSK_V[47]_i_2 
       (.I0(\acc_H1_FSK_V[47]_i_4_n_0 ),
        .I1(tmp_22_reg_1544_pp0_iter4_reg),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I3(p_Val2_4_reg_1510),
        .I4(ap_enable_reg_pp0_iter5),
        .O(acc_H1_FSK_V0));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \acc_H1_FSK_V[47]_i_3 
       (.I0(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .I1(\acc_H1_FSK_V[47]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[47]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \acc_H1_FSK_V[47]_i_4 
       (.I0(tmp_15_fu_1198_p2),
        .I1(tmp_3_reg_1602_pp0_iter4_reg),
        .I2(tmp_12_reg_1606_pp0_iter4_reg),
        .O(\acc_H1_FSK_V[47]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF3F5F3F0F3F5F3FF)) 
    \acc_H1_FSK_V[47]_i_5 
       (.I0(p_Val2_21_fu_1207_p2[47]),
        .I1(p_Val2_s_14_fu_1229_p2[47]),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(tmp_15_fu_1198_p2),
        .I5(acc_H1_FSK_V[47]),
        .O(\acc_H1_FSK_V[47]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \acc_H1_FSK_V[47]_i_8 
       (.I0(acc_H1_FSK_V[47]),
        .O(\acc_H1_FSK_V[47]_i_8_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \acc_H1_FSK_V[47]_i_9 
       (.I0(acc_H1_FSK_V[46]),
        .O(\acc_H1_FSK_V[47]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[4]_i_1 
       (.I0(\acc_H1_FSK_V[4]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[4]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[4]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[4]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[4]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[4]),
        .I5(p_0_out__4[42]),
        .O(\acc_H1_FSK_V[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[5]_i_1 
       (.I0(\acc_H1_FSK_V[5]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[5]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[5]));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[5]_i_10 
       (.I0(p_0_out__2_n_98),
        .I1(p_0_out__3_n_81),
        .I2(\p_0_out_n_0_[7] ),
        .I3(\acc_H1_FSK_V[5]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[5]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[5]_i_11 
       (.I0(p_0_out__2_n_99),
        .I1(p_0_out__3_n_82),
        .I2(\p_0_out_n_0_[6] ),
        .I3(\acc_H1_FSK_V[5]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[5]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[5]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[5]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[5]),
        .I5(p_0_out__4[43]),
        .O(\acc_H1_FSK_V[5]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[5]_i_4 
       (.I0(p_0_out__2_n_97),
        .I1(p_0_out__3_n_80),
        .I2(\p_0_out_n_0_[8] ),
        .O(\acc_H1_FSK_V[5]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[5]_i_5 
       (.I0(p_0_out__2_n_98),
        .I1(p_0_out__3_n_81),
        .I2(\p_0_out_n_0_[7] ),
        .O(\acc_H1_FSK_V[5]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[5]_i_6 
       (.I0(p_0_out__2_n_99),
        .I1(p_0_out__3_n_82),
        .I2(\p_0_out_n_0_[6] ),
        .O(\acc_H1_FSK_V[5]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[5]_i_7 
       (.I0(p_0_out__2_n_100),
        .I1(p_0_out__3_n_83),
        .I2(\p_0_out_n_0_[5] ),
        .O(\acc_H1_FSK_V[5]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[5]_i_8 
       (.I0(p_0_out__2_n_96),
        .I1(p_0_out__3_n_79),
        .I2(\p_0_out_n_0_[9] ),
        .I3(\acc_H1_FSK_V[5]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[5]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[5]_i_9 
       (.I0(p_0_out__2_n_97),
        .I1(p_0_out__3_n_80),
        .I2(\p_0_out_n_0_[8] ),
        .I3(\acc_H1_FSK_V[5]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[5]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[6]_i_1 
       (.I0(\acc_H1_FSK_V[6]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[6]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[6]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[6]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[6]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[6]),
        .I5(p_0_out__4[44]),
        .O(\acc_H1_FSK_V[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[7]_i_1 
       (.I0(\acc_H1_FSK_V[7]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[7]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[7]));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[7]_i_10 
       (.I0(acc_H1_FSK_V[6]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[6]),
        .O(\acc_H1_FSK_V[7]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[7]_i_11 
       (.I0(acc_H1_FSK_V[5]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[5]),
        .O(\acc_H1_FSK_V[7]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[7]_i_12 
       (.I0(acc_H1_FSK_V[4]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[4]),
        .O(\acc_H1_FSK_V[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[7]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[7]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[7]),
        .I5(p_0_out__4[45]),
        .O(\acc_H1_FSK_V[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[7]_i_5 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[7]),
        .I1(acc_H1_FSK_V[7]),
        .O(\acc_H1_FSK_V[7]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[7]_i_6 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[6]),
        .I1(acc_H1_FSK_V[6]),
        .O(\acc_H1_FSK_V[7]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[7]_i_7 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[5]),
        .I1(acc_H1_FSK_V[5]),
        .O(\acc_H1_FSK_V[7]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \acc_H1_FSK_V[7]_i_8 
       (.I0(p_Val2_12_reg_1560_pp0_iter4_reg[4]),
        .I1(acc_H1_FSK_V[4]),
        .O(\acc_H1_FSK_V[7]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_FSK_V[7]_i_9 
       (.I0(acc_H1_FSK_V[7]),
        .I1(p_Val2_12_reg_1560_pp0_iter4_reg[7]),
        .O(\acc_H1_FSK_V[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[8]_i_1 
       (.I0(\acc_H1_FSK_V[8]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[8]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[8]));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[8]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[8]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[8]),
        .I5(p_0_out__4[46]),
        .O(\acc_H1_FSK_V[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAABAAA8)) 
    \acc_H1_FSK_V[9]_i_1 
       (.I0(\acc_H1_FSK_V[9]_i_2_n_0 ),
        .I1(tmp_12_reg_1606_pp0_iter4_reg),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_15_fu_1198_p2),
        .I4(acc_H1_FSK_V[9]),
        .I5(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(p_1_in[9]));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[9]_i_10 
       (.I0(p_0_out__2_n_94),
        .I1(p_0_out__3_n_77),
        .I2(\p_0_out_n_0_[11] ),
        .I3(\acc_H1_FSK_V[9]_i_6_n_0 ),
        .O(\acc_H1_FSK_V[9]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[9]_i_11 
       (.I0(p_0_out__2_n_95),
        .I1(p_0_out__3_n_78),
        .I2(\p_0_out_n_0_[10] ),
        .I3(\acc_H1_FSK_V[9]_i_7_n_0 ),
        .O(\acc_H1_FSK_V[9]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFBF0FB0F080008)) 
    \acc_H1_FSK_V[9]_i_2 
       (.I0(p_Val2_21_fu_1207_p2[9]),
        .I1(tmp_15_fu_1198_p2),
        .I2(tmp_3_reg_1602_pp0_iter4_reg),
        .I3(tmp_12_reg_1606_pp0_iter4_reg),
        .I4(p_Val2_s_14_fu_1229_p2[9]),
        .I5(p_0_out__4[47]),
        .O(\acc_H1_FSK_V[9]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[9]_i_4 
       (.I0(p_0_out__2_n_93),
        .I1(p_0_out__3_n_76),
        .I2(\p_0_out_n_0_[12] ),
        .O(\acc_H1_FSK_V[9]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[9]_i_5 
       (.I0(p_0_out__2_n_94),
        .I1(p_0_out__3_n_77),
        .I2(\p_0_out_n_0_[11] ),
        .O(\acc_H1_FSK_V[9]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[9]_i_6 
       (.I0(p_0_out__2_n_95),
        .I1(p_0_out__3_n_78),
        .I2(\p_0_out_n_0_[10] ),
        .O(\acc_H1_FSK_V[9]_i_6_n_0 ));
  LUT3 #(
    .INIT(8'hE8)) 
    \acc_H1_FSK_V[9]_i_7 
       (.I0(p_0_out__2_n_96),
        .I1(p_0_out__3_n_79),
        .I2(\p_0_out_n_0_[9] ),
        .O(\acc_H1_FSK_V[9]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[9]_i_8 
       (.I0(p_0_out__2_n_92),
        .I1(p_0_out__3_n_75),
        .I2(\p_0_out_n_0_[13] ),
        .I3(\acc_H1_FSK_V[9]_i_4_n_0 ),
        .O(\acc_H1_FSK_V[9]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_FSK_V[9]_i_9 
       (.I0(p_0_out__2_n_93),
        .I1(p_0_out__3_n_76),
        .I2(\p_0_out_n_0_[12] ),
        .I3(\acc_H1_FSK_V[9]_i_5_n_0 ),
        .O(\acc_H1_FSK_V[9]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[0]),
        .Q(acc_H1_FSK_V[0]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[10]),
        .Q(acc_H1_FSK_V[10]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[11]),
        .Q(acc_H1_FSK_V[11]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[11]_i_3 
       (.CI(\acc_H1_FSK_V_reg[7]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[11]_i_3_n_0 ,\acc_H1_FSK_V_reg[11]_i_3_n_1 ,\acc_H1_FSK_V_reg[11]_i_3_n_2 ,\acc_H1_FSK_V_reg[11]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[11:8]),
        .O(p_Val2_21_fu_1207_p2[11:8]),
        .S({\acc_H1_FSK_V[11]_i_5_n_0 ,\acc_H1_FSK_V[11]_i_6_n_0 ,\acc_H1_FSK_V[11]_i_7_n_0 ,\acc_H1_FSK_V[11]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[11]_i_4 
       (.CI(\acc_H1_FSK_V_reg[7]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[11]_i_4_n_0 ,\acc_H1_FSK_V_reg[11]_i_4_n_1 ,\acc_H1_FSK_V_reg[11]_i_4_n_2 ,\acc_H1_FSK_V_reg[11]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[11:8]),
        .O(p_Val2_s_14_fu_1229_p2[11:8]),
        .S({\acc_H1_FSK_V[11]_i_9_n_0 ,\acc_H1_FSK_V[11]_i_10_n_0 ,\acc_H1_FSK_V[11]_i_11_n_0 ,\acc_H1_FSK_V[11]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[12]),
        .Q(acc_H1_FSK_V[12]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[13]),
        .Q(acc_H1_FSK_V[13]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[13]_i_3 
       (.CI(\acc_H1_FSK_V_reg[9]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[13]_i_3_n_0 ,\acc_H1_FSK_V_reg[13]_i_3_n_1 ,\acc_H1_FSK_V_reg[13]_i_3_n_2 ,\acc_H1_FSK_V_reg[13]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[13]_i_4_n_0 ,\acc_H1_FSK_V[13]_i_5_n_0 ,\acc_H1_FSK_V[13]_i_6_n_0 ,\acc_H1_FSK_V[13]_i_7_n_0 }),
        .O(p_0_out__4[51:48]),
        .S({\acc_H1_FSK_V[13]_i_8_n_0 ,\acc_H1_FSK_V[13]_i_9_n_0 ,\acc_H1_FSK_V[13]_i_10_n_0 ,\acc_H1_FSK_V[13]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[14]),
        .Q(acc_H1_FSK_V[14]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[15]),
        .Q(acc_H1_FSK_V[15]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[15]_i_3 
       (.CI(\acc_H1_FSK_V_reg[11]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[15]_i_3_n_0 ,\acc_H1_FSK_V_reg[15]_i_3_n_1 ,\acc_H1_FSK_V_reg[15]_i_3_n_2 ,\acc_H1_FSK_V_reg[15]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[15:12]),
        .O(p_Val2_21_fu_1207_p2[15:12]),
        .S({\acc_H1_FSK_V[15]_i_5_n_0 ,\acc_H1_FSK_V[15]_i_6_n_0 ,\acc_H1_FSK_V[15]_i_7_n_0 ,\acc_H1_FSK_V[15]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[15]_i_4 
       (.CI(\acc_H1_FSK_V_reg[11]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[15]_i_4_n_0 ,\acc_H1_FSK_V_reg[15]_i_4_n_1 ,\acc_H1_FSK_V_reg[15]_i_4_n_2 ,\acc_H1_FSK_V_reg[15]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[15:12]),
        .O(p_Val2_s_14_fu_1229_p2[15:12]),
        .S({\acc_H1_FSK_V[15]_i_9_n_0 ,\acc_H1_FSK_V[15]_i_10_n_0 ,\acc_H1_FSK_V[15]_i_11_n_0 ,\acc_H1_FSK_V[15]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[16]),
        .Q(acc_H1_FSK_V[16]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[17]),
        .Q(acc_H1_FSK_V[17]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[17]_i_3 
       (.CI(\acc_H1_FSK_V_reg[13]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[17]_i_3_n_0 ,\acc_H1_FSK_V_reg[17]_i_3_n_1 ,\acc_H1_FSK_V_reg[17]_i_3_n_2 ,\acc_H1_FSK_V_reg[17]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[17]_i_4_n_0 ,\acc_H1_FSK_V[17]_i_5_n_0 ,\acc_H1_FSK_V[17]_i_6_n_0 ,\acc_H1_FSK_V[17]_i_7_n_0 }),
        .O(p_0_out__4[55:52]),
        .S({\acc_H1_FSK_V[17]_i_8_n_0 ,\acc_H1_FSK_V[17]_i_9_n_0 ,\acc_H1_FSK_V[17]_i_10_n_0 ,\acc_H1_FSK_V[17]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[18]),
        .Q(acc_H1_FSK_V[18]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[19]),
        .Q(acc_H1_FSK_V[19]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[19]_i_3 
       (.CI(\acc_H1_FSK_V_reg[15]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[19]_i_3_n_0 ,\acc_H1_FSK_V_reg[19]_i_3_n_1 ,\acc_H1_FSK_V_reg[19]_i_3_n_2 ,\acc_H1_FSK_V_reg[19]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[19:16]),
        .O(p_Val2_21_fu_1207_p2[19:16]),
        .S({\acc_H1_FSK_V[19]_i_5_n_0 ,\acc_H1_FSK_V[19]_i_6_n_0 ,\acc_H1_FSK_V[19]_i_7_n_0 ,\acc_H1_FSK_V[19]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[19]_i_4 
       (.CI(\acc_H1_FSK_V_reg[15]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[19]_i_4_n_0 ,\acc_H1_FSK_V_reg[19]_i_4_n_1 ,\acc_H1_FSK_V_reg[19]_i_4_n_2 ,\acc_H1_FSK_V_reg[19]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[19:16]),
        .O(p_Val2_s_14_fu_1229_p2[19:16]),
        .S({\acc_H1_FSK_V[19]_i_9_n_0 ,\acc_H1_FSK_V[19]_i_10_n_0 ,\acc_H1_FSK_V[19]_i_11_n_0 ,\acc_H1_FSK_V[19]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[1]),
        .Q(acc_H1_FSK_V[1]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[1]_i_13 
       (.CI(\acc_H1_FSK_V_reg[1]_i_19_n_0 ),
        .CO({\acc_H1_FSK_V_reg[1]_i_13_n_0 ,\acc_H1_FSK_V_reg[1]_i_13_n_1 ,\acc_H1_FSK_V_reg[1]_i_13_n_2 ,\acc_H1_FSK_V_reg[1]_i_13_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__3_n_91,p_0_out__3_n_92,p_0_out__3_n_93,p_0_out__3_n_94}),
        .S({\acc_H1_FSK_V[1]_i_20_n_0 ,\acc_H1_FSK_V[1]_i_21_n_0 ,\acc_H1_FSK_V[1]_i_22_n_0 ,\acc_H1_FSK_V[1]_i_23_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[1]_i_19 
       (.CI(\acc_H1_FSK_V_reg[1]_i_24_n_0 ),
        .CO({\acc_H1_FSK_V_reg[1]_i_19_n_0 ,\acc_H1_FSK_V_reg[1]_i_19_n_1 ,\acc_H1_FSK_V_reg[1]_i_19_n_2 ,\acc_H1_FSK_V_reg[1]_i_19_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__3_n_95,p_0_out__3_n_96,p_0_out__3_n_97,p_0_out__3_n_98}),
        .S({\acc_H1_FSK_V[1]_i_25_n_0 ,\acc_H1_FSK_V[1]_i_26_n_0 ,\acc_H1_FSK_V[1]_i_27_n_0 ,\acc_H1_FSK_V[1]_i_28_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[1]_i_24 
       (.CI(\acc_H1_FSK_V_reg[1]_i_29_n_0 ),
        .CO({\acc_H1_FSK_V_reg[1]_i_24_n_0 ,\acc_H1_FSK_V_reg[1]_i_24_n_1 ,\acc_H1_FSK_V_reg[1]_i_24_n_2 ,\acc_H1_FSK_V_reg[1]_i_24_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__3_n_99,p_0_out__3_n_100,p_0_out__3_n_101,p_0_out__3_n_102}),
        .S({\acc_H1_FSK_V[1]_i_30_n_0 ,\acc_H1_FSK_V[1]_i_31_n_0 ,\acc_H1_FSK_V[1]_i_32_n_0 ,\acc_H1_FSK_V[1]_i_33_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[1]_i_29 
       (.CI(\<const0> ),
        .CO({\acc_H1_FSK_V_reg[1]_i_29_n_0 ,\acc_H1_FSK_V_reg[1]_i_29_n_1 ,\acc_H1_FSK_V_reg[1]_i_29_n_2 ,\acc_H1_FSK_V_reg[1]_i_29_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_0_out__3_n_103,p_0_out__3_n_104,p_0_out__3_n_105,\<const0> }),
        .S({\acc_H1_FSK_V[1]_i_34_n_0 ,\acc_H1_FSK_V[1]_i_35_n_0 ,\acc_H1_FSK_V[1]_i_36_n_0 ,\p_0_out[16]__1_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[1]_i_3 
       (.CI(\acc_H1_FSK_V_reg[1]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[1]_i_3_n_0 ,\acc_H1_FSK_V_reg[1]_i_3_n_1 ,\acc_H1_FSK_V_reg[1]_i_3_n_2 ,\acc_H1_FSK_V_reg[1]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[1]_i_5_n_0 ,\acc_H1_FSK_V[1]_i_6_n_0 ,\acc_H1_FSK_V[1]_i_7_n_0 ,\acc_H1_FSK_V[1]_i_8_n_0 }),
        .O({p_0_out__4[39:38],\NLW_acc_H1_FSK_V_reg[1]_i_3_O_UNCONNECTED [1:0]}),
        .S({\acc_H1_FSK_V[1]_i_9_n_0 ,\acc_H1_FSK_V[1]_i_10_n_0 ,\acc_H1_FSK_V[1]_i_11_n_0 ,\acc_H1_FSK_V[1]_i_12_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[1]_i_4 
       (.CI(\acc_H1_FSK_V_reg[1]_i_13_n_0 ),
        .CO({\acc_H1_FSK_V_reg[1]_i_4_n_0 ,\acc_H1_FSK_V_reg[1]_i_4_n_1 ,\acc_H1_FSK_V_reg[1]_i_4_n_2 ,\acc_H1_FSK_V_reg[1]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[1]_i_14_n_0 ,p_0_out__3_n_88,p_0_out__3_n_89,p_0_out__3_n_90}),
        .S({\acc_H1_FSK_V[1]_i_15_n_0 ,\acc_H1_FSK_V[1]_i_16_n_0 ,\acc_H1_FSK_V[1]_i_17_n_0 ,\acc_H1_FSK_V[1]_i_18_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[20]),
        .Q(acc_H1_FSK_V[20]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[21]),
        .Q(acc_H1_FSK_V[21]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[21]_i_3 
       (.CI(\acc_H1_FSK_V_reg[17]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[21]_i_3_n_0 ,\acc_H1_FSK_V_reg[21]_i_3_n_1 ,\acc_H1_FSK_V_reg[21]_i_3_n_2 ,\acc_H1_FSK_V_reg[21]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[21]_i_4_n_0 ,\acc_H1_FSK_V[21]_i_5_n_0 ,\acc_H1_FSK_V[21]_i_6_n_0 ,\acc_H1_FSK_V[21]_i_7_n_0 }),
        .O(p_0_out__4[59:56]),
        .S({\acc_H1_FSK_V[21]_i_8_n_0 ,\acc_H1_FSK_V[21]_i_9_n_0 ,\acc_H1_FSK_V[21]_i_10_n_0 ,\acc_H1_FSK_V[21]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[22]),
        .Q(acc_H1_FSK_V[22]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[23]),
        .Q(acc_H1_FSK_V[23]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[23]_i_3 
       (.CI(\acc_H1_FSK_V_reg[19]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[23]_i_3_n_0 ,\acc_H1_FSK_V_reg[23]_i_3_n_1 ,\acc_H1_FSK_V_reg[23]_i_3_n_2 ,\acc_H1_FSK_V_reg[23]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[23:20]),
        .O(p_Val2_21_fu_1207_p2[23:20]),
        .S({\acc_H1_FSK_V[23]_i_5_n_0 ,\acc_H1_FSK_V[23]_i_6_n_0 ,\acc_H1_FSK_V[23]_i_7_n_0 ,\acc_H1_FSK_V[23]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[23]_i_4 
       (.CI(\acc_H1_FSK_V_reg[19]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[23]_i_4_n_0 ,\acc_H1_FSK_V_reg[23]_i_4_n_1 ,\acc_H1_FSK_V_reg[23]_i_4_n_2 ,\acc_H1_FSK_V_reg[23]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[23:20]),
        .O(p_Val2_s_14_fu_1229_p2[23:20]),
        .S({\acc_H1_FSK_V[23]_i_9_n_0 ,\acc_H1_FSK_V[23]_i_10_n_0 ,\acc_H1_FSK_V[23]_i_11_n_0 ,\acc_H1_FSK_V[23]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[24]),
        .Q(acc_H1_FSK_V[24]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[25]),
        .Q(acc_H1_FSK_V[25]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[25]_i_3 
       (.CI(\acc_H1_FSK_V_reg[21]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[25]_i_3_n_0 ,\acc_H1_FSK_V_reg[25]_i_3_n_1 ,\acc_H1_FSK_V_reg[25]_i_3_n_2 ,\acc_H1_FSK_V_reg[25]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[25]_i_4_n_0 ,\acc_H1_FSK_V[25]_i_5_n_0 ,\acc_H1_FSK_V[25]_i_6_n_0 ,\acc_H1_FSK_V[25]_i_7_n_0 }),
        .O(p_0_out__4[63:60]),
        .S({\acc_H1_FSK_V[25]_i_8_n_0 ,\acc_H1_FSK_V[25]_i_9_n_0 ,\acc_H1_FSK_V[25]_i_10_n_0 ,\acc_H1_FSK_V[25]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[26]),
        .Q(acc_H1_FSK_V[26]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[27]),
        .Q(acc_H1_FSK_V[27]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[27]_i_3 
       (.CI(\acc_H1_FSK_V_reg[23]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[27]_i_3_n_0 ,\acc_H1_FSK_V_reg[27]_i_3_n_1 ,\acc_H1_FSK_V_reg[27]_i_3_n_2 ,\acc_H1_FSK_V_reg[27]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[27:24]),
        .O(p_Val2_21_fu_1207_p2[27:24]),
        .S({\acc_H1_FSK_V[27]_i_5_n_0 ,\acc_H1_FSK_V[27]_i_6_n_0 ,\acc_H1_FSK_V[27]_i_7_n_0 ,\acc_H1_FSK_V[27]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[27]_i_4 
       (.CI(\acc_H1_FSK_V_reg[23]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[27]_i_4_n_0 ,\acc_H1_FSK_V_reg[27]_i_4_n_1 ,\acc_H1_FSK_V_reg[27]_i_4_n_2 ,\acc_H1_FSK_V_reg[27]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[27:24]),
        .O(p_Val2_s_14_fu_1229_p2[27:24]),
        .S({\acc_H1_FSK_V[27]_i_9_n_0 ,\acc_H1_FSK_V[27]_i_10_n_0 ,\acc_H1_FSK_V[27]_i_11_n_0 ,\acc_H1_FSK_V[27]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[28]),
        .Q(acc_H1_FSK_V[28]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[29]),
        .Q(acc_H1_FSK_V[29]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[29]_i_3 
       (.CI(\acc_H1_FSK_V_reg[25]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[29]_i_3_n_0 ,\acc_H1_FSK_V_reg[29]_i_3_n_1 ,\acc_H1_FSK_V_reg[29]_i_3_n_2 ,\acc_H1_FSK_V_reg[29]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[29]_i_4_n_0 ,\acc_H1_FSK_V[29]_i_5_n_0 ,\acc_H1_FSK_V[29]_i_6_n_0 ,\acc_H1_FSK_V[29]_i_7_n_0 }),
        .O(p_0_out__4[67:64]),
        .S({\acc_H1_FSK_V[29]_i_8_n_0 ,\acc_H1_FSK_V[29]_i_9_n_0 ,\acc_H1_FSK_V[29]_i_10_n_0 ,\acc_H1_FSK_V[29]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[2]),
        .Q(acc_H1_FSK_V[2]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[30]),
        .Q(acc_H1_FSK_V[30]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[31]),
        .Q(acc_H1_FSK_V[31]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[31]_i_3 
       (.CI(\acc_H1_FSK_V_reg[27]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[31]_i_3_n_0 ,\acc_H1_FSK_V_reg[31]_i_3_n_1 ,\acc_H1_FSK_V_reg[31]_i_3_n_2 ,\acc_H1_FSK_V_reg[31]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[31:28]),
        .O(p_Val2_21_fu_1207_p2[31:28]),
        .S({\acc_H1_FSK_V[31]_i_5_n_0 ,\acc_H1_FSK_V[31]_i_6_n_0 ,\acc_H1_FSK_V[31]_i_7_n_0 ,\acc_H1_FSK_V[31]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[31]_i_4 
       (.CI(\acc_H1_FSK_V_reg[27]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[31]_i_4_n_0 ,\acc_H1_FSK_V_reg[31]_i_4_n_1 ,\acc_H1_FSK_V_reg[31]_i_4_n_2 ,\acc_H1_FSK_V_reg[31]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[31:28]),
        .O(p_Val2_s_14_fu_1229_p2[31:28]),
        .S({\acc_H1_FSK_V[31]_i_9_n_0 ,\acc_H1_FSK_V[31]_i_10_n_0 ,\acc_H1_FSK_V[31]_i_11_n_0 ,\acc_H1_FSK_V[31]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[32] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[32]),
        .Q(acc_H1_FSK_V[32]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[33] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[33]),
        .Q(acc_H1_FSK_V[33]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[33]_i_3 
       (.CI(\acc_H1_FSK_V_reg[29]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[33]_i_3_n_0 ,\acc_H1_FSK_V_reg[33]_i_3_n_1 ,\acc_H1_FSK_V_reg[33]_i_3_n_2 ,\acc_H1_FSK_V_reg[33]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[33]_i_4_n_0 ,\acc_H1_FSK_V[33]_i_5_n_0 ,\acc_H1_FSK_V[33]_i_6_n_0 ,\acc_H1_FSK_V[33]_i_7_n_0 }),
        .O(p_0_out__4[71:68]),
        .S({\acc_H1_FSK_V[33]_i_8_n_0 ,\acc_H1_FSK_V[33]_i_9_n_0 ,\acc_H1_FSK_V[33]_i_10_n_0 ,\acc_H1_FSK_V[33]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[34] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[34]),
        .Q(acc_H1_FSK_V[34]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[35] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[35]),
        .Q(acc_H1_FSK_V[35]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[35]_i_3 
       (.CI(\acc_H1_FSK_V_reg[31]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[35]_i_3_n_0 ,\acc_H1_FSK_V_reg[35]_i_3_n_1 ,\acc_H1_FSK_V_reg[35]_i_3_n_2 ,\acc_H1_FSK_V_reg[35]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[35:32]),
        .O(p_Val2_21_fu_1207_p2[35:32]),
        .S({\acc_H1_FSK_V[35]_i_5_n_0 ,\acc_H1_FSK_V[35]_i_6_n_0 ,\acc_H1_FSK_V[35]_i_7_n_0 ,\acc_H1_FSK_V[35]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[35]_i_4 
       (.CI(\acc_H1_FSK_V_reg[31]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[35]_i_4_n_0 ,\acc_H1_FSK_V_reg[35]_i_4_n_1 ,\acc_H1_FSK_V_reg[35]_i_4_n_2 ,\acc_H1_FSK_V_reg[35]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[35:32]),
        .O(p_Val2_s_14_fu_1229_p2[35:32]),
        .S({\acc_H1_FSK_V[35]_i_9_n_0 ,\acc_H1_FSK_V[35]_i_10_n_0 ,\acc_H1_FSK_V[35]_i_11_n_0 ,\acc_H1_FSK_V[35]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[36] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[36]),
        .Q(acc_H1_FSK_V[36]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[37] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[37]),
        .Q(acc_H1_FSK_V[37]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[37]_i_3 
       (.CI(\acc_H1_FSK_V_reg[33]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[37]_i_3_n_0 ,\acc_H1_FSK_V_reg[37]_i_3_n_1 ,\acc_H1_FSK_V_reg[37]_i_3_n_2 ,\acc_H1_FSK_V_reg[37]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[37]_i_4_n_0 ,\acc_H1_FSK_V[37]_i_5_n_0 ,\acc_H1_FSK_V[37]_i_6_n_0 ,\acc_H1_FSK_V[37]_i_7_n_0 }),
        .O(p_0_out__4[75:72]),
        .S({\acc_H1_FSK_V[37]_i_8_n_0 ,\acc_H1_FSK_V[37]_i_9_n_0 ,\acc_H1_FSK_V[37]_i_10_n_0 ,\acc_H1_FSK_V[37]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[38] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[38]),
        .Q(acc_H1_FSK_V[38]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[39] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[39]),
        .Q(acc_H1_FSK_V[39]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[39]_i_3 
       (.CI(\acc_H1_FSK_V_reg[35]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[39]_i_3_n_0 ,\acc_H1_FSK_V_reg[39]_i_3_n_1 ,\acc_H1_FSK_V_reg[39]_i_3_n_2 ,\acc_H1_FSK_V_reg[39]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[39:36]),
        .O(p_Val2_21_fu_1207_p2[39:36]),
        .S({\acc_H1_FSK_V[39]_i_5_n_0 ,\acc_H1_FSK_V[39]_i_6_n_0 ,\acc_H1_FSK_V[39]_i_7_n_0 ,\acc_H1_FSK_V[39]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[39]_i_4 
       (.CI(\acc_H1_FSK_V_reg[35]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[39]_i_4_n_0 ,\acc_H1_FSK_V_reg[39]_i_4_n_1 ,\acc_H1_FSK_V_reg[39]_i_4_n_2 ,\acc_H1_FSK_V_reg[39]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[39:36]),
        .O(p_Val2_s_14_fu_1229_p2[39:36]),
        .S({\acc_H1_FSK_V[39]_i_9_n_0 ,\acc_H1_FSK_V[39]_i_10_n_0 ,\acc_H1_FSK_V[39]_i_11_n_0 ,\acc_H1_FSK_V[39]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[3]),
        .Q(acc_H1_FSK_V[3]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[3]_i_3 
       (.CI(\<const0> ),
        .CO({\acc_H1_FSK_V_reg[3]_i_3_n_0 ,\acc_H1_FSK_V_reg[3]_i_3_n_1 ,\acc_H1_FSK_V_reg[3]_i_3_n_2 ,\acc_H1_FSK_V_reg[3]_i_3_n_3 }),
        .CYINIT(\<const1> ),
        .DI(acc_H1_FSK_V[3:0]),
        .O(p_Val2_21_fu_1207_p2[3:0]),
        .S({\acc_H1_FSK_V[3]_i_5_n_0 ,\acc_H1_FSK_V[3]_i_6_n_0 ,\acc_H1_FSK_V[3]_i_7_n_0 ,\acc_H1_FSK_V[3]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[3]_i_4 
       (.CI(\<const0> ),
        .CO({\acc_H1_FSK_V_reg[3]_i_4_n_0 ,\acc_H1_FSK_V_reg[3]_i_4_n_1 ,\acc_H1_FSK_V_reg[3]_i_4_n_2 ,\acc_H1_FSK_V_reg[3]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[3:0]),
        .O(p_Val2_s_14_fu_1229_p2[3:0]),
        .S({\acc_H1_FSK_V[3]_i_9_n_0 ,\acc_H1_FSK_V[3]_i_10_n_0 ,\acc_H1_FSK_V[3]_i_11_n_0 ,\acc_H1_FSK_V[3]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[40] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[40]),
        .Q(acc_H1_FSK_V[40]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[41] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[41]),
        .Q(acc_H1_FSK_V[41]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[41]_i_21 
       (.CI(\acc_H1_FSK_V_reg[41]_i_30_n_0 ),
        .CO({\acc_H1_FSK_V_reg[41]_i_21_n_0 ,\acc_H1_FSK_V_reg[41]_i_21_n_1 ,\acc_H1_FSK_V_reg[41]_i_21_n_2 ,\acc_H1_FSK_V_reg[41]_i_21_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[41]_i_31_n_0 ,\acc_H1_FSK_V[41]_i_32_n_0 ,\acc_H1_FSK_V[41]_i_33_n_0 ,\acc_H1_FSK_V[41]_i_34_n_0 }),
        .S({\acc_H1_FSK_V[41]_i_35_n_0 ,\acc_H1_FSK_V[41]_i_36_n_0 ,\acc_H1_FSK_V[41]_i_37_n_0 ,\acc_H1_FSK_V[41]_i_38_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[41]_i_3 
       (.CI(\acc_H1_FSK_V_reg[41]_i_5_n_0 ),
        .CO({tmp_15_fu_1198_p2,\acc_H1_FSK_V_reg[41]_i_3_n_1 ,\acc_H1_FSK_V_reg[41]_i_3_n_2 ,\acc_H1_FSK_V_reg[41]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[41]_i_6_n_0 ,\acc_H1_FSK_V[41]_i_7_n_0 ,\acc_H1_FSK_V[41]_i_8_n_0 ,\acc_H1_FSK_V[41]_i_9_n_0 }),
        .S({\acc_H1_FSK_V[41]_i_10_n_0 ,\acc_H1_FSK_V[41]_i_11_n_0 ,\acc_H1_FSK_V[41]_i_12_n_0 ,\acc_H1_FSK_V[41]_i_13_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[41]_i_30 
       (.CI(\<const0> ),
        .CO({\acc_H1_FSK_V_reg[41]_i_30_n_0 ,\acc_H1_FSK_V_reg[41]_i_30_n_1 ,\acc_H1_FSK_V_reg[41]_i_30_n_2 ,\acc_H1_FSK_V_reg[41]_i_30_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[41]_i_39_n_0 ,\acc_H1_FSK_V[41]_i_40_n_0 ,\acc_H1_FSK_V[41]_i_41_n_0 ,\acc_H1_FSK_V[41]_i_42_n_0 }),
        .S({\acc_H1_FSK_V[41]_i_43_n_0 ,\acc_H1_FSK_V[41]_i_44_n_0 ,\acc_H1_FSK_V[41]_i_45_n_0 ,\acc_H1_FSK_V[41]_i_46_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[41]_i_4 
       (.CI(\acc_H1_FSK_V_reg[37]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[41]_i_4_n_1 ,\acc_H1_FSK_V_reg[41]_i_4_n_2 ,\acc_H1_FSK_V_reg[41]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\acc_H1_FSK_V[41]_i_14_n_0 ,\acc_H1_FSK_V[41]_i_15_n_0 ,\acc_H1_FSK_V[41]_i_16_n_0 }),
        .O(p_0_out__4[79:76]),
        .S({\acc_H1_FSK_V[41]_i_17_n_0 ,\acc_H1_FSK_V[41]_i_18_n_0 ,\acc_H1_FSK_V[41]_i_19_n_0 ,\acc_H1_FSK_V[41]_i_20_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[41]_i_5 
       (.CI(\acc_H1_FSK_V_reg[41]_i_21_n_0 ),
        .CO({\acc_H1_FSK_V_reg[41]_i_5_n_0 ,\acc_H1_FSK_V_reg[41]_i_5_n_1 ,\acc_H1_FSK_V_reg[41]_i_5_n_2 ,\acc_H1_FSK_V_reg[41]_i_5_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[41]_i_22_n_0 ,\acc_H1_FSK_V[41]_i_23_n_0 ,\acc_H1_FSK_V[41]_i_24_n_0 ,\acc_H1_FSK_V[41]_i_25_n_0 }),
        .S({\acc_H1_FSK_V[41]_i_26_n_0 ,\acc_H1_FSK_V[41]_i_27_n_0 ,\acc_H1_FSK_V[41]_i_28_n_0 ,\acc_H1_FSK_V[41]_i_29_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[42] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(\acc_H1_FSK_V[42]_i_1_n_0 ),
        .Q(acc_H1_FSK_V[42]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[43] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(\acc_H1_FSK_V[43]_i_1_n_0 ),
        .Q(acc_H1_FSK_V[43]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[43]_i_3 
       (.CI(\acc_H1_FSK_V_reg[39]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[43]_i_3_n_0 ,\acc_H1_FSK_V_reg[43]_i_3_n_1 ,\acc_H1_FSK_V_reg[43]_i_3_n_2 ,\acc_H1_FSK_V_reg[43]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[43:40]),
        .O(p_Val2_21_fu_1207_p2[43:40]),
        .S({\acc_H1_FSK_V[43]_i_5_n_0 ,\acc_H1_FSK_V[43]_i_6_n_0 ,\acc_H1_FSK_V[43]_i_7_n_0 ,\acc_H1_FSK_V[43]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[43]_i_4 
       (.CI(\acc_H1_FSK_V_reg[39]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[43]_i_4_n_0 ,\acc_H1_FSK_V_reg[43]_i_4_n_1 ,\acc_H1_FSK_V_reg[43]_i_4_n_2 ,\acc_H1_FSK_V_reg[43]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,acc_H1_FSK_V[41:40]}),
        .O(p_Val2_s_14_fu_1229_p2[43:40]),
        .S({acc_H1_FSK_V[43:42],\acc_H1_FSK_V[43]_i_9_n_0 ,\acc_H1_FSK_V[43]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[44] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(\acc_H1_FSK_V[44]_i_1_n_0 ),
        .Q(acc_H1_FSK_V[44]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[45] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(\acc_H1_FSK_V[45]_i_1_n_0 ),
        .Q(acc_H1_FSK_V[45]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[46] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(\acc_H1_FSK_V[46]_i_1_n_0 ),
        .Q(acc_H1_FSK_V[46]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[47] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(\acc_H1_FSK_V[47]_i_3_n_0 ),
        .Q(acc_H1_FSK_V[47]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[47]_i_6 
       (.CI(\acc_H1_FSK_V_reg[43]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[47]_i_6_n_1 ,\acc_H1_FSK_V_reg[47]_i_6_n_2 ,\acc_H1_FSK_V_reg[47]_i_6_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,acc_H1_FSK_V[46:44]}),
        .O(p_Val2_21_fu_1207_p2[47:44]),
        .S({\acc_H1_FSK_V[47]_i_8_n_0 ,\acc_H1_FSK_V[47]_i_9_n_0 ,\acc_H1_FSK_V[47]_i_10_n_0 ,\acc_H1_FSK_V[47]_i_11_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[47]_i_7 
       (.CI(\acc_H1_FSK_V_reg[43]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[47]_i_7_n_1 ,\acc_H1_FSK_V_reg[47]_i_7_n_2 ,\acc_H1_FSK_V_reg[47]_i_7_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(p_Val2_s_14_fu_1229_p2[47:44]),
        .S(acc_H1_FSK_V[47:44]));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[4]),
        .Q(acc_H1_FSK_V[4]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[5]),
        .Q(acc_H1_FSK_V[5]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[5]_i_3 
       (.CI(\acc_H1_FSK_V_reg[1]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[5]_i_3_n_0 ,\acc_H1_FSK_V_reg[5]_i_3_n_1 ,\acc_H1_FSK_V_reg[5]_i_3_n_2 ,\acc_H1_FSK_V_reg[5]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[5]_i_4_n_0 ,\acc_H1_FSK_V[5]_i_5_n_0 ,\acc_H1_FSK_V[5]_i_6_n_0 ,\acc_H1_FSK_V[5]_i_7_n_0 }),
        .O(p_0_out__4[43:40]),
        .S({\acc_H1_FSK_V[5]_i_8_n_0 ,\acc_H1_FSK_V[5]_i_9_n_0 ,\acc_H1_FSK_V[5]_i_10_n_0 ,\acc_H1_FSK_V[5]_i_11_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[6]),
        .Q(acc_H1_FSK_V[6]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[7]),
        .Q(acc_H1_FSK_V[7]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[7]_i_3 
       (.CI(\acc_H1_FSK_V_reg[3]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[7]_i_3_n_0 ,\acc_H1_FSK_V_reg[7]_i_3_n_1 ,\acc_H1_FSK_V_reg[7]_i_3_n_2 ,\acc_H1_FSK_V_reg[7]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[7:4]),
        .O(p_Val2_21_fu_1207_p2[7:4]),
        .S({\acc_H1_FSK_V[7]_i_5_n_0 ,\acc_H1_FSK_V[7]_i_6_n_0 ,\acc_H1_FSK_V[7]_i_7_n_0 ,\acc_H1_FSK_V[7]_i_8_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[7]_i_4 
       (.CI(\acc_H1_FSK_V_reg[3]_i_4_n_0 ),
        .CO({\acc_H1_FSK_V_reg[7]_i_4_n_0 ,\acc_H1_FSK_V_reg[7]_i_4_n_1 ,\acc_H1_FSK_V_reg[7]_i_4_n_2 ,\acc_H1_FSK_V_reg[7]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(acc_H1_FSK_V[7:4]),
        .O(p_Val2_s_14_fu_1229_p2[7:4]),
        .S({\acc_H1_FSK_V[7]_i_9_n_0 ,\acc_H1_FSK_V[7]_i_10_n_0 ,\acc_H1_FSK_V[7]_i_11_n_0 ,\acc_H1_FSK_V[7]_i_12_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[8]),
        .Q(acc_H1_FSK_V[8]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_FSK_V_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_FSK_V0),
        .D(p_1_in[9]),
        .Q(acc_H1_FSK_V[9]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_FSK_V_reg[9]_i_3 
       (.CI(\acc_H1_FSK_V_reg[5]_i_3_n_0 ),
        .CO({\acc_H1_FSK_V_reg[9]_i_3_n_0 ,\acc_H1_FSK_V_reg[9]_i_3_n_1 ,\acc_H1_FSK_V_reg[9]_i_3_n_2 ,\acc_H1_FSK_V_reg[9]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_FSK_V[9]_i_4_n_0 ,\acc_H1_FSK_V[9]_i_5_n_0 ,\acc_H1_FSK_V[9]_i_6_n_0 ,\acc_H1_FSK_V[9]_i_7_n_0 }),
        .O(p_0_out__4[47:44]),
        .S({\acc_H1_FSK_V[9]_i_8_n_0 ,\acc_H1_FSK_V[9]_i_9_n_0 ,\acc_H1_FSK_V[9]_i_10_n_0 ,\acc_H1_FSK_V[9]_i_11_n_0 }));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \acc_H1_V[0]_i_1 
       (.I0(ap_rst),
        .I1(ap_enable_reg_pp0_iter3),
        .I2(p_Val2_4_reg_1510),
        .I3(tmp_22_reg_1544),
        .O(acc_H1_prog_V));
  LUT2 #(
    .INIT(4'h8)) 
    \acc_H1_V[0]_i_2 
       (.I0(p_Val2_4_reg_1510),
        .I1(ap_enable_reg_pp0_iter3),
        .O(acc_H1_V0));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[0]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I1(acc_H1_V_reg[3]),
        .O(\acc_H1_V[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[0]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .I1(acc_H1_V_reg[2]),
        .O(\acc_H1_V[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[0]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I1(acc_H1_V_reg[1]),
        .O(\acc_H1_V[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[0]_i_7 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .I1(acc_H1_V_reg[0]),
        .O(\acc_H1_V[0]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[12]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I1(acc_H1_V_reg[15]),
        .O(\acc_H1_V[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[12]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .I1(acc_H1_V_reg[14]),
        .O(\acc_H1_V[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[12]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I1(acc_H1_V_reg[13]),
        .O(\acc_H1_V[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[12]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .I1(acc_H1_V_reg[12]),
        .O(\acc_H1_V[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[16]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I1(acc_H1_V_reg[19]),
        .O(\acc_H1_V[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[16]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .I1(acc_H1_V_reg[18]),
        .O(\acc_H1_V[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[16]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I1(acc_H1_V_reg[17]),
        .O(\acc_H1_V[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[16]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .I1(acc_H1_V_reg[16]),
        .O(\acc_H1_V[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[20]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I1(acc_H1_V_reg[23]),
        .O(\acc_H1_V[20]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[20]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .I1(acc_H1_V_reg[22]),
        .O(\acc_H1_V[20]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[20]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I1(acc_H1_V_reg[21]),
        .O(\acc_H1_V[20]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[20]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .I1(acc_H1_V_reg[20]),
        .O(\acc_H1_V[20]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[24]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I1(acc_H1_V_reg[27]),
        .O(\acc_H1_V[24]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[24]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .I1(acc_H1_V_reg[26]),
        .O(\acc_H1_V[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[24]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I1(acc_H1_V_reg[25]),
        .O(\acc_H1_V[24]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[24]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .I1(acc_H1_V_reg[24]),
        .O(\acc_H1_V[24]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[28]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I1(acc_H1_V_reg[31]),
        .O(\acc_H1_V[28]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[28]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .I1(acc_H1_V_reg[30]),
        .O(\acc_H1_V[28]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[28]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I1(acc_H1_V_reg[29]),
        .O(\acc_H1_V[28]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[28]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .I1(acc_H1_V_reg[28]),
        .O(\acc_H1_V[28]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[32]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I1(acc_H1_V_reg[35]),
        .O(\acc_H1_V[32]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[32]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .I1(acc_H1_V_reg[34]),
        .O(\acc_H1_V[32]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[32]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I1(acc_H1_V_reg[33]),
        .O(\acc_H1_V[32]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[32]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .I1(acc_H1_V_reg[32]),
        .O(\acc_H1_V[32]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[36]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I1(acc_H1_V_reg[39]),
        .O(\acc_H1_V[36]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[36]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .I1(acc_H1_V_reg[38]),
        .O(\acc_H1_V[36]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[36]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I1(acc_H1_V_reg[37]),
        .O(\acc_H1_V[36]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[36]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .I1(acc_H1_V_reg[36]),
        .O(\acc_H1_V[36]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[40]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I1(acc_H1_V_reg[43]),
        .O(\acc_H1_V[40]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[40]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .I1(acc_H1_V_reg[42]),
        .O(\acc_H1_V[40]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[40]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I1(acc_H1_V_reg[41]),
        .O(\acc_H1_V[40]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[40]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .I1(acc_H1_V_reg[40]),
        .O(\acc_H1_V[40]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[44]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I1(acc_H1_V_reg[47]),
        .O(\acc_H1_V[44]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[44]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .I1(acc_H1_V_reg[46]),
        .O(\acc_H1_V[44]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[44]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I1(acc_H1_V_reg[45]),
        .O(\acc_H1_V[44]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[44]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .I1(acc_H1_V_reg[44]),
        .O(\acc_H1_V[44]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[4]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I1(acc_H1_V_reg[7]),
        .O(\acc_H1_V[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[4]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .I1(acc_H1_V_reg[6]),
        .O(\acc_H1_V[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[4]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I1(acc_H1_V_reg[5]),
        .O(\acc_H1_V[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[4]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .I1(acc_H1_V_reg[4]),
        .O(\acc_H1_V[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[8]_i_2 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I1(acc_H1_V_reg[11]),
        .O(\acc_H1_V[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[8]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .I1(acc_H1_V_reg[10]),
        .O(\acc_H1_V[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[8]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I1(acc_H1_V_reg[9]),
        .O(\acc_H1_V[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_V[8]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .I1(acc_H1_V_reg[8]),
        .O(\acc_H1_V[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[0]_i_3_n_7 ),
        .Q(acc_H1_V_reg[0]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[0]_i_3 
       (.CI(\<const0> ),
        .CO({\acc_H1_V_reg[0]_i_3_n_0 ,\acc_H1_V_reg[0]_i_3_n_1 ,\acc_H1_V_reg[0]_i_3_n_2 ,\acc_H1_V_reg[0]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3:0]),
        .O({\acc_H1_V_reg[0]_i_3_n_4 ,\acc_H1_V_reg[0]_i_3_n_5 ,\acc_H1_V_reg[0]_i_3_n_6 ,\acc_H1_V_reg[0]_i_3_n_7 }),
        .S({\acc_H1_V[0]_i_4_n_0 ,\acc_H1_V[0]_i_5_n_0 ,\acc_H1_V[0]_i_6_n_0 ,\acc_H1_V[0]_i_7_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[8]_i_1_n_5 ),
        .Q(acc_H1_V_reg[10]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[8]_i_1_n_4 ),
        .Q(acc_H1_V_reg[11]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[12]_i_1_n_7 ),
        .Q(acc_H1_V_reg[12]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[12]_i_1 
       (.CI(\acc_H1_V_reg[8]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[12]_i_1_n_0 ,\acc_H1_V_reg[12]_i_1_n_1 ,\acc_H1_V_reg[12]_i_1_n_2 ,\acc_H1_V_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15:12]),
        .O({\acc_H1_V_reg[12]_i_1_n_4 ,\acc_H1_V_reg[12]_i_1_n_5 ,\acc_H1_V_reg[12]_i_1_n_6 ,\acc_H1_V_reg[12]_i_1_n_7 }),
        .S({\acc_H1_V[12]_i_2_n_0 ,\acc_H1_V[12]_i_3_n_0 ,\acc_H1_V[12]_i_4_n_0 ,\acc_H1_V[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[12]_i_1_n_6 ),
        .Q(acc_H1_V_reg[13]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[12]_i_1_n_5 ),
        .Q(acc_H1_V_reg[14]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[12]_i_1_n_4 ),
        .Q(acc_H1_V_reg[15]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[16]_i_1_n_7 ),
        .Q(acc_H1_V_reg[16]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[16]_i_1 
       (.CI(\acc_H1_V_reg[12]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[16]_i_1_n_0 ,\acc_H1_V_reg[16]_i_1_n_1 ,\acc_H1_V_reg[16]_i_1_n_2 ,\acc_H1_V_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19:16]),
        .O({\acc_H1_V_reg[16]_i_1_n_4 ,\acc_H1_V_reg[16]_i_1_n_5 ,\acc_H1_V_reg[16]_i_1_n_6 ,\acc_H1_V_reg[16]_i_1_n_7 }),
        .S({\acc_H1_V[16]_i_2_n_0 ,\acc_H1_V[16]_i_3_n_0 ,\acc_H1_V[16]_i_4_n_0 ,\acc_H1_V[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[16]_i_1_n_6 ),
        .Q(acc_H1_V_reg[17]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[16]_i_1_n_5 ),
        .Q(acc_H1_V_reg[18]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[16]_i_1_n_4 ),
        .Q(acc_H1_V_reg[19]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[0]_i_3_n_6 ),
        .Q(acc_H1_V_reg[1]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[20]_i_1_n_7 ),
        .Q(acc_H1_V_reg[20]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[20]_i_1 
       (.CI(\acc_H1_V_reg[16]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[20]_i_1_n_0 ,\acc_H1_V_reg[20]_i_1_n_1 ,\acc_H1_V_reg[20]_i_1_n_2 ,\acc_H1_V_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23:20]),
        .O({\acc_H1_V_reg[20]_i_1_n_4 ,\acc_H1_V_reg[20]_i_1_n_5 ,\acc_H1_V_reg[20]_i_1_n_6 ,\acc_H1_V_reg[20]_i_1_n_7 }),
        .S({\acc_H1_V[20]_i_2_n_0 ,\acc_H1_V[20]_i_3_n_0 ,\acc_H1_V[20]_i_4_n_0 ,\acc_H1_V[20]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[20]_i_1_n_6 ),
        .Q(acc_H1_V_reg[21]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[20]_i_1_n_5 ),
        .Q(acc_H1_V_reg[22]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[20]_i_1_n_4 ),
        .Q(acc_H1_V_reg[23]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[24]_i_1_n_7 ),
        .Q(acc_H1_V_reg[24]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[24]_i_1 
       (.CI(\acc_H1_V_reg[20]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[24]_i_1_n_0 ,\acc_H1_V_reg[24]_i_1_n_1 ,\acc_H1_V_reg[24]_i_1_n_2 ,\acc_H1_V_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27:24]),
        .O({\acc_H1_V_reg[24]_i_1_n_4 ,\acc_H1_V_reg[24]_i_1_n_5 ,\acc_H1_V_reg[24]_i_1_n_6 ,\acc_H1_V_reg[24]_i_1_n_7 }),
        .S({\acc_H1_V[24]_i_2_n_0 ,\acc_H1_V[24]_i_3_n_0 ,\acc_H1_V[24]_i_4_n_0 ,\acc_H1_V[24]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[24]_i_1_n_6 ),
        .Q(acc_H1_V_reg[25]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[24]_i_1_n_5 ),
        .Q(acc_H1_V_reg[26]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[24]_i_1_n_4 ),
        .Q(acc_H1_V_reg[27]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[28]_i_1_n_7 ),
        .Q(acc_H1_V_reg[28]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[28]_i_1 
       (.CI(\acc_H1_V_reg[24]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[28]_i_1_n_0 ,\acc_H1_V_reg[28]_i_1_n_1 ,\acc_H1_V_reg[28]_i_1_n_2 ,\acc_H1_V_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31:28]),
        .O({\acc_H1_V_reg[28]_i_1_n_4 ,\acc_H1_V_reg[28]_i_1_n_5 ,\acc_H1_V_reg[28]_i_1_n_6 ,\acc_H1_V_reg[28]_i_1_n_7 }),
        .S({\acc_H1_V[28]_i_2_n_0 ,\acc_H1_V[28]_i_3_n_0 ,\acc_H1_V[28]_i_4_n_0 ,\acc_H1_V[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[28]_i_1_n_6 ),
        .Q(acc_H1_V_reg[29]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[0]_i_3_n_5 ),
        .Q(acc_H1_V_reg[2]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[28]_i_1_n_5 ),
        .Q(acc_H1_V_reg[30]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[28]_i_1_n_4 ),
        .Q(acc_H1_V_reg[31]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[32] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[32]_i_1_n_7 ),
        .Q(acc_H1_V_reg[32]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[32]_i_1 
       (.CI(\acc_H1_V_reg[28]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[32]_i_1_n_0 ,\acc_H1_V_reg[32]_i_1_n_1 ,\acc_H1_V_reg[32]_i_1_n_2 ,\acc_H1_V_reg[32]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35:32]),
        .O({\acc_H1_V_reg[32]_i_1_n_4 ,\acc_H1_V_reg[32]_i_1_n_5 ,\acc_H1_V_reg[32]_i_1_n_6 ,\acc_H1_V_reg[32]_i_1_n_7 }),
        .S({\acc_H1_V[32]_i_2_n_0 ,\acc_H1_V[32]_i_3_n_0 ,\acc_H1_V[32]_i_4_n_0 ,\acc_H1_V[32]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[33] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[32]_i_1_n_6 ),
        .Q(acc_H1_V_reg[33]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[34] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[32]_i_1_n_5 ),
        .Q(acc_H1_V_reg[34]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[35] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[32]_i_1_n_4 ),
        .Q(acc_H1_V_reg[35]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[36] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[36]_i_1_n_7 ),
        .Q(acc_H1_V_reg[36]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[36]_i_1 
       (.CI(\acc_H1_V_reg[32]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[36]_i_1_n_0 ,\acc_H1_V_reg[36]_i_1_n_1 ,\acc_H1_V_reg[36]_i_1_n_2 ,\acc_H1_V_reg[36]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39:36]),
        .O({\acc_H1_V_reg[36]_i_1_n_4 ,\acc_H1_V_reg[36]_i_1_n_5 ,\acc_H1_V_reg[36]_i_1_n_6 ,\acc_H1_V_reg[36]_i_1_n_7 }),
        .S({\acc_H1_V[36]_i_2_n_0 ,\acc_H1_V[36]_i_3_n_0 ,\acc_H1_V[36]_i_4_n_0 ,\acc_H1_V[36]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[37] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[36]_i_1_n_6 ),
        .Q(acc_H1_V_reg[37]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[38] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[36]_i_1_n_5 ),
        .Q(acc_H1_V_reg[38]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[39] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[36]_i_1_n_4 ),
        .Q(acc_H1_V_reg[39]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[0]_i_3_n_4 ),
        .Q(acc_H1_V_reg[3]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[40] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[40]_i_1_n_7 ),
        .Q(acc_H1_V_reg[40]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[40]_i_1 
       (.CI(\acc_H1_V_reg[36]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[40]_i_1_n_0 ,\acc_H1_V_reg[40]_i_1_n_1 ,\acc_H1_V_reg[40]_i_1_n_2 ,\acc_H1_V_reg[40]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43:40]),
        .O({\acc_H1_V_reg[40]_i_1_n_4 ,\acc_H1_V_reg[40]_i_1_n_5 ,\acc_H1_V_reg[40]_i_1_n_6 ,\acc_H1_V_reg[40]_i_1_n_7 }),
        .S({\acc_H1_V[40]_i_2_n_0 ,\acc_H1_V[40]_i_3_n_0 ,\acc_H1_V[40]_i_4_n_0 ,\acc_H1_V[40]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[41] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[40]_i_1_n_6 ),
        .Q(acc_H1_V_reg[41]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[42] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[40]_i_1_n_5 ),
        .Q(acc_H1_V_reg[42]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[43] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[40]_i_1_n_4 ),
        .Q(acc_H1_V_reg[43]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[44] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[44]_i_1_n_7 ),
        .Q(acc_H1_V_reg[44]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[44]_i_1 
       (.CI(\acc_H1_V_reg[40]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[44]_i_1_n_1 ,\acc_H1_V_reg[44]_i_1_n_2 ,\acc_H1_V_reg[44]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46:44]}),
        .O({\acc_H1_V_reg[44]_i_1_n_4 ,\acc_H1_V_reg[44]_i_1_n_5 ,\acc_H1_V_reg[44]_i_1_n_6 ,\acc_H1_V_reg[44]_i_1_n_7 }),
        .S({\acc_H1_V[44]_i_2_n_0 ,\acc_H1_V[44]_i_3_n_0 ,\acc_H1_V[44]_i_4_n_0 ,\acc_H1_V[44]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[45] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[44]_i_1_n_6 ),
        .Q(acc_H1_V_reg[45]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[46] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[44]_i_1_n_5 ),
        .Q(acc_H1_V_reg[46]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[47] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[44]_i_1_n_4 ),
        .Q(acc_H1_V_reg[47]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[4]_i_1_n_7 ),
        .Q(acc_H1_V_reg[4]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[4]_i_1 
       (.CI(\acc_H1_V_reg[0]_i_3_n_0 ),
        .CO({\acc_H1_V_reg[4]_i_1_n_0 ,\acc_H1_V_reg[4]_i_1_n_1 ,\acc_H1_V_reg[4]_i_1_n_2 ,\acc_H1_V_reg[4]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7:4]),
        .O({\acc_H1_V_reg[4]_i_1_n_4 ,\acc_H1_V_reg[4]_i_1_n_5 ,\acc_H1_V_reg[4]_i_1_n_6 ,\acc_H1_V_reg[4]_i_1_n_7 }),
        .S({\acc_H1_V[4]_i_2_n_0 ,\acc_H1_V[4]_i_3_n_0 ,\acc_H1_V[4]_i_4_n_0 ,\acc_H1_V[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[4]_i_1_n_6 ),
        .Q(acc_H1_V_reg[5]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[4]_i_1_n_5 ),
        .Q(acc_H1_V_reg[6]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[4]_i_1_n_4 ),
        .Q(acc_H1_V_reg[7]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[8]_i_1_n_7 ),
        .Q(acc_H1_V_reg[8]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_V_reg[8]_i_1 
       (.CI(\acc_H1_V_reg[4]_i_1_n_0 ),
        .CO({\acc_H1_V_reg[8]_i_1_n_0 ,\acc_H1_V_reg[8]_i_1_n_1 ,\acc_H1_V_reg[8]_i_1_n_2 ,\acc_H1_V_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11:8]),
        .O({\acc_H1_V_reg[8]_i_1_n_4 ,\acc_H1_V_reg[8]_i_1_n_5 ,\acc_H1_V_reg[8]_i_1_n_6 ,\acc_H1_V_reg[8]_i_1_n_7 }),
        .S({\acc_H1_V[8]_i_2_n_0 ,\acc_H1_V[8]_i_3_n_0 ,\acc_H1_V[8]_i_4_n_0 ,\acc_H1_V[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_V_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_V_reg[8]_i_1_n_6 ),
        .Q(acc_H1_V_reg[9]),
        .R(acc_H1_prog_V));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[0]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[3] ),
        .I1(acc_H1_prog_V_reg[3]),
        .O(\acc_H1_prog_V[0]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[0]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[2] ),
        .I1(acc_H1_prog_V_reg[2]),
        .O(\acc_H1_prog_V[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[0]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[1] ),
        .I1(acc_H1_prog_V_reg[1]),
        .O(\acc_H1_prog_V[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[0]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[0] ),
        .I1(acc_H1_prog_V_reg[0]),
        .O(\acc_H1_prog_V[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[12]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[15] ),
        .I1(acc_H1_prog_V_reg[15]),
        .O(\acc_H1_prog_V[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[12]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[14] ),
        .I1(acc_H1_prog_V_reg[14]),
        .O(\acc_H1_prog_V[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[12]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[13] ),
        .I1(acc_H1_prog_V_reg[13]),
        .O(\acc_H1_prog_V[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[12]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[12] ),
        .I1(acc_H1_prog_V_reg[12]),
        .O(\acc_H1_prog_V[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[16]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[19] ),
        .I1(acc_H1_prog_V_reg[19]),
        .O(\acc_H1_prog_V[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[16]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[18] ),
        .I1(acc_H1_prog_V_reg[18]),
        .O(\acc_H1_prog_V[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[16]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[17] ),
        .I1(acc_H1_prog_V_reg[17]),
        .O(\acc_H1_prog_V[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[16]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[16] ),
        .I1(acc_H1_prog_V_reg[16]),
        .O(\acc_H1_prog_V[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[20]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[23] ),
        .I1(acc_H1_prog_V_reg[23]),
        .O(\acc_H1_prog_V[20]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[20]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[22] ),
        .I1(acc_H1_prog_V_reg[22]),
        .O(\acc_H1_prog_V[20]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[20]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[21] ),
        .I1(acc_H1_prog_V_reg[21]),
        .O(\acc_H1_prog_V[20]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[20]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[20] ),
        .I1(acc_H1_prog_V_reg[20]),
        .O(\acc_H1_prog_V[20]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[24]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[27] ),
        .I1(acc_H1_prog_V_reg[27]),
        .O(\acc_H1_prog_V[24]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[24]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[26] ),
        .I1(acc_H1_prog_V_reg[26]),
        .O(\acc_H1_prog_V[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[24]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[25] ),
        .I1(acc_H1_prog_V_reg[25]),
        .O(\acc_H1_prog_V[24]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[24]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[24] ),
        .I1(acc_H1_prog_V_reg[24]),
        .O(\acc_H1_prog_V[24]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[28]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[31] ),
        .I1(acc_H1_prog_V_reg[31]),
        .O(\acc_H1_prog_V[28]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[28]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[30] ),
        .I1(acc_H1_prog_V_reg[30]),
        .O(\acc_H1_prog_V[28]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[28]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[29] ),
        .I1(acc_H1_prog_V_reg[29]),
        .O(\acc_H1_prog_V[28]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[28]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[28] ),
        .I1(acc_H1_prog_V_reg[28]),
        .O(\acc_H1_prog_V[28]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[32]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[35] ),
        .I1(acc_H1_prog_V_reg[35]),
        .O(\acc_H1_prog_V[32]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[32]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[34] ),
        .I1(acc_H1_prog_V_reg[34]),
        .O(\acc_H1_prog_V[32]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[32]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[33] ),
        .I1(acc_H1_prog_V_reg[33]),
        .O(\acc_H1_prog_V[32]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[32]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[32] ),
        .I1(acc_H1_prog_V_reg[32]),
        .O(\acc_H1_prog_V[32]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[36]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[39] ),
        .I1(acc_H1_prog_V_reg[39]),
        .O(\acc_H1_prog_V[36]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[36]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[38] ),
        .I1(acc_H1_prog_V_reg[38]),
        .O(\acc_H1_prog_V[36]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[36]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[37] ),
        .I1(acc_H1_prog_V_reg[37]),
        .O(\acc_H1_prog_V[36]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[36]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[36] ),
        .I1(acc_H1_prog_V_reg[36]),
        .O(\acc_H1_prog_V[36]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[40]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[43] ),
        .I1(acc_H1_prog_V_reg[43]),
        .O(\acc_H1_prog_V[40]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[40]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[42] ),
        .I1(acc_H1_prog_V_reg[42]),
        .O(\acc_H1_prog_V[40]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[40]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[41] ),
        .I1(acc_H1_prog_V_reg[41]),
        .O(\acc_H1_prog_V[40]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[40]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[40] ),
        .I1(acc_H1_prog_V_reg[40]),
        .O(\acc_H1_prog_V[40]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[44]_i_2 
       (.I0(acc_H1_prog_V_reg[47]),
        .I1(\inputs_current_ftw_H_reg_n_0_[47] ),
        .O(\acc_H1_prog_V[44]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[44]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[46] ),
        .I1(acc_H1_prog_V_reg[46]),
        .O(\acc_H1_prog_V[44]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[44]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[45] ),
        .I1(acc_H1_prog_V_reg[45]),
        .O(\acc_H1_prog_V[44]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[44]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[44] ),
        .I1(acc_H1_prog_V_reg[44]),
        .O(\acc_H1_prog_V[44]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[4]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[7] ),
        .I1(acc_H1_prog_V_reg[7]),
        .O(\acc_H1_prog_V[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[4]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[6] ),
        .I1(acc_H1_prog_V_reg[6]),
        .O(\acc_H1_prog_V[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[4]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[5] ),
        .I1(acc_H1_prog_V_reg[5]),
        .O(\acc_H1_prog_V[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[4]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[4] ),
        .I1(acc_H1_prog_V_reg[4]),
        .O(\acc_H1_prog_V[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[8]_i_2 
       (.I0(\inputs_current_ftw_H_reg_n_0_[11] ),
        .I1(acc_H1_prog_V_reg[11]),
        .O(\acc_H1_prog_V[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[8]_i_3 
       (.I0(\inputs_current_ftw_H_reg_n_0_[10] ),
        .I1(acc_H1_prog_V_reg[10]),
        .O(\acc_H1_prog_V[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[8]_i_4 
       (.I0(\inputs_current_ftw_H_reg_n_0_[9] ),
        .I1(acc_H1_prog_V_reg[9]),
        .O(\acc_H1_prog_V[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_prog_V[8]_i_5 
       (.I0(\inputs_current_ftw_H_reg_n_0_[8] ),
        .I1(acc_H1_prog_V_reg[8]),
        .O(\acc_H1_prog_V[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[0]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[0]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[0]_i_1 
       (.CI(\<const0> ),
        .CO({\acc_H1_prog_V_reg[0]_i_1_n_0 ,\acc_H1_prog_V_reg[0]_i_1_n_1 ,\acc_H1_prog_V_reg[0]_i_1_n_2 ,\acc_H1_prog_V_reg[0]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[3] ,\inputs_current_ftw_H_reg_n_0_[2] ,\inputs_current_ftw_H_reg_n_0_[1] ,\inputs_current_ftw_H_reg_n_0_[0] }),
        .O({\acc_H1_prog_V_reg[0]_i_1_n_4 ,\acc_H1_prog_V_reg[0]_i_1_n_5 ,\acc_H1_prog_V_reg[0]_i_1_n_6 ,\acc_H1_prog_V_reg[0]_i_1_n_7 }),
        .S({\acc_H1_prog_V[0]_i_2_n_0 ,\acc_H1_prog_V[0]_i_3_n_0 ,\acc_H1_prog_V[0]_i_4_n_0 ,\acc_H1_prog_V[0]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[8]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[10]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[8]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[11]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[12]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[12]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[12]_i_1 
       (.CI(\acc_H1_prog_V_reg[8]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[12]_i_1_n_0 ,\acc_H1_prog_V_reg[12]_i_1_n_1 ,\acc_H1_prog_V_reg[12]_i_1_n_2 ,\acc_H1_prog_V_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[15] ,\inputs_current_ftw_H_reg_n_0_[14] ,\inputs_current_ftw_H_reg_n_0_[13] ,\inputs_current_ftw_H_reg_n_0_[12] }),
        .O({\acc_H1_prog_V_reg[12]_i_1_n_4 ,\acc_H1_prog_V_reg[12]_i_1_n_5 ,\acc_H1_prog_V_reg[12]_i_1_n_6 ,\acc_H1_prog_V_reg[12]_i_1_n_7 }),
        .S({\acc_H1_prog_V[12]_i_2_n_0 ,\acc_H1_prog_V[12]_i_3_n_0 ,\acc_H1_prog_V[12]_i_4_n_0 ,\acc_H1_prog_V[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[12]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[13]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[12]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[14]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[12]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[15]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[16]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[16]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[16]_i_1 
       (.CI(\acc_H1_prog_V_reg[12]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[16]_i_1_n_0 ,\acc_H1_prog_V_reg[16]_i_1_n_1 ,\acc_H1_prog_V_reg[16]_i_1_n_2 ,\acc_H1_prog_V_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[19] ,\inputs_current_ftw_H_reg_n_0_[18] ,\inputs_current_ftw_H_reg_n_0_[17] ,\inputs_current_ftw_H_reg_n_0_[16] }),
        .O({\acc_H1_prog_V_reg[16]_i_1_n_4 ,\acc_H1_prog_V_reg[16]_i_1_n_5 ,\acc_H1_prog_V_reg[16]_i_1_n_6 ,\acc_H1_prog_V_reg[16]_i_1_n_7 }),
        .S({\acc_H1_prog_V[16]_i_2_n_0 ,\acc_H1_prog_V[16]_i_3_n_0 ,\acc_H1_prog_V[16]_i_4_n_0 ,\acc_H1_prog_V[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[16]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[17]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[16]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[18]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[16]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[19]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[0]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[1]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[20]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[20]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[20]_i_1 
       (.CI(\acc_H1_prog_V_reg[16]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[20]_i_1_n_0 ,\acc_H1_prog_V_reg[20]_i_1_n_1 ,\acc_H1_prog_V_reg[20]_i_1_n_2 ,\acc_H1_prog_V_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[23] ,\inputs_current_ftw_H_reg_n_0_[22] ,\inputs_current_ftw_H_reg_n_0_[21] ,\inputs_current_ftw_H_reg_n_0_[20] }),
        .O({\acc_H1_prog_V_reg[20]_i_1_n_4 ,\acc_H1_prog_V_reg[20]_i_1_n_5 ,\acc_H1_prog_V_reg[20]_i_1_n_6 ,\acc_H1_prog_V_reg[20]_i_1_n_7 }),
        .S({\acc_H1_prog_V[20]_i_2_n_0 ,\acc_H1_prog_V[20]_i_3_n_0 ,\acc_H1_prog_V[20]_i_4_n_0 ,\acc_H1_prog_V[20]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[20]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[21]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[20]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[22]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[20]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[23]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[24]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[24]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[24]_i_1 
       (.CI(\acc_H1_prog_V_reg[20]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[24]_i_1_n_0 ,\acc_H1_prog_V_reg[24]_i_1_n_1 ,\acc_H1_prog_V_reg[24]_i_1_n_2 ,\acc_H1_prog_V_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[27] ,\inputs_current_ftw_H_reg_n_0_[26] ,\inputs_current_ftw_H_reg_n_0_[25] ,\inputs_current_ftw_H_reg_n_0_[24] }),
        .O({\acc_H1_prog_V_reg[24]_i_1_n_4 ,\acc_H1_prog_V_reg[24]_i_1_n_5 ,\acc_H1_prog_V_reg[24]_i_1_n_6 ,\acc_H1_prog_V_reg[24]_i_1_n_7 }),
        .S({\acc_H1_prog_V[24]_i_2_n_0 ,\acc_H1_prog_V[24]_i_3_n_0 ,\acc_H1_prog_V[24]_i_4_n_0 ,\acc_H1_prog_V[24]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[24]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[25]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[24]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[26]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[24]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[27]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[28]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[28]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[28]_i_1 
       (.CI(\acc_H1_prog_V_reg[24]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[28]_i_1_n_0 ,\acc_H1_prog_V_reg[28]_i_1_n_1 ,\acc_H1_prog_V_reg[28]_i_1_n_2 ,\acc_H1_prog_V_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[31] ,\inputs_current_ftw_H_reg_n_0_[30] ,\inputs_current_ftw_H_reg_n_0_[29] ,\inputs_current_ftw_H_reg_n_0_[28] }),
        .O({\acc_H1_prog_V_reg[28]_i_1_n_4 ,\acc_H1_prog_V_reg[28]_i_1_n_5 ,\acc_H1_prog_V_reg[28]_i_1_n_6 ,\acc_H1_prog_V_reg[28]_i_1_n_7 }),
        .S({\acc_H1_prog_V[28]_i_2_n_0 ,\acc_H1_prog_V[28]_i_3_n_0 ,\acc_H1_prog_V[28]_i_4_n_0 ,\acc_H1_prog_V[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[28]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[29]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[0]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[2]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[28]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[30]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[28]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[31]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[32] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[32]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[32]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[32]_i_1 
       (.CI(\acc_H1_prog_V_reg[28]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[32]_i_1_n_0 ,\acc_H1_prog_V_reg[32]_i_1_n_1 ,\acc_H1_prog_V_reg[32]_i_1_n_2 ,\acc_H1_prog_V_reg[32]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[35] ,\inputs_current_ftw_H_reg_n_0_[34] ,\inputs_current_ftw_H_reg_n_0_[33] ,\inputs_current_ftw_H_reg_n_0_[32] }),
        .O({\acc_H1_prog_V_reg[32]_i_1_n_4 ,\acc_H1_prog_V_reg[32]_i_1_n_5 ,\acc_H1_prog_V_reg[32]_i_1_n_6 ,\acc_H1_prog_V_reg[32]_i_1_n_7 }),
        .S({\acc_H1_prog_V[32]_i_2_n_0 ,\acc_H1_prog_V[32]_i_3_n_0 ,\acc_H1_prog_V[32]_i_4_n_0 ,\acc_H1_prog_V[32]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[33] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[32]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[33]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[34] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[32]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[34]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[35] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[32]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[35]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[36] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[36]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[36]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[36]_i_1 
       (.CI(\acc_H1_prog_V_reg[32]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[36]_i_1_n_0 ,\acc_H1_prog_V_reg[36]_i_1_n_1 ,\acc_H1_prog_V_reg[36]_i_1_n_2 ,\acc_H1_prog_V_reg[36]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[39] ,\inputs_current_ftw_H_reg_n_0_[38] ,\inputs_current_ftw_H_reg_n_0_[37] ,\inputs_current_ftw_H_reg_n_0_[36] }),
        .O({\acc_H1_prog_V_reg[36]_i_1_n_4 ,\acc_H1_prog_V_reg[36]_i_1_n_5 ,\acc_H1_prog_V_reg[36]_i_1_n_6 ,\acc_H1_prog_V_reg[36]_i_1_n_7 }),
        .S({\acc_H1_prog_V[36]_i_2_n_0 ,\acc_H1_prog_V[36]_i_3_n_0 ,\acc_H1_prog_V[36]_i_4_n_0 ,\acc_H1_prog_V[36]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[37] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[36]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[37]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[38] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[36]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[38]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[39] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[36]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[39]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[0]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[3]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[40] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[40]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[40]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[40]_i_1 
       (.CI(\acc_H1_prog_V_reg[36]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[40]_i_1_n_0 ,\acc_H1_prog_V_reg[40]_i_1_n_1 ,\acc_H1_prog_V_reg[40]_i_1_n_2 ,\acc_H1_prog_V_reg[40]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[43] ,\inputs_current_ftw_H_reg_n_0_[42] ,\inputs_current_ftw_H_reg_n_0_[41] ,\inputs_current_ftw_H_reg_n_0_[40] }),
        .O({\acc_H1_prog_V_reg[40]_i_1_n_4 ,\acc_H1_prog_V_reg[40]_i_1_n_5 ,\acc_H1_prog_V_reg[40]_i_1_n_6 ,\acc_H1_prog_V_reg[40]_i_1_n_7 }),
        .S({\acc_H1_prog_V[40]_i_2_n_0 ,\acc_H1_prog_V[40]_i_3_n_0 ,\acc_H1_prog_V[40]_i_4_n_0 ,\acc_H1_prog_V[40]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[41] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[40]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[41]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[42] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[40]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[42]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[43] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[40]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[43]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[44] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[44]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[44]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[44]_i_1 
       (.CI(\acc_H1_prog_V_reg[40]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[44]_i_1_n_1 ,\acc_H1_prog_V_reg[44]_i_1_n_2 ,\acc_H1_prog_V_reg[44]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\inputs_current_ftw_H_reg_n_0_[46] ,\inputs_current_ftw_H_reg_n_0_[45] ,\inputs_current_ftw_H_reg_n_0_[44] }),
        .O({\acc_H1_prog_V_reg[44]_i_1_n_4 ,\acc_H1_prog_V_reg[44]_i_1_n_5 ,\acc_H1_prog_V_reg[44]_i_1_n_6 ,\acc_H1_prog_V_reg[44]_i_1_n_7 }),
        .S({\acc_H1_prog_V[44]_i_2_n_0 ,\acc_H1_prog_V[44]_i_3_n_0 ,\acc_H1_prog_V[44]_i_4_n_0 ,\acc_H1_prog_V[44]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[45] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[44]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[45]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[46] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[44]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[46]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[47] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[44]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[47]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[4]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[4]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[4]_i_1 
       (.CI(\acc_H1_prog_V_reg[0]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[4]_i_1_n_0 ,\acc_H1_prog_V_reg[4]_i_1_n_1 ,\acc_H1_prog_V_reg[4]_i_1_n_2 ,\acc_H1_prog_V_reg[4]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[7] ,\inputs_current_ftw_H_reg_n_0_[6] ,\inputs_current_ftw_H_reg_n_0_[5] ,\inputs_current_ftw_H_reg_n_0_[4] }),
        .O({\acc_H1_prog_V_reg[4]_i_1_n_4 ,\acc_H1_prog_V_reg[4]_i_1_n_5 ,\acc_H1_prog_V_reg[4]_i_1_n_6 ,\acc_H1_prog_V_reg[4]_i_1_n_7 }),
        .S({\acc_H1_prog_V[4]_i_2_n_0 ,\acc_H1_prog_V[4]_i_3_n_0 ,\acc_H1_prog_V[4]_i_4_n_0 ,\acc_H1_prog_V[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[4]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[5]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[4]_i_1_n_5 ),
        .Q(acc_H1_prog_V_reg[6]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[4]_i_1_n_4 ),
        .Q(acc_H1_prog_V_reg[7]),
        .R(acc_H1_prog_V));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[8]_i_1_n_7 ),
        .Q(acc_H1_prog_V_reg[8]),
        .R(acc_H1_prog_V));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_prog_V_reg[8]_i_1 
       (.CI(\acc_H1_prog_V_reg[4]_i_1_n_0 ),
        .CO({\acc_H1_prog_V_reg[8]_i_1_n_0 ,\acc_H1_prog_V_reg[8]_i_1_n_1 ,\acc_H1_prog_V_reg[8]_i_1_n_2 ,\acc_H1_prog_V_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_H_reg_n_0_[11] ,\inputs_current_ftw_H_reg_n_0_[10] ,\inputs_current_ftw_H_reg_n_0_[9] ,\inputs_current_ftw_H_reg_n_0_[8] }),
        .O({\acc_H1_prog_V_reg[8]_i_1_n_4 ,\acc_H1_prog_V_reg[8]_i_1_n_5 ,\acc_H1_prog_V_reg[8]_i_1_n_6 ,\acc_H1_prog_V_reg[8]_i_1_n_7 }),
        .S({\acc_H1_prog_V[8]_i_2_n_0 ,\acc_H1_prog_V[8]_i_3_n_0 ,\acc_H1_prog_V[8]_i_4_n_0 ,\acc_H1_prog_V[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_prog_V_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_V0),
        .D(\acc_H1_prog_V_reg[8]_i_1_n_6 ),
        .Q(acc_H1_prog_V_reg[9]),
        .R(acc_H1_prog_V));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[0]_i_1 
       (.I0(tmp_8_fu_673_p3[0]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[0]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[10]_i_1 
       (.I0(tmp_8_fu_673_p3[10]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[10]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[11]_i_1 
       (.I0(tmp_8_fu_673_p3[11]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[11]));
  (* HLUTNM = "lutpair8" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[11]_i_10 
       (.I0(acc_H1_slip_V[8]),
        .I1(inputs_current_dftw_s[8]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[11]_i_6_n_0 ),
        .O(\acc_H1_slip_V[11]_i_10_n_0 ));
  (* HLUTNM = "lutpair10" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[11]_i_3 
       (.I0(acc_H1_slip_V[10]),
        .I1(inputs_current_dftw_s[10]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[11]_i_3_n_0 ));
  (* HLUTNM = "lutpair9" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[11]_i_4 
       (.I0(acc_H1_slip_V[9]),
        .I1(inputs_current_dftw_s[9]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[11]_i_4_n_0 ));
  (* HLUTNM = "lutpair8" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[11]_i_5 
       (.I0(acc_H1_slip_V[8]),
        .I1(inputs_current_dftw_s[8]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[11]_i_5_n_0 ));
  (* HLUTNM = "lutpair7" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[11]_i_6 
       (.I0(acc_H1_slip_V[7]),
        .I1(inputs_current_dftw_s[7]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[11]_i_6_n_0 ));
  (* HLUTNM = "lutpair11" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[11]_i_7 
       (.I0(acc_H1_slip_V[11]),
        .I1(inputs_current_dftw_s[11]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[11]_i_3_n_0 ),
        .O(\acc_H1_slip_V[11]_i_7_n_0 ));
  (* HLUTNM = "lutpair10" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[11]_i_8 
       (.I0(acc_H1_slip_V[10]),
        .I1(inputs_current_dftw_s[10]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[11]_i_4_n_0 ),
        .O(\acc_H1_slip_V[11]_i_8_n_0 ));
  (* HLUTNM = "lutpair9" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[11]_i_9 
       (.I0(acc_H1_slip_V[9]),
        .I1(inputs_current_dftw_s[9]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[11]_i_5_n_0 ),
        .O(\acc_H1_slip_V[11]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[12]_i_1 
       (.I0(tmp_8_fu_673_p3[12]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[12]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[13]_i_1 
       (.I0(tmp_8_fu_673_p3[13]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[13]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[14]_i_1 
       (.I0(tmp_8_fu_673_p3[14]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[14]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[15]_i_1 
       (.I0(tmp_8_fu_673_p3[15]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[15]));
  (* HLUTNM = "lutpair12" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[15]_i_10 
       (.I0(acc_H1_slip_V[12]),
        .I1(inputs_current_dftw_s[12]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[15]_i_6_n_0 ),
        .O(\acc_H1_slip_V[15]_i_10_n_0 ));
  (* HLUTNM = "lutpair14" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[15]_i_3 
       (.I0(acc_H1_slip_V[14]),
        .I1(inputs_current_dftw_s[14]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[15]_i_3_n_0 ));
  (* HLUTNM = "lutpair13" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[15]_i_4 
       (.I0(acc_H1_slip_V[13]),
        .I1(inputs_current_dftw_s[13]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[15]_i_4_n_0 ));
  (* HLUTNM = "lutpair12" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[15]_i_5 
       (.I0(acc_H1_slip_V[12]),
        .I1(inputs_current_dftw_s[12]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[15]_i_5_n_0 ));
  (* HLUTNM = "lutpair11" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[15]_i_6 
       (.I0(acc_H1_slip_V[11]),
        .I1(inputs_current_dftw_s[11]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[15]_i_6_n_0 ));
  (* HLUTNM = "lutpair15" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[15]_i_7 
       (.I0(acc_H1_slip_V[15]),
        .I1(inputs_current_dftw_s[15]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[15]_i_3_n_0 ),
        .O(\acc_H1_slip_V[15]_i_7_n_0 ));
  (* HLUTNM = "lutpair14" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[15]_i_8 
       (.I0(acc_H1_slip_V[14]),
        .I1(inputs_current_dftw_s[14]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[15]_i_4_n_0 ),
        .O(\acc_H1_slip_V[15]_i_8_n_0 ));
  (* HLUTNM = "lutpair13" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[15]_i_9 
       (.I0(acc_H1_slip_V[13]),
        .I1(inputs_current_dftw_s[13]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[15]_i_5_n_0 ),
        .O(\acc_H1_slip_V[15]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[16]_i_1 
       (.I0(tmp_8_fu_673_p3[16]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[16]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[17]_i_1 
       (.I0(tmp_8_fu_673_p3[17]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[17]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[18]_i_1 
       (.I0(tmp_8_fu_673_p3[18]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[18]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[19]_i_1 
       (.I0(tmp_8_fu_673_p3[19]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[19]));
  (* HLUTNM = "lutpair16" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[19]_i_10 
       (.I0(acc_H1_slip_V[16]),
        .I1(inputs_current_dftw_s[16]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[19]_i_6_n_0 ),
        .O(\acc_H1_slip_V[19]_i_10_n_0 ));
  (* HLUTNM = "lutpair18" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[19]_i_3 
       (.I0(acc_H1_slip_V[18]),
        .I1(inputs_current_dftw_s[18]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[19]_i_3_n_0 ));
  (* HLUTNM = "lutpair17" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[19]_i_4 
       (.I0(acc_H1_slip_V[17]),
        .I1(inputs_current_dftw_s[17]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[19]_i_4_n_0 ));
  (* HLUTNM = "lutpair16" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[19]_i_5 
       (.I0(acc_H1_slip_V[16]),
        .I1(inputs_current_dftw_s[16]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[19]_i_5_n_0 ));
  (* HLUTNM = "lutpair15" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[19]_i_6 
       (.I0(acc_H1_slip_V[15]),
        .I1(inputs_current_dftw_s[15]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[19]_i_6_n_0 ));
  (* HLUTNM = "lutpair19" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[19]_i_7 
       (.I0(acc_H1_slip_V[19]),
        .I1(inputs_current_dftw_s[19]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[19]_i_3_n_0 ),
        .O(\acc_H1_slip_V[19]_i_7_n_0 ));
  (* HLUTNM = "lutpair18" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[19]_i_8 
       (.I0(acc_H1_slip_V[18]),
        .I1(inputs_current_dftw_s[18]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[19]_i_4_n_0 ),
        .O(\acc_H1_slip_V[19]_i_8_n_0 ));
  (* HLUTNM = "lutpair17" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[19]_i_9 
       (.I0(acc_H1_slip_V[17]),
        .I1(inputs_current_dftw_s[17]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[19]_i_5_n_0 ),
        .O(\acc_H1_slip_V[19]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[1]_i_1 
       (.I0(tmp_8_fu_673_p3[1]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[1]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[20]_i_1 
       (.I0(tmp_8_fu_673_p3[20]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[20]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[21]_i_1 
       (.I0(tmp_8_fu_673_p3[21]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[21]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[22]_i_1 
       (.I0(tmp_8_fu_673_p3[22]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[22]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[23]_i_1 
       (.I0(tmp_8_fu_673_p3[23]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[23]));
  (* HLUTNM = "lutpair20" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[23]_i_10 
       (.I0(acc_H1_slip_V[20]),
        .I1(inputs_current_dftw_s[20]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[23]_i_6_n_0 ),
        .O(\acc_H1_slip_V[23]_i_10_n_0 ));
  (* HLUTNM = "lutpair22" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[23]_i_3 
       (.I0(acc_H1_slip_V[22]),
        .I1(inputs_current_dftw_s[22]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[23]_i_3_n_0 ));
  (* HLUTNM = "lutpair21" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[23]_i_4 
       (.I0(acc_H1_slip_V[21]),
        .I1(inputs_current_dftw_s[21]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[23]_i_4_n_0 ));
  (* HLUTNM = "lutpair20" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[23]_i_5 
       (.I0(acc_H1_slip_V[20]),
        .I1(inputs_current_dftw_s[20]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[23]_i_5_n_0 ));
  (* HLUTNM = "lutpair19" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[23]_i_6 
       (.I0(acc_H1_slip_V[19]),
        .I1(inputs_current_dftw_s[19]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[23]_i_6_n_0 ));
  (* HLUTNM = "lutpair23" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[23]_i_7 
       (.I0(acc_H1_slip_V[23]),
        .I1(inputs_current_dftw_s[23]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[23]_i_3_n_0 ),
        .O(\acc_H1_slip_V[23]_i_7_n_0 ));
  (* HLUTNM = "lutpair22" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[23]_i_8 
       (.I0(acc_H1_slip_V[22]),
        .I1(inputs_current_dftw_s[22]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[23]_i_4_n_0 ),
        .O(\acc_H1_slip_V[23]_i_8_n_0 ));
  (* HLUTNM = "lutpair21" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[23]_i_9 
       (.I0(acc_H1_slip_V[21]),
        .I1(inputs_current_dftw_s[21]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[23]_i_5_n_0 ),
        .O(\acc_H1_slip_V[23]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[24]_i_1 
       (.I0(tmp_8_fu_673_p3[24]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[24]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[25]_i_1 
       (.I0(tmp_8_fu_673_p3[25]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[25]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[26]_i_1 
       (.I0(tmp_8_fu_673_p3[26]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[26]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[27]_i_1 
       (.I0(tmp_8_fu_673_p3[27]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[27]));
  (* HLUTNM = "lutpair24" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[27]_i_10 
       (.I0(acc_H1_slip_V[24]),
        .I1(inputs_current_dftw_s[24]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[27]_i_6_n_0 ),
        .O(\acc_H1_slip_V[27]_i_10_n_0 ));
  (* HLUTNM = "lutpair26" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[27]_i_3 
       (.I0(acc_H1_slip_V[26]),
        .I1(inputs_current_dftw_s[26]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[27]_i_3_n_0 ));
  (* HLUTNM = "lutpair25" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[27]_i_4 
       (.I0(acc_H1_slip_V[25]),
        .I1(inputs_current_dftw_s[25]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[27]_i_4_n_0 ));
  (* HLUTNM = "lutpair24" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[27]_i_5 
       (.I0(acc_H1_slip_V[24]),
        .I1(inputs_current_dftw_s[24]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[27]_i_5_n_0 ));
  (* HLUTNM = "lutpair23" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[27]_i_6 
       (.I0(acc_H1_slip_V[23]),
        .I1(inputs_current_dftw_s[23]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[27]_i_6_n_0 ));
  (* HLUTNM = "lutpair27" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[27]_i_7 
       (.I0(acc_H1_slip_V[27]),
        .I1(inputs_current_dftw_s[27]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[27]_i_3_n_0 ),
        .O(\acc_H1_slip_V[27]_i_7_n_0 ));
  (* HLUTNM = "lutpair26" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[27]_i_8 
       (.I0(acc_H1_slip_V[26]),
        .I1(inputs_current_dftw_s[26]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[27]_i_4_n_0 ),
        .O(\acc_H1_slip_V[27]_i_8_n_0 ));
  (* HLUTNM = "lutpair25" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[27]_i_9 
       (.I0(acc_H1_slip_V[25]),
        .I1(inputs_current_dftw_s[25]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[27]_i_5_n_0 ),
        .O(\acc_H1_slip_V[27]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[28]_i_1 
       (.I0(tmp_8_fu_673_p3[28]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[28]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[29]_i_1 
       (.I0(tmp_8_fu_673_p3[29]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[29]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[2]_i_1 
       (.I0(tmp_8_fu_673_p3[2]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[2]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[30]_i_1 
       (.I0(tmp_8_fu_673_p3[30]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[30]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[31]_i_1 
       (.I0(tmp_8_fu_673_p3[31]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[31]));
  (* HLUTNM = "lutpair28" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[31]_i_10 
       (.I0(acc_H1_slip_V[28]),
        .I1(inputs_current_dftw_s[28]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[31]_i_6_n_0 ),
        .O(\acc_H1_slip_V[31]_i_10_n_0 ));
  (* HLUTNM = "lutpair30" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[31]_i_3 
       (.I0(acc_H1_slip_V[30]),
        .I1(inputs_current_dftw_s[30]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[31]_i_3_n_0 ));
  (* HLUTNM = "lutpair29" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[31]_i_4 
       (.I0(acc_H1_slip_V[29]),
        .I1(inputs_current_dftw_s[29]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[31]_i_4_n_0 ));
  (* HLUTNM = "lutpair28" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[31]_i_5 
       (.I0(acc_H1_slip_V[28]),
        .I1(inputs_current_dftw_s[28]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[31]_i_5_n_0 ));
  (* HLUTNM = "lutpair27" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[31]_i_6 
       (.I0(acc_H1_slip_V[27]),
        .I1(inputs_current_dftw_s[27]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[31]_i_6_n_0 ));
  (* HLUTNM = "lutpair31" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[31]_i_7 
       (.I0(acc_H1_slip_V[31]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[31]_i_3_n_0 ),
        .O(\acc_H1_slip_V[31]_i_7_n_0 ));
  (* HLUTNM = "lutpair30" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[31]_i_8 
       (.I0(acc_H1_slip_V[30]),
        .I1(inputs_current_dftw_s[30]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[31]_i_4_n_0 ),
        .O(\acc_H1_slip_V[31]_i_8_n_0 ));
  (* HLUTNM = "lutpair29" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[31]_i_9 
       (.I0(acc_H1_slip_V[29]),
        .I1(inputs_current_dftw_s[29]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[31]_i_5_n_0 ),
        .O(\acc_H1_slip_V[31]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[32]_i_1 
       (.I0(tmp_8_fu_673_p3[32]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[32]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[33]_i_1 
       (.I0(tmp_8_fu_673_p3[33]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[33]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[34]_i_1 
       (.I0(tmp_8_fu_673_p3[34]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[34]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[35]_i_1 
       (.I0(tmp_8_fu_673_p3[35]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[35]));
  (* HLUTNM = "lutpair32" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[35]_i_10 
       (.I0(acc_H1_slip_V[32]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[35]_i_6_n_0 ),
        .O(\acc_H1_slip_V[35]_i_10_n_0 ));
  (* HLUTNM = "lutpair34" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[35]_i_3 
       (.I0(acc_H1_slip_V[34]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[35]_i_3_n_0 ));
  (* HLUTNM = "lutpair33" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[35]_i_4 
       (.I0(acc_H1_slip_V[33]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[35]_i_4_n_0 ));
  (* HLUTNM = "lutpair32" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[35]_i_5 
       (.I0(acc_H1_slip_V[32]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[35]_i_5_n_0 ));
  (* HLUTNM = "lutpair31" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[35]_i_6 
       (.I0(acc_H1_slip_V[31]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[35]_i_6_n_0 ));
  (* HLUTNM = "lutpair35" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[35]_i_7 
       (.I0(acc_H1_slip_V[35]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[35]_i_3_n_0 ),
        .O(\acc_H1_slip_V[35]_i_7_n_0 ));
  (* HLUTNM = "lutpair34" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[35]_i_8 
       (.I0(acc_H1_slip_V[34]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[35]_i_4_n_0 ),
        .O(\acc_H1_slip_V[35]_i_8_n_0 ));
  (* HLUTNM = "lutpair33" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[35]_i_9 
       (.I0(acc_H1_slip_V[33]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[35]_i_5_n_0 ),
        .O(\acc_H1_slip_V[35]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[36]_i_1 
       (.I0(tmp_8_fu_673_p3[36]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[36]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[37]_i_1 
       (.I0(tmp_8_fu_673_p3[37]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[37]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[38]_i_1 
       (.I0(tmp_8_fu_673_p3[38]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[38]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[39]_i_1 
       (.I0(tmp_8_fu_673_p3[39]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[39]));
  (* HLUTNM = "lutpair36" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[39]_i_10 
       (.I0(acc_H1_slip_V[36]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[39]_i_6_n_0 ),
        .O(\acc_H1_slip_V[39]_i_10_n_0 ));
  (* HLUTNM = "lutpair38" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[39]_i_3 
       (.I0(acc_H1_slip_V[38]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[39]_i_3_n_0 ));
  (* HLUTNM = "lutpair37" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[39]_i_4 
       (.I0(acc_H1_slip_V[37]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[39]_i_4_n_0 ));
  (* HLUTNM = "lutpair36" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[39]_i_5 
       (.I0(acc_H1_slip_V[36]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[39]_i_5_n_0 ));
  (* HLUTNM = "lutpair35" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[39]_i_6 
       (.I0(acc_H1_slip_V[35]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[39]_i_6_n_0 ));
  (* HLUTNM = "lutpair39" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[39]_i_7 
       (.I0(acc_H1_slip_V[39]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[39]_i_3_n_0 ),
        .O(\acc_H1_slip_V[39]_i_7_n_0 ));
  (* HLUTNM = "lutpair38" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[39]_i_8 
       (.I0(acc_H1_slip_V[38]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[39]_i_4_n_0 ),
        .O(\acc_H1_slip_V[39]_i_8_n_0 ));
  (* HLUTNM = "lutpair37" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[39]_i_9 
       (.I0(acc_H1_slip_V[37]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[39]_i_5_n_0 ),
        .O(\acc_H1_slip_V[39]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[3]_i_1 
       (.I0(tmp_8_fu_673_p3[3]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[3]));
  (* HLUTNM = "lutpair2" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[3]_i_3 
       (.I0(acc_H1_slip_V[2]),
        .I1(inputs_current_dftw_s[2]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[3]_i_3_n_0 ));
  (* HLUTNM = "lutpair1" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[3]_i_4 
       (.I0(acc_H1_slip_V[1]),
        .I1(inputs_current_dftw_s[1]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[3]_i_4_n_0 ));
  (* HLUTNM = "lutpair0" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \acc_H1_slip_V[3]_i_5 
       (.I0(acc_H1_slip_V[0]),
        .I1(inputs_current_dftw_s[0]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[3]_i_5_n_0 ));
  (* HLUTNM = "lutpair3" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[3]_i_6 
       (.I0(acc_H1_slip_V[3]),
        .I1(inputs_current_dftw_s[3]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[3]_i_3_n_0 ),
        .O(\acc_H1_slip_V[3]_i_6_n_0 ));
  (* HLUTNM = "lutpair2" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[3]_i_7 
       (.I0(acc_H1_slip_V[2]),
        .I1(inputs_current_dftw_s[2]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[3]_i_4_n_0 ),
        .O(\acc_H1_slip_V[3]_i_7_n_0 ));
  (* HLUTNM = "lutpair1" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[3]_i_8 
       (.I0(acc_H1_slip_V[1]),
        .I1(inputs_current_dftw_s[1]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[3]_i_5_n_0 ),
        .O(\acc_H1_slip_V[3]_i_8_n_0 ));
  (* HLUTNM = "lutpair0" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \acc_H1_slip_V[3]_i_9 
       (.I0(acc_H1_slip_V[0]),
        .I1(inputs_current_dftw_s[0]),
        .O(\acc_H1_slip_V[3]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[40]_i_1 
       (.I0(tmp_8_fu_673_p3[40]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[40]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[41]_i_1 
       (.I0(tmp_8_fu_673_p3[41]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[41]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[42]_i_1 
       (.I0(tmp_8_fu_673_p3[42]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[42]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[43]_i_1 
       (.I0(tmp_8_fu_673_p3[43]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[43]));
  (* HLUTNM = "lutpair40" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[43]_i_10 
       (.I0(acc_H1_slip_V[40]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[43]_i_6_n_0 ),
        .O(\acc_H1_slip_V[43]_i_10_n_0 ));
  (* HLUTNM = "lutpair42" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[43]_i_3 
       (.I0(acc_H1_slip_V[42]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[43]_i_3_n_0 ));
  (* HLUTNM = "lutpair41" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[43]_i_4 
       (.I0(acc_H1_slip_V[41]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[43]_i_4_n_0 ));
  (* HLUTNM = "lutpair40" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[43]_i_5 
       (.I0(acc_H1_slip_V[40]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[43]_i_5_n_0 ));
  (* HLUTNM = "lutpair39" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[43]_i_6 
       (.I0(acc_H1_slip_V[39]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[43]_i_6_n_0 ));
  (* HLUTNM = "lutpair43" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[43]_i_7 
       (.I0(acc_H1_slip_V[43]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[43]_i_3_n_0 ),
        .O(\acc_H1_slip_V[43]_i_7_n_0 ));
  (* HLUTNM = "lutpair42" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[43]_i_8 
       (.I0(acc_H1_slip_V[42]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[43]_i_4_n_0 ),
        .O(\acc_H1_slip_V[43]_i_8_n_0 ));
  (* HLUTNM = "lutpair41" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[43]_i_9 
       (.I0(acc_H1_slip_V[41]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[43]_i_5_n_0 ),
        .O(\acc_H1_slip_V[43]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[44]_i_1 
       (.I0(tmp_8_fu_673_p3[44]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[44]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[45]_i_1 
       (.I0(tmp_8_fu_673_p3[45]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[45]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[46]_i_1 
       (.I0(tmp_8_fu_673_p3[46]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[46]));
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    \acc_H1_slip_V[47]_i_1 
       (.I0(ap_rst),
        .I1(ap_enable_reg_pp0_iter2),
        .I2(p_Val2_4_reg_1510),
        .I3(inputs_valid_read_reg_1420),
        .I4(inputs_reset_NCO_rea_reg_1398),
        .O(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* HLUTNM = "lutpair44" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[47]_i_10 
       (.I0(acc_H1_slip_V[44]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[47]_i_6_n_0 ),
        .O(\acc_H1_slip_V[47]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[47]_i_2 
       (.I0(tmp_8_fu_673_p3[47]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[47]));
  (* HLUTNM = "lutpair45" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[47]_i_4 
       (.I0(acc_H1_slip_V[45]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[47]_i_4_n_0 ));
  (* HLUTNM = "lutpair44" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[47]_i_5 
       (.I0(acc_H1_slip_V[44]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[47]_i_5_n_0 ));
  (* HLUTNM = "lutpair43" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[47]_i_6 
       (.I0(acc_H1_slip_V[43]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[47]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hA99A)) 
    \acc_H1_slip_V[47]_i_7 
       (.I0(acc_H1_slip_V[47]),
        .I1(acc_H1_slip_V[46]),
        .I2(inputs_current_slip_s),
        .I3(inputs_current_dftw_s[31]),
        .O(\acc_H1_slip_V[47]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[47]_i_8 
       (.I0(\acc_H1_slip_V[47]_i_4_n_0 ),
        .I1(inputs_current_slip_s),
        .I2(inputs_current_dftw_s[31]),
        .I3(acc_H1_slip_V[46]),
        .O(\acc_H1_slip_V[47]_i_8_n_0 ));
  (* HLUTNM = "lutpair45" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[47]_i_9 
       (.I0(acc_H1_slip_V[45]),
        .I1(inputs_current_dftw_s[31]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[47]_i_5_n_0 ),
        .O(\acc_H1_slip_V[47]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[4]_i_1 
       (.I0(tmp_8_fu_673_p3[4]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[4]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[5]_i_1 
       (.I0(tmp_8_fu_673_p3[5]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[5]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[6]_i_1 
       (.I0(tmp_8_fu_673_p3[6]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[6]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[7]_i_1 
       (.I0(tmp_8_fu_673_p3[7]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[7]));
  (* HLUTNM = "lutpair4" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[7]_i_10 
       (.I0(acc_H1_slip_V[4]),
        .I1(inputs_current_dftw_s[4]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[7]_i_6_n_0 ),
        .O(\acc_H1_slip_V[7]_i_10_n_0 ));
  (* HLUTNM = "lutpair6" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[7]_i_3 
       (.I0(acc_H1_slip_V[6]),
        .I1(inputs_current_dftw_s[6]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[7]_i_3_n_0 ));
  (* HLUTNM = "lutpair5" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[7]_i_4 
       (.I0(acc_H1_slip_V[5]),
        .I1(inputs_current_dftw_s[5]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[7]_i_4_n_0 ));
  (* HLUTNM = "lutpair4" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[7]_i_5 
       (.I0(acc_H1_slip_V[4]),
        .I1(inputs_current_dftw_s[4]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[7]_i_5_n_0 ));
  (* HLUTNM = "lutpair3" *) 
  LUT3 #(
    .INIT(8'h28)) 
    \acc_H1_slip_V[7]_i_6 
       (.I0(acc_H1_slip_V[3]),
        .I1(inputs_current_dftw_s[3]),
        .I2(inputs_current_slip_s),
        .O(\acc_H1_slip_V[7]_i_6_n_0 ));
  (* HLUTNM = "lutpair7" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[7]_i_7 
       (.I0(acc_H1_slip_V[7]),
        .I1(inputs_current_dftw_s[7]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[7]_i_3_n_0 ),
        .O(\acc_H1_slip_V[7]_i_7_n_0 ));
  (* HLUTNM = "lutpair6" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[7]_i_8 
       (.I0(acc_H1_slip_V[6]),
        .I1(inputs_current_dftw_s[6]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[7]_i_4_n_0 ),
        .O(\acc_H1_slip_V[7]_i_8_n_0 ));
  (* HLUTNM = "lutpair5" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \acc_H1_slip_V[7]_i_9 
       (.I0(acc_H1_slip_V[5]),
        .I1(inputs_current_dftw_s[5]),
        .I2(inputs_current_slip_s),
        .I3(\acc_H1_slip_V[7]_i_5_n_0 ),
        .O(\acc_H1_slip_V[7]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[8]_i_1 
       (.I0(tmp_8_fu_673_p3[8]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[8]));
  LUT5 #(
    .INIT(32'h20222A22)) 
    \acc_H1_slip_V[9]_i_1 
       (.I0(tmp_8_fu_673_p3[9]),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_reset),
        .O(p_tmp_8_fu_693_p3[9]));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[0]),
        .Q(acc_H1_slip_V[0]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[10]),
        .Q(acc_H1_slip_V[10]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[11]),
        .Q(acc_H1_slip_V[11]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[11]_i_2 
       (.CI(\acc_H1_slip_V_reg[7]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[11]_i_2_n_0 ,\acc_H1_slip_V_reg[11]_i_2_n_1 ,\acc_H1_slip_V_reg[11]_i_2_n_2 ,\acc_H1_slip_V_reg[11]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[11]_i_3_n_0 ,\acc_H1_slip_V[11]_i_4_n_0 ,\acc_H1_slip_V[11]_i_5_n_0 ,\acc_H1_slip_V[11]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[11:8]),
        .S({\acc_H1_slip_V[11]_i_7_n_0 ,\acc_H1_slip_V[11]_i_8_n_0 ,\acc_H1_slip_V[11]_i_9_n_0 ,\acc_H1_slip_V[11]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[12]),
        .Q(acc_H1_slip_V[12]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[13]),
        .Q(acc_H1_slip_V[13]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[14]),
        .Q(acc_H1_slip_V[14]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[15]),
        .Q(acc_H1_slip_V[15]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[15]_i_2 
       (.CI(\acc_H1_slip_V_reg[11]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[15]_i_2_n_0 ,\acc_H1_slip_V_reg[15]_i_2_n_1 ,\acc_H1_slip_V_reg[15]_i_2_n_2 ,\acc_H1_slip_V_reg[15]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[15]_i_3_n_0 ,\acc_H1_slip_V[15]_i_4_n_0 ,\acc_H1_slip_V[15]_i_5_n_0 ,\acc_H1_slip_V[15]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[15:12]),
        .S({\acc_H1_slip_V[15]_i_7_n_0 ,\acc_H1_slip_V[15]_i_8_n_0 ,\acc_H1_slip_V[15]_i_9_n_0 ,\acc_H1_slip_V[15]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[16]),
        .Q(acc_H1_slip_V[16]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[17]),
        .Q(acc_H1_slip_V[17]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[18]),
        .Q(acc_H1_slip_V[18]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[19]),
        .Q(acc_H1_slip_V[19]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[19]_i_2 
       (.CI(\acc_H1_slip_V_reg[15]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[19]_i_2_n_0 ,\acc_H1_slip_V_reg[19]_i_2_n_1 ,\acc_H1_slip_V_reg[19]_i_2_n_2 ,\acc_H1_slip_V_reg[19]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[19]_i_3_n_0 ,\acc_H1_slip_V[19]_i_4_n_0 ,\acc_H1_slip_V[19]_i_5_n_0 ,\acc_H1_slip_V[19]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[19:16]),
        .S({\acc_H1_slip_V[19]_i_7_n_0 ,\acc_H1_slip_V[19]_i_8_n_0 ,\acc_H1_slip_V[19]_i_9_n_0 ,\acc_H1_slip_V[19]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[1]),
        .Q(acc_H1_slip_V[1]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[20]),
        .Q(acc_H1_slip_V[20]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[21]),
        .Q(acc_H1_slip_V[21]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[22]),
        .Q(acc_H1_slip_V[22]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[23]),
        .Q(acc_H1_slip_V[23]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[23]_i_2 
       (.CI(\acc_H1_slip_V_reg[19]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[23]_i_2_n_0 ,\acc_H1_slip_V_reg[23]_i_2_n_1 ,\acc_H1_slip_V_reg[23]_i_2_n_2 ,\acc_H1_slip_V_reg[23]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[23]_i_3_n_0 ,\acc_H1_slip_V[23]_i_4_n_0 ,\acc_H1_slip_V[23]_i_5_n_0 ,\acc_H1_slip_V[23]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[23:20]),
        .S({\acc_H1_slip_V[23]_i_7_n_0 ,\acc_H1_slip_V[23]_i_8_n_0 ,\acc_H1_slip_V[23]_i_9_n_0 ,\acc_H1_slip_V[23]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[24]),
        .Q(acc_H1_slip_V[24]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[25]),
        .Q(acc_H1_slip_V[25]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[26]),
        .Q(acc_H1_slip_V[26]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[27]),
        .Q(acc_H1_slip_V[27]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[27]_i_2 
       (.CI(\acc_H1_slip_V_reg[23]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[27]_i_2_n_0 ,\acc_H1_slip_V_reg[27]_i_2_n_1 ,\acc_H1_slip_V_reg[27]_i_2_n_2 ,\acc_H1_slip_V_reg[27]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[27]_i_3_n_0 ,\acc_H1_slip_V[27]_i_4_n_0 ,\acc_H1_slip_V[27]_i_5_n_0 ,\acc_H1_slip_V[27]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[27:24]),
        .S({\acc_H1_slip_V[27]_i_7_n_0 ,\acc_H1_slip_V[27]_i_8_n_0 ,\acc_H1_slip_V[27]_i_9_n_0 ,\acc_H1_slip_V[27]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[28]),
        .Q(acc_H1_slip_V[28]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[29]),
        .Q(acc_H1_slip_V[29]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[2]),
        .Q(acc_H1_slip_V[2]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[30]),
        .Q(acc_H1_slip_V[30]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[31]),
        .Q(acc_H1_slip_V[31]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[31]_i_2 
       (.CI(\acc_H1_slip_V_reg[27]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[31]_i_2_n_0 ,\acc_H1_slip_V_reg[31]_i_2_n_1 ,\acc_H1_slip_V_reg[31]_i_2_n_2 ,\acc_H1_slip_V_reg[31]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[31]_i_3_n_0 ,\acc_H1_slip_V[31]_i_4_n_0 ,\acc_H1_slip_V[31]_i_5_n_0 ,\acc_H1_slip_V[31]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[31:28]),
        .S({\acc_H1_slip_V[31]_i_7_n_0 ,\acc_H1_slip_V[31]_i_8_n_0 ,\acc_H1_slip_V[31]_i_9_n_0 ,\acc_H1_slip_V[31]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[32] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[32]),
        .Q(acc_H1_slip_V[32]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[33] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[33]),
        .Q(acc_H1_slip_V[33]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[34] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[34]),
        .Q(acc_H1_slip_V[34]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[35] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[35]),
        .Q(acc_H1_slip_V[35]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[35]_i_2 
       (.CI(\acc_H1_slip_V_reg[31]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[35]_i_2_n_0 ,\acc_H1_slip_V_reg[35]_i_2_n_1 ,\acc_H1_slip_V_reg[35]_i_2_n_2 ,\acc_H1_slip_V_reg[35]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[35]_i_3_n_0 ,\acc_H1_slip_V[35]_i_4_n_0 ,\acc_H1_slip_V[35]_i_5_n_0 ,\acc_H1_slip_V[35]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[35:32]),
        .S({\acc_H1_slip_V[35]_i_7_n_0 ,\acc_H1_slip_V[35]_i_8_n_0 ,\acc_H1_slip_V[35]_i_9_n_0 ,\acc_H1_slip_V[35]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[36] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[36]),
        .Q(acc_H1_slip_V[36]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[37] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[37]),
        .Q(acc_H1_slip_V[37]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[38] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[38]),
        .Q(acc_H1_slip_V[38]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[39] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[39]),
        .Q(acc_H1_slip_V[39]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[39]_i_2 
       (.CI(\acc_H1_slip_V_reg[35]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[39]_i_2_n_0 ,\acc_H1_slip_V_reg[39]_i_2_n_1 ,\acc_H1_slip_V_reg[39]_i_2_n_2 ,\acc_H1_slip_V_reg[39]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[39]_i_3_n_0 ,\acc_H1_slip_V[39]_i_4_n_0 ,\acc_H1_slip_V[39]_i_5_n_0 ,\acc_H1_slip_V[39]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[39:36]),
        .S({\acc_H1_slip_V[39]_i_7_n_0 ,\acc_H1_slip_V[39]_i_8_n_0 ,\acc_H1_slip_V[39]_i_9_n_0 ,\acc_H1_slip_V[39]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[3]),
        .Q(acc_H1_slip_V[3]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[3]_i_2 
       (.CI(\<const0> ),
        .CO({\acc_H1_slip_V_reg[3]_i_2_n_0 ,\acc_H1_slip_V_reg[3]_i_2_n_1 ,\acc_H1_slip_V_reg[3]_i_2_n_2 ,\acc_H1_slip_V_reg[3]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[3]_i_3_n_0 ,\acc_H1_slip_V[3]_i_4_n_0 ,\acc_H1_slip_V[3]_i_5_n_0 ,\<const0> }),
        .O(tmp_8_fu_673_p3[3:0]),
        .S({\acc_H1_slip_V[3]_i_6_n_0 ,\acc_H1_slip_V[3]_i_7_n_0 ,\acc_H1_slip_V[3]_i_8_n_0 ,\acc_H1_slip_V[3]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[40] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[40]),
        .Q(acc_H1_slip_V[40]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[41] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[41]),
        .Q(acc_H1_slip_V[41]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[42] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[42]),
        .Q(acc_H1_slip_V[42]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[43] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[43]),
        .Q(acc_H1_slip_V[43]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[43]_i_2 
       (.CI(\acc_H1_slip_V_reg[39]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[43]_i_2_n_0 ,\acc_H1_slip_V_reg[43]_i_2_n_1 ,\acc_H1_slip_V_reg[43]_i_2_n_2 ,\acc_H1_slip_V_reg[43]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[43]_i_3_n_0 ,\acc_H1_slip_V[43]_i_4_n_0 ,\acc_H1_slip_V[43]_i_5_n_0 ,\acc_H1_slip_V[43]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[43:40]),
        .S({\acc_H1_slip_V[43]_i_7_n_0 ,\acc_H1_slip_V[43]_i_8_n_0 ,\acc_H1_slip_V[43]_i_9_n_0 ,\acc_H1_slip_V[43]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[44] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[44]),
        .Q(acc_H1_slip_V[44]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[45] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[45]),
        .Q(acc_H1_slip_V[45]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[46] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[46]),
        .Q(acc_H1_slip_V[46]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[47] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[47]),
        .Q(acc_H1_slip_V[47]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[47]_i_3 
       (.CI(\acc_H1_slip_V_reg[43]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[47]_i_3_n_1 ,\acc_H1_slip_V_reg[47]_i_3_n_2 ,\acc_H1_slip_V_reg[47]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\acc_H1_slip_V[47]_i_4_n_0 ,\acc_H1_slip_V[47]_i_5_n_0 ,\acc_H1_slip_V[47]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[47:44]),
        .S({\acc_H1_slip_V[47]_i_7_n_0 ,\acc_H1_slip_V[47]_i_8_n_0 ,\acc_H1_slip_V[47]_i_9_n_0 ,\acc_H1_slip_V[47]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[4]),
        .Q(acc_H1_slip_V[4]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[5]),
        .Q(acc_H1_slip_V[5]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[6]),
        .Q(acc_H1_slip_V[6]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[7]),
        .Q(acc_H1_slip_V[7]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_H1_slip_V_reg[7]_i_2 
       (.CI(\acc_H1_slip_V_reg[3]_i_2_n_0 ),
        .CO({\acc_H1_slip_V_reg[7]_i_2_n_0 ,\acc_H1_slip_V_reg[7]_i_2_n_1 ,\acc_H1_slip_V_reg[7]_i_2_n_2 ,\acc_H1_slip_V_reg[7]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\acc_H1_slip_V[7]_i_3_n_0 ,\acc_H1_slip_V[7]_i_4_n_0 ,\acc_H1_slip_V[7]_i_5_n_0 ,\acc_H1_slip_V[7]_i_6_n_0 }),
        .O(tmp_8_fu_673_p3[7:4]),
        .S({\acc_H1_slip_V[7]_i_7_n_0 ,\acc_H1_slip_V[7]_i_8_n_0 ,\acc_H1_slip_V[7]_i_9_n_0 ,\acc_H1_slip_V[7]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[8]),
        .Q(acc_H1_slip_V[8]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_H1_slip_V_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(p_tmp_8_fu_693_p3[9]),
        .Q(acc_H1_slip_V[9]),
        .R(\acc_H1_slip_V[47]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \acc_LO_0_V[0]_i_1 
       (.I0(p_Val2_4_reg_1510),
        .I1(ap_enable_reg_pp0_iter5),
        .O(acc_LO_0_V0));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[0]_i_3 
       (.I0(in[3]),
        .I1(acc_LO_0_V_reg[3]),
        .O(\acc_LO_0_V[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[0]_i_4 
       (.I0(in[2]),
        .I1(acc_LO_0_V_reg[2]),
        .O(\acc_LO_0_V[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[0]_i_5 
       (.I0(in[1]),
        .I1(acc_LO_0_V_reg[1]),
        .O(\acc_LO_0_V[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[0]_i_6 
       (.I0(in[0]),
        .I1(acc_LO_0_V_reg[0]),
        .O(\acc_LO_0_V[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[12]_i_2 
       (.I0(in[15]),
        .I1(acc_LO_0_V_reg[15]),
        .O(\acc_LO_0_V[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[12]_i_3 
       (.I0(in[14]),
        .I1(acc_LO_0_V_reg[14]),
        .O(\acc_LO_0_V[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[12]_i_4 
       (.I0(in[13]),
        .I1(acc_LO_0_V_reg[13]),
        .O(\acc_LO_0_V[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[12]_i_5 
       (.I0(in[12]),
        .I1(acc_LO_0_V_reg[12]),
        .O(\acc_LO_0_V[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[16]_i_2 
       (.I0(in[19]),
        .I1(acc_LO_0_V_reg[19]),
        .O(\acc_LO_0_V[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[16]_i_3 
       (.I0(in[18]),
        .I1(acc_LO_0_V_reg[18]),
        .O(\acc_LO_0_V[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[16]_i_4 
       (.I0(in[17]),
        .I1(acc_LO_0_V_reg[17]),
        .O(\acc_LO_0_V[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[16]_i_5 
       (.I0(in[16]),
        .I1(acc_LO_0_V_reg[16]),
        .O(\acc_LO_0_V[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[20]_i_2 
       (.I0(in[23]),
        .I1(acc_LO_0_V_reg[23]),
        .O(\acc_LO_0_V[20]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[20]_i_3 
       (.I0(in[22]),
        .I1(acc_LO_0_V_reg[22]),
        .O(\acc_LO_0_V[20]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[20]_i_4 
       (.I0(in[21]),
        .I1(acc_LO_0_V_reg[21]),
        .O(\acc_LO_0_V[20]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[20]_i_5 
       (.I0(in[20]),
        .I1(acc_LO_0_V_reg[20]),
        .O(\acc_LO_0_V[20]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[24]_i_2 
       (.I0(in[27]),
        .I1(acc_LO_0_V_reg[27]),
        .O(\acc_LO_0_V[24]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[24]_i_3 
       (.I0(in[26]),
        .I1(acc_LO_0_V_reg[26]),
        .O(\acc_LO_0_V[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[24]_i_4 
       (.I0(in[25]),
        .I1(acc_LO_0_V_reg[25]),
        .O(\acc_LO_0_V[24]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[24]_i_5 
       (.I0(in[24]),
        .I1(acc_LO_0_V_reg[24]),
        .O(\acc_LO_0_V[24]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[28]_i_2 
       (.I0(in[31]),
        .I1(acc_LO_0_V_reg[31]),
        .O(\acc_LO_0_V[28]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[28]_i_3 
       (.I0(in[30]),
        .I1(acc_LO_0_V_reg[30]),
        .O(\acc_LO_0_V[28]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[28]_i_4 
       (.I0(in[29]),
        .I1(acc_LO_0_V_reg[29]),
        .O(\acc_LO_0_V[28]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[28]_i_5 
       (.I0(in[28]),
        .I1(acc_LO_0_V_reg[28]),
        .O(\acc_LO_0_V[28]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[32]_i_2 
       (.I0(in[35]),
        .I1(acc_LO_0_V_reg[35]),
        .O(\acc_LO_0_V[32]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[32]_i_3 
       (.I0(in[34]),
        .I1(acc_LO_0_V_reg[34]),
        .O(\acc_LO_0_V[32]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[32]_i_4 
       (.I0(in[33]),
        .I1(acc_LO_0_V_reg[33]),
        .O(\acc_LO_0_V[32]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[32]_i_5 
       (.I0(in[32]),
        .I1(acc_LO_0_V_reg[32]),
        .O(\acc_LO_0_V[32]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[36]_i_2 
       (.I0(in[39]),
        .I1(acc_LO_0_V_reg[39]),
        .O(\acc_LO_0_V[36]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[36]_i_3 
       (.I0(in[38]),
        .I1(acc_LO_0_V_reg[38]),
        .O(\acc_LO_0_V[36]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[36]_i_4 
       (.I0(in[37]),
        .I1(acc_LO_0_V_reg[37]),
        .O(\acc_LO_0_V[36]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[36]_i_5 
       (.I0(in[36]),
        .I1(acc_LO_0_V_reg[36]),
        .O(\acc_LO_0_V[36]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[40]_i_2 
       (.I0(in[43]),
        .I1(acc_LO_0_V_reg[43]),
        .O(\acc_LO_0_V[40]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[40]_i_3 
       (.I0(in[42]),
        .I1(acc_LO_0_V_reg[42]),
        .O(\acc_LO_0_V[40]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[40]_i_4 
       (.I0(in[41]),
        .I1(acc_LO_0_V_reg[41]),
        .O(\acc_LO_0_V[40]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[40]_i_5 
       (.I0(in[40]),
        .I1(acc_LO_0_V_reg[40]),
        .O(\acc_LO_0_V[40]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[44]_i_2 
       (.I0(acc_LO_0_V_reg[47]),
        .I1(in[47]),
        .O(\acc_LO_0_V[44]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[44]_i_3 
       (.I0(in[46]),
        .I1(acc_LO_0_V_reg[46]),
        .O(\acc_LO_0_V[44]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[44]_i_4 
       (.I0(in[45]),
        .I1(acc_LO_0_V_reg[45]),
        .O(\acc_LO_0_V[44]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[44]_i_5 
       (.I0(in[44]),
        .I1(acc_LO_0_V_reg[44]),
        .O(\acc_LO_0_V[44]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[4]_i_2 
       (.I0(in[7]),
        .I1(acc_LO_0_V_reg[7]),
        .O(\acc_LO_0_V[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[4]_i_3 
       (.I0(in[6]),
        .I1(acc_LO_0_V_reg[6]),
        .O(\acc_LO_0_V[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[4]_i_4 
       (.I0(in[5]),
        .I1(acc_LO_0_V_reg[5]),
        .O(\acc_LO_0_V[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[4]_i_5 
       (.I0(in[4]),
        .I1(acc_LO_0_V_reg[4]),
        .O(\acc_LO_0_V[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[8]_i_2 
       (.I0(in[11]),
        .I1(acc_LO_0_V_reg[11]),
        .O(\acc_LO_0_V[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[8]_i_3 
       (.I0(in[10]),
        .I1(acc_LO_0_V_reg[10]),
        .O(\acc_LO_0_V[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[8]_i_4 
       (.I0(in[9]),
        .I1(acc_LO_0_V_reg[9]),
        .O(\acc_LO_0_V[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_0_V[8]_i_5 
       (.I0(in[8]),
        .I1(acc_LO_0_V_reg[8]),
        .O(\acc_LO_0_V[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[0] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[0]_i_2_n_7 ),
        .Q(acc_LO_0_V_reg[0]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[0]_i_2 
       (.CI(\<const0> ),
        .CO({\acc_LO_0_V_reg[0]_i_2_n_0 ,\acc_LO_0_V_reg[0]_i_2_n_1 ,\acc_LO_0_V_reg[0]_i_2_n_2 ,\acc_LO_0_V_reg[0]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[3:0]),
        .O({\acc_LO_0_V_reg[0]_i_2_n_4 ,\acc_LO_0_V_reg[0]_i_2_n_5 ,\acc_LO_0_V_reg[0]_i_2_n_6 ,\acc_LO_0_V_reg[0]_i_2_n_7 }),
        .S({\acc_LO_0_V[0]_i_3_n_0 ,\acc_LO_0_V[0]_i_4_n_0 ,\acc_LO_0_V[0]_i_5_n_0 ,\acc_LO_0_V[0]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[10] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[8]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[10]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[11] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[8]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[11]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[12] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[12]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[12]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[12]_i_1 
       (.CI(\acc_LO_0_V_reg[8]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[12]_i_1_n_0 ,\acc_LO_0_V_reg[12]_i_1_n_1 ,\acc_LO_0_V_reg[12]_i_1_n_2 ,\acc_LO_0_V_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[15:12]),
        .O({\acc_LO_0_V_reg[12]_i_1_n_4 ,\acc_LO_0_V_reg[12]_i_1_n_5 ,\acc_LO_0_V_reg[12]_i_1_n_6 ,\acc_LO_0_V_reg[12]_i_1_n_7 }),
        .S({\acc_LO_0_V[12]_i_2_n_0 ,\acc_LO_0_V[12]_i_3_n_0 ,\acc_LO_0_V[12]_i_4_n_0 ,\acc_LO_0_V[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[13] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[12]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[13]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[14] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[12]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[14]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[15] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[12]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[15]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[16] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[16]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[16]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[16]_i_1 
       (.CI(\acc_LO_0_V_reg[12]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[16]_i_1_n_0 ,\acc_LO_0_V_reg[16]_i_1_n_1 ,\acc_LO_0_V_reg[16]_i_1_n_2 ,\acc_LO_0_V_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[19:16]),
        .O({\acc_LO_0_V_reg[16]_i_1_n_4 ,\acc_LO_0_V_reg[16]_i_1_n_5 ,\acc_LO_0_V_reg[16]_i_1_n_6 ,\acc_LO_0_V_reg[16]_i_1_n_7 }),
        .S({\acc_LO_0_V[16]_i_2_n_0 ,\acc_LO_0_V[16]_i_3_n_0 ,\acc_LO_0_V[16]_i_4_n_0 ,\acc_LO_0_V[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[17] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[16]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[17]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[18] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[16]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[18]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[19] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[16]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[19]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[1] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[0]_i_2_n_6 ),
        .Q(acc_LO_0_V_reg[1]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[20] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[20]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[20]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[20]_i_1 
       (.CI(\acc_LO_0_V_reg[16]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[20]_i_1_n_0 ,\acc_LO_0_V_reg[20]_i_1_n_1 ,\acc_LO_0_V_reg[20]_i_1_n_2 ,\acc_LO_0_V_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[23:20]),
        .O({\acc_LO_0_V_reg[20]_i_1_n_4 ,\acc_LO_0_V_reg[20]_i_1_n_5 ,\acc_LO_0_V_reg[20]_i_1_n_6 ,\acc_LO_0_V_reg[20]_i_1_n_7 }),
        .S({\acc_LO_0_V[20]_i_2_n_0 ,\acc_LO_0_V[20]_i_3_n_0 ,\acc_LO_0_V[20]_i_4_n_0 ,\acc_LO_0_V[20]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[21] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[20]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[21]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[22] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[20]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[22]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[23] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[20]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[23]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[24] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[24]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[24]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[24]_i_1 
       (.CI(\acc_LO_0_V_reg[20]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[24]_i_1_n_0 ,\acc_LO_0_V_reg[24]_i_1_n_1 ,\acc_LO_0_V_reg[24]_i_1_n_2 ,\acc_LO_0_V_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[27:24]),
        .O({\acc_LO_0_V_reg[24]_i_1_n_4 ,\acc_LO_0_V_reg[24]_i_1_n_5 ,\acc_LO_0_V_reg[24]_i_1_n_6 ,\acc_LO_0_V_reg[24]_i_1_n_7 }),
        .S({\acc_LO_0_V[24]_i_2_n_0 ,\acc_LO_0_V[24]_i_3_n_0 ,\acc_LO_0_V[24]_i_4_n_0 ,\acc_LO_0_V[24]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[25] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[24]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[25]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[26] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[24]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[26]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[27] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[24]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[27]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[28] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[28]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[28]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[28]_i_1 
       (.CI(\acc_LO_0_V_reg[24]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[28]_i_1_n_0 ,\acc_LO_0_V_reg[28]_i_1_n_1 ,\acc_LO_0_V_reg[28]_i_1_n_2 ,\acc_LO_0_V_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[31:28]),
        .O({\acc_LO_0_V_reg[28]_i_1_n_4 ,\acc_LO_0_V_reg[28]_i_1_n_5 ,\acc_LO_0_V_reg[28]_i_1_n_6 ,\acc_LO_0_V_reg[28]_i_1_n_7 }),
        .S({\acc_LO_0_V[28]_i_2_n_0 ,\acc_LO_0_V[28]_i_3_n_0 ,\acc_LO_0_V[28]_i_4_n_0 ,\acc_LO_0_V[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[29] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[28]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[29]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[2] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[0]_i_2_n_5 ),
        .Q(acc_LO_0_V_reg[2]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[30] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[28]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[30]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[31] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[28]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[31]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[32] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[32]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[32]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[32]_i_1 
       (.CI(\acc_LO_0_V_reg[28]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[32]_i_1_n_0 ,\acc_LO_0_V_reg[32]_i_1_n_1 ,\acc_LO_0_V_reg[32]_i_1_n_2 ,\acc_LO_0_V_reg[32]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[35:32]),
        .O({\acc_LO_0_V_reg[32]_i_1_n_4 ,\acc_LO_0_V_reg[32]_i_1_n_5 ,\acc_LO_0_V_reg[32]_i_1_n_6 ,\acc_LO_0_V_reg[32]_i_1_n_7 }),
        .S({\acc_LO_0_V[32]_i_2_n_0 ,\acc_LO_0_V[32]_i_3_n_0 ,\acc_LO_0_V[32]_i_4_n_0 ,\acc_LO_0_V[32]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[33] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[32]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[33]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[34] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[32]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[34]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[35] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[32]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[35]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[36] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[36]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[36]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[36]_i_1 
       (.CI(\acc_LO_0_V_reg[32]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[36]_i_1_n_0 ,\acc_LO_0_V_reg[36]_i_1_n_1 ,\acc_LO_0_V_reg[36]_i_1_n_2 ,\acc_LO_0_V_reg[36]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[39:36]),
        .O({\acc_LO_0_V_reg[36]_i_1_n_4 ,\acc_LO_0_V_reg[36]_i_1_n_5 ,\acc_LO_0_V_reg[36]_i_1_n_6 ,\acc_LO_0_V_reg[36]_i_1_n_7 }),
        .S({\acc_LO_0_V[36]_i_2_n_0 ,\acc_LO_0_V[36]_i_3_n_0 ,\acc_LO_0_V[36]_i_4_n_0 ,\acc_LO_0_V[36]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[37] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[36]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[37]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[38] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[36]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[38]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[39] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[36]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[39]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[3] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[0]_i_2_n_4 ),
        .Q(acc_LO_0_V_reg[3]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[40] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[40]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[40]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[40]_i_1 
       (.CI(\acc_LO_0_V_reg[36]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[40]_i_1_n_0 ,\acc_LO_0_V_reg[40]_i_1_n_1 ,\acc_LO_0_V_reg[40]_i_1_n_2 ,\acc_LO_0_V_reg[40]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[43:40]),
        .O({\acc_LO_0_V_reg[40]_i_1_n_4 ,\acc_LO_0_V_reg[40]_i_1_n_5 ,\acc_LO_0_V_reg[40]_i_1_n_6 ,\acc_LO_0_V_reg[40]_i_1_n_7 }),
        .S({\acc_LO_0_V[40]_i_2_n_0 ,\acc_LO_0_V[40]_i_3_n_0 ,\acc_LO_0_V[40]_i_4_n_0 ,\acc_LO_0_V[40]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[41] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[40]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[41]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[42] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[40]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[42]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[43] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[40]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[43]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[44] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[44]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[44]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[44]_i_1 
       (.CI(\acc_LO_0_V_reg[40]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[44]_i_1_n_1 ,\acc_LO_0_V_reg[44]_i_1_n_2 ,\acc_LO_0_V_reg[44]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,in[46:44]}),
        .O({\acc_LO_0_V_reg[44]_i_1_n_4 ,\acc_LO_0_V_reg[44]_i_1_n_5 ,\acc_LO_0_V_reg[44]_i_1_n_6 ,\acc_LO_0_V_reg[44]_i_1_n_7 }),
        .S({\acc_LO_0_V[44]_i_2_n_0 ,\acc_LO_0_V[44]_i_3_n_0 ,\acc_LO_0_V[44]_i_4_n_0 ,\acc_LO_0_V[44]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[45] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[44]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[45]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[46] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[44]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[46]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[47] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[44]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[47]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[4] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[4]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[4]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[4]_i_1 
       (.CI(\acc_LO_0_V_reg[0]_i_2_n_0 ),
        .CO({\acc_LO_0_V_reg[4]_i_1_n_0 ,\acc_LO_0_V_reg[4]_i_1_n_1 ,\acc_LO_0_V_reg[4]_i_1_n_2 ,\acc_LO_0_V_reg[4]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[7:4]),
        .O({\acc_LO_0_V_reg[4]_i_1_n_4 ,\acc_LO_0_V_reg[4]_i_1_n_5 ,\acc_LO_0_V_reg[4]_i_1_n_6 ,\acc_LO_0_V_reg[4]_i_1_n_7 }),
        .S({\acc_LO_0_V[4]_i_2_n_0 ,\acc_LO_0_V[4]_i_3_n_0 ,\acc_LO_0_V[4]_i_4_n_0 ,\acc_LO_0_V[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[5] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[4]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[5]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[6] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[4]_i_1_n_5 ),
        .Q(acc_LO_0_V_reg[6]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[7] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[4]_i_1_n_4 ),
        .Q(acc_LO_0_V_reg[7]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[8] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[8]_i_1_n_7 ),
        .Q(acc_LO_0_V_reg[8]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_0_V_reg[8]_i_1 
       (.CI(\acc_LO_0_V_reg[4]_i_1_n_0 ),
        .CO({\acc_LO_0_V_reg[8]_i_1_n_0 ,\acc_LO_0_V_reg[8]_i_1_n_1 ,\acc_LO_0_V_reg[8]_i_1_n_2 ,\acc_LO_0_V_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(in[11:8]),
        .O({\acc_LO_0_V_reg[8]_i_1_n_4 ,\acc_LO_0_V_reg[8]_i_1_n_5 ,\acc_LO_0_V_reg[8]_i_1_n_6 ,\acc_LO_0_V_reg[8]_i_1_n_7 }),
        .S({\acc_LO_0_V[8]_i_2_n_0 ,\acc_LO_0_V[8]_i_3_n_0 ,\acc_LO_0_V[8]_i_4_n_0 ,\acc_LO_0_V[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_0_V_reg[9] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_0_V_reg[8]_i_1_n_6 ),
        .Q(acc_LO_0_V_reg[9]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[0]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[3] ),
        .I1(acc_LO_1_V_reg[3]),
        .O(\acc_LO_1_V[0]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[0]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[2] ),
        .I1(acc_LO_1_V_reg[2]),
        .O(\acc_LO_1_V[0]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[0]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[1] ),
        .I1(acc_LO_1_V_reg[1]),
        .O(\acc_LO_1_V[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[0]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[0] ),
        .I1(acc_LO_1_V_reg[0]),
        .O(\acc_LO_1_V[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[12]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[15] ),
        .I1(acc_LO_1_V_reg[15]),
        .O(\acc_LO_1_V[12]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[12]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[14] ),
        .I1(acc_LO_1_V_reg[14]),
        .O(\acc_LO_1_V[12]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[12]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[13] ),
        .I1(acc_LO_1_V_reg[13]),
        .O(\acc_LO_1_V[12]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[12]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[12] ),
        .I1(acc_LO_1_V_reg[12]),
        .O(\acc_LO_1_V[12]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[16]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[19] ),
        .I1(acc_LO_1_V_reg[19]),
        .O(\acc_LO_1_V[16]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[16]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[18] ),
        .I1(acc_LO_1_V_reg[18]),
        .O(\acc_LO_1_V[16]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[16]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[17] ),
        .I1(acc_LO_1_V_reg[17]),
        .O(\acc_LO_1_V[16]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[16]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[16] ),
        .I1(acc_LO_1_V_reg[16]),
        .O(\acc_LO_1_V[16]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[20]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[23] ),
        .I1(acc_LO_1_V_reg[23]),
        .O(\acc_LO_1_V[20]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[20]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[22] ),
        .I1(acc_LO_1_V_reg[22]),
        .O(\acc_LO_1_V[20]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[20]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[21] ),
        .I1(acc_LO_1_V_reg[21]),
        .O(\acc_LO_1_V[20]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[20]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[20] ),
        .I1(acc_LO_1_V_reg[20]),
        .O(\acc_LO_1_V[20]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[24]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[27] ),
        .I1(acc_LO_1_V_reg[27]),
        .O(\acc_LO_1_V[24]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[24]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[26] ),
        .I1(acc_LO_1_V_reg[26]),
        .O(\acc_LO_1_V[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[24]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[25] ),
        .I1(acc_LO_1_V_reg[25]),
        .O(\acc_LO_1_V[24]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[24]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[24] ),
        .I1(acc_LO_1_V_reg[24]),
        .O(\acc_LO_1_V[24]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[28]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[31] ),
        .I1(acc_LO_1_V_reg[31]),
        .O(\acc_LO_1_V[28]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[28]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[30] ),
        .I1(acc_LO_1_V_reg[30]),
        .O(\acc_LO_1_V[28]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[28]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[29] ),
        .I1(acc_LO_1_V_reg[29]),
        .O(\acc_LO_1_V[28]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[28]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[28] ),
        .I1(acc_LO_1_V_reg[28]),
        .O(\acc_LO_1_V[28]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[32]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[35] ),
        .I1(acc_LO_1_V_reg[35]),
        .O(\acc_LO_1_V[32]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[32]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[34] ),
        .I1(acc_LO_1_V_reg[34]),
        .O(\acc_LO_1_V[32]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[32]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[33] ),
        .I1(acc_LO_1_V_reg[33]),
        .O(\acc_LO_1_V[32]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[32]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[32] ),
        .I1(acc_LO_1_V_reg[32]),
        .O(\acc_LO_1_V[32]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[36]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[39] ),
        .I1(acc_LO_1_V_reg[39]),
        .O(\acc_LO_1_V[36]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[36]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[38] ),
        .I1(acc_LO_1_V_reg[38]),
        .O(\acc_LO_1_V[36]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[36]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[37] ),
        .I1(acc_LO_1_V_reg[37]),
        .O(\acc_LO_1_V[36]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[36]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[36] ),
        .I1(acc_LO_1_V_reg[36]),
        .O(\acc_LO_1_V[36]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[40]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[43] ),
        .I1(acc_LO_1_V_reg[43]),
        .O(\acc_LO_1_V[40]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[40]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[42] ),
        .I1(acc_LO_1_V_reg[42]),
        .O(\acc_LO_1_V[40]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[40]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[41] ),
        .I1(acc_LO_1_V_reg[41]),
        .O(\acc_LO_1_V[40]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[40]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[40] ),
        .I1(acc_LO_1_V_reg[40]),
        .O(\acc_LO_1_V[40]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[44]_i_2 
       (.I0(acc_LO_1_V_reg[47]),
        .I1(\inputs_current_ftw_L_reg_n_0_[47] ),
        .O(\acc_LO_1_V[44]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[44]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[46] ),
        .I1(acc_LO_1_V_reg[46]),
        .O(\acc_LO_1_V[44]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[44]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[45] ),
        .I1(acc_LO_1_V_reg[45]),
        .O(\acc_LO_1_V[44]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[44]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[44] ),
        .I1(acc_LO_1_V_reg[44]),
        .O(\acc_LO_1_V[44]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[4]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[7] ),
        .I1(acc_LO_1_V_reg[7]),
        .O(\acc_LO_1_V[4]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[4]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[6] ),
        .I1(acc_LO_1_V_reg[6]),
        .O(\acc_LO_1_V[4]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[4]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[5] ),
        .I1(acc_LO_1_V_reg[5]),
        .O(\acc_LO_1_V[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[4]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[4] ),
        .I1(acc_LO_1_V_reg[4]),
        .O(\acc_LO_1_V[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[8]_i_2 
       (.I0(\inputs_current_ftw_L_reg_n_0_[11] ),
        .I1(acc_LO_1_V_reg[11]),
        .O(\acc_LO_1_V[8]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[8]_i_3 
       (.I0(\inputs_current_ftw_L_reg_n_0_[10] ),
        .I1(acc_LO_1_V_reg[10]),
        .O(\acc_LO_1_V[8]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[8]_i_4 
       (.I0(\inputs_current_ftw_L_reg_n_0_[9] ),
        .I1(acc_LO_1_V_reg[9]),
        .O(\acc_LO_1_V[8]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \acc_LO_1_V[8]_i_5 
       (.I0(\inputs_current_ftw_L_reg_n_0_[8] ),
        .I1(acc_LO_1_V_reg[8]),
        .O(\acc_LO_1_V[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[0] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[0]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[0]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[0]_i_1 
       (.CI(\<const0> ),
        .CO({\acc_LO_1_V_reg[0]_i_1_n_0 ,\acc_LO_1_V_reg[0]_i_1_n_1 ,\acc_LO_1_V_reg[0]_i_1_n_2 ,\acc_LO_1_V_reg[0]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[3] ,\inputs_current_ftw_L_reg_n_0_[2] ,\inputs_current_ftw_L_reg_n_0_[1] ,\inputs_current_ftw_L_reg_n_0_[0] }),
        .O({\acc_LO_1_V_reg[0]_i_1_n_4 ,\acc_LO_1_V_reg[0]_i_1_n_5 ,\acc_LO_1_V_reg[0]_i_1_n_6 ,\acc_LO_1_V_reg[0]_i_1_n_7 }),
        .S({\acc_LO_1_V[0]_i_2_n_0 ,\acc_LO_1_V[0]_i_3_n_0 ,\acc_LO_1_V[0]_i_4_n_0 ,\acc_LO_1_V[0]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[10] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[8]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[10]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[11] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[8]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[11]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[12] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[12]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[12]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[12]_i_1 
       (.CI(\acc_LO_1_V_reg[8]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[12]_i_1_n_0 ,\acc_LO_1_V_reg[12]_i_1_n_1 ,\acc_LO_1_V_reg[12]_i_1_n_2 ,\acc_LO_1_V_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[15] ,\inputs_current_ftw_L_reg_n_0_[14] ,\inputs_current_ftw_L_reg_n_0_[13] ,\inputs_current_ftw_L_reg_n_0_[12] }),
        .O({\acc_LO_1_V_reg[12]_i_1_n_4 ,\acc_LO_1_V_reg[12]_i_1_n_5 ,\acc_LO_1_V_reg[12]_i_1_n_6 ,\acc_LO_1_V_reg[12]_i_1_n_7 }),
        .S({\acc_LO_1_V[12]_i_2_n_0 ,\acc_LO_1_V[12]_i_3_n_0 ,\acc_LO_1_V[12]_i_4_n_0 ,\acc_LO_1_V[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[13] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[12]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[13]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[14] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[12]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[14]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[15] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[12]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[15]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[16] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[16]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[16]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[16]_i_1 
       (.CI(\acc_LO_1_V_reg[12]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[16]_i_1_n_0 ,\acc_LO_1_V_reg[16]_i_1_n_1 ,\acc_LO_1_V_reg[16]_i_1_n_2 ,\acc_LO_1_V_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[19] ,\inputs_current_ftw_L_reg_n_0_[18] ,\inputs_current_ftw_L_reg_n_0_[17] ,\inputs_current_ftw_L_reg_n_0_[16] }),
        .O({\acc_LO_1_V_reg[16]_i_1_n_4 ,\acc_LO_1_V_reg[16]_i_1_n_5 ,\acc_LO_1_V_reg[16]_i_1_n_6 ,\acc_LO_1_V_reg[16]_i_1_n_7 }),
        .S({\acc_LO_1_V[16]_i_2_n_0 ,\acc_LO_1_V[16]_i_3_n_0 ,\acc_LO_1_V[16]_i_4_n_0 ,\acc_LO_1_V[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[17] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[16]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[17]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[18] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[16]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[18]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[19] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[16]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[19]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[1] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[0]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[1]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[20] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[20]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[20]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[20]_i_1 
       (.CI(\acc_LO_1_V_reg[16]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[20]_i_1_n_0 ,\acc_LO_1_V_reg[20]_i_1_n_1 ,\acc_LO_1_V_reg[20]_i_1_n_2 ,\acc_LO_1_V_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[23] ,\inputs_current_ftw_L_reg_n_0_[22] ,\inputs_current_ftw_L_reg_n_0_[21] ,\inputs_current_ftw_L_reg_n_0_[20] }),
        .O({\acc_LO_1_V_reg[20]_i_1_n_4 ,\acc_LO_1_V_reg[20]_i_1_n_5 ,\acc_LO_1_V_reg[20]_i_1_n_6 ,\acc_LO_1_V_reg[20]_i_1_n_7 }),
        .S({\acc_LO_1_V[20]_i_2_n_0 ,\acc_LO_1_V[20]_i_3_n_0 ,\acc_LO_1_V[20]_i_4_n_0 ,\acc_LO_1_V[20]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[21] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[20]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[21]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[22] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[20]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[22]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[23] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[20]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[23]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[24] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[24]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[24]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[24]_i_1 
       (.CI(\acc_LO_1_V_reg[20]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[24]_i_1_n_0 ,\acc_LO_1_V_reg[24]_i_1_n_1 ,\acc_LO_1_V_reg[24]_i_1_n_2 ,\acc_LO_1_V_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[27] ,\inputs_current_ftw_L_reg_n_0_[26] ,\inputs_current_ftw_L_reg_n_0_[25] ,\inputs_current_ftw_L_reg_n_0_[24] }),
        .O({\acc_LO_1_V_reg[24]_i_1_n_4 ,\acc_LO_1_V_reg[24]_i_1_n_5 ,\acc_LO_1_V_reg[24]_i_1_n_6 ,\acc_LO_1_V_reg[24]_i_1_n_7 }),
        .S({\acc_LO_1_V[24]_i_2_n_0 ,\acc_LO_1_V[24]_i_3_n_0 ,\acc_LO_1_V[24]_i_4_n_0 ,\acc_LO_1_V[24]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[25] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[24]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[25]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[26] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[24]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[26]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[27] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[24]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[27]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[28] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[28]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[28]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[28]_i_1 
       (.CI(\acc_LO_1_V_reg[24]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[28]_i_1_n_0 ,\acc_LO_1_V_reg[28]_i_1_n_1 ,\acc_LO_1_V_reg[28]_i_1_n_2 ,\acc_LO_1_V_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[31] ,\inputs_current_ftw_L_reg_n_0_[30] ,\inputs_current_ftw_L_reg_n_0_[29] ,\inputs_current_ftw_L_reg_n_0_[28] }),
        .O({\acc_LO_1_V_reg[28]_i_1_n_4 ,\acc_LO_1_V_reg[28]_i_1_n_5 ,\acc_LO_1_V_reg[28]_i_1_n_6 ,\acc_LO_1_V_reg[28]_i_1_n_7 }),
        .S({\acc_LO_1_V[28]_i_2_n_0 ,\acc_LO_1_V[28]_i_3_n_0 ,\acc_LO_1_V[28]_i_4_n_0 ,\acc_LO_1_V[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[29] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[28]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[29]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[2] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[0]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[2]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[30] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[28]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[30]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[31] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[28]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[31]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[32] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[32]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[32]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[32]_i_1 
       (.CI(\acc_LO_1_V_reg[28]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[32]_i_1_n_0 ,\acc_LO_1_V_reg[32]_i_1_n_1 ,\acc_LO_1_V_reg[32]_i_1_n_2 ,\acc_LO_1_V_reg[32]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[35] ,\inputs_current_ftw_L_reg_n_0_[34] ,\inputs_current_ftw_L_reg_n_0_[33] ,\inputs_current_ftw_L_reg_n_0_[32] }),
        .O({\acc_LO_1_V_reg[32]_i_1_n_4 ,\acc_LO_1_V_reg[32]_i_1_n_5 ,\acc_LO_1_V_reg[32]_i_1_n_6 ,\acc_LO_1_V_reg[32]_i_1_n_7 }),
        .S({\acc_LO_1_V[32]_i_2_n_0 ,\acc_LO_1_V[32]_i_3_n_0 ,\acc_LO_1_V[32]_i_4_n_0 ,\acc_LO_1_V[32]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[33] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[32]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[33]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[34] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[32]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[34]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[35] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[32]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[35]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[36] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[36]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[36]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[36]_i_1 
       (.CI(\acc_LO_1_V_reg[32]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[36]_i_1_n_0 ,\acc_LO_1_V_reg[36]_i_1_n_1 ,\acc_LO_1_V_reg[36]_i_1_n_2 ,\acc_LO_1_V_reg[36]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[39] ,\inputs_current_ftw_L_reg_n_0_[38] ,\inputs_current_ftw_L_reg_n_0_[37] ,\inputs_current_ftw_L_reg_n_0_[36] }),
        .O({\acc_LO_1_V_reg[36]_i_1_n_4 ,\acc_LO_1_V_reg[36]_i_1_n_5 ,\acc_LO_1_V_reg[36]_i_1_n_6 ,\acc_LO_1_V_reg[36]_i_1_n_7 }),
        .S({\acc_LO_1_V[36]_i_2_n_0 ,\acc_LO_1_V[36]_i_3_n_0 ,\acc_LO_1_V[36]_i_4_n_0 ,\acc_LO_1_V[36]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[37] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[36]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[37]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[38] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[36]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[38]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[39] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[36]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[39]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[3] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[0]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[3]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[40] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[40]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[40]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[40]_i_1 
       (.CI(\acc_LO_1_V_reg[36]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[40]_i_1_n_0 ,\acc_LO_1_V_reg[40]_i_1_n_1 ,\acc_LO_1_V_reg[40]_i_1_n_2 ,\acc_LO_1_V_reg[40]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[43] ,\inputs_current_ftw_L_reg_n_0_[42] ,\inputs_current_ftw_L_reg_n_0_[41] ,\inputs_current_ftw_L_reg_n_0_[40] }),
        .O({\acc_LO_1_V_reg[40]_i_1_n_4 ,\acc_LO_1_V_reg[40]_i_1_n_5 ,\acc_LO_1_V_reg[40]_i_1_n_6 ,\acc_LO_1_V_reg[40]_i_1_n_7 }),
        .S({\acc_LO_1_V[40]_i_2_n_0 ,\acc_LO_1_V[40]_i_3_n_0 ,\acc_LO_1_V[40]_i_4_n_0 ,\acc_LO_1_V[40]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[41] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[40]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[41]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[42] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[40]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[42]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[43] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[40]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[43]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[44] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[44]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[44]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[44]_i_1 
       (.CI(\acc_LO_1_V_reg[40]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[44]_i_1_n_1 ,\acc_LO_1_V_reg[44]_i_1_n_2 ,\acc_LO_1_V_reg[44]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\inputs_current_ftw_L_reg_n_0_[46] ,\inputs_current_ftw_L_reg_n_0_[45] ,\inputs_current_ftw_L_reg_n_0_[44] }),
        .O({\acc_LO_1_V_reg[44]_i_1_n_4 ,\acc_LO_1_V_reg[44]_i_1_n_5 ,\acc_LO_1_V_reg[44]_i_1_n_6 ,\acc_LO_1_V_reg[44]_i_1_n_7 }),
        .S({\acc_LO_1_V[44]_i_2_n_0 ,\acc_LO_1_V[44]_i_3_n_0 ,\acc_LO_1_V[44]_i_4_n_0 ,\acc_LO_1_V[44]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[45] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[44]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[45]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[46] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[44]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[46]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[47] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[44]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[47]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[4] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[4]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[4]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[4]_i_1 
       (.CI(\acc_LO_1_V_reg[0]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[4]_i_1_n_0 ,\acc_LO_1_V_reg[4]_i_1_n_1 ,\acc_LO_1_V_reg[4]_i_1_n_2 ,\acc_LO_1_V_reg[4]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[7] ,\inputs_current_ftw_L_reg_n_0_[6] ,\inputs_current_ftw_L_reg_n_0_[5] ,\inputs_current_ftw_L_reg_n_0_[4] }),
        .O({\acc_LO_1_V_reg[4]_i_1_n_4 ,\acc_LO_1_V_reg[4]_i_1_n_5 ,\acc_LO_1_V_reg[4]_i_1_n_6 ,\acc_LO_1_V_reg[4]_i_1_n_7 }),
        .S({\acc_LO_1_V[4]_i_2_n_0 ,\acc_LO_1_V[4]_i_3_n_0 ,\acc_LO_1_V[4]_i_4_n_0 ,\acc_LO_1_V[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[5] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[4]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[5]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[6] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[4]_i_1_n_5 ),
        .Q(acc_LO_1_V_reg[6]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[7] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[4]_i_1_n_4 ),
        .Q(acc_LO_1_V_reg[7]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[8] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[8]_i_1_n_7 ),
        .Q(acc_LO_1_V_reg[8]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \acc_LO_1_V_reg[8]_i_1 
       (.CI(\acc_LO_1_V_reg[4]_i_1_n_0 ),
        .CO({\acc_LO_1_V_reg[8]_i_1_n_0 ,\acc_LO_1_V_reg[8]_i_1_n_1 ,\acc_LO_1_V_reg[8]_i_1_n_2 ,\acc_LO_1_V_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\inputs_current_ftw_L_reg_n_0_[11] ,\inputs_current_ftw_L_reg_n_0_[10] ,\inputs_current_ftw_L_reg_n_0_[9] ,\inputs_current_ftw_L_reg_n_0_[8] }),
        .O({\acc_LO_1_V_reg[8]_i_1_n_4 ,\acc_LO_1_V_reg[8]_i_1_n_5 ,\acc_LO_1_V_reg[8]_i_1_n_6 ,\acc_LO_1_V_reg[8]_i_1_n_7 }),
        .S({\acc_LO_1_V[8]_i_2_n_0 ,\acc_LO_1_V[8]_i_3_n_0 ,\acc_LO_1_V[8]_i_4_n_0 ,\acc_LO_1_V[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \acc_LO_1_V_reg[9] 
       (.C(ap_clk),
        .CE(acc_LO_0_V0),
        .D(\acc_LO_1_V_reg[8]_i_1_n_6 ),
        .Q(acc_LO_1_V_reg[9]),
        .R(\acc_H1_FSK_V[47]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000002FFFFFFFF)) 
    ap_enable_reg_pp0_iter1_i_1
       (.I0(ap_enable_reg_pp0_iter1_i_2_n_0),
        .I1(ap_enable_reg_pp0_iter1_i_3_n_0),
        .I2(ap_enable_reg_pp0_iter1_i_4_n_0),
        .I3(ap_enable_reg_pp0_iter1_i_5_n_0),
        .I4(ap_enable_reg_pp0_iter1_i_6_n_0),
        .I5(ap_enable_reg_pp0_iter1),
        .O(p_Val2_4_reg_1510));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    ap_enable_reg_pp0_iter1_i_2
       (.I0(inputs_force_AM_ap_vld_preg),
        .I1(inputs_ftw_H1_V_ap_vld_preg),
        .I2(inputs_coef_V_ap_vld_preg),
        .I3(inputs_reset_FSK_ap_vld_preg),
        .I4(inputs_offset_AM_off_V_ap_vld_preg),
        .I5(inputs_rate_V_ap_vld_preg),
        .O(ap_enable_reg_pp0_iter1_i_2_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    ap_enable_reg_pp0_iter1_i_3
       (.I0(inputs_ftw_H1_on_V_ap_vld_preg),
        .I1(inputs_phase_H1_comp_V_ap_vld_preg),
        .I2(inputs_enable_FSK_ap_vld_preg),
        .I3(inputs_offset_AM_on_V_ap_vld_preg),
        .O(ap_enable_reg_pp0_iter1_i_3_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    ap_enable_reg_pp0_iter1_i_4
       (.I0(inputs_dftw_H1_slip_V_ap_vld_preg),
        .I1(inputs_ftw_LO_0_V_ap_vld_preg),
        .I2(inputs_offset_FSK_V_ap_vld_preg),
        .I3(inputs_ftw_LO_1_V_ap_vld_preg),
        .O(ap_enable_reg_pp0_iter1_i_4_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    ap_enable_reg_pp0_iter1_i_5
       (.I0(inputs_reset_slip_ap_vld_preg),
        .I1(inputs_offset_V_ap_vld_preg),
        .I2(inputs_H_V_ap_vld_preg),
        .I3(inputs_valid_ap_vld_preg),
        .O(ap_enable_reg_pp0_iter1_i_5_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    ap_enable_reg_pp0_iter1_i_6
       (.I0(inputs_reset_NCO_ap_vld_preg),
        .I1(inputs_enable_slip_ap_vld_preg),
        .I2(inputs_slip_sign_ap_vld_preg),
        .I3(inputs_ftw_H1_prog_V_ap_vld_preg),
        .O(ap_enable_reg_pp0_iter1_i_6_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter1_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_4_reg_1510),
        .Q(ap_enable_reg_pp0_iter1),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter2_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_enable_reg_pp0_iter1),
        .Q(ap_enable_reg_pp0_iter2),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter3_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_enable_reg_pp0_iter2),
        .Q(ap_enable_reg_pp0_iter3),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter4_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_enable_reg_pp0_iter3),
        .Q(ap_enable_reg_pp0_iter4),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter5_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_enable_reg_pp0_iter4),
        .Q(ap_enable_reg_pp0_iter5),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter6_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_enable_reg_pp0_iter5),
        .Q(ap_enable_reg_pp0_iter6),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    ap_enable_reg_pp0_iter7_reg
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_enable_reg_pp0_iter6),
        .Q(ap_enable_reg_pp0_iter7),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'hD8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428[0]_i_1 
       (.I0(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .I1(inputs_valid_preg),
        .I2(ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[0]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[10]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[10]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[11]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[11]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[12]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[12]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[13]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[13]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[14]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[14]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[15]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[15]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[16]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[16]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[17]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[17]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[18]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[18]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[19]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[19]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[1]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[1]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[20]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[20]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[21]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[21]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[22]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[22]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[23]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[23]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[24]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[24]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[25]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[25]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[26]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[26]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[27]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[27]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[28]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[28]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[29]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[29]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[2]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[2]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[30]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[30]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[31]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[31]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[3]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[3]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[4]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[4]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[5]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[5]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[6]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[6]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[7]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[7]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[8]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[8]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[9]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_coef_V_preg[9]),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[10] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[10]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[11] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[11]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[12] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[12]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[13] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[13]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[14] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[14]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[15] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[15]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[16] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[16]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[17] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[17]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[18] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[18]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[19] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[19]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[1] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[20] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[20]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[21] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[21]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[22] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[22]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[23] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[23]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[24] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[24]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[25] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[25]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[26] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[26]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[27] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[27]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[28] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[28]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[29] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[29]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[2] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[30] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[30]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[31] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[31]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[3] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[3]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[4] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[4]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[5] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[5]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[6] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[6]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[7] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[7]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[8] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[8]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496_reg[9] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[9]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[9]),
        .R(ap_rst));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    \ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1 
       (.I0(ap_enable_reg_pp0_iter1_i_2_n_0),
        .I1(ap_enable_reg_pp0_iter1_i_3_n_0),
        .I2(ap_enable_reg_pp0_iter1_i_4_n_0),
        .I3(ap_enable_reg_pp0_iter1_i_5_n_0),
        .I4(ap_enable_reg_pp0_iter1_i_6_n_0),
        .I5(ap_enable_reg_pp0_iter1),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_2 
       (.I0(inputs_valid_preg),
        .I1(inputs_enable_FSK_preg),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_2_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_force_AM_preg),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_reset_slip_preg),
        .O(\ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_inputs_current_reset_4_reg_459),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_rate_V_preg[0]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_rate_V_preg[1]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_rate_V_preg[2]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440_reg[1] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_3_reg_440_reg[2] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[0]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[10]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[10]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[11]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[11]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[12]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[12]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[13]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[13]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[14]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[14]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[15]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[15]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[16]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[16]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[17]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[17]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[18]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[18]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[19]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[19]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[1]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[1]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[20]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[20]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[21]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[21]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[22]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[22]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[23]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[23]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[24]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[24]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[25]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[25]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[26]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[26]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[27]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[27]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[28]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[28]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[29]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[29]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[2]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[2]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[30]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[30]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[31]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[31]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[32]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[32]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[33]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[33]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[34]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[34]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[35]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[35]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[36]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[36]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[37]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[37]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[38]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[38]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[39]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[39]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[3]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[3]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[40]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[40]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[41]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[41]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[42]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[42]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[43]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[43]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[44]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[44]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[45]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[45]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[46]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[46]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[47]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[47]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[4]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[4]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[5]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[5]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[6]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[6]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[7]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[7]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[8]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[8]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[9]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_on_V_preg[9]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[10] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[10]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[11] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[11]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[12] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[12]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[13] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[13]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[14] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[14]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[15] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[15]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[16] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[16]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[17] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[17]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[18] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[18]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[19] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[19]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[1] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[20] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[20]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[21] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[21]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[22] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[22]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[23] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[23]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[24] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[24]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[25] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[25]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[26] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[26]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[27] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[27]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[28] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[28]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[29] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[29]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[2] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[30] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[30]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[31] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[31]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[32] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[32]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[33] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[33]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[34] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[34]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[35] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[35]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[36] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[36]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[37] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[37]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[38] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[38]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[39] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[39]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[3] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[3]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[40] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[40]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[41] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[41]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[42] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[42]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[43] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[43]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[44] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[44]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[45] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[45]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[46] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[46]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[47] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[47]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[4] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[4]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[5] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[5]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[6] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[6]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[7] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[7]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[8] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[8]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_7_reg_487_reg[9] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[9]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[0]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[10]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[10]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[11]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[11]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[12]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[12]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[13]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[13]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[14]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[14]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[15]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[15]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[16]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[16]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[17]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[17]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[18]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[18]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[19]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[19]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[1]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[1]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[20]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[20]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[21]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[21]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[22]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[22]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[23]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[23]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[24]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[24]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[25]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[25]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[26]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[26]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[27]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[27]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[28]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[28]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[29]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[29]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[2]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[2]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[30]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[30]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[31]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[31]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[32]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[32]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[33]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[33]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[34]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[34]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[35]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[35]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[36]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[36]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[37]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[37]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[38]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[38]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[39]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[39]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[3]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[3]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[40]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[40]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[41]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[41]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[42]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[42]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[43]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[43]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[44]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[44]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[45]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[45]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[46]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[46]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[47]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[47]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[4]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[4]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[5]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[5]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[6]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[6]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[7]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[7]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[8]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[8]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[9]_i_1 
       (.I0(inputs_valid_preg),
        .I1(inputs_ftw_H1_V_preg[9]),
        .O(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[0] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[10] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[10]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[11] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[11]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[12] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[12]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[13] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[13]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[14] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[14]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[15] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[15]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[16] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[16]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[17] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[17]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[18] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[18]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[19] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[19]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[1] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[20] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[20]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[21] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[21]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[22] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[22]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[23] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[23]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[24] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[24]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[25] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[25]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[26] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[26]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[27] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[27]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[28] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[28]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[29] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[29]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[2] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[30] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[30]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[31] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[31]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[32] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[32]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[33] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[33]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[34] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[34]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[35] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[35]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[36] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[36]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[37] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[37]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[38] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[38]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[39] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[39]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[3] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[3]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[40] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[40]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[41] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[41]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[42] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[42]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[43] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[43]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[44] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[44]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[45] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[45]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[46] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[46]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[47] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[47]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[4] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[4]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[5] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[5]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[6] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[6]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[7] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[7]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[8] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[8]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter2_p_Val2_8_reg_478_reg[9] 
       (.C(ap_clk),
        .CE(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .D(\ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[9]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[0]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[0]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[10]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[10]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[11]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[11]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[12]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[12]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[13]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[13]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[14]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[14]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[15]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[15]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[16]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[16]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[17]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[17]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[18]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[18]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[19]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[19]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[1]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[1]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[20]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[20]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[21]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[21]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[22]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[22]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[23]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[23]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[24]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[24]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[25]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[25]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[26]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[26]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[27]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[27]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[28]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[28]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[29]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[29]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[2]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[2]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[30]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[30]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[31]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[31]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[3]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[3]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[4]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[4]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[5]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[5]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[6]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[6]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[7]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[7]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[8]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[8]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_coef_3_reg_496[9]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_coef_s[9]),
        .O(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[0]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[0]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[10]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[10]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[11]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[11]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[12]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[12]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[13]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[13]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[14]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[14]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[15]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[15]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[16]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[16]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[17]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[17]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[18]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[18]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[19]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[19]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[1]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[1]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[20]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[20]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[21]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[21]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[22]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[22]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[23]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[23]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[24]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[24]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[25]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[25]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[26]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[26]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[27]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[27]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[28]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[28]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[29]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[29]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[2]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[2]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[30]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[30]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[31]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[31]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[32]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[32]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[33]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[33]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[34]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[34]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[35]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[35]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[36]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[36]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[37]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[37]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[38]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[38]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[39]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[39]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[3]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[3]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[40]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[40]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[41]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[41]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[42]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[42]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[43]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[43]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[44]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[44]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[45]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[45]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[46]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[46]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[47]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[47]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[4]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[4]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[5]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[5]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[6]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[6]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[7]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[7]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[8]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[8]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_7_reg_487[9]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_2[9]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[32] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[33] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[34] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[35] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[36] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[37] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[38] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[39] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[40] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[41] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[42] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[43] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[44] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[45] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[46] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[47] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_7_reg_487_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[0]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[0]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[10]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[10]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[11]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[11]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[12]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[12]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[13]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[13]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[14]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[14]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[15]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[15]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[16]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[16]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[17]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[17]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[18]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[18]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[19]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[19]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[1]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[1]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[20]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[20]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[21]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[21]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[22]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[22]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[23]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[23]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[24]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[24]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[25]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[25]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[26]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[26]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[27]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[27]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[28]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[28]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[29]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[29]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[2]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[2]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[30]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[30]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[31]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[31]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[32]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[32]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[33]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[33]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[34]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[34]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[35]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[35]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[36]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[36]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[37]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[37]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[38]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[38]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[39]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[39]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[3]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[3]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[40]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[40]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[41]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[41]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[42]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[42]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[43]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[43]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[44]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[44]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[45]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[45]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[46]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[46]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[47]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[47]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[4]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[4]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[5]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[5]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[6]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[6]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[7]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[7]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[8]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[8]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_8_reg_478[9]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_ftw_H_1[9]),
        .O(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[10] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[11] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[12] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[13] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[14] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[15] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[16] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[17] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[18] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[19] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[20] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[21] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[22] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[23] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[24] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[25] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[26] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[27] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[28] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[29] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[30] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[31] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[32] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[33] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[34] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[35] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[36] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[37] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[38] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[39] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[3] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[40] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[41] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[42] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[43] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[44] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[45] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[46] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[47] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[4] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[5] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[6] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[7] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[8] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \ap_phi_reg_pp0_iter3_p_Val2_8_reg_478_reg[9] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]_i_1_n_0 ),
        .Q(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h10000000)) 
    \clk_off[0]_i_1 
       (.I0(tmp_12_reg_1606_pp0_iter4_reg),
        .I1(tmp_3_reg_1602_pp0_iter4_reg),
        .I2(tmp_15_fu_1198_p2),
        .I3(p_Val2_4_reg_1510),
        .I4(ap_enable_reg_pp0_iter5),
        .O(clk_off));
  LUT1 #(
    .INIT(2'h1)) 
    \clk_off[0]_i_3 
       (.I0(clk_off_reg[0]),
        .O(\clk_off[0]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[0] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[0]_i_2_n_7 ),
        .Q(clk_off_reg[0]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[0]_i_2 
       (.CI(\<const0> ),
        .CO({\clk_off_reg[0]_i_2_n_0 ,\clk_off_reg[0]_i_2_n_1 ,\clk_off_reg[0]_i_2_n_2 ,\clk_off_reg[0]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }),
        .O({\clk_off_reg[0]_i_2_n_4 ,\clk_off_reg[0]_i_2_n_5 ,\clk_off_reg[0]_i_2_n_6 ,\clk_off_reg[0]_i_2_n_7 }),
        .S({clk_off_reg[3:1],\clk_off[0]_i_3_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[10] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[8]_i_1_n_5 ),
        .Q(clk_off_reg[10]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[11] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[8]_i_1_n_4 ),
        .Q(clk_off_reg[11]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[12] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[12]_i_1_n_7 ),
        .Q(clk_off_reg[12]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[12]_i_1 
       (.CI(\clk_off_reg[8]_i_1_n_0 ),
        .CO({\clk_off_reg[12]_i_1_n_0 ,\clk_off_reg[12]_i_1_n_1 ,\clk_off_reg[12]_i_1_n_2 ,\clk_off_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[12]_i_1_n_4 ,\clk_off_reg[12]_i_1_n_5 ,\clk_off_reg[12]_i_1_n_6 ,\clk_off_reg[12]_i_1_n_7 }),
        .S(clk_off_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[13] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[12]_i_1_n_6 ),
        .Q(clk_off_reg[13]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[14] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[12]_i_1_n_5 ),
        .Q(clk_off_reg[14]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[15] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[12]_i_1_n_4 ),
        .Q(clk_off_reg[15]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[16] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[16]_i_1_n_7 ),
        .Q(clk_off_reg[16]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[16]_i_1 
       (.CI(\clk_off_reg[12]_i_1_n_0 ),
        .CO({\clk_off_reg[16]_i_1_n_0 ,\clk_off_reg[16]_i_1_n_1 ,\clk_off_reg[16]_i_1_n_2 ,\clk_off_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[16]_i_1_n_4 ,\clk_off_reg[16]_i_1_n_5 ,\clk_off_reg[16]_i_1_n_6 ,\clk_off_reg[16]_i_1_n_7 }),
        .S(clk_off_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[17] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[16]_i_1_n_6 ),
        .Q(clk_off_reg[17]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[18] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[16]_i_1_n_5 ),
        .Q(clk_off_reg[18]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[19] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[16]_i_1_n_4 ),
        .Q(clk_off_reg[19]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[1] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[0]_i_2_n_6 ),
        .Q(clk_off_reg[1]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[20] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[20]_i_1_n_7 ),
        .Q(clk_off_reg[20]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[20]_i_1 
       (.CI(\clk_off_reg[16]_i_1_n_0 ),
        .CO({\clk_off_reg[20]_i_1_n_0 ,\clk_off_reg[20]_i_1_n_1 ,\clk_off_reg[20]_i_1_n_2 ,\clk_off_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[20]_i_1_n_4 ,\clk_off_reg[20]_i_1_n_5 ,\clk_off_reg[20]_i_1_n_6 ,\clk_off_reg[20]_i_1_n_7 }),
        .S(clk_off_reg[23:20]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[21] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[20]_i_1_n_6 ),
        .Q(clk_off_reg[21]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[22] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[20]_i_1_n_5 ),
        .Q(clk_off_reg[22]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[23] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[20]_i_1_n_4 ),
        .Q(clk_off_reg[23]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[24] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[24]_i_1_n_7 ),
        .Q(clk_off_reg[24]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[24]_i_1 
       (.CI(\clk_off_reg[20]_i_1_n_0 ),
        .CO({\clk_off_reg[24]_i_1_n_0 ,\clk_off_reg[24]_i_1_n_1 ,\clk_off_reg[24]_i_1_n_2 ,\clk_off_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[24]_i_1_n_4 ,\clk_off_reg[24]_i_1_n_5 ,\clk_off_reg[24]_i_1_n_6 ,\clk_off_reg[24]_i_1_n_7 }),
        .S(clk_off_reg[27:24]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[25] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[24]_i_1_n_6 ),
        .Q(clk_off_reg[25]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[26] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[24]_i_1_n_5 ),
        .Q(clk_off_reg[26]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[27] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[24]_i_1_n_4 ),
        .Q(clk_off_reg[27]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[28] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[28]_i_1_n_7 ),
        .Q(clk_off_reg[28]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[28]_i_1 
       (.CI(\clk_off_reg[24]_i_1_n_0 ),
        .CO({\clk_off_reg[28]_i_1_n_1 ,\clk_off_reg[28]_i_1_n_2 ,\clk_off_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[28]_i_1_n_4 ,\clk_off_reg[28]_i_1_n_5 ,\clk_off_reg[28]_i_1_n_6 ,\clk_off_reg[28]_i_1_n_7 }),
        .S(clk_off_reg[31:28]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[29] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[28]_i_1_n_6 ),
        .Q(clk_off_reg[29]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[2] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[0]_i_2_n_5 ),
        .Q(clk_off_reg[2]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[30] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[28]_i_1_n_5 ),
        .Q(clk_off_reg[30]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[31] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[28]_i_1_n_4 ),
        .Q(clk_off_reg[31]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[3] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[0]_i_2_n_4 ),
        .Q(clk_off_reg[3]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[4] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[4]_i_1_n_7 ),
        .Q(clk_off_reg[4]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[4]_i_1 
       (.CI(\clk_off_reg[0]_i_2_n_0 ),
        .CO({\clk_off_reg[4]_i_1_n_0 ,\clk_off_reg[4]_i_1_n_1 ,\clk_off_reg[4]_i_1_n_2 ,\clk_off_reg[4]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[4]_i_1_n_4 ,\clk_off_reg[4]_i_1_n_5 ,\clk_off_reg[4]_i_1_n_6 ,\clk_off_reg[4]_i_1_n_7 }),
        .S(clk_off_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[5] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[4]_i_1_n_6 ),
        .Q(clk_off_reg[5]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[6] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[4]_i_1_n_5 ),
        .Q(clk_off_reg[6]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[7] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[4]_i_1_n_4 ),
        .Q(clk_off_reg[7]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[8] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[8]_i_1_n_7 ),
        .Q(clk_off_reg[8]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_off_reg[8]_i_1 
       (.CI(\clk_off_reg[4]_i_1_n_0 ),
        .CO({\clk_off_reg[8]_i_1_n_0 ,\clk_off_reg[8]_i_1_n_1 ,\clk_off_reg[8]_i_1_n_2 ,\clk_off_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_off_reg[8]_i_1_n_4 ,\clk_off_reg[8]_i_1_n_5 ,\clk_off_reg[8]_i_1_n_6 ,\clk_off_reg[8]_i_1_n_7 }),
        .S(clk_off_reg[11:8]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_off_reg[9] 
       (.C(ap_clk),
        .CE(clk_off),
        .D(\clk_off_reg[8]_i_1_n_6 ),
        .Q(clk_off_reg[9]),
        .R(clk_on));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \clk_on[0]_i_1 
       (.I0(ap_rst),
        .I1(ap_enable_reg_pp0_iter5),
        .I2(p_Val2_4_reg_1510),
        .I3(tmp_3_reg_1602_pp0_iter4_reg),
        .O(clk_on));
  LUT3 #(
    .INIT(8'h80)) 
    \clk_on[0]_i_2 
       (.I0(tmp_12_reg_1606_pp0_iter4_reg),
        .I1(p_Val2_4_reg_1510),
        .I2(ap_enable_reg_pp0_iter5),
        .O(\clk_on[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \clk_on[0]_i_4 
       (.I0(clk_on_reg[0]),
        .O(\clk_on[0]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[0] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[0]_i_3_n_7 ),
        .Q(clk_on_reg[0]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[0]_i_3 
       (.CI(\<const0> ),
        .CO({\clk_on_reg[0]_i_3_n_0 ,\clk_on_reg[0]_i_3_n_1 ,\clk_on_reg[0]_i_3_n_2 ,\clk_on_reg[0]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const1> }),
        .O({\clk_on_reg[0]_i_3_n_4 ,\clk_on_reg[0]_i_3_n_5 ,\clk_on_reg[0]_i_3_n_6 ,\clk_on_reg[0]_i_3_n_7 }),
        .S({clk_on_reg[3:1],\clk_on[0]_i_4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[10] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[8]_i_1_n_5 ),
        .Q(clk_on_reg[10]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[11] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[8]_i_1_n_4 ),
        .Q(clk_on_reg[11]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[12] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[12]_i_1_n_7 ),
        .Q(clk_on_reg[12]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[12]_i_1 
       (.CI(\clk_on_reg[8]_i_1_n_0 ),
        .CO({\clk_on_reg[12]_i_1_n_0 ,\clk_on_reg[12]_i_1_n_1 ,\clk_on_reg[12]_i_1_n_2 ,\clk_on_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[12]_i_1_n_4 ,\clk_on_reg[12]_i_1_n_5 ,\clk_on_reg[12]_i_1_n_6 ,\clk_on_reg[12]_i_1_n_7 }),
        .S(clk_on_reg[15:12]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[13] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[12]_i_1_n_6 ),
        .Q(clk_on_reg[13]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[14] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[12]_i_1_n_5 ),
        .Q(clk_on_reg[14]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[15] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[12]_i_1_n_4 ),
        .Q(clk_on_reg[15]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[16] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[16]_i_1_n_7 ),
        .Q(clk_on_reg[16]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[16]_i_1 
       (.CI(\clk_on_reg[12]_i_1_n_0 ),
        .CO({\clk_on_reg[16]_i_1_n_0 ,\clk_on_reg[16]_i_1_n_1 ,\clk_on_reg[16]_i_1_n_2 ,\clk_on_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[16]_i_1_n_4 ,\clk_on_reg[16]_i_1_n_5 ,\clk_on_reg[16]_i_1_n_6 ,\clk_on_reg[16]_i_1_n_7 }),
        .S(clk_on_reg[19:16]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[17] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[16]_i_1_n_6 ),
        .Q(clk_on_reg[17]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[18] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[16]_i_1_n_5 ),
        .Q(clk_on_reg[18]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[19] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[16]_i_1_n_4 ),
        .Q(clk_on_reg[19]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[1] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[0]_i_3_n_6 ),
        .Q(clk_on_reg[1]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[20] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[20]_i_1_n_7 ),
        .Q(clk_on_reg[20]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[20]_i_1 
       (.CI(\clk_on_reg[16]_i_1_n_0 ),
        .CO({\clk_on_reg[20]_i_1_n_0 ,\clk_on_reg[20]_i_1_n_1 ,\clk_on_reg[20]_i_1_n_2 ,\clk_on_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[20]_i_1_n_4 ,\clk_on_reg[20]_i_1_n_5 ,\clk_on_reg[20]_i_1_n_6 ,\clk_on_reg[20]_i_1_n_7 }),
        .S(clk_on_reg[23:20]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[21] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[20]_i_1_n_6 ),
        .Q(clk_on_reg[21]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[22] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[20]_i_1_n_5 ),
        .Q(clk_on_reg[22]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[23] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[20]_i_1_n_4 ),
        .Q(clk_on_reg[23]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[24] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[24]_i_1_n_7 ),
        .Q(clk_on_reg[24]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[24]_i_1 
       (.CI(\clk_on_reg[20]_i_1_n_0 ),
        .CO({\clk_on_reg[24]_i_1_n_0 ,\clk_on_reg[24]_i_1_n_1 ,\clk_on_reg[24]_i_1_n_2 ,\clk_on_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[24]_i_1_n_4 ,\clk_on_reg[24]_i_1_n_5 ,\clk_on_reg[24]_i_1_n_6 ,\clk_on_reg[24]_i_1_n_7 }),
        .S(clk_on_reg[27:24]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[25] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[24]_i_1_n_6 ),
        .Q(clk_on_reg[25]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[26] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[24]_i_1_n_5 ),
        .Q(clk_on_reg[26]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[27] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[24]_i_1_n_4 ),
        .Q(clk_on_reg[27]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[28] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[28]_i_1_n_7 ),
        .Q(clk_on_reg[28]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[28]_i_1 
       (.CI(\clk_on_reg[24]_i_1_n_0 ),
        .CO({\clk_on_reg[28]_i_1_n_1 ,\clk_on_reg[28]_i_1_n_2 ,\clk_on_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[28]_i_1_n_4 ,\clk_on_reg[28]_i_1_n_5 ,\clk_on_reg[28]_i_1_n_6 ,\clk_on_reg[28]_i_1_n_7 }),
        .S(clk_on_reg[31:28]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[29] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[28]_i_1_n_6 ),
        .Q(clk_on_reg[29]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[2] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[0]_i_3_n_5 ),
        .Q(clk_on_reg[2]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[30] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[28]_i_1_n_5 ),
        .Q(clk_on_reg[30]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[31] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[28]_i_1_n_4 ),
        .Q(clk_on_reg[31]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[3] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[0]_i_3_n_4 ),
        .Q(clk_on_reg[3]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[4] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[4]_i_1_n_7 ),
        .Q(clk_on_reg[4]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[4]_i_1 
       (.CI(\clk_on_reg[0]_i_3_n_0 ),
        .CO({\clk_on_reg[4]_i_1_n_0 ,\clk_on_reg[4]_i_1_n_1 ,\clk_on_reg[4]_i_1_n_2 ,\clk_on_reg[4]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[4]_i_1_n_4 ,\clk_on_reg[4]_i_1_n_5 ,\clk_on_reg[4]_i_1_n_6 ,\clk_on_reg[4]_i_1_n_7 }),
        .S(clk_on_reg[7:4]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[5] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[4]_i_1_n_6 ),
        .Q(clk_on_reg[5]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[6] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[4]_i_1_n_5 ),
        .Q(clk_on_reg[6]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[7] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[4]_i_1_n_4 ),
        .Q(clk_on_reg[7]),
        .R(clk_on));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[8] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[8]_i_1_n_7 ),
        .Q(clk_on_reg[8]),
        .R(clk_on));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \clk_on_reg[8]_i_1 
       (.CI(\clk_on_reg[4]_i_1_n_0 ),
        .CO({\clk_on_reg[8]_i_1_n_0 ,\clk_on_reg[8]_i_1_n_1 ,\clk_on_reg[8]_i_1_n_2 ,\clk_on_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O({\clk_on_reg[8]_i_1_n_4 ,\clk_on_reg[8]_i_1_n_5 ,\clk_on_reg[8]_i_1_n_6 ,\clk_on_reg[8]_i_1_n_7 }),
        .S(clk_on_reg[11:8]));
  FDRE #(
    .INIT(1'b0)) 
    \clk_on_reg[9] 
       (.C(ap_clk),
        .CE(\clk_on[0]_i_2_n_0 ),
        .D(\clk_on_reg[8]_i_1_n_6 ),
        .Q(clk_on_reg[9]),
        .R(clk_on));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_H_V_ap_vld_preg_i_1
       (.I0(inputs_H_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_H_V_ap_vld_preg),
        .O(inputs_H_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_H_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_H_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_H_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[0]),
        .Q(inputs_H_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[10]),
        .Q(inputs_H_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[11]),
        .Q(inputs_H_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[12]),
        .Q(inputs_H_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[13]),
        .Q(inputs_H_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[14]),
        .Q(inputs_H_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[15]),
        .Q(inputs_H_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[1]),
        .Q(inputs_H_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[2]),
        .Q(inputs_H_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[3]),
        .Q(inputs_H_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[4]),
        .Q(inputs_H_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[5]),
        .Q(inputs_H_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[6]),
        .Q(inputs_H_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[7]),
        .Q(inputs_H_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[8]),
        .Q(inputs_H_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_H_V_ap_vld),
        .D(inputs_H_V[9]),
        .Q(inputs_H_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[0]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[10]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[11]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[12]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[13]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[14]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[15]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[1]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[2]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[3]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[4]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[5]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[6]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[7]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[8]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter2_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490[9]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter2_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[0]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[10]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[11]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[12]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[13]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[14]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[15]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[1]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[2]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[3]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[4]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[5]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[6]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[7]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[8]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_pp0_iter3_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_read_reg_1490_pp0_iter2_reg[9]),
        .Q(inputs_H_V_read_reg_1490_pp0_iter3_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[0]),
        .Q(inputs_H_V_read_reg_1490[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[10]),
        .Q(inputs_H_V_read_reg_1490[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[11]),
        .Q(inputs_H_V_read_reg_1490[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[12]),
        .Q(inputs_H_V_read_reg_1490[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[13]),
        .Q(inputs_H_V_read_reg_1490[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[14]),
        .Q(inputs_H_V_read_reg_1490[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[15]),
        .Q(inputs_H_V_read_reg_1490[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[1]),
        .Q(inputs_H_V_read_reg_1490[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[2]),
        .Q(inputs_H_V_read_reg_1490[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[3]),
        .Q(inputs_H_V_read_reg_1490[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[4]),
        .Q(inputs_H_V_read_reg_1490[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[5]),
        .Q(inputs_H_V_read_reg_1490[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[6]),
        .Q(inputs_H_V_read_reg_1490[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[7]),
        .Q(inputs_H_V_read_reg_1490[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[8]),
        .Q(inputs_H_V_read_reg_1490[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_H_V_read_reg_1490_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_H_V_preg[9]),
        .Q(inputs_H_V_read_reg_1490[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_coef_V_ap_vld_preg_i_1
       (.I0(inputs_coef_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_coef_V_ap_vld_preg),
        .O(inputs_coef_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_coef_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_coef_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_coef_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[0]),
        .Q(inputs_coef_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[10]),
        .Q(inputs_coef_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[11]),
        .Q(inputs_coef_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[12]),
        .Q(inputs_coef_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[13]),
        .Q(inputs_coef_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[14]),
        .Q(inputs_coef_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[15]),
        .Q(inputs_coef_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[16]),
        .Q(inputs_coef_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[17]),
        .Q(inputs_coef_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[18]),
        .Q(inputs_coef_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[19]),
        .Q(inputs_coef_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[1]),
        .Q(inputs_coef_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[20]),
        .Q(inputs_coef_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[21]),
        .Q(inputs_coef_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[22]),
        .Q(inputs_coef_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[23]),
        .Q(inputs_coef_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[24]),
        .Q(inputs_coef_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[25]),
        .Q(inputs_coef_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[26]),
        .Q(inputs_coef_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[27]),
        .Q(inputs_coef_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[28]),
        .Q(inputs_coef_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[29]),
        .Q(inputs_coef_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[2]),
        .Q(inputs_coef_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[30]),
        .Q(inputs_coef_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[31]),
        .Q(inputs_coef_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[3]),
        .Q(inputs_coef_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[4]),
        .Q(inputs_coef_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[5]),
        .Q(inputs_coef_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[6]),
        .Q(inputs_coef_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[7]),
        .Q(inputs_coef_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[8]),
        .Q(inputs_coef_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_coef_V_ap_vld),
        .D(inputs_coef_V[9]),
        .Q(inputs_coef_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[0]),
        .Q(inputs_coef_V_read_reg_1457[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[10]),
        .Q(inputs_coef_V_read_reg_1457[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[11]),
        .Q(inputs_coef_V_read_reg_1457[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[12]),
        .Q(inputs_coef_V_read_reg_1457[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[13]),
        .Q(inputs_coef_V_read_reg_1457[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[14]),
        .Q(inputs_coef_V_read_reg_1457[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[15]),
        .Q(inputs_coef_V_read_reg_1457[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[16]),
        .Q(inputs_coef_V_read_reg_1457[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[17]),
        .Q(inputs_coef_V_read_reg_1457[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[18]),
        .Q(inputs_coef_V_read_reg_1457[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[19]),
        .Q(inputs_coef_V_read_reg_1457[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[1]),
        .Q(inputs_coef_V_read_reg_1457[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[20]),
        .Q(inputs_coef_V_read_reg_1457[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[21]),
        .Q(inputs_coef_V_read_reg_1457[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[22]),
        .Q(inputs_coef_V_read_reg_1457[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[23]),
        .Q(inputs_coef_V_read_reg_1457[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[24]),
        .Q(inputs_coef_V_read_reg_1457[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[25]),
        .Q(inputs_coef_V_read_reg_1457[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[26]),
        .Q(inputs_coef_V_read_reg_1457[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[27]),
        .Q(inputs_coef_V_read_reg_1457[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[28]),
        .Q(inputs_coef_V_read_reg_1457[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[29]),
        .Q(inputs_coef_V_read_reg_1457[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[2]),
        .Q(inputs_coef_V_read_reg_1457[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[30]),
        .Q(inputs_coef_V_read_reg_1457[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[31]),
        .Q(inputs_coef_V_read_reg_1457[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[3]),
        .Q(inputs_coef_V_read_reg_1457[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[4]),
        .Q(inputs_coef_V_read_reg_1457[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[5]),
        .Q(inputs_coef_V_read_reg_1457[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[6]),
        .Q(inputs_coef_V_read_reg_1457[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[7]),
        .Q(inputs_coef_V_read_reg_1457[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[8]),
        .Q(inputs_coef_V_read_reg_1457[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_coef_V_read_reg_1457_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_coef_V_preg[9]),
        .Q(inputs_coef_V_read_reg_1457[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[0]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[10]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[11]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[12]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[13]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[14]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[15]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[16]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[17]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[18]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[19]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[1]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[20]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[21]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[22]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[23]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[24]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[25]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[26]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[27]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[28]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[29]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[2]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[30]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[31]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[3]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[4]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[5]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[6]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[7]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[8]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter4_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554[9]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter4_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[0]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[10]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[11]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[12]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[13]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[14]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[15]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[16]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[17]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[18]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[19]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[1]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[20]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[21]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[22]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[23]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[24]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[25]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[26]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[27]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[28]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[29]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[2]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[30]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[31]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[3]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[4]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[5]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[6]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[7]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[8]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter5_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter4_reg[9]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter5_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[0]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[10]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[11]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[12]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[13]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[14]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[15]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[16]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[17]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[18]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[19]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[1]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[20]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[21]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[22]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[23]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[24]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[25]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[26]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[27]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[28]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[29]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[2]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[30]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[31]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[3]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[4]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[5]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[6]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[7]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[8]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_coef_6_reg_1554_pp0_iter5_reg[9]),
        .Q(inputs_current_coef_6_reg_1554_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]),
        .Q(inputs_current_coef_6_reg_1554[0]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]),
        .Q(inputs_current_coef_6_reg_1554[10]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]),
        .Q(inputs_current_coef_6_reg_1554[11]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]),
        .Q(inputs_current_coef_6_reg_1554[12]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]),
        .Q(inputs_current_coef_6_reg_1554[13]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]),
        .Q(inputs_current_coef_6_reg_1554[14]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]),
        .Q(inputs_current_coef_6_reg_1554[15]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]),
        .Q(inputs_current_coef_6_reg_1554[16]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]),
        .Q(inputs_current_coef_6_reg_1554[17]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]),
        .Q(inputs_current_coef_6_reg_1554[18]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]),
        .Q(inputs_current_coef_6_reg_1554[19]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]),
        .Q(inputs_current_coef_6_reg_1554[1]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]),
        .Q(inputs_current_coef_6_reg_1554[20]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]),
        .Q(inputs_current_coef_6_reg_1554[21]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]),
        .Q(inputs_current_coef_6_reg_1554[22]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]),
        .Q(inputs_current_coef_6_reg_1554[23]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]),
        .Q(inputs_current_coef_6_reg_1554[24]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]),
        .Q(inputs_current_coef_6_reg_1554[25]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]),
        .Q(inputs_current_coef_6_reg_1554[26]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]),
        .Q(inputs_current_coef_6_reg_1554[27]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]),
        .Q(inputs_current_coef_6_reg_1554[28]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]),
        .Q(inputs_current_coef_6_reg_1554[29]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]),
        .Q(inputs_current_coef_6_reg_1554[2]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]),
        .Q(inputs_current_coef_6_reg_1554[30]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]),
        .Q(inputs_current_coef_6_reg_1554[31]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]),
        .Q(inputs_current_coef_6_reg_1554[3]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]),
        .Q(inputs_current_coef_6_reg_1554[4]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]),
        .Q(inputs_current_coef_6_reg_1554[5]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]),
        .Q(inputs_current_coef_6_reg_1554[6]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]),
        .Q(inputs_current_coef_6_reg_1554[7]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]),
        .Q(inputs_current_coef_6_reg_1554[8]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_6_reg_1554_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]),
        .Q(inputs_current_coef_6_reg_1554[9]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  LUT4 #(
    .INIT(16'hFF08)) 
    \inputs_current_coef_s[31]_i_1 
       (.I0(p_Val2_4_reg_1510),
        .I1(ap_enable_reg_pp0_iter2),
        .I2(p_0_in47_out),
        .I3(ap_rst),
        .O(\inputs_current_coef_s[31]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8F000000)) 
    \inputs_current_coef_s[31]_i_2 
       (.I0(inputs_valid_read_reg_1420),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_coef_2_reg_428),
        .I2(p_0_in47_out),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(p_Val2_4_reg_1510),
        .O(inputs_current_coef_s0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[0]),
        .Q(inputs_current_coef_s[0]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[10]),
        .Q(inputs_current_coef_s[10]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[11]),
        .Q(inputs_current_coef_s[11]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[12]),
        .Q(inputs_current_coef_s[12]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[13]),
        .Q(inputs_current_coef_s[13]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[14]),
        .Q(inputs_current_coef_s[14]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[15]),
        .Q(inputs_current_coef_s[15]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[16]),
        .Q(inputs_current_coef_s[16]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[17]),
        .Q(inputs_current_coef_s[17]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[18]),
        .Q(inputs_current_coef_s[18]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[19]),
        .Q(inputs_current_coef_s[19]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[1]),
        .Q(inputs_current_coef_s[1]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[20]),
        .Q(inputs_current_coef_s[20]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[21]),
        .Q(inputs_current_coef_s[21]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[22]),
        .Q(inputs_current_coef_s[22]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[23]),
        .Q(inputs_current_coef_s[23]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[24]),
        .Q(inputs_current_coef_s[24]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[25]),
        .Q(inputs_current_coef_s[25]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[26]),
        .Q(inputs_current_coef_s[26]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[27]),
        .Q(inputs_current_coef_s[27]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[28]),
        .Q(inputs_current_coef_s[28]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[29]),
        .Q(inputs_current_coef_s[29]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[2]),
        .Q(inputs_current_coef_s[2]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[30]),
        .Q(inputs_current_coef_s[30]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[31]),
        .Q(inputs_current_coef_s[31]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[3]),
        .Q(inputs_current_coef_s[3]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[4]),
        .Q(inputs_current_coef_s[4]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[5]),
        .Q(inputs_current_coef_s[5]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[6]),
        .Q(inputs_current_coef_s[6]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[7]),
        .Q(inputs_current_coef_s[7]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[8]),
        .Q(inputs_current_coef_s[8]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_coef_s_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_coef_s0),
        .D(inputs_coef_V_read_reg_1457[9]),
        .Q(inputs_current_coef_s[9]),
        .R(\inputs_current_coef_s[31]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[0]),
        .Q(inputs_current_dftw_s[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[10]),
        .Q(inputs_current_dftw_s[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[11]),
        .Q(inputs_current_dftw_s[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[12]),
        .Q(inputs_current_dftw_s[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[13]),
        .Q(inputs_current_dftw_s[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[14]),
        .Q(inputs_current_dftw_s[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[15]),
        .Q(inputs_current_dftw_s[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[16]),
        .Q(inputs_current_dftw_s[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[17]),
        .Q(inputs_current_dftw_s[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[18]),
        .Q(inputs_current_dftw_s[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[19]),
        .Q(inputs_current_dftw_s[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[1]),
        .Q(inputs_current_dftw_s[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[20]),
        .Q(inputs_current_dftw_s[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[21]),
        .Q(inputs_current_dftw_s[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[22]),
        .Q(inputs_current_dftw_s[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[23]),
        .Q(inputs_current_dftw_s[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[24]),
        .Q(inputs_current_dftw_s[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[25]),
        .Q(inputs_current_dftw_s[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[26]),
        .Q(inputs_current_dftw_s[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[27]),
        .Q(inputs_current_dftw_s[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[28]),
        .Q(inputs_current_dftw_s[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[29]),
        .Q(inputs_current_dftw_s[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[2]),
        .Q(inputs_current_dftw_s[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[30]),
        .Q(inputs_current_dftw_s[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[31]),
        .Q(inputs_current_dftw_s[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[3]),
        .Q(inputs_current_dftw_s[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[4]),
        .Q(inputs_current_dftw_s[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[5]),
        .Q(inputs_current_dftw_s[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[6]),
        .Q(inputs_current_dftw_s[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[7]),
        .Q(inputs_current_dftw_s[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[8]),
        .Q(inputs_current_dftw_s[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_dftw_s_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_dftw_H1_slip_V_preg[9]),
        .Q(inputs_current_dftw_s[9]),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'h80)) 
    \inputs_current_enabl_1[0]_i_1 
       (.I0(inputs_valid_read_reg_1420),
        .I1(ap_enable_reg_pp0_iter2),
        .I2(p_Val2_4_reg_1510),
        .O(inputs_current_enabl_10));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_enabl_1_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_enable_FSK_re_reg_1414),
        .Q(inputs_current_enabl_1),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_enabl_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_enable_slip_preg),
        .Q(inputs_current_enabl),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_current_force_2_reg_468[0]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_force),
        .O(\inputs_current_force_2_reg_468[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_force_2_reg_468_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\inputs_current_force_2_reg_468[0]_i_1_n_0 ),
        .Q(inputs_current_force_2_reg_468),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_force_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_force_AM_read_reg_1392),
        .Q(inputs_current_force),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[0]),
        .Q(inputs_current_ftw_H_1[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[10]),
        .Q(inputs_current_ftw_H_1[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[11]),
        .Q(inputs_current_ftw_H_1[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[12]),
        .Q(inputs_current_ftw_H_1[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[13]),
        .Q(inputs_current_ftw_H_1[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[14]),
        .Q(inputs_current_ftw_H_1[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[15]),
        .Q(inputs_current_ftw_H_1[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[16]),
        .Q(inputs_current_ftw_H_1[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[17]),
        .Q(inputs_current_ftw_H_1[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[18]),
        .Q(inputs_current_ftw_H_1[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[19]),
        .Q(inputs_current_ftw_H_1[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[1]),
        .Q(inputs_current_ftw_H_1[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[20]),
        .Q(inputs_current_ftw_H_1[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[21]),
        .Q(inputs_current_ftw_H_1[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[22]),
        .Q(inputs_current_ftw_H_1[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[23]),
        .Q(inputs_current_ftw_H_1[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[24]),
        .Q(inputs_current_ftw_H_1[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[25]),
        .Q(inputs_current_ftw_H_1[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[26]),
        .Q(inputs_current_ftw_H_1[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[27]),
        .Q(inputs_current_ftw_H_1[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[28]),
        .Q(inputs_current_ftw_H_1[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[29]),
        .Q(inputs_current_ftw_H_1[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[2]),
        .Q(inputs_current_ftw_H_1[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[30]),
        .Q(inputs_current_ftw_H_1[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[31]),
        .Q(inputs_current_ftw_H_1[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[32]),
        .Q(inputs_current_ftw_H_1[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[33]),
        .Q(inputs_current_ftw_H_1[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[34]),
        .Q(inputs_current_ftw_H_1[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[35]),
        .Q(inputs_current_ftw_H_1[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[36]),
        .Q(inputs_current_ftw_H_1[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[37]),
        .Q(inputs_current_ftw_H_1[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[38]),
        .Q(inputs_current_ftw_H_1[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[39]),
        .Q(inputs_current_ftw_H_1[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[3]),
        .Q(inputs_current_ftw_H_1[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[40]),
        .Q(inputs_current_ftw_H_1[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[41]),
        .Q(inputs_current_ftw_H_1[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[42]),
        .Q(inputs_current_ftw_H_1[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[43]),
        .Q(inputs_current_ftw_H_1[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[44]),
        .Q(inputs_current_ftw_H_1[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[45]),
        .Q(inputs_current_ftw_H_1[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[46]),
        .Q(inputs_current_ftw_H_1[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[47]),
        .Q(inputs_current_ftw_H_1[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[4]),
        .Q(inputs_current_ftw_H_1[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[5]),
        .Q(inputs_current_ftw_H_1[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[6]),
        .Q(inputs_current_ftw_H_1[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[7]),
        .Q(inputs_current_ftw_H_1[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[8]),
        .Q(inputs_current_ftw_H_1[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_1_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_V_read_reg_1484[9]),
        .Q(inputs_current_ftw_H_1[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[0]),
        .Q(inputs_current_ftw_H_2[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[10]),
        .Q(inputs_current_ftw_H_2[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[11]),
        .Q(inputs_current_ftw_H_2[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[12]),
        .Q(inputs_current_ftw_H_2[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[13]),
        .Q(inputs_current_ftw_H_2[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[14]),
        .Q(inputs_current_ftw_H_2[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[15]),
        .Q(inputs_current_ftw_H_2[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[16]),
        .Q(inputs_current_ftw_H_2[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[17]),
        .Q(inputs_current_ftw_H_2[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[18]),
        .Q(inputs_current_ftw_H_2[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[19]),
        .Q(inputs_current_ftw_H_2[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[1]),
        .Q(inputs_current_ftw_H_2[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[20]),
        .Q(inputs_current_ftw_H_2[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[21]),
        .Q(inputs_current_ftw_H_2[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[22]),
        .Q(inputs_current_ftw_H_2[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[23]),
        .Q(inputs_current_ftw_H_2[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[24]),
        .Q(inputs_current_ftw_H_2[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[25]),
        .Q(inputs_current_ftw_H_2[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[26]),
        .Q(inputs_current_ftw_H_2[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[27]),
        .Q(inputs_current_ftw_H_2[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[28]),
        .Q(inputs_current_ftw_H_2[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[29]),
        .Q(inputs_current_ftw_H_2[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[2]),
        .Q(inputs_current_ftw_H_2[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[30]),
        .Q(inputs_current_ftw_H_2[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[31]),
        .Q(inputs_current_ftw_H_2[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[32]),
        .Q(inputs_current_ftw_H_2[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[33]),
        .Q(inputs_current_ftw_H_2[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[34]),
        .Q(inputs_current_ftw_H_2[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[35]),
        .Q(inputs_current_ftw_H_2[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[36]),
        .Q(inputs_current_ftw_H_2[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[37]),
        .Q(inputs_current_ftw_H_2[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[38]),
        .Q(inputs_current_ftw_H_2[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[39]),
        .Q(inputs_current_ftw_H_2[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[3]),
        .Q(inputs_current_ftw_H_2[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[40]),
        .Q(inputs_current_ftw_H_2[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[41]),
        .Q(inputs_current_ftw_H_2[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[42]),
        .Q(inputs_current_ftw_H_2[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[43]),
        .Q(inputs_current_ftw_H_2[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[44]),
        .Q(inputs_current_ftw_H_2[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[45]),
        .Q(inputs_current_ftw_H_2[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[46]),
        .Q(inputs_current_ftw_H_2[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[47]),
        .Q(inputs_current_ftw_H_2[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[4]),
        .Q(inputs_current_ftw_H_2[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[5]),
        .Q(inputs_current_ftw_H_2[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[6]),
        .Q(inputs_current_ftw_H_2[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[7]),
        .Q(inputs_current_ftw_H_2[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[8]),
        .Q(inputs_current_ftw_H_2[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_2_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_on_V_r_reg_1463[9]),
        .Q(inputs_current_ftw_H_2[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[0]),
        .Q(\inputs_current_ftw_H_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[10]),
        .Q(\inputs_current_ftw_H_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[11]),
        .Q(\inputs_current_ftw_H_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[12]),
        .Q(\inputs_current_ftw_H_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[13]),
        .Q(\inputs_current_ftw_H_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[14]),
        .Q(\inputs_current_ftw_H_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[15]),
        .Q(\inputs_current_ftw_H_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[16]),
        .Q(\inputs_current_ftw_H_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[17]),
        .Q(\inputs_current_ftw_H_reg_n_0_[17] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[18]),
        .Q(\inputs_current_ftw_H_reg_n_0_[18] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[19]),
        .Q(\inputs_current_ftw_H_reg_n_0_[19] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[1]),
        .Q(\inputs_current_ftw_H_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[20]),
        .Q(\inputs_current_ftw_H_reg_n_0_[20] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[21]),
        .Q(\inputs_current_ftw_H_reg_n_0_[21] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[22]),
        .Q(\inputs_current_ftw_H_reg_n_0_[22] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[23]),
        .Q(\inputs_current_ftw_H_reg_n_0_[23] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[24]),
        .Q(\inputs_current_ftw_H_reg_n_0_[24] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[25]),
        .Q(\inputs_current_ftw_H_reg_n_0_[25] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[26]),
        .Q(\inputs_current_ftw_H_reg_n_0_[26] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[27]),
        .Q(\inputs_current_ftw_H_reg_n_0_[27] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[28]),
        .Q(\inputs_current_ftw_H_reg_n_0_[28] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[29]),
        .Q(\inputs_current_ftw_H_reg_n_0_[29] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[2]),
        .Q(\inputs_current_ftw_H_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[30]),
        .Q(\inputs_current_ftw_H_reg_n_0_[30] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[31]),
        .Q(\inputs_current_ftw_H_reg_n_0_[31] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[32]),
        .Q(\inputs_current_ftw_H_reg_n_0_[32] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[33]),
        .Q(\inputs_current_ftw_H_reg_n_0_[33] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[34]),
        .Q(\inputs_current_ftw_H_reg_n_0_[34] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[35]),
        .Q(\inputs_current_ftw_H_reg_n_0_[35] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[36]),
        .Q(\inputs_current_ftw_H_reg_n_0_[36] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[37]),
        .Q(\inputs_current_ftw_H_reg_n_0_[37] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[38]),
        .Q(\inputs_current_ftw_H_reg_n_0_[38] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[39]),
        .Q(\inputs_current_ftw_H_reg_n_0_[39] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[3]),
        .Q(\inputs_current_ftw_H_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[40]),
        .Q(\inputs_current_ftw_H_reg_n_0_[40] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[41]),
        .Q(\inputs_current_ftw_H_reg_n_0_[41] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[42]),
        .Q(\inputs_current_ftw_H_reg_n_0_[42] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[43]),
        .Q(\inputs_current_ftw_H_reg_n_0_[43] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[44]),
        .Q(\inputs_current_ftw_H_reg_n_0_[44] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[45]),
        .Q(\inputs_current_ftw_H_reg_n_0_[45] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[46]),
        .Q(\inputs_current_ftw_H_reg_n_0_[46] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[47]),
        .Q(\inputs_current_ftw_H_reg_n_0_[47] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[4]),
        .Q(\inputs_current_ftw_H_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[5]),
        .Q(\inputs_current_ftw_H_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[6]),
        .Q(\inputs_current_ftw_H_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[7]),
        .Q(\inputs_current_ftw_H_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[8]),
        .Q(\inputs_current_ftw_H_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_H_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_ftw_H1_prog_V_1_reg_1479[9]),
        .Q(\inputs_current_ftw_H_reg_n_0_[9] ),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'h80)) 
    \inputs_current_ftw_L_1[47]_i_1 
       (.I0(p_Val2_4_reg_1510),
        .I1(inputs_valid_read_reg_1420_pp0_iter3_reg),
        .I2(ap_enable_reg_pp0_iter4),
        .O(inputs_current_ftw_L0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[0]),
        .Q(in[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[10]),
        .Q(in[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[11]),
        .Q(in[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[12]),
        .Q(in[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[13]),
        .Q(in[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[14]),
        .Q(in[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[15]),
        .Q(in[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[16]),
        .Q(in[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[17]),
        .Q(in[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[18]),
        .Q(in[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[19]),
        .Q(in[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[1]),
        .Q(in[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[20]),
        .Q(in[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[21]),
        .Q(in[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[22]),
        .Q(in[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[23]),
        .Q(in[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[24]),
        .Q(in[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[25]),
        .Q(in[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[26]),
        .Q(in[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[27]),
        .Q(in[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[28]),
        .Q(in[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[29]),
        .Q(in[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[2]),
        .Q(in[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[30]),
        .Q(in[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[31]),
        .Q(in[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[32]),
        .Q(in[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[33]),
        .Q(in[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[34]),
        .Q(in[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[35]),
        .Q(in[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[36]),
        .Q(in[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[37]),
        .Q(in[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[38]),
        .Q(in[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[39]),
        .Q(in[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[3]),
        .Q(in[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[40]),
        .Q(in[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[41]),
        .Q(in[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[42]),
        .Q(in[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[43]),
        .Q(in[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[44]),
        .Q(in[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[45]),
        .Q(in[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[46]),
        .Q(in[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[47]),
        .Q(in[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[4]),
        .Q(in[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[5]),
        .Q(in[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[6]),
        .Q(in[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[7]),
        .Q(in[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[8]),
        .Q(in[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_1_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[9]),
        .Q(in[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[0]),
        .Q(\inputs_current_ftw_L_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[10]),
        .Q(\inputs_current_ftw_L_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[11]),
        .Q(\inputs_current_ftw_L_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[12]),
        .Q(\inputs_current_ftw_L_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[13]),
        .Q(\inputs_current_ftw_L_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[14]),
        .Q(\inputs_current_ftw_L_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[15]),
        .Q(\inputs_current_ftw_L_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[16]),
        .Q(\inputs_current_ftw_L_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[17]),
        .Q(\inputs_current_ftw_L_reg_n_0_[17] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[18]),
        .Q(\inputs_current_ftw_L_reg_n_0_[18] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[19]),
        .Q(\inputs_current_ftw_L_reg_n_0_[19] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[1]),
        .Q(\inputs_current_ftw_L_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[20]),
        .Q(\inputs_current_ftw_L_reg_n_0_[20] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[21]),
        .Q(\inputs_current_ftw_L_reg_n_0_[21] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[22]),
        .Q(\inputs_current_ftw_L_reg_n_0_[22] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[23]),
        .Q(\inputs_current_ftw_L_reg_n_0_[23] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[24]),
        .Q(\inputs_current_ftw_L_reg_n_0_[24] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[25]),
        .Q(\inputs_current_ftw_L_reg_n_0_[25] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[26]),
        .Q(\inputs_current_ftw_L_reg_n_0_[26] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[27]),
        .Q(\inputs_current_ftw_L_reg_n_0_[27] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[28]),
        .Q(\inputs_current_ftw_L_reg_n_0_[28] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[29]),
        .Q(\inputs_current_ftw_L_reg_n_0_[29] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[2]),
        .Q(\inputs_current_ftw_L_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[30]),
        .Q(\inputs_current_ftw_L_reg_n_0_[30] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[31]),
        .Q(\inputs_current_ftw_L_reg_n_0_[31] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[32]),
        .Q(\inputs_current_ftw_L_reg_n_0_[32] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[33]),
        .Q(\inputs_current_ftw_L_reg_n_0_[33] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[34]),
        .Q(\inputs_current_ftw_L_reg_n_0_[34] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[35]),
        .Q(\inputs_current_ftw_L_reg_n_0_[35] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[36]),
        .Q(\inputs_current_ftw_L_reg_n_0_[36] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[37]),
        .Q(\inputs_current_ftw_L_reg_n_0_[37] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[38]),
        .Q(\inputs_current_ftw_L_reg_n_0_[38] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[39]),
        .Q(\inputs_current_ftw_L_reg_n_0_[39] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[3]),
        .Q(\inputs_current_ftw_L_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[40]),
        .Q(\inputs_current_ftw_L_reg_n_0_[40] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[41]),
        .Q(\inputs_current_ftw_L_reg_n_0_[41] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[42]),
        .Q(\inputs_current_ftw_L_reg_n_0_[42] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[43]),
        .Q(\inputs_current_ftw_L_reg_n_0_[43] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[44]),
        .Q(\inputs_current_ftw_L_reg_n_0_[44] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[45]),
        .Q(\inputs_current_ftw_L_reg_n_0_[45] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[46]),
        .Q(\inputs_current_ftw_L_reg_n_0_[46] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[47]),
        .Q(\inputs_current_ftw_L_reg_n_0_[47] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[4]),
        .Q(\inputs_current_ftw_L_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[5]),
        .Q(\inputs_current_ftw_L_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[6]),
        .Q(\inputs_current_ftw_L_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[7]),
        .Q(\inputs_current_ftw_L_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[8]),
        .Q(\inputs_current_ftw_L_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_ftw_L_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[9]),
        .Q(\inputs_current_ftw_L_reg_n_0_[9] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[0]),
        .Q(inputs_current_offse_1[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[10]),
        .Q(inputs_current_offse_1[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[11]),
        .Q(inputs_current_offse_1[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[12]),
        .Q(inputs_current_offse_1[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[13]),
        .Q(inputs_current_offse_1[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[14]),
        .Q(inputs_current_offse_1[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[15]),
        .Q(inputs_current_offse_1[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[16]),
        .Q(inputs_current_offse_1[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[17]),
        .Q(inputs_current_offse_1[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[18]),
        .Q(inputs_current_offse_1[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[19]),
        .Q(inputs_current_offse_1[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[1]),
        .Q(inputs_current_offse_1[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[20]),
        .Q(inputs_current_offse_1[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[21]),
        .Q(inputs_current_offse_1[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[22]),
        .Q(inputs_current_offse_1[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[23]),
        .Q(inputs_current_offse_1[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[24]),
        .Q(inputs_current_offse_1[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[25]),
        .Q(inputs_current_offse_1[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[26]),
        .Q(inputs_current_offse_1[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[27]),
        .Q(inputs_current_offse_1[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[28]),
        .Q(inputs_current_offse_1[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[29]),
        .Q(inputs_current_offse_1[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[2]),
        .Q(inputs_current_offse_1[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[30]),
        .Q(inputs_current_offse_1[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[31]),
        .Q(inputs_current_offse_1[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[32]),
        .Q(inputs_current_offse_1[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[33]),
        .Q(inputs_current_offse_1[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[34]),
        .Q(inputs_current_offse_1[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[35]),
        .Q(inputs_current_offse_1[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[36]),
        .Q(inputs_current_offse_1[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[37]),
        .Q(inputs_current_offse_1[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[38]),
        .Q(inputs_current_offse_1[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[39]),
        .Q(inputs_current_offse_1[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[3]),
        .Q(inputs_current_offse_1[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[40]),
        .Q(inputs_current_offse_1[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[41]),
        .Q(inputs_current_offse_1[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[42]),
        .Q(inputs_current_offse_1[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[43]),
        .Q(inputs_current_offse_1[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[44]),
        .Q(inputs_current_offse_1[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[45]),
        .Q(inputs_current_offse_1[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[46]),
        .Q(inputs_current_offse_1[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[47]),
        .Q(inputs_current_offse_1[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[4]),
        .Q(inputs_current_offse_1[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[5]),
        .Q(inputs_current_offse_1[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[6]),
        .Q(inputs_current_offse_1[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[7]),
        .Q(inputs_current_offse_1[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[8]),
        .Q(inputs_current_offse_1[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_1_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_V_read_reg_1452[9]),
        .Q(inputs_current_offse_1[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[0]),
        .Q(inputs_current_offse_3[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[10]),
        .Q(inputs_current_offse_3[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[11]),
        .Q(inputs_current_offse_3[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[12]),
        .Q(inputs_current_offse_3[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[13]),
        .Q(inputs_current_offse_3[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[14]),
        .Q(inputs_current_offse_3[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[15]),
        .Q(inputs_current_offse_3[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[16]),
        .Q(inputs_current_offse_3[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[17]),
        .Q(inputs_current_offse_3[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[18]),
        .Q(inputs_current_offse_3[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[19]),
        .Q(inputs_current_offse_3[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[1]),
        .Q(inputs_current_offse_3[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[20]),
        .Q(inputs_current_offse_3[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[21]),
        .Q(inputs_current_offse_3[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[22]),
        .Q(inputs_current_offse_3[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[23]),
        .Q(inputs_current_offse_3[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[24]),
        .Q(inputs_current_offse_3[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[25]),
        .Q(inputs_current_offse_3[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[26]),
        .Q(inputs_current_offse_3[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[27]),
        .Q(inputs_current_offse_3[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[28]),
        .Q(inputs_current_offse_3[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[29]),
        .Q(inputs_current_offse_3[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[2]),
        .Q(inputs_current_offse_3[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[30]),
        .Q(inputs_current_offse_3[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[31]),
        .Q(inputs_current_offse_3[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[32]),
        .Q(inputs_current_offse_3[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[33]),
        .Q(inputs_current_offse_3[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[34]),
        .Q(inputs_current_offse_3[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[35]),
        .Q(inputs_current_offse_3[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[36]),
        .Q(inputs_current_offse_3[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[37]),
        .Q(inputs_current_offse_3[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[38]),
        .Q(inputs_current_offse_3[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[39]),
        .Q(inputs_current_offse_3[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[3]),
        .Q(inputs_current_offse_3[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[40]),
        .Q(inputs_current_offse_3[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[41]),
        .Q(inputs_current_offse_3[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[42]),
        .Q(inputs_current_offse_3[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[43]),
        .Q(inputs_current_offse_3[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[44]),
        .Q(inputs_current_offse_3[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[45]),
        .Q(inputs_current_offse_3[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[46]),
        .Q(inputs_current_offse_3[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[47]),
        .Q(inputs_current_offse_3[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[4]),
        .Q(inputs_current_offse_3[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[5]),
        .Q(inputs_current_offse_3[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[6]),
        .Q(inputs_current_offse_3[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[7]),
        .Q(inputs_current_offse_3[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[8]),
        .Q(inputs_current_offse_3[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_3_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_off_reg_1437[9]),
        .Q(inputs_current_offse_3[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[0]),
        .Q(inputs_current_offse_4[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[10]),
        .Q(inputs_current_offse_4[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[11]),
        .Q(inputs_current_offse_4[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[12]),
        .Q(inputs_current_offse_4[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[13]),
        .Q(inputs_current_offse_4[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[14]),
        .Q(inputs_current_offse_4[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[15]),
        .Q(inputs_current_offse_4[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[16]),
        .Q(inputs_current_offse_4[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[17]),
        .Q(inputs_current_offse_4[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[18]),
        .Q(inputs_current_offse_4[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[19]),
        .Q(inputs_current_offse_4[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[1]),
        .Q(inputs_current_offse_4[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[20]),
        .Q(inputs_current_offse_4[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[21]),
        .Q(inputs_current_offse_4[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[22]),
        .Q(inputs_current_offse_4[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[23]),
        .Q(inputs_current_offse_4[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[24]),
        .Q(inputs_current_offse_4[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[25]),
        .Q(inputs_current_offse_4[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[26]),
        .Q(inputs_current_offse_4[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[27]),
        .Q(inputs_current_offse_4[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[28]),
        .Q(inputs_current_offse_4[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[29]),
        .Q(inputs_current_offse_4[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[2]),
        .Q(inputs_current_offse_4[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[30]),
        .Q(inputs_current_offse_4[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[31]),
        .Q(inputs_current_offse_4[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[32]),
        .Q(inputs_current_offse_4[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[33]),
        .Q(inputs_current_offse_4[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[34]),
        .Q(inputs_current_offse_4[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[35]),
        .Q(inputs_current_offse_4[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[36]),
        .Q(inputs_current_offse_4[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[37]),
        .Q(inputs_current_offse_4[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[38]),
        .Q(inputs_current_offse_4[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[39]),
        .Q(inputs_current_offse_4[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[3]),
        .Q(inputs_current_offse_4[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[40]),
        .Q(inputs_current_offse_4[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[41]),
        .Q(inputs_current_offse_4[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[42]),
        .Q(inputs_current_offse_4[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[43]),
        .Q(inputs_current_offse_4[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[44]),
        .Q(inputs_current_offse_4[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[45]),
        .Q(inputs_current_offse_4[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[46]),
        .Q(inputs_current_offse_4[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[47]),
        .Q(inputs_current_offse_4[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[4]),
        .Q(inputs_current_offse_4[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[5]),
        .Q(inputs_current_offse_4[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[6]),
        .Q(inputs_current_offse_4[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[7]),
        .Q(inputs_current_offse_4[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[8]),
        .Q(inputs_current_offse_4[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_4_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_AM_on_s_reg_1442[9]),
        .Q(inputs_current_offse_4[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[0]),
        .Q(inputs_current_offse[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[10]),
        .Q(inputs_current_offse[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[11]),
        .Q(inputs_current_offse[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[12]),
        .Q(inputs_current_offse[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[13]),
        .Q(inputs_current_offse[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[14]),
        .Q(inputs_current_offse[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[15]),
        .Q(inputs_current_offse[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[16]),
        .Q(inputs_current_offse[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[17]),
        .Q(inputs_current_offse[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[18]),
        .Q(inputs_current_offse[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[19]),
        .Q(inputs_current_offse[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[1]),
        .Q(inputs_current_offse[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[20]),
        .Q(inputs_current_offse[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[21]),
        .Q(inputs_current_offse[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[22]),
        .Q(inputs_current_offse[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[23]),
        .Q(inputs_current_offse[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[24]),
        .Q(inputs_current_offse[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[25]),
        .Q(inputs_current_offse[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[26]),
        .Q(inputs_current_offse[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[27]),
        .Q(inputs_current_offse[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[28]),
        .Q(inputs_current_offse[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[29]),
        .Q(inputs_current_offse[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[2]),
        .Q(inputs_current_offse[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[30]),
        .Q(inputs_current_offse[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[31]),
        .Q(inputs_current_offse[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[32]),
        .Q(inputs_current_offse[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[33]),
        .Q(inputs_current_offse[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[34]),
        .Q(inputs_current_offse[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[35]),
        .Q(inputs_current_offse[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[36]),
        .Q(inputs_current_offse[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[37]),
        .Q(inputs_current_offse[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[38]),
        .Q(inputs_current_offse[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[39]),
        .Q(inputs_current_offse[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[3]),
        .Q(inputs_current_offse[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[40]),
        .Q(inputs_current_offse[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[41]),
        .Q(inputs_current_offse[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[42]),
        .Q(inputs_current_offse[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[43]),
        .Q(inputs_current_offse[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[44]),
        .Q(inputs_current_offse[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[45]),
        .Q(inputs_current_offse[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[46]),
        .Q(inputs_current_offse[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[47]),
        .Q(inputs_current_offse[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[4]),
        .Q(inputs_current_offse[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[5]),
        .Q(inputs_current_offse[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[6]),
        .Q(inputs_current_offse[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[7]),
        .Q(inputs_current_offse[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[8]),
        .Q(inputs_current_offse[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_offse_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_offset_FSK_V_s_reg_1447[9]),
        .Q(inputs_current_offse[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[0]),
        .Q(inputs_current_phase[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[10] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[10]),
        .Q(inputs_current_phase[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[11] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[11]),
        .Q(inputs_current_phase[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[12] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[12]),
        .Q(inputs_current_phase[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[13] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[13]),
        .Q(inputs_current_phase[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[14] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[14]),
        .Q(inputs_current_phase[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[15] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[15]),
        .Q(inputs_current_phase[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[16] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[16]),
        .Q(inputs_current_phase[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[17] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[17]),
        .Q(inputs_current_phase[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[18] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[18]),
        .Q(inputs_current_phase[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[19] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[19]),
        .Q(inputs_current_phase[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[1]),
        .Q(inputs_current_phase[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[20] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[20]),
        .Q(inputs_current_phase[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[21] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[21]),
        .Q(inputs_current_phase[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[22] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[22]),
        .Q(inputs_current_phase[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[23] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[23]),
        .Q(inputs_current_phase[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[24] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[24]),
        .Q(inputs_current_phase[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[25] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[25]),
        .Q(inputs_current_phase[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[26] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[26]),
        .Q(inputs_current_phase[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[27] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[27]),
        .Q(inputs_current_phase[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[28] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[28]),
        .Q(inputs_current_phase[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[29] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[29]),
        .Q(inputs_current_phase[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[2]),
        .Q(inputs_current_phase[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[30] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[30]),
        .Q(inputs_current_phase[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[31] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[31]),
        .Q(inputs_current_phase[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[32] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[32]),
        .Q(inputs_current_phase[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[33] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[33]),
        .Q(inputs_current_phase[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[34] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[34]),
        .Q(inputs_current_phase[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[35] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[35]),
        .Q(inputs_current_phase[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[36] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[36]),
        .Q(inputs_current_phase[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[37] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[37]),
        .Q(inputs_current_phase[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[38] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[38]),
        .Q(inputs_current_phase[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[39] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[39]),
        .Q(inputs_current_phase[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[3] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[3]),
        .Q(inputs_current_phase[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[40] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[40]),
        .Q(inputs_current_phase[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[41] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[41]),
        .Q(inputs_current_phase[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[42] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[42]),
        .Q(inputs_current_phase[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[43] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[43]),
        .Q(inputs_current_phase[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[44] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[44]),
        .Q(inputs_current_phase[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[45] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[45]),
        .Q(inputs_current_phase[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[46] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[46]),
        .Q(inputs_current_phase[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[47] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[47]),
        .Q(inputs_current_phase[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[4] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[4]),
        .Q(inputs_current_phase[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[5] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[5]),
        .Q(inputs_current_phase[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[6] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[6]),
        .Q(inputs_current_phase[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[7] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[7]),
        .Q(inputs_current_phase[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[8] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[8]),
        .Q(inputs_current_phase[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_phase_reg[9] 
       (.C(ap_clk),
        .CE(inputs_current_ftw_L0),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[9]),
        .Q(inputs_current_phase[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_rate_s_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_rate_V_read_reg_1426[0]),
        .Q(inputs_current_rate_s[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_rate_s_reg[1] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_rate_V_read_reg_1426[1]),
        .Q(inputs_current_rate_s[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_rate_s_reg[2] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_rate_V_read_reg_1426[2]),
        .Q(inputs_current_rate_s[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_reset_1_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_reset_FSK_rea_reg_1409),
        .Q(inputs_current_reset_1),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_reset_3_reg_1615_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_reset_3_reg_1615),
        .Q(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_reset_3_reg_1615_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_current_reset_1),
        .Q(inputs_current_reset_3_reg_1615),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_reset_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_enabl_10),
        .D(inputs_reset_slip_re_reg_1403),
        .Q(inputs_current_reset),
        .R(ap_rst));
  LUT2 #(
    .INIT(4'h8)) 
    \inputs_current_slip_s[0]_i_1 
       (.I0(inputs_valid_preg),
        .I1(\ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450[0]_i_1_n_0 ),
        .O(inputs_current_dftw_s0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_current_slip_s_reg[0] 
       (.C(ap_clk),
        .CE(inputs_current_dftw_s0),
        .D(inputs_slip_sign_preg),
        .Q(inputs_current_slip_s),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_dftw_H1_slip_V_ap_vld_preg_i_1
       (.I0(inputs_dftw_H1_slip_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_dftw_H1_slip_V_ap_vld_preg),
        .O(inputs_dftw_H1_slip_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_dftw_H1_slip_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_dftw_H1_slip_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_dftw_H1_slip_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[0]),
        .Q(inputs_dftw_H1_slip_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[10]),
        .Q(inputs_dftw_H1_slip_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[11]),
        .Q(inputs_dftw_H1_slip_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[12]),
        .Q(inputs_dftw_H1_slip_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[13]),
        .Q(inputs_dftw_H1_slip_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[14]),
        .Q(inputs_dftw_H1_slip_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[15]),
        .Q(inputs_dftw_H1_slip_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[16]),
        .Q(inputs_dftw_H1_slip_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[17]),
        .Q(inputs_dftw_H1_slip_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[18]),
        .Q(inputs_dftw_H1_slip_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[19]),
        .Q(inputs_dftw_H1_slip_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[1]),
        .Q(inputs_dftw_H1_slip_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[20]),
        .Q(inputs_dftw_H1_slip_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[21]),
        .Q(inputs_dftw_H1_slip_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[22]),
        .Q(inputs_dftw_H1_slip_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[23]),
        .Q(inputs_dftw_H1_slip_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[24]),
        .Q(inputs_dftw_H1_slip_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[25]),
        .Q(inputs_dftw_H1_slip_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[26]),
        .Q(inputs_dftw_H1_slip_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[27]),
        .Q(inputs_dftw_H1_slip_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[28]),
        .Q(inputs_dftw_H1_slip_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[29]),
        .Q(inputs_dftw_H1_slip_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[2]),
        .Q(inputs_dftw_H1_slip_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[30]),
        .Q(inputs_dftw_H1_slip_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[31]),
        .Q(inputs_dftw_H1_slip_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[3]),
        .Q(inputs_dftw_H1_slip_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[4]),
        .Q(inputs_dftw_H1_slip_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[5]),
        .Q(inputs_dftw_H1_slip_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[6]),
        .Q(inputs_dftw_H1_slip_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[7]),
        .Q(inputs_dftw_H1_slip_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[8]),
        .Q(inputs_dftw_H1_slip_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_dftw_H1_slip_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_dftw_H1_slip_V_ap_vld),
        .D(inputs_dftw_H1_slip_V[9]),
        .Q(inputs_dftw_H1_slip_V_preg[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_enable_FSK_ap_vld_preg_i_1
       (.I0(inputs_enable_FSK_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_enable_FSK_ap_vld_preg),
        .O(inputs_enable_FSK_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_enable_FSK_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_enable_FSK_ap_vld_preg_i_1_n_0),
        .Q(inputs_enable_FSK_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_enable_FSK_preg[0]_i_1 
       (.I0(inputs_enable_FSK),
        .I1(inputs_enable_FSK_ap_vld),
        .I2(inputs_enable_FSK_preg),
        .O(\inputs_enable_FSK_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_enable_FSK_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_enable_FSK_preg[0]_i_1_n_0 ),
        .Q(inputs_enable_FSK_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_enable_FSK_re_reg_1414_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_enable_FSK_preg),
        .Q(inputs_enable_FSK_re_reg_1414),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_enable_slip_ap_vld_preg_i_1
       (.I0(inputs_enable_slip_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_enable_slip_ap_vld_preg),
        .O(inputs_enable_slip_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_enable_slip_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_enable_slip_ap_vld_preg_i_1_n_0),
        .Q(inputs_enable_slip_ap_vld_preg),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_enable_slip_preg[0]_i_1 
       (.I0(inputs_enable_slip),
        .I1(inputs_enable_slip_ap_vld),
        .I2(inputs_enable_slip_preg),
        .O(\inputs_enable_slip_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_enable_slip_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_enable_slip_preg[0]_i_1_n_0 ),
        .Q(inputs_enable_slip_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_force_AM_ap_vld_preg_i_1
       (.I0(inputs_force_AM_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_force_AM_ap_vld_preg),
        .O(inputs_force_AM_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_force_AM_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_force_AM_ap_vld_preg_i_1_n_0),
        .Q(inputs_force_AM_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_force_AM_preg[0]_i_1 
       (.I0(inputs_force_AM),
        .I1(inputs_force_AM_ap_vld),
        .I2(inputs_force_AM_preg),
        .O(\inputs_force_AM_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_force_AM_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_force_AM_preg[0]_i_1_n_0 ),
        .Q(inputs_force_AM_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_force_AM_read_reg_1392_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_force_AM_preg),
        .Q(inputs_force_AM_read_reg_1392),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_ftw_H1_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_H1_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_ftw_H1_V_ap_vld_preg),
        .O(inputs_ftw_H1_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_H1_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_H1_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_H1_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[0]),
        .Q(inputs_ftw_H1_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[10]),
        .Q(inputs_ftw_H1_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[11]),
        .Q(inputs_ftw_H1_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[12]),
        .Q(inputs_ftw_H1_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[13]),
        .Q(inputs_ftw_H1_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[14]),
        .Q(inputs_ftw_H1_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[15]),
        .Q(inputs_ftw_H1_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[16]),
        .Q(inputs_ftw_H1_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[17]),
        .Q(inputs_ftw_H1_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[18]),
        .Q(inputs_ftw_H1_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[19]),
        .Q(inputs_ftw_H1_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[1]),
        .Q(inputs_ftw_H1_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[20]),
        .Q(inputs_ftw_H1_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[21]),
        .Q(inputs_ftw_H1_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[22]),
        .Q(inputs_ftw_H1_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[23]),
        .Q(inputs_ftw_H1_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[24]),
        .Q(inputs_ftw_H1_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[25]),
        .Q(inputs_ftw_H1_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[26]),
        .Q(inputs_ftw_H1_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[27]),
        .Q(inputs_ftw_H1_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[28]),
        .Q(inputs_ftw_H1_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[29]),
        .Q(inputs_ftw_H1_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[2]),
        .Q(inputs_ftw_H1_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[30]),
        .Q(inputs_ftw_H1_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[31]),
        .Q(inputs_ftw_H1_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[32]),
        .Q(inputs_ftw_H1_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[33]),
        .Q(inputs_ftw_H1_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[34]),
        .Q(inputs_ftw_H1_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[35]),
        .Q(inputs_ftw_H1_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[36]),
        .Q(inputs_ftw_H1_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[37]),
        .Q(inputs_ftw_H1_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[38]),
        .Q(inputs_ftw_H1_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[39]),
        .Q(inputs_ftw_H1_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[3]),
        .Q(inputs_ftw_H1_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[40]),
        .Q(inputs_ftw_H1_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[41]),
        .Q(inputs_ftw_H1_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[42]),
        .Q(inputs_ftw_H1_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[43]),
        .Q(inputs_ftw_H1_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[44]),
        .Q(inputs_ftw_H1_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[45]),
        .Q(inputs_ftw_H1_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[46]),
        .Q(inputs_ftw_H1_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[47]),
        .Q(inputs_ftw_H1_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[4]),
        .Q(inputs_ftw_H1_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[5]),
        .Q(inputs_ftw_H1_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[6]),
        .Q(inputs_ftw_H1_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[7]),
        .Q(inputs_ftw_H1_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[8]),
        .Q(inputs_ftw_H1_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_V_ap_vld),
        .D(inputs_ftw_H1_V[9]),
        .Q(inputs_ftw_H1_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[0]),
        .Q(inputs_ftw_H1_V_read_reg_1484[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[10]),
        .Q(inputs_ftw_H1_V_read_reg_1484[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[11]),
        .Q(inputs_ftw_H1_V_read_reg_1484[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[12]),
        .Q(inputs_ftw_H1_V_read_reg_1484[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[13]),
        .Q(inputs_ftw_H1_V_read_reg_1484[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[14]),
        .Q(inputs_ftw_H1_V_read_reg_1484[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[15]),
        .Q(inputs_ftw_H1_V_read_reg_1484[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[16]),
        .Q(inputs_ftw_H1_V_read_reg_1484[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[17]),
        .Q(inputs_ftw_H1_V_read_reg_1484[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[18]),
        .Q(inputs_ftw_H1_V_read_reg_1484[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[19]),
        .Q(inputs_ftw_H1_V_read_reg_1484[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[1]),
        .Q(inputs_ftw_H1_V_read_reg_1484[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[20]),
        .Q(inputs_ftw_H1_V_read_reg_1484[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[21]),
        .Q(inputs_ftw_H1_V_read_reg_1484[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[22]),
        .Q(inputs_ftw_H1_V_read_reg_1484[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[23]),
        .Q(inputs_ftw_H1_V_read_reg_1484[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[24]),
        .Q(inputs_ftw_H1_V_read_reg_1484[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[25]),
        .Q(inputs_ftw_H1_V_read_reg_1484[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[26]),
        .Q(inputs_ftw_H1_V_read_reg_1484[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[27]),
        .Q(inputs_ftw_H1_V_read_reg_1484[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[28]),
        .Q(inputs_ftw_H1_V_read_reg_1484[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[29]),
        .Q(inputs_ftw_H1_V_read_reg_1484[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[2]),
        .Q(inputs_ftw_H1_V_read_reg_1484[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[30]),
        .Q(inputs_ftw_H1_V_read_reg_1484[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[31]),
        .Q(inputs_ftw_H1_V_read_reg_1484[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[32]),
        .Q(inputs_ftw_H1_V_read_reg_1484[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[33]),
        .Q(inputs_ftw_H1_V_read_reg_1484[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[34]),
        .Q(inputs_ftw_H1_V_read_reg_1484[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[35]),
        .Q(inputs_ftw_H1_V_read_reg_1484[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[36]),
        .Q(inputs_ftw_H1_V_read_reg_1484[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[37]),
        .Q(inputs_ftw_H1_V_read_reg_1484[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[38]),
        .Q(inputs_ftw_H1_V_read_reg_1484[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[39]),
        .Q(inputs_ftw_H1_V_read_reg_1484[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[3]),
        .Q(inputs_ftw_H1_V_read_reg_1484[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[40]),
        .Q(inputs_ftw_H1_V_read_reg_1484[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[41]),
        .Q(inputs_ftw_H1_V_read_reg_1484[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[42]),
        .Q(inputs_ftw_H1_V_read_reg_1484[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[43]),
        .Q(inputs_ftw_H1_V_read_reg_1484[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[44]),
        .Q(inputs_ftw_H1_V_read_reg_1484[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[45]),
        .Q(inputs_ftw_H1_V_read_reg_1484[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[46]),
        .Q(inputs_ftw_H1_V_read_reg_1484[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[47]),
        .Q(inputs_ftw_H1_V_read_reg_1484[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[4]),
        .Q(inputs_ftw_H1_V_read_reg_1484[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[5]),
        .Q(inputs_ftw_H1_V_read_reg_1484[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[6]),
        .Q(inputs_ftw_H1_V_read_reg_1484[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[7]),
        .Q(inputs_ftw_H1_V_read_reg_1484[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[8]),
        .Q(inputs_ftw_H1_V_read_reg_1484[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_V_read_reg_1484_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_V_preg[9]),
        .Q(inputs_ftw_H1_V_read_reg_1484[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_ftw_H1_on_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_H1_on_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_ftw_H1_on_V_ap_vld_preg),
        .O(inputs_ftw_H1_on_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_H1_on_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_H1_on_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_H1_on_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[0]),
        .Q(inputs_ftw_H1_on_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[10]),
        .Q(inputs_ftw_H1_on_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[11]),
        .Q(inputs_ftw_H1_on_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[12]),
        .Q(inputs_ftw_H1_on_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[13]),
        .Q(inputs_ftw_H1_on_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[14]),
        .Q(inputs_ftw_H1_on_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[15]),
        .Q(inputs_ftw_H1_on_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[16]),
        .Q(inputs_ftw_H1_on_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[17]),
        .Q(inputs_ftw_H1_on_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[18]),
        .Q(inputs_ftw_H1_on_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[19]),
        .Q(inputs_ftw_H1_on_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[1]),
        .Q(inputs_ftw_H1_on_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[20]),
        .Q(inputs_ftw_H1_on_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[21]),
        .Q(inputs_ftw_H1_on_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[22]),
        .Q(inputs_ftw_H1_on_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[23]),
        .Q(inputs_ftw_H1_on_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[24]),
        .Q(inputs_ftw_H1_on_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[25]),
        .Q(inputs_ftw_H1_on_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[26]),
        .Q(inputs_ftw_H1_on_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[27]),
        .Q(inputs_ftw_H1_on_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[28]),
        .Q(inputs_ftw_H1_on_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[29]),
        .Q(inputs_ftw_H1_on_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[2]),
        .Q(inputs_ftw_H1_on_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[30]),
        .Q(inputs_ftw_H1_on_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[31]),
        .Q(inputs_ftw_H1_on_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[32]),
        .Q(inputs_ftw_H1_on_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[33]),
        .Q(inputs_ftw_H1_on_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[34]),
        .Q(inputs_ftw_H1_on_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[35]),
        .Q(inputs_ftw_H1_on_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[36]),
        .Q(inputs_ftw_H1_on_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[37]),
        .Q(inputs_ftw_H1_on_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[38]),
        .Q(inputs_ftw_H1_on_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[39]),
        .Q(inputs_ftw_H1_on_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[3]),
        .Q(inputs_ftw_H1_on_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[40]),
        .Q(inputs_ftw_H1_on_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[41]),
        .Q(inputs_ftw_H1_on_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[42]),
        .Q(inputs_ftw_H1_on_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[43]),
        .Q(inputs_ftw_H1_on_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[44]),
        .Q(inputs_ftw_H1_on_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[45]),
        .Q(inputs_ftw_H1_on_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[46]),
        .Q(inputs_ftw_H1_on_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[47]),
        .Q(inputs_ftw_H1_on_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[4]),
        .Q(inputs_ftw_H1_on_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[5]),
        .Q(inputs_ftw_H1_on_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[6]),
        .Q(inputs_ftw_H1_on_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[7]),
        .Q(inputs_ftw_H1_on_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[8]),
        .Q(inputs_ftw_H1_on_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_on_V_ap_vld),
        .D(inputs_ftw_H1_on_V[9]),
        .Q(inputs_ftw_H1_on_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[0]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[10]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[11]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[12]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[13]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[14]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[15]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[16]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[17]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[18]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[19]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[1]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[20]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[21]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[22]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[23]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[24]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[25]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[26]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[27]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[28]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[29]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[2]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[30]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[31]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[32]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[33]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[34]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[35]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[36]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[37]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[38]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[39]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[3]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[40]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[41]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[42]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[43]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[44]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[45]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[46]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[47]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[4]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[5]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[6]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[7]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[8]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_on_V_r_reg_1463_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_on_V_preg[9]),
        .Q(inputs_ftw_H1_on_V_r_reg_1463[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[0]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[10]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[11]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[12]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[13]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[14]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[15]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[16]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[17]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[18]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[19]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[1]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[20]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[21]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[22]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[23]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[24]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[25]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[26]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[27]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[28]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[29]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[2]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[30]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[31]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[32]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[33]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[34]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[35]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[36]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[37]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[38]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[39]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[3]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[40]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[41]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[42]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[43]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[44]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[45]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[46]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[47]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[4]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[5]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[6]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[7]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[8]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_1_reg_1479_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_H1_prog_V_preg[9]),
        .Q(inputs_ftw_H1_prog_V_1_reg_1479[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_ftw_H1_prog_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_H1_prog_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_ftw_H1_prog_V_ap_vld_preg),
        .O(inputs_ftw_H1_prog_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_H1_prog_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_H1_prog_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_H1_prog_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[0]),
        .Q(inputs_ftw_H1_prog_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[10]),
        .Q(inputs_ftw_H1_prog_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[11]),
        .Q(inputs_ftw_H1_prog_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[12]),
        .Q(inputs_ftw_H1_prog_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[13]),
        .Q(inputs_ftw_H1_prog_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[14]),
        .Q(inputs_ftw_H1_prog_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[15]),
        .Q(inputs_ftw_H1_prog_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[16]),
        .Q(inputs_ftw_H1_prog_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[17]),
        .Q(inputs_ftw_H1_prog_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[18]),
        .Q(inputs_ftw_H1_prog_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[19]),
        .Q(inputs_ftw_H1_prog_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[1]),
        .Q(inputs_ftw_H1_prog_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[20]),
        .Q(inputs_ftw_H1_prog_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[21]),
        .Q(inputs_ftw_H1_prog_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[22]),
        .Q(inputs_ftw_H1_prog_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[23]),
        .Q(inputs_ftw_H1_prog_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[24]),
        .Q(inputs_ftw_H1_prog_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[25]),
        .Q(inputs_ftw_H1_prog_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[26]),
        .Q(inputs_ftw_H1_prog_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[27]),
        .Q(inputs_ftw_H1_prog_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[28]),
        .Q(inputs_ftw_H1_prog_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[29]),
        .Q(inputs_ftw_H1_prog_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[2]),
        .Q(inputs_ftw_H1_prog_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[30]),
        .Q(inputs_ftw_H1_prog_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[31]),
        .Q(inputs_ftw_H1_prog_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[32]),
        .Q(inputs_ftw_H1_prog_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[33]),
        .Q(inputs_ftw_H1_prog_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[34]),
        .Q(inputs_ftw_H1_prog_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[35]),
        .Q(inputs_ftw_H1_prog_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[36]),
        .Q(inputs_ftw_H1_prog_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[37]),
        .Q(inputs_ftw_H1_prog_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[38]),
        .Q(inputs_ftw_H1_prog_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[39]),
        .Q(inputs_ftw_H1_prog_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[3]),
        .Q(inputs_ftw_H1_prog_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[40]),
        .Q(inputs_ftw_H1_prog_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[41]),
        .Q(inputs_ftw_H1_prog_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[42]),
        .Q(inputs_ftw_H1_prog_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[43]),
        .Q(inputs_ftw_H1_prog_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[44]),
        .Q(inputs_ftw_H1_prog_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[45]),
        .Q(inputs_ftw_H1_prog_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[46]),
        .Q(inputs_ftw_H1_prog_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[47]),
        .Q(inputs_ftw_H1_prog_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[4]),
        .Q(inputs_ftw_H1_prog_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[5]),
        .Q(inputs_ftw_H1_prog_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[6]),
        .Q(inputs_ftw_H1_prog_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[7]),
        .Q(inputs_ftw_H1_prog_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[8]),
        .Q(inputs_ftw_H1_prog_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_H1_prog_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_H1_prog_V_ap_vld),
        .D(inputs_ftw_H1_prog_V[9]),
        .Q(inputs_ftw_H1_prog_V_preg[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_ftw_LO_0_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_LO_0_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_ftw_LO_0_V_ap_vld_preg),
        .O(inputs_ftw_LO_0_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_LO_0_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_LO_0_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_LO_0_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[0]),
        .Q(inputs_ftw_LO_0_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[10]),
        .Q(inputs_ftw_LO_0_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[11]),
        .Q(inputs_ftw_LO_0_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[12]),
        .Q(inputs_ftw_LO_0_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[13]),
        .Q(inputs_ftw_LO_0_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[14]),
        .Q(inputs_ftw_LO_0_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[15]),
        .Q(inputs_ftw_LO_0_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[16]),
        .Q(inputs_ftw_LO_0_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[17]),
        .Q(inputs_ftw_LO_0_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[18]),
        .Q(inputs_ftw_LO_0_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[19]),
        .Q(inputs_ftw_LO_0_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[1]),
        .Q(inputs_ftw_LO_0_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[20]),
        .Q(inputs_ftw_LO_0_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[21]),
        .Q(inputs_ftw_LO_0_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[22]),
        .Q(inputs_ftw_LO_0_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[23]),
        .Q(inputs_ftw_LO_0_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[24]),
        .Q(inputs_ftw_LO_0_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[25]),
        .Q(inputs_ftw_LO_0_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[26]),
        .Q(inputs_ftw_LO_0_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[27]),
        .Q(inputs_ftw_LO_0_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[28]),
        .Q(inputs_ftw_LO_0_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[29]),
        .Q(inputs_ftw_LO_0_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[2]),
        .Q(inputs_ftw_LO_0_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[30]),
        .Q(inputs_ftw_LO_0_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[31]),
        .Q(inputs_ftw_LO_0_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[32]),
        .Q(inputs_ftw_LO_0_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[33]),
        .Q(inputs_ftw_LO_0_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[34]),
        .Q(inputs_ftw_LO_0_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[35]),
        .Q(inputs_ftw_LO_0_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[36]),
        .Q(inputs_ftw_LO_0_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[37]),
        .Q(inputs_ftw_LO_0_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[38]),
        .Q(inputs_ftw_LO_0_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[39]),
        .Q(inputs_ftw_LO_0_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[3]),
        .Q(inputs_ftw_LO_0_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[40]),
        .Q(inputs_ftw_LO_0_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[41]),
        .Q(inputs_ftw_LO_0_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[42]),
        .Q(inputs_ftw_LO_0_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[43]),
        .Q(inputs_ftw_LO_0_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[44]),
        .Q(inputs_ftw_LO_0_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[45]),
        .Q(inputs_ftw_LO_0_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[46]),
        .Q(inputs_ftw_LO_0_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[47]),
        .Q(inputs_ftw_LO_0_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[4]),
        .Q(inputs_ftw_LO_0_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[5]),
        .Q(inputs_ftw_LO_0_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[6]),
        .Q(inputs_ftw_LO_0_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[7]),
        .Q(inputs_ftw_LO_0_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[8]),
        .Q(inputs_ftw_LO_0_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_0_V_ap_vld),
        .D(inputs_ftw_LO_0_V[9]),
        .Q(inputs_ftw_LO_0_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[0]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[10]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[11]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[12]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[13]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[14]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[15]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[16]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[17]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[18]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[19]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[1]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[20]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[21]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[22]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[23]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[24]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[25]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[26]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[27]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[28]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[29]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[2]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[30]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[31]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[32]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[33]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[34]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[35]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[36]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[37]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[38]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[39]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[3]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[40]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[41]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[42]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[43]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[44]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[45]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[46]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[47]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[4]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[5]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[6]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[7]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[8]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474[9]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[0]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[10]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[11]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[12]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[13]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[14]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[15]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[16]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[17]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[18]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[19]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[1]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[20]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[21]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[22]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[23]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[24]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[25]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[26]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[27]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[28]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[29]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[2]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[30]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[31]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[32]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[33]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[34]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[35]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[36]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[37]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[38]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[39]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[3]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[40]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[41]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[42]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[43]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[44]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[45]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[46]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[47]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[4]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[5]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[6]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[7]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[8]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter2_reg[9]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474_pp0_iter3_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[0]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[10]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[11]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[12]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[13]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[14]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[15]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[16]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[17]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[18]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[19]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[1]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[20]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[21]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[22]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[23]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[24]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[25]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[26]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[27]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[28]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[29]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[2]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[30]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[31]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[32]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[33]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[34]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[35]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[36]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[37]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[38]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[39]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[3]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[40]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[41]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[42]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[43]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[44]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[45]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[46]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[47]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[4]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[5]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[6]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[7]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[8]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_0_V_re_reg_1474_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_0_V_preg[9]),
        .Q(inputs_ftw_LO_0_V_re_reg_1474[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_ftw_LO_1_V_ap_vld_preg_i_1
       (.I0(inputs_ftw_LO_1_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_ftw_LO_1_V_ap_vld_preg),
        .O(inputs_ftw_LO_1_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_ftw_LO_1_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_ftw_LO_1_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_ftw_LO_1_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[0]),
        .Q(inputs_ftw_LO_1_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[10]),
        .Q(inputs_ftw_LO_1_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[11]),
        .Q(inputs_ftw_LO_1_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[12]),
        .Q(inputs_ftw_LO_1_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[13]),
        .Q(inputs_ftw_LO_1_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[14]),
        .Q(inputs_ftw_LO_1_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[15]),
        .Q(inputs_ftw_LO_1_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[16]),
        .Q(inputs_ftw_LO_1_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[17]),
        .Q(inputs_ftw_LO_1_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[18]),
        .Q(inputs_ftw_LO_1_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[19]),
        .Q(inputs_ftw_LO_1_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[1]),
        .Q(inputs_ftw_LO_1_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[20]),
        .Q(inputs_ftw_LO_1_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[21]),
        .Q(inputs_ftw_LO_1_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[22]),
        .Q(inputs_ftw_LO_1_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[23]),
        .Q(inputs_ftw_LO_1_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[24]),
        .Q(inputs_ftw_LO_1_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[25]),
        .Q(inputs_ftw_LO_1_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[26]),
        .Q(inputs_ftw_LO_1_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[27]),
        .Q(inputs_ftw_LO_1_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[28]),
        .Q(inputs_ftw_LO_1_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[29]),
        .Q(inputs_ftw_LO_1_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[2]),
        .Q(inputs_ftw_LO_1_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[30]),
        .Q(inputs_ftw_LO_1_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[31]),
        .Q(inputs_ftw_LO_1_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[32]),
        .Q(inputs_ftw_LO_1_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[33]),
        .Q(inputs_ftw_LO_1_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[34]),
        .Q(inputs_ftw_LO_1_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[35]),
        .Q(inputs_ftw_LO_1_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[36]),
        .Q(inputs_ftw_LO_1_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[37]),
        .Q(inputs_ftw_LO_1_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[38]),
        .Q(inputs_ftw_LO_1_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[39]),
        .Q(inputs_ftw_LO_1_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[3]),
        .Q(inputs_ftw_LO_1_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[40]),
        .Q(inputs_ftw_LO_1_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[41]),
        .Q(inputs_ftw_LO_1_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[42]),
        .Q(inputs_ftw_LO_1_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[43]),
        .Q(inputs_ftw_LO_1_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[44]),
        .Q(inputs_ftw_LO_1_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[45]),
        .Q(inputs_ftw_LO_1_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[46]),
        .Q(inputs_ftw_LO_1_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[47]),
        .Q(inputs_ftw_LO_1_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[4]),
        .Q(inputs_ftw_LO_1_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[5]),
        .Q(inputs_ftw_LO_1_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[6]),
        .Q(inputs_ftw_LO_1_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[7]),
        .Q(inputs_ftw_LO_1_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[8]),
        .Q(inputs_ftw_LO_1_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_ftw_LO_1_V_ap_vld),
        .D(inputs_ftw_LO_1_V[9]),
        .Q(inputs_ftw_LO_1_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[0]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[10]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[11]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[12]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[13]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[14]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[15]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[16]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[17]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[18]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[19]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[1]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[20]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[21]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[22]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[23]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[24]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[25]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[26]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[27]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[28]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[29]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[2]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[30]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[31]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[32]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[33]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[34]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[35]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[36]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[37]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[38]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[39]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[3]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[40]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[41]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[42]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[43]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[44]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[45]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[46]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[47]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[4]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[5]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[6]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[7]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[8]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469[9]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[0]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[10]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[11]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[12]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[13]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[14]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[15]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[16]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[17]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[18]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[19]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[1]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[20]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[21]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[22]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[23]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[24]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[25]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[26]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[27]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[28]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[29]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[2]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[30]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[31]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[32]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[33]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[34]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[35]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[36]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[37]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[38]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[39]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[3]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[40]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[41]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[42]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[43]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[44]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[45]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[46]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[47]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[4]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[5]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[6]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[7]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[8]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter2_reg[9]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469_pp0_iter3_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[0]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[10]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[11]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[12]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[13]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[14]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[15]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[16]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[17]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[18]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[19]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[1]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[20]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[21]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[22]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[23]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[24]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[25]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[26]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[27]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[28]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[29]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[2]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[30]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[31]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[32]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[33]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[34]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[35]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[36]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[37]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[38]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[39]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[3]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[40]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[41]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[42]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[43]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[44]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[45]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[46]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[47]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[4]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[5]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[6]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[7]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[8]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_ftw_LO_1_V_re_reg_1469_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_ftw_LO_1_V_preg[9]),
        .Q(inputs_ftw_LO_1_V_re_reg_1469[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_offset_AM_off_V_ap_vld_preg_i_1
       (.I0(inputs_offset_AM_off_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_offset_AM_off_V_ap_vld_preg),
        .O(inputs_offset_AM_off_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_offset_AM_off_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_offset_AM_off_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_offset_AM_off_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[0]),
        .Q(inputs_offset_AM_off_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[10]),
        .Q(inputs_offset_AM_off_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[11]),
        .Q(inputs_offset_AM_off_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[12]),
        .Q(inputs_offset_AM_off_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[13]),
        .Q(inputs_offset_AM_off_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[14]),
        .Q(inputs_offset_AM_off_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[15]),
        .Q(inputs_offset_AM_off_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[16]),
        .Q(inputs_offset_AM_off_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[17]),
        .Q(inputs_offset_AM_off_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[18]),
        .Q(inputs_offset_AM_off_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[19]),
        .Q(inputs_offset_AM_off_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[1]),
        .Q(inputs_offset_AM_off_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[20]),
        .Q(inputs_offset_AM_off_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[21]),
        .Q(inputs_offset_AM_off_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[22]),
        .Q(inputs_offset_AM_off_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[23]),
        .Q(inputs_offset_AM_off_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[24]),
        .Q(inputs_offset_AM_off_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[25]),
        .Q(inputs_offset_AM_off_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[26]),
        .Q(inputs_offset_AM_off_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[27]),
        .Q(inputs_offset_AM_off_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[28]),
        .Q(inputs_offset_AM_off_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[29]),
        .Q(inputs_offset_AM_off_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[2]),
        .Q(inputs_offset_AM_off_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[30]),
        .Q(inputs_offset_AM_off_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[31]),
        .Q(inputs_offset_AM_off_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[32]),
        .Q(inputs_offset_AM_off_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[33]),
        .Q(inputs_offset_AM_off_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[34]),
        .Q(inputs_offset_AM_off_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[35]),
        .Q(inputs_offset_AM_off_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[36]),
        .Q(inputs_offset_AM_off_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[37]),
        .Q(inputs_offset_AM_off_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[38]),
        .Q(inputs_offset_AM_off_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[39]),
        .Q(inputs_offset_AM_off_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[3]),
        .Q(inputs_offset_AM_off_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[40]),
        .Q(inputs_offset_AM_off_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[41]),
        .Q(inputs_offset_AM_off_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[42]),
        .Q(inputs_offset_AM_off_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[43]),
        .Q(inputs_offset_AM_off_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[44]),
        .Q(inputs_offset_AM_off_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[45]),
        .Q(inputs_offset_AM_off_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[46]),
        .Q(inputs_offset_AM_off_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[47]),
        .Q(inputs_offset_AM_off_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[4]),
        .Q(inputs_offset_AM_off_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[5]),
        .Q(inputs_offset_AM_off_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[6]),
        .Q(inputs_offset_AM_off_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[7]),
        .Q(inputs_offset_AM_off_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[8]),
        .Q(inputs_offset_AM_off_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_off_V_ap_vld),
        .D(inputs_offset_AM_off_V[9]),
        .Q(inputs_offset_AM_off_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[0]),
        .Q(inputs_offset_AM_off_reg_1437[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[10]),
        .Q(inputs_offset_AM_off_reg_1437[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[11]),
        .Q(inputs_offset_AM_off_reg_1437[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[12]),
        .Q(inputs_offset_AM_off_reg_1437[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[13]),
        .Q(inputs_offset_AM_off_reg_1437[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[14]),
        .Q(inputs_offset_AM_off_reg_1437[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[15]),
        .Q(inputs_offset_AM_off_reg_1437[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[16]),
        .Q(inputs_offset_AM_off_reg_1437[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[17]),
        .Q(inputs_offset_AM_off_reg_1437[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[18]),
        .Q(inputs_offset_AM_off_reg_1437[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[19]),
        .Q(inputs_offset_AM_off_reg_1437[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[1]),
        .Q(inputs_offset_AM_off_reg_1437[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[20]),
        .Q(inputs_offset_AM_off_reg_1437[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[21]),
        .Q(inputs_offset_AM_off_reg_1437[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[22]),
        .Q(inputs_offset_AM_off_reg_1437[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[23]),
        .Q(inputs_offset_AM_off_reg_1437[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[24]),
        .Q(inputs_offset_AM_off_reg_1437[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[25]),
        .Q(inputs_offset_AM_off_reg_1437[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[26]),
        .Q(inputs_offset_AM_off_reg_1437[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[27]),
        .Q(inputs_offset_AM_off_reg_1437[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[28]),
        .Q(inputs_offset_AM_off_reg_1437[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[29]),
        .Q(inputs_offset_AM_off_reg_1437[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[2]),
        .Q(inputs_offset_AM_off_reg_1437[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[30]),
        .Q(inputs_offset_AM_off_reg_1437[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[31]),
        .Q(inputs_offset_AM_off_reg_1437[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[32]),
        .Q(inputs_offset_AM_off_reg_1437[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[33]),
        .Q(inputs_offset_AM_off_reg_1437[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[34]),
        .Q(inputs_offset_AM_off_reg_1437[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[35]),
        .Q(inputs_offset_AM_off_reg_1437[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[36]),
        .Q(inputs_offset_AM_off_reg_1437[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[37]),
        .Q(inputs_offset_AM_off_reg_1437[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[38]),
        .Q(inputs_offset_AM_off_reg_1437[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[39]),
        .Q(inputs_offset_AM_off_reg_1437[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[3]),
        .Q(inputs_offset_AM_off_reg_1437[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[40]),
        .Q(inputs_offset_AM_off_reg_1437[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[41]),
        .Q(inputs_offset_AM_off_reg_1437[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[42]),
        .Q(inputs_offset_AM_off_reg_1437[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[43]),
        .Q(inputs_offset_AM_off_reg_1437[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[44]),
        .Q(inputs_offset_AM_off_reg_1437[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[45]),
        .Q(inputs_offset_AM_off_reg_1437[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[46]),
        .Q(inputs_offset_AM_off_reg_1437[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[47]),
        .Q(inputs_offset_AM_off_reg_1437[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[4]),
        .Q(inputs_offset_AM_off_reg_1437[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[5]),
        .Q(inputs_offset_AM_off_reg_1437[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[6]),
        .Q(inputs_offset_AM_off_reg_1437[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[7]),
        .Q(inputs_offset_AM_off_reg_1437[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[8]),
        .Q(inputs_offset_AM_off_reg_1437[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_off_reg_1437_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_off_V_preg[9]),
        .Q(inputs_offset_AM_off_reg_1437[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_offset_AM_on_V_ap_vld_preg_i_1
       (.I0(inputs_offset_AM_on_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_offset_AM_on_V_ap_vld_preg),
        .O(inputs_offset_AM_on_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_offset_AM_on_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_offset_AM_on_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_offset_AM_on_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[0]),
        .Q(inputs_offset_AM_on_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[10]),
        .Q(inputs_offset_AM_on_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[11]),
        .Q(inputs_offset_AM_on_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[12]),
        .Q(inputs_offset_AM_on_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[13]),
        .Q(inputs_offset_AM_on_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[14]),
        .Q(inputs_offset_AM_on_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[15]),
        .Q(inputs_offset_AM_on_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[16]),
        .Q(inputs_offset_AM_on_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[17]),
        .Q(inputs_offset_AM_on_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[18]),
        .Q(inputs_offset_AM_on_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[19]),
        .Q(inputs_offset_AM_on_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[1]),
        .Q(inputs_offset_AM_on_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[20]),
        .Q(inputs_offset_AM_on_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[21]),
        .Q(inputs_offset_AM_on_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[22]),
        .Q(inputs_offset_AM_on_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[23]),
        .Q(inputs_offset_AM_on_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[24]),
        .Q(inputs_offset_AM_on_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[25]),
        .Q(inputs_offset_AM_on_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[26]),
        .Q(inputs_offset_AM_on_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[27]),
        .Q(inputs_offset_AM_on_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[28]),
        .Q(inputs_offset_AM_on_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[29]),
        .Q(inputs_offset_AM_on_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[2]),
        .Q(inputs_offset_AM_on_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[30]),
        .Q(inputs_offset_AM_on_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[31]),
        .Q(inputs_offset_AM_on_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[32]),
        .Q(inputs_offset_AM_on_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[33]),
        .Q(inputs_offset_AM_on_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[34]),
        .Q(inputs_offset_AM_on_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[35]),
        .Q(inputs_offset_AM_on_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[36]),
        .Q(inputs_offset_AM_on_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[37]),
        .Q(inputs_offset_AM_on_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[38]),
        .Q(inputs_offset_AM_on_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[39]),
        .Q(inputs_offset_AM_on_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[3]),
        .Q(inputs_offset_AM_on_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[40]),
        .Q(inputs_offset_AM_on_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[41]),
        .Q(inputs_offset_AM_on_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[42]),
        .Q(inputs_offset_AM_on_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[43]),
        .Q(inputs_offset_AM_on_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[44]),
        .Q(inputs_offset_AM_on_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[45]),
        .Q(inputs_offset_AM_on_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[46]),
        .Q(inputs_offset_AM_on_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[47]),
        .Q(inputs_offset_AM_on_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[4]),
        .Q(inputs_offset_AM_on_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[5]),
        .Q(inputs_offset_AM_on_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[6]),
        .Q(inputs_offset_AM_on_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[7]),
        .Q(inputs_offset_AM_on_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[8]),
        .Q(inputs_offset_AM_on_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_offset_AM_on_V_ap_vld),
        .D(inputs_offset_AM_on_V[9]),
        .Q(inputs_offset_AM_on_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[0]),
        .Q(inputs_offset_AM_on_s_reg_1442[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[10]),
        .Q(inputs_offset_AM_on_s_reg_1442[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[11]),
        .Q(inputs_offset_AM_on_s_reg_1442[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[12]),
        .Q(inputs_offset_AM_on_s_reg_1442[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[13]),
        .Q(inputs_offset_AM_on_s_reg_1442[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[14]),
        .Q(inputs_offset_AM_on_s_reg_1442[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[15]),
        .Q(inputs_offset_AM_on_s_reg_1442[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[16]),
        .Q(inputs_offset_AM_on_s_reg_1442[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[17]),
        .Q(inputs_offset_AM_on_s_reg_1442[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[18]),
        .Q(inputs_offset_AM_on_s_reg_1442[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[19]),
        .Q(inputs_offset_AM_on_s_reg_1442[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[1]),
        .Q(inputs_offset_AM_on_s_reg_1442[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[20]),
        .Q(inputs_offset_AM_on_s_reg_1442[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[21]),
        .Q(inputs_offset_AM_on_s_reg_1442[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[22]),
        .Q(inputs_offset_AM_on_s_reg_1442[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[23]),
        .Q(inputs_offset_AM_on_s_reg_1442[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[24]),
        .Q(inputs_offset_AM_on_s_reg_1442[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[25]),
        .Q(inputs_offset_AM_on_s_reg_1442[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[26]),
        .Q(inputs_offset_AM_on_s_reg_1442[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[27]),
        .Q(inputs_offset_AM_on_s_reg_1442[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[28]),
        .Q(inputs_offset_AM_on_s_reg_1442[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[29]),
        .Q(inputs_offset_AM_on_s_reg_1442[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[2]),
        .Q(inputs_offset_AM_on_s_reg_1442[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[30]),
        .Q(inputs_offset_AM_on_s_reg_1442[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[31]),
        .Q(inputs_offset_AM_on_s_reg_1442[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[32]),
        .Q(inputs_offset_AM_on_s_reg_1442[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[33]),
        .Q(inputs_offset_AM_on_s_reg_1442[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[34]),
        .Q(inputs_offset_AM_on_s_reg_1442[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[35]),
        .Q(inputs_offset_AM_on_s_reg_1442[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[36]),
        .Q(inputs_offset_AM_on_s_reg_1442[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[37]),
        .Q(inputs_offset_AM_on_s_reg_1442[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[38]),
        .Q(inputs_offset_AM_on_s_reg_1442[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[39]),
        .Q(inputs_offset_AM_on_s_reg_1442[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[3]),
        .Q(inputs_offset_AM_on_s_reg_1442[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[40]),
        .Q(inputs_offset_AM_on_s_reg_1442[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[41]),
        .Q(inputs_offset_AM_on_s_reg_1442[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[42]),
        .Q(inputs_offset_AM_on_s_reg_1442[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[43]),
        .Q(inputs_offset_AM_on_s_reg_1442[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[44]),
        .Q(inputs_offset_AM_on_s_reg_1442[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[45]),
        .Q(inputs_offset_AM_on_s_reg_1442[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[46]),
        .Q(inputs_offset_AM_on_s_reg_1442[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[47]),
        .Q(inputs_offset_AM_on_s_reg_1442[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[4]),
        .Q(inputs_offset_AM_on_s_reg_1442[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[5]),
        .Q(inputs_offset_AM_on_s_reg_1442[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[6]),
        .Q(inputs_offset_AM_on_s_reg_1442[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[7]),
        .Q(inputs_offset_AM_on_s_reg_1442[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[8]),
        .Q(inputs_offset_AM_on_s_reg_1442[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_AM_on_s_reg_1442_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_AM_on_V_preg[9]),
        .Q(inputs_offset_AM_on_s_reg_1442[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_offset_FSK_V_ap_vld_preg_i_1
       (.I0(inputs_offset_FSK_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_offset_FSK_V_ap_vld_preg),
        .O(inputs_offset_FSK_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_offset_FSK_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_offset_FSK_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_offset_FSK_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[0]),
        .Q(inputs_offset_FSK_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[10]),
        .Q(inputs_offset_FSK_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[11]),
        .Q(inputs_offset_FSK_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[12]),
        .Q(inputs_offset_FSK_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[13]),
        .Q(inputs_offset_FSK_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[14]),
        .Q(inputs_offset_FSK_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[15]),
        .Q(inputs_offset_FSK_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[16]),
        .Q(inputs_offset_FSK_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[17]),
        .Q(inputs_offset_FSK_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[18]),
        .Q(inputs_offset_FSK_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[19]),
        .Q(inputs_offset_FSK_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[1]),
        .Q(inputs_offset_FSK_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[20]),
        .Q(inputs_offset_FSK_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[21]),
        .Q(inputs_offset_FSK_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[22]),
        .Q(inputs_offset_FSK_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[23]),
        .Q(inputs_offset_FSK_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[24]),
        .Q(inputs_offset_FSK_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[25]),
        .Q(inputs_offset_FSK_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[26]),
        .Q(inputs_offset_FSK_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[27]),
        .Q(inputs_offset_FSK_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[28]),
        .Q(inputs_offset_FSK_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[29]),
        .Q(inputs_offset_FSK_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[2]),
        .Q(inputs_offset_FSK_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[30]),
        .Q(inputs_offset_FSK_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[31]),
        .Q(inputs_offset_FSK_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[32]),
        .Q(inputs_offset_FSK_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[33]),
        .Q(inputs_offset_FSK_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[34]),
        .Q(inputs_offset_FSK_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[35]),
        .Q(inputs_offset_FSK_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[36]),
        .Q(inputs_offset_FSK_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[37]),
        .Q(inputs_offset_FSK_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[38]),
        .Q(inputs_offset_FSK_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[39]),
        .Q(inputs_offset_FSK_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[3]),
        .Q(inputs_offset_FSK_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[40]),
        .Q(inputs_offset_FSK_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[41]),
        .Q(inputs_offset_FSK_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[42]),
        .Q(inputs_offset_FSK_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[43]),
        .Q(inputs_offset_FSK_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[44]),
        .Q(inputs_offset_FSK_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[45]),
        .Q(inputs_offset_FSK_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[46]),
        .Q(inputs_offset_FSK_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[47]),
        .Q(inputs_offset_FSK_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[4]),
        .Q(inputs_offset_FSK_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[5]),
        .Q(inputs_offset_FSK_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[6]),
        .Q(inputs_offset_FSK_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[7]),
        .Q(inputs_offset_FSK_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[8]),
        .Q(inputs_offset_FSK_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_offset_FSK_V_ap_vld),
        .D(inputs_offset_FSK_V[9]),
        .Q(inputs_offset_FSK_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[0]),
        .Q(inputs_offset_FSK_V_s_reg_1447[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[10]),
        .Q(inputs_offset_FSK_V_s_reg_1447[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[11]),
        .Q(inputs_offset_FSK_V_s_reg_1447[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[12]),
        .Q(inputs_offset_FSK_V_s_reg_1447[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[13]),
        .Q(inputs_offset_FSK_V_s_reg_1447[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[14]),
        .Q(inputs_offset_FSK_V_s_reg_1447[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[15]),
        .Q(inputs_offset_FSK_V_s_reg_1447[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[16]),
        .Q(inputs_offset_FSK_V_s_reg_1447[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[17]),
        .Q(inputs_offset_FSK_V_s_reg_1447[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[18]),
        .Q(inputs_offset_FSK_V_s_reg_1447[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[19]),
        .Q(inputs_offset_FSK_V_s_reg_1447[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[1]),
        .Q(inputs_offset_FSK_V_s_reg_1447[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[20]),
        .Q(inputs_offset_FSK_V_s_reg_1447[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[21]),
        .Q(inputs_offset_FSK_V_s_reg_1447[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[22]),
        .Q(inputs_offset_FSK_V_s_reg_1447[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[23]),
        .Q(inputs_offset_FSK_V_s_reg_1447[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[24]),
        .Q(inputs_offset_FSK_V_s_reg_1447[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[25]),
        .Q(inputs_offset_FSK_V_s_reg_1447[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[26]),
        .Q(inputs_offset_FSK_V_s_reg_1447[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[27]),
        .Q(inputs_offset_FSK_V_s_reg_1447[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[28]),
        .Q(inputs_offset_FSK_V_s_reg_1447[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[29]),
        .Q(inputs_offset_FSK_V_s_reg_1447[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[2]),
        .Q(inputs_offset_FSK_V_s_reg_1447[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[30]),
        .Q(inputs_offset_FSK_V_s_reg_1447[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[31]),
        .Q(inputs_offset_FSK_V_s_reg_1447[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[32]),
        .Q(inputs_offset_FSK_V_s_reg_1447[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[33]),
        .Q(inputs_offset_FSK_V_s_reg_1447[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[34]),
        .Q(inputs_offset_FSK_V_s_reg_1447[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[35]),
        .Q(inputs_offset_FSK_V_s_reg_1447[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[36]),
        .Q(inputs_offset_FSK_V_s_reg_1447[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[37]),
        .Q(inputs_offset_FSK_V_s_reg_1447[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[38]),
        .Q(inputs_offset_FSK_V_s_reg_1447[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[39]),
        .Q(inputs_offset_FSK_V_s_reg_1447[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[3]),
        .Q(inputs_offset_FSK_V_s_reg_1447[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[40]),
        .Q(inputs_offset_FSK_V_s_reg_1447[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[41]),
        .Q(inputs_offset_FSK_V_s_reg_1447[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[42]),
        .Q(inputs_offset_FSK_V_s_reg_1447[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[43]),
        .Q(inputs_offset_FSK_V_s_reg_1447[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[44]),
        .Q(inputs_offset_FSK_V_s_reg_1447[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[45]),
        .Q(inputs_offset_FSK_V_s_reg_1447[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[46]),
        .Q(inputs_offset_FSK_V_s_reg_1447[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[47]),
        .Q(inputs_offset_FSK_V_s_reg_1447[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[4]),
        .Q(inputs_offset_FSK_V_s_reg_1447[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[5]),
        .Q(inputs_offset_FSK_V_s_reg_1447[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[6]),
        .Q(inputs_offset_FSK_V_s_reg_1447[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[7]),
        .Q(inputs_offset_FSK_V_s_reg_1447[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[8]),
        .Q(inputs_offset_FSK_V_s_reg_1447[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_FSK_V_s_reg_1447_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_FSK_V_preg[9]),
        .Q(inputs_offset_FSK_V_s_reg_1447[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_offset_V_ap_vld_preg_i_1
       (.I0(inputs_offset_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_offset_V_ap_vld_preg),
        .O(inputs_offset_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_offset_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_offset_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_offset_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[0]),
        .Q(inputs_offset_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[10]),
        .Q(inputs_offset_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[11]),
        .Q(inputs_offset_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[12]),
        .Q(inputs_offset_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[13]),
        .Q(inputs_offset_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[14]),
        .Q(inputs_offset_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[15]),
        .Q(inputs_offset_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[16]),
        .Q(inputs_offset_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[17]),
        .Q(inputs_offset_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[18]),
        .Q(inputs_offset_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[19]),
        .Q(inputs_offset_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[1]),
        .Q(inputs_offset_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[20]),
        .Q(inputs_offset_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[21]),
        .Q(inputs_offset_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[22]),
        .Q(inputs_offset_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[23]),
        .Q(inputs_offset_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[24]),
        .Q(inputs_offset_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[25]),
        .Q(inputs_offset_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[26]),
        .Q(inputs_offset_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[27]),
        .Q(inputs_offset_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[28]),
        .Q(inputs_offset_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[29]),
        .Q(inputs_offset_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[2]),
        .Q(inputs_offset_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[30]),
        .Q(inputs_offset_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[31]),
        .Q(inputs_offset_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[32]),
        .Q(inputs_offset_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[33]),
        .Q(inputs_offset_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[34]),
        .Q(inputs_offset_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[35]),
        .Q(inputs_offset_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[36]),
        .Q(inputs_offset_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[37]),
        .Q(inputs_offset_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[38]),
        .Q(inputs_offset_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[39]),
        .Q(inputs_offset_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[3]),
        .Q(inputs_offset_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[40]),
        .Q(inputs_offset_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[41]),
        .Q(inputs_offset_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[42]),
        .Q(inputs_offset_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[43]),
        .Q(inputs_offset_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[44]),
        .Q(inputs_offset_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[45]),
        .Q(inputs_offset_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[46]),
        .Q(inputs_offset_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[47]),
        .Q(inputs_offset_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[4]),
        .Q(inputs_offset_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[5]),
        .Q(inputs_offset_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[6]),
        .Q(inputs_offset_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[7]),
        .Q(inputs_offset_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[8]),
        .Q(inputs_offset_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_offset_V_ap_vld),
        .D(inputs_offset_V[9]),
        .Q(inputs_offset_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[0]),
        .Q(inputs_offset_V_read_reg_1452[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[10]),
        .Q(inputs_offset_V_read_reg_1452[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[11]),
        .Q(inputs_offset_V_read_reg_1452[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[12]),
        .Q(inputs_offset_V_read_reg_1452[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[13]),
        .Q(inputs_offset_V_read_reg_1452[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[14]),
        .Q(inputs_offset_V_read_reg_1452[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[15]),
        .Q(inputs_offset_V_read_reg_1452[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[16]),
        .Q(inputs_offset_V_read_reg_1452[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[17]),
        .Q(inputs_offset_V_read_reg_1452[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[18]),
        .Q(inputs_offset_V_read_reg_1452[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[19]),
        .Q(inputs_offset_V_read_reg_1452[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[1]),
        .Q(inputs_offset_V_read_reg_1452[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[20]),
        .Q(inputs_offset_V_read_reg_1452[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[21]),
        .Q(inputs_offset_V_read_reg_1452[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[22]),
        .Q(inputs_offset_V_read_reg_1452[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[23]),
        .Q(inputs_offset_V_read_reg_1452[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[24]),
        .Q(inputs_offset_V_read_reg_1452[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[25]),
        .Q(inputs_offset_V_read_reg_1452[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[26]),
        .Q(inputs_offset_V_read_reg_1452[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[27]),
        .Q(inputs_offset_V_read_reg_1452[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[28]),
        .Q(inputs_offset_V_read_reg_1452[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[29]),
        .Q(inputs_offset_V_read_reg_1452[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[2]),
        .Q(inputs_offset_V_read_reg_1452[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[30]),
        .Q(inputs_offset_V_read_reg_1452[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[31]),
        .Q(inputs_offset_V_read_reg_1452[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[32]),
        .Q(inputs_offset_V_read_reg_1452[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[33]),
        .Q(inputs_offset_V_read_reg_1452[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[34]),
        .Q(inputs_offset_V_read_reg_1452[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[35]),
        .Q(inputs_offset_V_read_reg_1452[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[36]),
        .Q(inputs_offset_V_read_reg_1452[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[37]),
        .Q(inputs_offset_V_read_reg_1452[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[38]),
        .Q(inputs_offset_V_read_reg_1452[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[39]),
        .Q(inputs_offset_V_read_reg_1452[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[3]),
        .Q(inputs_offset_V_read_reg_1452[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[40]),
        .Q(inputs_offset_V_read_reg_1452[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[41]),
        .Q(inputs_offset_V_read_reg_1452[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[42]),
        .Q(inputs_offset_V_read_reg_1452[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[43]),
        .Q(inputs_offset_V_read_reg_1452[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[44]),
        .Q(inputs_offset_V_read_reg_1452[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[45]),
        .Q(inputs_offset_V_read_reg_1452[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[46]),
        .Q(inputs_offset_V_read_reg_1452[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[47]),
        .Q(inputs_offset_V_read_reg_1452[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[4]),
        .Q(inputs_offset_V_read_reg_1452[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[5]),
        .Q(inputs_offset_V_read_reg_1452[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[6]),
        .Q(inputs_offset_V_read_reg_1452[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[7]),
        .Q(inputs_offset_V_read_reg_1452[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[8]),
        .Q(inputs_offset_V_read_reg_1452[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offset_V_read_reg_1452_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_offset_V_preg[9]),
        .Q(inputs_offset_V_read_reg_1452[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_phase_H1_comp_V_ap_vld_preg_i_1
       (.I0(inputs_phase_H1_comp_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_phase_H1_comp_V_ap_vld_preg),
        .O(inputs_phase_H1_comp_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_phase_H1_comp_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_phase_H1_comp_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_phase_H1_comp_V_ap_vld_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[0]),
        .Q(inputs_phase_H1_comp_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[10] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[10]),
        .Q(inputs_phase_H1_comp_V_preg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[11] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[11]),
        .Q(inputs_phase_H1_comp_V_preg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[12] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[12]),
        .Q(inputs_phase_H1_comp_V_preg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[13] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[13]),
        .Q(inputs_phase_H1_comp_V_preg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[14] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[14]),
        .Q(inputs_phase_H1_comp_V_preg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[15] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[15]),
        .Q(inputs_phase_H1_comp_V_preg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[16] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[16]),
        .Q(inputs_phase_H1_comp_V_preg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[17] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[17]),
        .Q(inputs_phase_H1_comp_V_preg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[18] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[18]),
        .Q(inputs_phase_H1_comp_V_preg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[19] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[19]),
        .Q(inputs_phase_H1_comp_V_preg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[1]),
        .Q(inputs_phase_H1_comp_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[20] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[20]),
        .Q(inputs_phase_H1_comp_V_preg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[21] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[21]),
        .Q(inputs_phase_H1_comp_V_preg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[22] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[22]),
        .Q(inputs_phase_H1_comp_V_preg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[23] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[23]),
        .Q(inputs_phase_H1_comp_V_preg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[24] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[24]),
        .Q(inputs_phase_H1_comp_V_preg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[25] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[25]),
        .Q(inputs_phase_H1_comp_V_preg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[26] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[26]),
        .Q(inputs_phase_H1_comp_V_preg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[27] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[27]),
        .Q(inputs_phase_H1_comp_V_preg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[28] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[28]),
        .Q(inputs_phase_H1_comp_V_preg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[29] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[29]),
        .Q(inputs_phase_H1_comp_V_preg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[2]),
        .Q(inputs_phase_H1_comp_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[30] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[30]),
        .Q(inputs_phase_H1_comp_V_preg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[31] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[31]),
        .Q(inputs_phase_H1_comp_V_preg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[32] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[32]),
        .Q(inputs_phase_H1_comp_V_preg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[33] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[33]),
        .Q(inputs_phase_H1_comp_V_preg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[34] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[34]),
        .Q(inputs_phase_H1_comp_V_preg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[35] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[35]),
        .Q(inputs_phase_H1_comp_V_preg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[36] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[36]),
        .Q(inputs_phase_H1_comp_V_preg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[37] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[37]),
        .Q(inputs_phase_H1_comp_V_preg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[38] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[38]),
        .Q(inputs_phase_H1_comp_V_preg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[39] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[39]),
        .Q(inputs_phase_H1_comp_V_preg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[3] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[3]),
        .Q(inputs_phase_H1_comp_V_preg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[40] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[40]),
        .Q(inputs_phase_H1_comp_V_preg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[41] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[41]),
        .Q(inputs_phase_H1_comp_V_preg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[42] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[42]),
        .Q(inputs_phase_H1_comp_V_preg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[43] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[43]),
        .Q(inputs_phase_H1_comp_V_preg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[44] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[44]),
        .Q(inputs_phase_H1_comp_V_preg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[45] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[45]),
        .Q(inputs_phase_H1_comp_V_preg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[46] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[46]),
        .Q(inputs_phase_H1_comp_V_preg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[47] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[47]),
        .Q(inputs_phase_H1_comp_V_preg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[4] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[4]),
        .Q(inputs_phase_H1_comp_V_preg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[5] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[5]),
        .Q(inputs_phase_H1_comp_V_preg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[6] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[6]),
        .Q(inputs_phase_H1_comp_V_preg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[7] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[7]),
        .Q(inputs_phase_H1_comp_V_preg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[8] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[8]),
        .Q(inputs_phase_H1_comp_V_preg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_V_preg_reg[9] 
       (.C(ap_clk),
        .CE(inputs_phase_H1_comp_V_ap_vld),
        .D(inputs_phase_H1_comp_V[9]),
        .Q(inputs_phase_H1_comp_V_preg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[0]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[10]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[11]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[12]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[13]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[14]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[15]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[16]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[17]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[18]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[19]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[1]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[20]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[21]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[22]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[23]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[24]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[25]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[26]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[27]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[28]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[29]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[2]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[30]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[31]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[32]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[33]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[34]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[35]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[36]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[37]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[38]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[39]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[3]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[40]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[41]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[42]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[43]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[44]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[45]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[46]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[47]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[4]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[5]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[6]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[7]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[8]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter2_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432[9]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[0]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[10]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[11]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[12]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[13]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[14]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[15]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[16]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[17]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[18]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[19]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[1]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[20]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[21]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[22]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[23]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[24]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[25]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[26]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[27]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[28]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[29]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[2]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[30]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[31]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[32]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[33]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[34]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[35]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[36]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[37]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[38]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[39]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[3]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[40]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[41]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[42]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[43]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[44]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[45]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[46]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[47]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[4]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[5]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[6]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[7]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[8]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_pp0_iter3_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_reg_1432_pp0_iter2_reg[9]),
        .Q(inputs_phase_H1_comp_reg_1432_pp0_iter3_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[0]),
        .Q(inputs_phase_H1_comp_reg_1432[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[10]),
        .Q(inputs_phase_H1_comp_reg_1432[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[11]),
        .Q(inputs_phase_H1_comp_reg_1432[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[12]),
        .Q(inputs_phase_H1_comp_reg_1432[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[13]),
        .Q(inputs_phase_H1_comp_reg_1432[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[14]),
        .Q(inputs_phase_H1_comp_reg_1432[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[15]),
        .Q(inputs_phase_H1_comp_reg_1432[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[16]),
        .Q(inputs_phase_H1_comp_reg_1432[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[17]),
        .Q(inputs_phase_H1_comp_reg_1432[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[18]),
        .Q(inputs_phase_H1_comp_reg_1432[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[19]),
        .Q(inputs_phase_H1_comp_reg_1432[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[1]),
        .Q(inputs_phase_H1_comp_reg_1432[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[20]),
        .Q(inputs_phase_H1_comp_reg_1432[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[21]),
        .Q(inputs_phase_H1_comp_reg_1432[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[22]),
        .Q(inputs_phase_H1_comp_reg_1432[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[23]),
        .Q(inputs_phase_H1_comp_reg_1432[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[24]),
        .Q(inputs_phase_H1_comp_reg_1432[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[25]),
        .Q(inputs_phase_H1_comp_reg_1432[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[26]),
        .Q(inputs_phase_H1_comp_reg_1432[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[27]),
        .Q(inputs_phase_H1_comp_reg_1432[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[28]),
        .Q(inputs_phase_H1_comp_reg_1432[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[29]),
        .Q(inputs_phase_H1_comp_reg_1432[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[2]),
        .Q(inputs_phase_H1_comp_reg_1432[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[30]),
        .Q(inputs_phase_H1_comp_reg_1432[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[31]),
        .Q(inputs_phase_H1_comp_reg_1432[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[32]),
        .Q(inputs_phase_H1_comp_reg_1432[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[33]),
        .Q(inputs_phase_H1_comp_reg_1432[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[34]),
        .Q(inputs_phase_H1_comp_reg_1432[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[35]),
        .Q(inputs_phase_H1_comp_reg_1432[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[36]),
        .Q(inputs_phase_H1_comp_reg_1432[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[37]),
        .Q(inputs_phase_H1_comp_reg_1432[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[38]),
        .Q(inputs_phase_H1_comp_reg_1432[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[39]),
        .Q(inputs_phase_H1_comp_reg_1432[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[3]),
        .Q(inputs_phase_H1_comp_reg_1432[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[40]),
        .Q(inputs_phase_H1_comp_reg_1432[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[41]),
        .Q(inputs_phase_H1_comp_reg_1432[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[42]),
        .Q(inputs_phase_H1_comp_reg_1432[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[43]),
        .Q(inputs_phase_H1_comp_reg_1432[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[44]),
        .Q(inputs_phase_H1_comp_reg_1432[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[45]),
        .Q(inputs_phase_H1_comp_reg_1432[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[46]),
        .Q(inputs_phase_H1_comp_reg_1432[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[47]),
        .Q(inputs_phase_H1_comp_reg_1432[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[4]),
        .Q(inputs_phase_H1_comp_reg_1432[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[5]),
        .Q(inputs_phase_H1_comp_reg_1432[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[6]),
        .Q(inputs_phase_H1_comp_reg_1432[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[7]),
        .Q(inputs_phase_H1_comp_reg_1432[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[8]),
        .Q(inputs_phase_H1_comp_reg_1432[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_phase_H1_comp_reg_1432_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_phase_H1_comp_V_preg[9]),
        .Q(inputs_phase_H1_comp_reg_1432[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_rate_V_ap_vld_preg_i_1
       (.I0(inputs_rate_V_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_rate_V_ap_vld_preg),
        .O(inputs_rate_V_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_rate_V_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_rate_V_ap_vld_preg_i_1_n_0),
        .Q(inputs_rate_V_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_rate_V_preg[0]_i_1 
       (.I0(inputs_rate_V[0]),
        .I1(inputs_rate_V_ap_vld),
        .I2(inputs_rate_V_preg[0]),
        .O(\inputs_rate_V_preg[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_rate_V_preg[1]_i_1 
       (.I0(inputs_rate_V[1]),
        .I1(inputs_rate_V_ap_vld),
        .I2(inputs_rate_V_preg[1]),
        .O(\inputs_rate_V_preg[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_rate_V_preg[2]_i_1 
       (.I0(inputs_rate_V[2]),
        .I1(inputs_rate_V_ap_vld),
        .I2(inputs_rate_V_preg[2]),
        .O(\inputs_rate_V_preg[2]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_rate_V_preg[0]_i_1_n_0 ),
        .Q(inputs_rate_V_preg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_preg_reg[1] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_rate_V_preg[1]_i_1_n_0 ),
        .Q(inputs_rate_V_preg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_preg_reg[2] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_rate_V_preg[2]_i_1_n_0 ),
        .Q(inputs_rate_V_preg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_read_reg_1426_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_rate_V_preg[0]),
        .Q(inputs_rate_V_read_reg_1426[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_read_reg_1426_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_rate_V_preg[1]),
        .Q(inputs_rate_V_read_reg_1426[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_V_read_reg_1426_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_rate_V_preg[2]),
        .Q(inputs_rate_V_read_reg_1426[2]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_reset_FSK_ap_vld_preg_i_1
       (.I0(inputs_reset_FSK_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_reset_FSK_ap_vld_preg),
        .O(inputs_reset_FSK_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_reset_FSK_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_reset_FSK_ap_vld_preg_i_1_n_0),
        .Q(inputs_reset_FSK_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_reset_FSK_preg[0]_i_1 
       (.I0(inputs_reset_FSK),
        .I1(inputs_reset_FSK_ap_vld),
        .I2(inputs_reset_FSK_preg),
        .O(\inputs_reset_FSK_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_reset_FSK_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_reset_FSK_preg[0]_i_1_n_0 ),
        .Q(inputs_reset_FSK_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_reset_FSK_rea_reg_1409_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_reset_FSK_preg),
        .Q(inputs_reset_FSK_rea_reg_1409),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_reset_NCO_ap_vld_preg_i_1
       (.I0(inputs_reset_NCO_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_reset_NCO_ap_vld_preg),
        .O(inputs_reset_NCO_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_reset_NCO_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_reset_NCO_ap_vld_preg_i_1_n_0),
        .Q(inputs_reset_NCO_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_reset_NCO_preg[0]_i_1 
       (.I0(inputs_reset_NCO),
        .I1(inputs_reset_NCO_ap_vld),
        .I2(inputs_reset_NCO_preg),
        .O(\inputs_reset_NCO_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_reset_NCO_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_reset_NCO_preg[0]_i_1_n_0 ),
        .Q(inputs_reset_NCO_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_reset_NCO_rea_reg_1398_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_reset_NCO_preg),
        .Q(inputs_reset_NCO_rea_reg_1398),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_reset_slip_ap_vld_preg_i_1
       (.I0(inputs_reset_slip_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_reset_slip_ap_vld_preg),
        .O(inputs_reset_slip_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_reset_slip_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_reset_slip_ap_vld_preg_i_1_n_0),
        .Q(inputs_reset_slip_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_reset_slip_preg[0]_i_1 
       (.I0(inputs_reset_slip),
        .I1(inputs_reset_slip_ap_vld),
        .I2(inputs_reset_slip_preg),
        .O(\inputs_reset_slip_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_reset_slip_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_reset_slip_preg[0]_i_1_n_0 ),
        .Q(inputs_reset_slip_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_reset_slip_re_reg_1403_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_reset_slip_preg),
        .Q(inputs_reset_slip_re_reg_1403),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_slip_sign_ap_vld_preg_i_1
       (.I0(inputs_slip_sign_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_slip_sign_ap_vld_preg),
        .O(inputs_slip_sign_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_slip_sign_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_slip_sign_ap_vld_preg_i_1_n_0),
        .Q(inputs_slip_sign_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_slip_sign_preg[0]_i_1 
       (.I0(inputs_slip_sign),
        .I1(inputs_slip_sign_ap_vld),
        .I2(inputs_slip_sign_preg),
        .O(\inputs_slip_sign_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_slip_sign_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_slip_sign_preg[0]_i_1_n_0 ),
        .Q(inputs_slip_sign_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    inputs_valid_ap_vld_preg_i_1
       (.I0(inputs_valid_ap_vld),
        .I1(p_Val2_4_reg_1510),
        .I2(inputs_valid_ap_vld_preg),
        .O(inputs_valid_ap_vld_preg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_valid_ap_vld_preg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(inputs_valid_ap_vld_preg_i_1_n_0),
        .Q(inputs_valid_ap_vld_preg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \inputs_valid_preg[0]_i_1 
       (.I0(inputs_valid),
        .I1(inputs_valid_ap_vld),
        .I2(inputs_valid_preg),
        .O(\inputs_valid_preg[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_preg_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\inputs_valid_preg[0]_i_1_n_0 ),
        .Q(inputs_valid_preg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_read_reg_1420_pp0_iter2_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_valid_read_reg_1420),
        .Q(inputs_valid_read_reg_1420_pp0_iter2_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_read_reg_1420_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_valid_read_reg_1420_pp0_iter2_reg),
        .Q(inputs_valid_read_reg_1420_pp0_iter3_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_read_reg_1420_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_valid_read_reg_1420_pp0_iter3_reg),
        .Q(inputs_valid_read_reg_1420_pp0_iter4_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_read_reg_1420_pp0_iter5_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_valid_read_reg_1420_pp0_iter4_reg),
        .Q(inputs_valid_read_reg_1420_pp0_iter5_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_read_reg_1420_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_valid_read_reg_1420_pp0_iter5_reg),
        .Q(inputs_valid_read_reg_1420_pp0_iter6_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_valid_read_reg_1420_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(inputs_valid_preg),
        .Q(inputs_valid_read_reg_1420),
        .R(ap_rst));
  LUT6 #(
    .INIT(64'hFFBBFCB800000000)) 
    \or_cond_reg_1520[0]_i_1 
       (.I0(inputs_current_force),
        .I1(\or_cond_reg_1520[0]_i_2_n_0 ),
        .I2(ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468),
        .I3(inputs_current_enabl_1),
        .I4(ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450),
        .I5(\or_cond_reg_1520[0]_i_3_n_0 ),
        .O(p_1_in48_out));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \or_cond_reg_1520[0]_i_2 
       (.I0(ap_enable_reg_pp0_iter2),
        .I1(inputs_valid_read_reg_1420),
        .O(\or_cond_reg_1520[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFF0000FE00)) 
    \or_cond_reg_1520[0]_i_3 
       (.I0(inputs_current_rate_s[2]),
        .I1(inputs_current_rate_s[0]),
        .I2(inputs_current_rate_s[1]),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_valid_read_reg_1420),
        .I5(\or_cond_reg_1520[0]_i_4_n_0 ),
        .O(\or_cond_reg_1520[0]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \or_cond_reg_1520[0]_i_4 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]),
        .I1(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]),
        .I2(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]),
        .O(\or_cond_reg_1520[0]_i_4_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \or_cond_reg_1520_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_1_in48_out),
        .Q(or_cond_reg_1520),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    outputs_AM_1_data_reg_reg
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(storemerge_reg_1641_pp0_iter6_reg),
        .Q(outputs_AM),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    outputs_AM_auto_on_1_data_reg_reg
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(AM_auto_on_3_reg_1571_pp0_iter6_reg),
        .Q(outputs_AM_auto_on),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[0]),
        .Q(outputs_coef_muxed_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[10]),
        .Q(outputs_coef_muxed_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[11]),
        .Q(outputs_coef_muxed_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[12]),
        .Q(outputs_coef_muxed_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[13]),
        .Q(outputs_coef_muxed_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[14]),
        .Q(outputs_coef_muxed_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[15]),
        .Q(outputs_coef_muxed_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[16]),
        .Q(outputs_coef_muxed_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[17]),
        .Q(outputs_coef_muxed_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[18]),
        .Q(outputs_coef_muxed_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[19]),
        .Q(outputs_coef_muxed_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[1]),
        .Q(outputs_coef_muxed_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[20]),
        .Q(outputs_coef_muxed_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[21]),
        .Q(outputs_coef_muxed_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[22]),
        .Q(outputs_coef_muxed_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[23]),
        .Q(outputs_coef_muxed_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[24]),
        .Q(outputs_coef_muxed_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[25]),
        .Q(outputs_coef_muxed_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[26]),
        .Q(outputs_coef_muxed_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[27]),
        .Q(outputs_coef_muxed_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[28]),
        .Q(outputs_coef_muxed_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[29]),
        .Q(outputs_coef_muxed_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[2]),
        .Q(outputs_coef_muxed_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[30]),
        .Q(outputs_coef_muxed_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[31]),
        .Q(outputs_coef_muxed_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[3]),
        .Q(outputs_coef_muxed_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[4]),
        .Q(outputs_coef_muxed_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[5]),
        .Q(outputs_coef_muxed_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[6]),
        .Q(outputs_coef_muxed_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[7]),
        .Q(outputs_coef_muxed_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[8]),
        .Q(outputs_coef_muxed_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_coef_muxed_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_current_coef_6_reg_1554_pp0_iter6_reg[9]),
        .Q(outputs_coef_muxed_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    outputs_frev_1_data_reg_reg
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(tmp_19_reg_1621_pp0_iter6_reg),
        .Q(outputs_frev),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    outputs_frev_main_1_data_reg_reg
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(tmp_20_reg_1626_pp0_iter6_reg),
        .Q(outputs_frev_main),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[0]),
        .Q(outputs_ftw_H1_muxed_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[10]),
        .Q(outputs_ftw_H1_muxed_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[11]),
        .Q(outputs_ftw_H1_muxed_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[12]),
        .Q(outputs_ftw_H1_muxed_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[13]),
        .Q(outputs_ftw_H1_muxed_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[14]),
        .Q(outputs_ftw_H1_muxed_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[15]),
        .Q(outputs_ftw_H1_muxed_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[16]),
        .Q(outputs_ftw_H1_muxed_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[17]),
        .Q(outputs_ftw_H1_muxed_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[18]),
        .Q(outputs_ftw_H1_muxed_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[19]),
        .Q(outputs_ftw_H1_muxed_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[1]),
        .Q(outputs_ftw_H1_muxed_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[20]),
        .Q(outputs_ftw_H1_muxed_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[21]),
        .Q(outputs_ftw_H1_muxed_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[22]),
        .Q(outputs_ftw_H1_muxed_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[23]),
        .Q(outputs_ftw_H1_muxed_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[24]),
        .Q(outputs_ftw_H1_muxed_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[25]),
        .Q(outputs_ftw_H1_muxed_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[26]),
        .Q(outputs_ftw_H1_muxed_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[27]),
        .Q(outputs_ftw_H1_muxed_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[28]),
        .Q(outputs_ftw_H1_muxed_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[29]),
        .Q(outputs_ftw_H1_muxed_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[2]),
        .Q(outputs_ftw_H1_muxed_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[30]),
        .Q(outputs_ftw_H1_muxed_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[31]),
        .Q(outputs_ftw_H1_muxed_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[32]),
        .Q(outputs_ftw_H1_muxed_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[33]),
        .Q(outputs_ftw_H1_muxed_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[34]),
        .Q(outputs_ftw_H1_muxed_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[35]),
        .Q(outputs_ftw_H1_muxed_V[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[36]),
        .Q(outputs_ftw_H1_muxed_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[37]),
        .Q(outputs_ftw_H1_muxed_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[38]),
        .Q(outputs_ftw_H1_muxed_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[39]),
        .Q(outputs_ftw_H1_muxed_V[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[3]),
        .Q(outputs_ftw_H1_muxed_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[40]),
        .Q(outputs_ftw_H1_muxed_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[41]),
        .Q(outputs_ftw_H1_muxed_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[42]),
        .Q(outputs_ftw_H1_muxed_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[43]),
        .Q(outputs_ftw_H1_muxed_V[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[44]),
        .Q(outputs_ftw_H1_muxed_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[45]),
        .Q(outputs_ftw_H1_muxed_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[46]),
        .Q(outputs_ftw_H1_muxed_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[47]),
        .Q(outputs_ftw_H1_muxed_V[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[4]),
        .Q(outputs_ftw_H1_muxed_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[5]),
        .Q(outputs_ftw_H1_muxed_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[6]),
        .Q(outputs_ftw_H1_muxed_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[7]),
        .Q(outputs_ftw_H1_muxed_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[8]),
        .Q(outputs_ftw_H1_muxed_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_ftw_H1_muxed_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_33_reg_1631_pp0_iter6_reg[9]),
        .Q(outputs_ftw_H1_muxed_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[0]),
        .Q(outputs_phase_H1_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[10]),
        .Q(outputs_phase_H1_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[11]),
        .Q(outputs_phase_H1_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[12]),
        .Q(outputs_phase_H1_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[13]),
        .Q(outputs_phase_H1_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[14]),
        .Q(outputs_phase_H1_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[15]),
        .Q(outputs_phase_H1_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[16]),
        .Q(outputs_phase_H1_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[17]),
        .Q(outputs_phase_H1_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[18]),
        .Q(outputs_phase_H1_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[19]),
        .Q(outputs_phase_H1_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[1]),
        .Q(outputs_phase_H1_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[20]),
        .Q(outputs_phase_H1_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[21]),
        .Q(outputs_phase_H1_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[22]),
        .Q(outputs_phase_H1_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[23]),
        .Q(outputs_phase_H1_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[24]),
        .Q(outputs_phase_H1_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[25]),
        .Q(outputs_phase_H1_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[26]),
        .Q(outputs_phase_H1_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[27]),
        .Q(outputs_phase_H1_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[28]),
        .Q(outputs_phase_H1_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[29]),
        .Q(outputs_phase_H1_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[2]),
        .Q(outputs_phase_H1_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[30]),
        .Q(outputs_phase_H1_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[31]),
        .Q(outputs_phase_H1_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[32]),
        .Q(outputs_phase_H1_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[33]),
        .Q(outputs_phase_H1_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[34]),
        .Q(outputs_phase_H1_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[35]),
        .Q(outputs_phase_H1_V[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[36]),
        .Q(outputs_phase_H1_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[37]),
        .Q(outputs_phase_H1_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[38]),
        .Q(outputs_phase_H1_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[39]),
        .Q(outputs_phase_H1_V[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[3]),
        .Q(outputs_phase_H1_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[40]),
        .Q(outputs_phase_H1_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[41]),
        .Q(outputs_phase_H1_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[42]),
        .Q(outputs_phase_H1_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[43]),
        .Q(outputs_phase_H1_V[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[44]),
        .Q(outputs_phase_H1_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[45]),
        .Q(outputs_phase_H1_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[46]),
        .Q(outputs_phase_H1_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[47]),
        .Q(outputs_phase_H1_V[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[4]),
        .Q(outputs_phase_H1_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[5]),
        .Q(outputs_phase_H1_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[6]),
        .Q(outputs_phase_H1_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[7]),
        .Q(outputs_phase_H1_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[8]),
        .Q(outputs_phase_H1_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_27_reg_1649_pp0_iter6_reg[9]),
        .Q(outputs_phase_H1_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[0]),
        .Q(outputs_phase_H1_main_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[10]),
        .Q(outputs_phase_H1_main_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[11]),
        .Q(outputs_phase_H1_main_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[12]),
        .Q(outputs_phase_H1_main_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[13]),
        .Q(outputs_phase_H1_main_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[14]),
        .Q(outputs_phase_H1_main_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[15]),
        .Q(outputs_phase_H1_main_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[16]),
        .Q(outputs_phase_H1_main_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[17]),
        .Q(outputs_phase_H1_main_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[18]),
        .Q(outputs_phase_H1_main_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[19]),
        .Q(outputs_phase_H1_main_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[1]),
        .Q(outputs_phase_H1_main_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[20]),
        .Q(outputs_phase_H1_main_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[21]),
        .Q(outputs_phase_H1_main_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[22]),
        .Q(outputs_phase_H1_main_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[23]),
        .Q(outputs_phase_H1_main_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[24]),
        .Q(outputs_phase_H1_main_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[25]),
        .Q(outputs_phase_H1_main_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[26]),
        .Q(outputs_phase_H1_main_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[27]),
        .Q(outputs_phase_H1_main_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[28]),
        .Q(outputs_phase_H1_main_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[29]),
        .Q(outputs_phase_H1_main_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[2]),
        .Q(outputs_phase_H1_main_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[30]),
        .Q(outputs_phase_H1_main_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[31]),
        .Q(outputs_phase_H1_main_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[32]),
        .Q(outputs_phase_H1_main_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[33]),
        .Q(outputs_phase_H1_main_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[34]),
        .Q(outputs_phase_H1_main_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[35]),
        .Q(outputs_phase_H1_main_V[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[36]),
        .Q(outputs_phase_H1_main_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[37]),
        .Q(outputs_phase_H1_main_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[38]),
        .Q(outputs_phase_H1_main_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[39]),
        .Q(outputs_phase_H1_main_V[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[3]),
        .Q(outputs_phase_H1_main_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[40]),
        .Q(outputs_phase_H1_main_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[41]),
        .Q(outputs_phase_H1_main_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[42]),
        .Q(outputs_phase_H1_main_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[43]),
        .Q(outputs_phase_H1_main_V[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[44]),
        .Q(outputs_phase_H1_main_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[45]),
        .Q(outputs_phase_H1_main_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[46]),
        .Q(outputs_phase_H1_main_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[47]),
        .Q(outputs_phase_H1_main_V[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[4]),
        .Q(outputs_phase_H1_main_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[5]),
        .Q(outputs_phase_H1_main_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[6]),
        .Q(outputs_phase_H1_main_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[7]),
        .Q(outputs_phase_H1_main_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[8]),
        .Q(outputs_phase_H1_main_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_main_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_13_reg_1576_pp0_iter6_reg[9]),
        .Q(outputs_phase_H1_main_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[0]),
        .Q(outputs_phase_H1_offset_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[10]),
        .Q(outputs_phase_H1_offset_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[11]),
        .Q(outputs_phase_H1_offset_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[12]),
        .Q(outputs_phase_H1_offset_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[13]),
        .Q(outputs_phase_H1_offset_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[14]),
        .Q(outputs_phase_H1_offset_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[15]),
        .Q(outputs_phase_H1_offset_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[16]),
        .Q(outputs_phase_H1_offset_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[17]),
        .Q(outputs_phase_H1_offset_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[18]),
        .Q(outputs_phase_H1_offset_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[19]),
        .Q(outputs_phase_H1_offset_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[1]),
        .Q(outputs_phase_H1_offset_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[20]),
        .Q(outputs_phase_H1_offset_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[21]),
        .Q(outputs_phase_H1_offset_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[22]),
        .Q(outputs_phase_H1_offset_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[23]),
        .Q(outputs_phase_H1_offset_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[24]),
        .Q(outputs_phase_H1_offset_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[25]),
        .Q(outputs_phase_H1_offset_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[26]),
        .Q(outputs_phase_H1_offset_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[27]),
        .Q(outputs_phase_H1_offset_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[28]),
        .Q(outputs_phase_H1_offset_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[29]),
        .Q(outputs_phase_H1_offset_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[2]),
        .Q(outputs_phase_H1_offset_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[30]),
        .Q(outputs_phase_H1_offset_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[31]),
        .Q(outputs_phase_H1_offset_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[32]),
        .Q(outputs_phase_H1_offset_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[33]),
        .Q(outputs_phase_H1_offset_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[34]),
        .Q(outputs_phase_H1_offset_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[35]),
        .Q(outputs_phase_H1_offset_V[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[36]),
        .Q(outputs_phase_H1_offset_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[37]),
        .Q(outputs_phase_H1_offset_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[38]),
        .Q(outputs_phase_H1_offset_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[39]),
        .Q(outputs_phase_H1_offset_V[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[3]),
        .Q(outputs_phase_H1_offset_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[40]),
        .Q(outputs_phase_H1_offset_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[41]),
        .Q(outputs_phase_H1_offset_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[42]),
        .Q(outputs_phase_H1_offset_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[43]),
        .Q(outputs_phase_H1_offset_V[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[44]),
        .Q(outputs_phase_H1_offset_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[45]),
        .Q(outputs_phase_H1_offset_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[46]),
        .Q(outputs_phase_H1_offset_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[47]),
        .Q(outputs_phase_H1_offset_V[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[4]),
        .Q(outputs_phase_H1_offset_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[5]),
        .Q(outputs_phase_H1_offset_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[6]),
        .Q(outputs_phase_H1_offset_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[7]),
        .Q(outputs_phase_H1_offset_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[8]),
        .Q(outputs_phase_H1_offset_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_offset_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_15_reg_1581_pp0_iter6_reg[9]),
        .Q(outputs_phase_H1_offset_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[0]),
        .Q(outputs_phase_H1_prog_offset_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[10]),
        .Q(outputs_phase_H1_prog_offset_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[11]),
        .Q(outputs_phase_H1_prog_offset_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[12]),
        .Q(outputs_phase_H1_prog_offset_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[13]),
        .Q(outputs_phase_H1_prog_offset_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[14]),
        .Q(outputs_phase_H1_prog_offset_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[15]),
        .Q(outputs_phase_H1_prog_offset_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[16]),
        .Q(outputs_phase_H1_prog_offset_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[17]),
        .Q(outputs_phase_H1_prog_offset_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[18]),
        .Q(outputs_phase_H1_prog_offset_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[19]),
        .Q(outputs_phase_H1_prog_offset_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[1]),
        .Q(outputs_phase_H1_prog_offset_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[20]),
        .Q(outputs_phase_H1_prog_offset_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[21]),
        .Q(outputs_phase_H1_prog_offset_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[22]),
        .Q(outputs_phase_H1_prog_offset_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[23]),
        .Q(outputs_phase_H1_prog_offset_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[24]),
        .Q(outputs_phase_H1_prog_offset_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[25]),
        .Q(outputs_phase_H1_prog_offset_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[26]),
        .Q(outputs_phase_H1_prog_offset_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[27]),
        .Q(outputs_phase_H1_prog_offset_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[28]),
        .Q(outputs_phase_H1_prog_offset_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[29]),
        .Q(outputs_phase_H1_prog_offset_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[2]),
        .Q(outputs_phase_H1_prog_offset_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[30]),
        .Q(outputs_phase_H1_prog_offset_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[31]),
        .Q(outputs_phase_H1_prog_offset_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[32]),
        .Q(outputs_phase_H1_prog_offset_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[33]),
        .Q(outputs_phase_H1_prog_offset_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[34]),
        .Q(outputs_phase_H1_prog_offset_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[35]),
        .Q(outputs_phase_H1_prog_offset_V[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[36]),
        .Q(outputs_phase_H1_prog_offset_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[37]),
        .Q(outputs_phase_H1_prog_offset_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[38]),
        .Q(outputs_phase_H1_prog_offset_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[39]),
        .Q(outputs_phase_H1_prog_offset_V[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[3]),
        .Q(outputs_phase_H1_prog_offset_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[40]),
        .Q(outputs_phase_H1_prog_offset_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[41]),
        .Q(outputs_phase_H1_prog_offset_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[42]),
        .Q(outputs_phase_H1_prog_offset_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[43]),
        .Q(outputs_phase_H1_prog_offset_V[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[44]),
        .Q(outputs_phase_H1_prog_offset_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[45]),
        .Q(outputs_phase_H1_prog_offset_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[46]),
        .Q(outputs_phase_H1_prog_offset_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[47]),
        .Q(outputs_phase_H1_prog_offset_V[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[4]),
        .Q(outputs_phase_H1_prog_offset_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[5]),
        .Q(outputs_phase_H1_prog_offset_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[6]),
        .Q(outputs_phase_H1_prog_offset_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[7]),
        .Q(outputs_phase_H1_prog_offset_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[8]),
        .Q(outputs_phase_H1_prog_offset_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_prog_offset_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[9]),
        .Q(outputs_phase_H1_prog_offset_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[0]),
        .Q(outputs_phase_H1_slip_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[10]),
        .Q(outputs_phase_H1_slip_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[11]),
        .Q(outputs_phase_H1_slip_V[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[12]),
        .Q(outputs_phase_H1_slip_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[13]),
        .Q(outputs_phase_H1_slip_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[14]),
        .Q(outputs_phase_H1_slip_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[15]),
        .Q(outputs_phase_H1_slip_V[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[16]),
        .Q(outputs_phase_H1_slip_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[17]),
        .Q(outputs_phase_H1_slip_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[18]),
        .Q(outputs_phase_H1_slip_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[19]),
        .Q(outputs_phase_H1_slip_V[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[1]),
        .Q(outputs_phase_H1_slip_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[20]),
        .Q(outputs_phase_H1_slip_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[21]),
        .Q(outputs_phase_H1_slip_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[22]),
        .Q(outputs_phase_H1_slip_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[23]),
        .Q(outputs_phase_H1_slip_V[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[24]),
        .Q(outputs_phase_H1_slip_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[25]),
        .Q(outputs_phase_H1_slip_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[26]),
        .Q(outputs_phase_H1_slip_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[27]),
        .Q(outputs_phase_H1_slip_V[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[28]),
        .Q(outputs_phase_H1_slip_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[29]),
        .Q(outputs_phase_H1_slip_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[2]),
        .Q(outputs_phase_H1_slip_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[30]),
        .Q(outputs_phase_H1_slip_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[31]),
        .Q(outputs_phase_H1_slip_V[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[32]),
        .Q(outputs_phase_H1_slip_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[33]),
        .Q(outputs_phase_H1_slip_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[34]),
        .Q(outputs_phase_H1_slip_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[35]),
        .Q(outputs_phase_H1_slip_V[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[36]),
        .Q(outputs_phase_H1_slip_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[37]),
        .Q(outputs_phase_H1_slip_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[38]),
        .Q(outputs_phase_H1_slip_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[39]),
        .Q(outputs_phase_H1_slip_V[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[3]),
        .Q(outputs_phase_H1_slip_V[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[40]),
        .Q(outputs_phase_H1_slip_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[41]),
        .Q(outputs_phase_H1_slip_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[42]),
        .Q(outputs_phase_H1_slip_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[43]),
        .Q(outputs_phase_H1_slip_V[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[44]),
        .Q(outputs_phase_H1_slip_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[45]),
        .Q(outputs_phase_H1_slip_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[46]),
        .Q(outputs_phase_H1_slip_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[47]),
        .Q(outputs_phase_H1_slip_V[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[4]),
        .Q(outputs_phase_H1_slip_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[5]),
        .Q(outputs_phase_H1_slip_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[6]),
        .Q(outputs_phase_H1_slip_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[7]),
        .Q(outputs_phase_H1_slip_V[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[8]),
        .Q(outputs_phase_H1_slip_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_H1_slip_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_tmp_8_reg_1515_pp0_iter6_reg[9]),
        .Q(outputs_phase_H1_slip_V[9]),
        .R(ap_rst));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[11]_i_2 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[11] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[11]),
        .O(\outputs_phase_IF_0_V_1_data_reg[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[11]_i_3 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[10] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[10]),
        .O(\outputs_phase_IF_0_V_1_data_reg[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[11]_i_4 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[9] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[9]),
        .O(\outputs_phase_IF_0_V_1_data_reg[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[11]_i_5 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[8] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[8]),
        .O(\outputs_phase_IF_0_V_1_data_reg[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[15]_i_2 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[15] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[15]),
        .O(\outputs_phase_IF_0_V_1_data_reg[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[15]_i_3 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[14] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[14]),
        .O(\outputs_phase_IF_0_V_1_data_reg[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[15]_i_4 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[13] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[13]),
        .O(\outputs_phase_IF_0_V_1_data_reg[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[15]_i_5 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[12] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[12]),
        .O(\outputs_phase_IF_0_V_1_data_reg[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[19]_i_2 
       (.I0(p_Val2_30_reg_1678_reg__1_n_103),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[19]),
        .O(\outputs_phase_IF_0_V_1_data_reg[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[19]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__1_n_104),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[18]),
        .O(\outputs_phase_IF_0_V_1_data_reg[19]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[19]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__1_n_105),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[17]),
        .O(\outputs_phase_IF_0_V_1_data_reg[19]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[19]_i_5 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[16] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[16]),
        .O(\outputs_phase_IF_0_V_1_data_reg[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[23]_i_2 
       (.I0(p_Val2_30_reg_1678_reg__1_n_99),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[23]),
        .O(\outputs_phase_IF_0_V_1_data_reg[23]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[23]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__1_n_100),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[22]),
        .O(\outputs_phase_IF_0_V_1_data_reg[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[23]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__1_n_101),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[21]),
        .O(\outputs_phase_IF_0_V_1_data_reg[23]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[23]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__1_n_102),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[20]),
        .O(\outputs_phase_IF_0_V_1_data_reg[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[27]_i_2 
       (.I0(p_Val2_30_reg_1678_reg__1_n_95),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[27]),
        .O(\outputs_phase_IF_0_V_1_data_reg[27]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[27]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__1_n_96),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[26]),
        .O(\outputs_phase_IF_0_V_1_data_reg[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[27]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__1_n_97),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[25]),
        .O(\outputs_phase_IF_0_V_1_data_reg[27]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[27]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__1_n_98),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[24]),
        .O(\outputs_phase_IF_0_V_1_data_reg[27]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[31]_i_2 
       (.I0(p_Val2_30_reg_1678_reg__1_n_91),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[31]),
        .O(\outputs_phase_IF_0_V_1_data_reg[31]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[31]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__1_n_92),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[30]),
        .O(\outputs_phase_IF_0_V_1_data_reg[31]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[31]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__1_n_93),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[29]),
        .O(\outputs_phase_IF_0_V_1_data_reg[31]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[31]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__1_n_94),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[28]),
        .O(\outputs_phase_IF_0_V_1_data_reg[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[35]_i_2 
       (.I0(p_Val2_30_reg_1678_reg__2[35]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[35]),
        .O(\outputs_phase_IF_0_V_1_data_reg[35]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[35]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__2[34]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[34]),
        .O(\outputs_phase_IF_0_V_1_data_reg[35]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[35]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__2[33]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[33]),
        .O(\outputs_phase_IF_0_V_1_data_reg[35]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[35]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__1_n_90),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[32]),
        .O(\outputs_phase_IF_0_V_1_data_reg[35]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__2[39]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[39]),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__2[38]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[38]),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__2[37]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[37]),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_6 
       (.I0(p_Val2_30_reg_1678_reg__2[36]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[36]),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_7 
       (.I0(p_Val2_30_reg_1678_reg__1_n_86),
        .I1(p_Val2_30_reg_1678_reg_n_103),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_8 
       (.I0(p_Val2_30_reg_1678_reg__1_n_87),
        .I1(p_Val2_30_reg_1678_reg_n_104),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[39]_i_9 
       (.I0(p_Val2_30_reg_1678_reg__1_n_88),
        .I1(p_Val2_30_reg_1678_reg_n_105),
        .O(\outputs_phase_IF_0_V_1_data_reg[39]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[3]_i_2 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[3] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[3]),
        .O(\outputs_phase_IF_0_V_1_data_reg[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[3]_i_3 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[2] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[2]),
        .O(\outputs_phase_IF_0_V_1_data_reg[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[3]_i_4 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[1] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[1]),
        .O(\outputs_phase_IF_0_V_1_data_reg[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[3]_i_5 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[0] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[0]),
        .O(\outputs_phase_IF_0_V_1_data_reg[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_10 
       (.I0(p_Val2_30_reg_1678_reg__1_n_85),
        .I1(p_Val2_30_reg_1678_reg_n_102),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_3 
       (.I0(p_Val2_30_reg_1678_reg__2[43]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[43]),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_4 
       (.I0(p_Val2_30_reg_1678_reg__2[42]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[42]),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__2[41]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[41]),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_6 
       (.I0(p_Val2_30_reg_1678_reg__2[40]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[40]),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_7 
       (.I0(p_Val2_30_reg_1678_reg__1_n_82),
        .I1(p_Val2_30_reg_1678_reg_n_99),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_8 
       (.I0(p_Val2_30_reg_1678_reg__1_n_83),
        .I1(p_Val2_30_reg_1678_reg_n_100),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[43]_i_9 
       (.I0(p_Val2_30_reg_1678_reg__1_n_84),
        .I1(p_Val2_30_reg_1678_reg_n_101),
        .O(\outputs_phase_IF_0_V_1_data_reg[43]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_1 
       (.I0(ap_enable_reg_pp0_iter7),
        .I1(p_Val2_4_reg_1510),
        .O(outputs_phase_IF_0_V_1_data_reg0));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_10 
       (.I0(p_Val2_30_reg_1678_reg__1_n_76),
        .I1(p_Val2_30_reg_1678_reg_n_93),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_11 
       (.I0(p_Val2_30_reg_1678_reg__1_n_77),
        .I1(p_Val2_30_reg_1678_reg_n_94),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_12 
       (.I0(p_Val2_30_reg_1678_reg__1_n_78),
        .I1(p_Val2_30_reg_1678_reg_n_95),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_13 
       (.I0(p_Val2_30_reg_1678_reg__1_n_79),
        .I1(p_Val2_30_reg_1678_reg_n_96),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_14 
       (.I0(p_Val2_30_reg_1678_reg__1_n_80),
        .I1(p_Val2_30_reg_1678_reg_n_97),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_15 
       (.I0(p_Val2_30_reg_1678_reg__1_n_81),
        .I1(p_Val2_30_reg_1678_reg_n_98),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_5 
       (.I0(p_Val2_30_reg_1678_reg__2[47]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[47]),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_6 
       (.I0(p_Val2_30_reg_1678_reg__2[46]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[46]),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_7 
       (.I0(p_Val2_30_reg_1678_reg__2[45]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[45]),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_8 
       (.I0(p_Val2_30_reg_1678_reg__2[44]),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[44]),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_0_V_1_data_reg[47]_i_9 
       (.I0(p_Val2_30_reg_1678_reg__1_n_75),
        .I1(p_Val2_30_reg_1678_reg_n_92),
        .O(\outputs_phase_IF_0_V_1_data_reg[47]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[7]_i_2 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[7] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[7]),
        .O(\outputs_phase_IF_0_V_1_data_reg[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[7]_i_3 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[6] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[6]),
        .O(\outputs_phase_IF_0_V_1_data_reg[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[7]_i_4 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[5] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[5]),
        .O(\outputs_phase_IF_0_V_1_data_reg[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_0_V_1_data_reg[7]_i_5 
       (.I0(\p_Val2_30_reg_1678_reg_n_0_[4] ),
        .I1(p_Val2_38_reg_1664_pp0_iter6_reg[4]),
        .O(\outputs_phase_IF_0_V_1_data_reg[7]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[0]),
        .Q(outputs_phase_IF_0_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[10]),
        .Q(outputs_phase_IF_0_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[11]),
        .Q(outputs_phase_IF_0_V[11]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_30_reg_1678_reg_n_0_[11] ,\p_Val2_30_reg_1678_reg_n_0_[10] ,\p_Val2_30_reg_1678_reg_n_0_[9] ,\p_Val2_30_reg_1678_reg_n_0_[8] }),
        .O(p_Val2_31_fu_1382_p23_out[11:8]),
        .S({\outputs_phase_IF_0_V_1_data_reg[11]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[11]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[11]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[11]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[12]),
        .Q(outputs_phase_IF_0_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[13]),
        .Q(outputs_phase_IF_0_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[14]),
        .Q(outputs_phase_IF_0_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[15]),
        .Q(outputs_phase_IF_0_V[15]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[11]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_30_reg_1678_reg_n_0_[15] ,\p_Val2_30_reg_1678_reg_n_0_[14] ,\p_Val2_30_reg_1678_reg_n_0_[13] ,\p_Val2_30_reg_1678_reg_n_0_[12] }),
        .O(p_Val2_31_fu_1382_p23_out[15:12]),
        .S({\outputs_phase_IF_0_V_1_data_reg[15]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[15]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[15]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[15]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[16]),
        .Q(outputs_phase_IF_0_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[17]),
        .Q(outputs_phase_IF_0_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[18]),
        .Q(outputs_phase_IF_0_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[19]),
        .Q(outputs_phase_IF_0_V[19]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[15]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_103,p_Val2_30_reg_1678_reg__1_n_104,p_Val2_30_reg_1678_reg__1_n_105,\p_Val2_30_reg_1678_reg_n_0_[16] }),
        .O(p_Val2_31_fu_1382_p23_out[19:16]),
        .S({\outputs_phase_IF_0_V_1_data_reg[19]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[19]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[19]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[19]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[1]),
        .Q(outputs_phase_IF_0_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[20]),
        .Q(outputs_phase_IF_0_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[21]),
        .Q(outputs_phase_IF_0_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[22]),
        .Q(outputs_phase_IF_0_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[23]),
        .Q(outputs_phase_IF_0_V[23]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[19]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_99,p_Val2_30_reg_1678_reg__1_n_100,p_Val2_30_reg_1678_reg__1_n_101,p_Val2_30_reg_1678_reg__1_n_102}),
        .O(p_Val2_31_fu_1382_p23_out[23:20]),
        .S({\outputs_phase_IF_0_V_1_data_reg[23]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[23]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[23]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[23]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[24]),
        .Q(outputs_phase_IF_0_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[25]),
        .Q(outputs_phase_IF_0_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[26]),
        .Q(outputs_phase_IF_0_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[27]),
        .Q(outputs_phase_IF_0_V[27]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[23]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_95,p_Val2_30_reg_1678_reg__1_n_96,p_Val2_30_reg_1678_reg__1_n_97,p_Val2_30_reg_1678_reg__1_n_98}),
        .O(p_Val2_31_fu_1382_p23_out[27:24]),
        .S({\outputs_phase_IF_0_V_1_data_reg[27]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[27]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[27]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[27]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[28]),
        .Q(outputs_phase_IF_0_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[29]),
        .Q(outputs_phase_IF_0_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[2]),
        .Q(outputs_phase_IF_0_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[30]),
        .Q(outputs_phase_IF_0_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[31]),
        .Q(outputs_phase_IF_0_V[31]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[27]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_91,p_Val2_30_reg_1678_reg__1_n_92,p_Val2_30_reg_1678_reg__1_n_93,p_Val2_30_reg_1678_reg__1_n_94}),
        .O(p_Val2_31_fu_1382_p23_out[31:28]),
        .S({\outputs_phase_IF_0_V_1_data_reg[31]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[31]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[31]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[31]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[32]),
        .Q(outputs_phase_IF_0_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[33]),
        .Q(outputs_phase_IF_0_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[34]),
        .Q(outputs_phase_IF_0_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[35]),
        .Q(outputs_phase_IF_0_V[35]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[31]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__2[35:33],p_Val2_30_reg_1678_reg__1_n_90}),
        .O(p_Val2_31_fu_1382_p23_out[35:32]),
        .S({\outputs_phase_IF_0_V_1_data_reg[35]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[35]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[35]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[35]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[36]),
        .Q(outputs_phase_IF_0_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[37]),
        .Q(outputs_phase_IF_0_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[38]),
        .Q(outputs_phase_IF_0_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[39]),
        .Q(outputs_phase_IF_0_V[39]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[35]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_30_reg_1678_reg__2[39:36]),
        .O(p_Val2_31_fu_1382_p23_out[39:36]),
        .S({\outputs_phase_IF_0_V_1_data_reg[39]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[39]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[39]_i_5_n_0 ,\outputs_phase_IF_0_V_1_data_reg[39]_i_6_n_0 }));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2 
       (.CI(\<const0> ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_86,p_Val2_30_reg_1678_reg__1_n_87,p_Val2_30_reg_1678_reg__1_n_88,\<const0> }),
        .O(p_Val2_30_reg_1678_reg__2[36:33]),
        .S({\outputs_phase_IF_0_V_1_data_reg[39]_i_7_n_0 ,\outputs_phase_IF_0_V_1_data_reg[39]_i_8_n_0 ,\outputs_phase_IF_0_V_1_data_reg[39]_i_9_n_0 ,p_Val2_30_reg_1678_reg__1_n_89}));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[3]),
        .Q(outputs_phase_IF_0_V[3]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1 
       (.CI(\<const0> ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_3 }),
        .CYINIT(\<const1> ),
        .DI({\p_Val2_30_reg_1678_reg_n_0_[3] ,\p_Val2_30_reg_1678_reg_n_0_[2] ,\p_Val2_30_reg_1678_reg_n_0_[1] ,\p_Val2_30_reg_1678_reg_n_0_[0] }),
        .O(p_Val2_31_fu_1382_p23_out[3:0]),
        .S({\outputs_phase_IF_0_V_1_data_reg[3]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[3]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[3]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[3]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[40]),
        .Q(outputs_phase_IF_0_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[41]),
        .Q(outputs_phase_IF_0_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[42]),
        .Q(outputs_phase_IF_0_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[43]),
        .Q(outputs_phase_IF_0_V[43]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_30_reg_1678_reg__2[43:40]),
        .O(p_Val2_31_fu_1382_p23_out[43:40]),
        .S({\outputs_phase_IF_0_V_1_data_reg[43]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[43]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[43]_i_5_n_0 ,\outputs_phase_IF_0_V_1_data_reg[43]_i_6_n_0 }));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[39]_i_2_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_82,p_Val2_30_reg_1678_reg__1_n_83,p_Val2_30_reg_1678_reg__1_n_84,p_Val2_30_reg_1678_reg__1_n_85}),
        .O(p_Val2_30_reg_1678_reg__2[40:37]),
        .S({\outputs_phase_IF_0_V_1_data_reg[43]_i_7_n_0 ,\outputs_phase_IF_0_V_1_data_reg[43]_i_8_n_0 ,\outputs_phase_IF_0_V_1_data_reg[43]_i_9_n_0 ,\outputs_phase_IF_0_V_1_data_reg[43]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[44]),
        .Q(outputs_phase_IF_0_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[45]),
        .Q(outputs_phase_IF_0_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[46]),
        .Q(outputs_phase_IF_0_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[47]),
        .Q(outputs_phase_IF_0_V[47]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_Val2_30_reg_1678_reg__2[46:44]}),
        .O(p_Val2_31_fu_1382_p23_out[47:44]),
        .S({\outputs_phase_IF_0_V_1_data_reg[47]_i_5_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_6_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_7_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_8_n_0 }));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_3 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_3_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,p_Val2_30_reg_1678_reg__1_n_76,p_Val2_30_reg_1678_reg__1_n_77}),
        .O(p_Val2_30_reg_1678_reg__2[47:45]),
        .S({\<const0> ,\outputs_phase_IF_0_V_1_data_reg[47]_i_9_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_10_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_11_n_0 }));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[43]_i_2_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[47]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_30_reg_1678_reg__1_n_78,p_Val2_30_reg_1678_reg__1_n_79,p_Val2_30_reg_1678_reg__1_n_80,p_Val2_30_reg_1678_reg__1_n_81}),
        .O(p_Val2_30_reg_1678_reg__2[44:41]),
        .S({\outputs_phase_IF_0_V_1_data_reg[47]_i_12_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_13_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_14_n_0 ,\outputs_phase_IF_0_V_1_data_reg[47]_i_15_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[4]),
        .Q(outputs_phase_IF_0_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[5]),
        .Q(outputs_phase_IF_0_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[6]),
        .Q(outputs_phase_IF_0_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[7]),
        .Q(outputs_phase_IF_0_V[7]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1 
       (.CI(\outputs_phase_IF_0_V_1_data_reg_reg[3]_i_1_n_0 ),
        .CO({\outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_0 ,\outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_1 ,\outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_2 ,\outputs_phase_IF_0_V_1_data_reg_reg[7]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_30_reg_1678_reg_n_0_[7] ,\p_Val2_30_reg_1678_reg_n_0_[6] ,\p_Val2_30_reg_1678_reg_n_0_[5] ,\p_Val2_30_reg_1678_reg_n_0_[4] }),
        .O(p_Val2_31_fu_1382_p23_out[7:4]),
        .S({\outputs_phase_IF_0_V_1_data_reg[7]_i_2_n_0 ,\outputs_phase_IF_0_V_1_data_reg[7]_i_3_n_0 ,\outputs_phase_IF_0_V_1_data_reg[7]_i_4_n_0 ,\outputs_phase_IF_0_V_1_data_reg[7]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[8]),
        .Q(outputs_phase_IF_0_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_0_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_31_fu_1382_p23_out[9]),
        .Q(outputs_phase_IF_0_V[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h8)) 
    outputs_phase_IF_0_V_1_vld_reg_i_1
       (.I0(ap_enable_reg_pp0_iter7),
        .I1(p_Val2_4_reg_1510),
        .O(outputs_phase_IF_0_V_1_vld_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    outputs_phase_IF_0_V_1_vld_reg_reg
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(outputs_phase_IF_0_V_1_vld_reg_i_1_n_0),
        .Q(outputs_phase_IF_1_V_ap_vld),
        .R(ap_rst));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[11]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[11]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[11] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[11]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[10]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[10] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[11]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[9]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[9] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[11]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[8]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[8] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[15]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[15]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[15] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[15]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[14]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[14] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[15]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[13]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[13] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[15]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[12]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[12] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[19]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[19]),
        .I1(p_Val2_26_reg_1683_reg__1_n_103),
        .O(\outputs_phase_IF_1_V_1_data_reg[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[19]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[18]),
        .I1(p_Val2_26_reg_1683_reg__1_n_104),
        .O(\outputs_phase_IF_1_V_1_data_reg[19]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[19]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[17]),
        .I1(p_Val2_26_reg_1683_reg__1_n_105),
        .O(\outputs_phase_IF_1_V_1_data_reg[19]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[19]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[16]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[16] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[23]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[23]),
        .I1(p_Val2_26_reg_1683_reg__1_n_99),
        .O(\outputs_phase_IF_1_V_1_data_reg[23]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[23]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[22]),
        .I1(p_Val2_26_reg_1683_reg__1_n_100),
        .O(\outputs_phase_IF_1_V_1_data_reg[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[23]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[21]),
        .I1(p_Val2_26_reg_1683_reg__1_n_101),
        .O(\outputs_phase_IF_1_V_1_data_reg[23]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[23]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[20]),
        .I1(p_Val2_26_reg_1683_reg__1_n_102),
        .O(\outputs_phase_IF_1_V_1_data_reg[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[27]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[27]),
        .I1(p_Val2_26_reg_1683_reg__1_n_95),
        .O(\outputs_phase_IF_1_V_1_data_reg[27]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[27]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[26]),
        .I1(p_Val2_26_reg_1683_reg__1_n_96),
        .O(\outputs_phase_IF_1_V_1_data_reg[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[27]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[25]),
        .I1(p_Val2_26_reg_1683_reg__1_n_97),
        .O(\outputs_phase_IF_1_V_1_data_reg[27]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[27]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[24]),
        .I1(p_Val2_26_reg_1683_reg__1_n_98),
        .O(\outputs_phase_IF_1_V_1_data_reg[27]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[31]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[31]),
        .I1(p_Val2_26_reg_1683_reg__1_n_91),
        .O(\outputs_phase_IF_1_V_1_data_reg[31]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[31]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[30]),
        .I1(p_Val2_26_reg_1683_reg__1_n_92),
        .O(\outputs_phase_IF_1_V_1_data_reg[31]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[31]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[29]),
        .I1(p_Val2_26_reg_1683_reg__1_n_93),
        .O(\outputs_phase_IF_1_V_1_data_reg[31]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[31]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[28]),
        .I1(p_Val2_26_reg_1683_reg__1_n_94),
        .O(\outputs_phase_IF_1_V_1_data_reg[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[35]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[35]),
        .I1(p_Val2_26_reg_1683_reg__2[35]),
        .O(\outputs_phase_IF_1_V_1_data_reg[35]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[35]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[34]),
        .I1(p_Val2_26_reg_1683_reg__2[34]),
        .O(\outputs_phase_IF_1_V_1_data_reg[35]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[35]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[33]),
        .I1(p_Val2_26_reg_1683_reg__2[33]),
        .O(\outputs_phase_IF_1_V_1_data_reg[35]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[35]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[32]),
        .I1(p_Val2_26_reg_1683_reg__1_n_90),
        .O(\outputs_phase_IF_1_V_1_data_reg[35]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[39]),
        .I1(p_Val2_26_reg_1683_reg__2[39]),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[38]),
        .I1(p_Val2_26_reg_1683_reg__2[38]),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[37]),
        .I1(p_Val2_26_reg_1683_reg__2[37]),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[36]),
        .I1(p_Val2_26_reg_1683_reg__2[36]),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_7 
       (.I0(p_Val2_26_reg_1683_reg__1_n_86),
        .I1(p_Val2_26_reg_1683_reg_n_103),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_8 
       (.I0(p_Val2_26_reg_1683_reg__1_n_87),
        .I1(p_Val2_26_reg_1683_reg_n_104),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[39]_i_9 
       (.I0(p_Val2_26_reg_1683_reg__1_n_88),
        .I1(p_Val2_26_reg_1683_reg_n_105),
        .O(\outputs_phase_IF_1_V_1_data_reg[39]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[3]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[3]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[3] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[3]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[2]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[2] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[3]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[1]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[1] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[3]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[0]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[0] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_10 
       (.I0(p_Val2_26_reg_1683_reg__1_n_85),
        .I1(p_Val2_26_reg_1683_reg_n_102),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[43]),
        .I1(p_Val2_26_reg_1683_reg__2[43]),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[42]),
        .I1(p_Val2_26_reg_1683_reg__2[42]),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[41]),
        .I1(p_Val2_26_reg_1683_reg__2[41]),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[40]),
        .I1(p_Val2_26_reg_1683_reg__2[40]),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_7 
       (.I0(p_Val2_26_reg_1683_reg__1_n_82),
        .I1(p_Val2_26_reg_1683_reg_n_99),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_8 
       (.I0(p_Val2_26_reg_1683_reg__1_n_83),
        .I1(p_Val2_26_reg_1683_reg_n_100),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[43]_i_9 
       (.I0(p_Val2_26_reg_1683_reg__1_n_84),
        .I1(p_Val2_26_reg_1683_reg_n_101),
        .O(\outputs_phase_IF_1_V_1_data_reg[43]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_10 
       (.I0(p_Val2_26_reg_1683_reg__1_n_77),
        .I1(p_Val2_26_reg_1683_reg_n_94),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_11 
       (.I0(p_Val2_26_reg_1683_reg__1_n_78),
        .I1(p_Val2_26_reg_1683_reg_n_95),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_12 
       (.I0(p_Val2_26_reg_1683_reg__1_n_79),
        .I1(p_Val2_26_reg_1683_reg_n_96),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_13 
       (.I0(p_Val2_26_reg_1683_reg__1_n_80),
        .I1(p_Val2_26_reg_1683_reg_n_97),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_14 
       (.I0(p_Val2_26_reg_1683_reg__1_n_81),
        .I1(p_Val2_26_reg_1683_reg_n_98),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[47]),
        .I1(p_Val2_26_reg_1683_reg__2[47]),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[46]),
        .I1(p_Val2_26_reg_1683_reg__2[46]),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[45]),
        .I1(p_Val2_26_reg_1683_reg__2[45]),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[44]),
        .I1(p_Val2_26_reg_1683_reg__2[44]),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_8 
       (.I0(p_Val2_26_reg_1683_reg__1_n_75),
        .I1(p_Val2_26_reg_1683_reg_n_92),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \outputs_phase_IF_1_V_1_data_reg[47]_i_9 
       (.I0(p_Val2_26_reg_1683_reg__1_n_76),
        .I1(p_Val2_26_reg_1683_reg_n_93),
        .O(\outputs_phase_IF_1_V_1_data_reg[47]_i_9_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[7]_i_2 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[7]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[7] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[7]_i_3 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[6]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[6] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[7]_i_4 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[5]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[5] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \outputs_phase_IF_1_V_1_data_reg[7]_i_5 
       (.I0(p_Val2_39_reg_1669_pp0_iter6_reg[4]),
        .I1(\p_Val2_26_reg_1683_reg_n_0_[4] ),
        .O(\outputs_phase_IF_1_V_1_data_reg[7]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[0] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[0]),
        .Q(outputs_phase_IF_1_V[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[10] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[10]),
        .Q(outputs_phase_IF_1_V[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[11] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[11]),
        .Q(outputs_phase_IF_1_V[11]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[11:8]),
        .O(p_Val2_32_fu_1387_p22_out[11:8]),
        .S({\outputs_phase_IF_1_V_1_data_reg[11]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[11]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[11]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[11]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[12] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[12]),
        .Q(outputs_phase_IF_1_V[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[13] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[13]),
        .Q(outputs_phase_IF_1_V[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[14] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[14]),
        .Q(outputs_phase_IF_1_V[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[15] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[15]),
        .Q(outputs_phase_IF_1_V[15]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[11]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[15:12]),
        .O(p_Val2_32_fu_1387_p22_out[15:12]),
        .S({\outputs_phase_IF_1_V_1_data_reg[15]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[15]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[15]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[15]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[16] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[16]),
        .Q(outputs_phase_IF_1_V[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[17] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[17]),
        .Q(outputs_phase_IF_1_V[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[18] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[18]),
        .Q(outputs_phase_IF_1_V[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[19] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[19]),
        .Q(outputs_phase_IF_1_V[19]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[15]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[19:16]),
        .O(p_Val2_32_fu_1387_p22_out[19:16]),
        .S({\outputs_phase_IF_1_V_1_data_reg[19]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[19]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[19]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[19]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[1] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[1]),
        .Q(outputs_phase_IF_1_V[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[20] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[20]),
        .Q(outputs_phase_IF_1_V[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[21] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[21]),
        .Q(outputs_phase_IF_1_V[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[22] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[22]),
        .Q(outputs_phase_IF_1_V[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[23] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[23]),
        .Q(outputs_phase_IF_1_V[23]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[19]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[23:20]),
        .O(p_Val2_32_fu_1387_p22_out[23:20]),
        .S({\outputs_phase_IF_1_V_1_data_reg[23]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[23]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[23]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[23]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[24] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[24]),
        .Q(outputs_phase_IF_1_V[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[25] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[25]),
        .Q(outputs_phase_IF_1_V[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[26] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[26]),
        .Q(outputs_phase_IF_1_V[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[27] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[27]),
        .Q(outputs_phase_IF_1_V[27]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[23]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[27:24]),
        .O(p_Val2_32_fu_1387_p22_out[27:24]),
        .S({\outputs_phase_IF_1_V_1_data_reg[27]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[27]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[27]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[27]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[28] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[28]),
        .Q(outputs_phase_IF_1_V[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[29] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[29]),
        .Q(outputs_phase_IF_1_V[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[2] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[2]),
        .Q(outputs_phase_IF_1_V[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[30] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[30]),
        .Q(outputs_phase_IF_1_V[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[31] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[31]),
        .Q(outputs_phase_IF_1_V[31]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[27]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[31:28]),
        .O(p_Val2_32_fu_1387_p22_out[31:28]),
        .S({\outputs_phase_IF_1_V_1_data_reg[31]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[31]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[31]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[31]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[32] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[32]),
        .Q(outputs_phase_IF_1_V[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[33] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[33]),
        .Q(outputs_phase_IF_1_V[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[34] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[34]),
        .Q(outputs_phase_IF_1_V[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[35] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[35]),
        .Q(outputs_phase_IF_1_V[35]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[31]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[35:32]),
        .O(p_Val2_32_fu_1387_p22_out[35:32]),
        .S({\outputs_phase_IF_1_V_1_data_reg[35]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[35]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[35]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[35]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[36] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[36]),
        .Q(outputs_phase_IF_1_V[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[37] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[37]),
        .Q(outputs_phase_IF_1_V[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[38] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[38]),
        .Q(outputs_phase_IF_1_V[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[39] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[39]),
        .Q(outputs_phase_IF_1_V[39]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[35]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[39:36]),
        .O(p_Val2_32_fu_1387_p22_out[39:36]),
        .S({\outputs_phase_IF_1_V_1_data_reg[39]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[39]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[39]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[39]_i_5_n_0 }));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6 
       (.CI(\<const0> ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_26_reg_1683_reg__1_n_86,p_Val2_26_reg_1683_reg__1_n_87,p_Val2_26_reg_1683_reg__1_n_88,\<const0> }),
        .O(p_Val2_26_reg_1683_reg__2[36:33]),
        .S({\outputs_phase_IF_1_V_1_data_reg[39]_i_7_n_0 ,\outputs_phase_IF_1_V_1_data_reg[39]_i_8_n_0 ,\outputs_phase_IF_1_V_1_data_reg[39]_i_9_n_0 ,p_Val2_26_reg_1683_reg__1_n_89}));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[3] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[3]),
        .Q(outputs_phase_IF_1_V[3]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1 
       (.CI(\<const0> ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_3 }),
        .CYINIT(\<const1> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[3:0]),
        .O(p_Val2_32_fu_1387_p22_out[3:0]),
        .S({\outputs_phase_IF_1_V_1_data_reg[3]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[3]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[3]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[3]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[40] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[40]),
        .Q(outputs_phase_IF_1_V[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[41] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[41]),
        .Q(outputs_phase_IF_1_V[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[42] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[42]),
        .Q(outputs_phase_IF_1_V[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[43] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[43]),
        .Q(outputs_phase_IF_1_V[43]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[43:40]),
        .O(p_Val2_32_fu_1387_p22_out[43:40]),
        .S({\outputs_phase_IF_1_V_1_data_reg[43]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[43]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[43]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[43]_i_5_n_0 }));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[39]_i_6_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_26_reg_1683_reg__1_n_82,p_Val2_26_reg_1683_reg__1_n_83,p_Val2_26_reg_1683_reg__1_n_84,p_Val2_26_reg_1683_reg__1_n_85}),
        .O(p_Val2_26_reg_1683_reg__2[40:37]),
        .S({\outputs_phase_IF_1_V_1_data_reg[43]_i_7_n_0 ,\outputs_phase_IF_1_V_1_data_reg[43]_i_8_n_0 ,\outputs_phase_IF_1_V_1_data_reg[43]_i_9_n_0 ,\outputs_phase_IF_1_V_1_data_reg[43]_i_10_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[44] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[44]),
        .Q(outputs_phase_IF_1_V[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[45] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[45]),
        .Q(outputs_phase_IF_1_V[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[46] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[46]),
        .Q(outputs_phase_IF_1_V[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[47] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[47]),
        .Q(outputs_phase_IF_1_V[47]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_Val2_39_reg_1669_pp0_iter6_reg[46:44]}),
        .O(p_Val2_32_fu_1387_p22_out[47:44]),
        .S({\outputs_phase_IF_1_V_1_data_reg[47]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_5_n_0 }));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_6 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_6_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_6_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,p_Val2_26_reg_1683_reg__1_n_76,p_Val2_26_reg_1683_reg__1_n_77}),
        .O(p_Val2_26_reg_1683_reg__2[47:45]),
        .S({\<const0> ,\outputs_phase_IF_1_V_1_data_reg[47]_i_8_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_9_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_10_n_0 }));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[43]_i_6_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[47]_i_7_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_26_reg_1683_reg__1_n_78,p_Val2_26_reg_1683_reg__1_n_79,p_Val2_26_reg_1683_reg__1_n_80,p_Val2_26_reg_1683_reg__1_n_81}),
        .O(p_Val2_26_reg_1683_reg__2[44:41]),
        .S({\outputs_phase_IF_1_V_1_data_reg[47]_i_11_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_12_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_13_n_0 ,\outputs_phase_IF_1_V_1_data_reg[47]_i_14_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[4] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[4]),
        .Q(outputs_phase_IF_1_V[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[5] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[5]),
        .Q(outputs_phase_IF_1_V[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[6] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[6]),
        .Q(outputs_phase_IF_1_V[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[7] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[7]),
        .Q(outputs_phase_IF_1_V[7]),
        .R(ap_rst));
  CARRY4 \outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1 
       (.CI(\outputs_phase_IF_1_V_1_data_reg_reg[3]_i_1_n_0 ),
        .CO({\outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_0 ,\outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_1 ,\outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_2 ,\outputs_phase_IF_1_V_1_data_reg_reg[7]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_39_reg_1669_pp0_iter6_reg[7:4]),
        .O(p_Val2_32_fu_1387_p22_out[7:4]),
        .S({\outputs_phase_IF_1_V_1_data_reg[7]_i_2_n_0 ,\outputs_phase_IF_1_V_1_data_reg[7]_i_3_n_0 ,\outputs_phase_IF_1_V_1_data_reg[7]_i_4_n_0 ,\outputs_phase_IF_1_V_1_data_reg[7]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[8] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[8]),
        .Q(outputs_phase_IF_1_V[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \outputs_phase_IF_1_V_1_data_reg_reg[9] 
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(p_Val2_32_fu_1387_p22_out[9]),
        .Q(outputs_phase_IF_1_V[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    outputs_valid_1_data_reg_reg
       (.C(ap_clk),
        .CE(outputs_phase_IF_0_V_1_data_reg0),
        .D(inputs_valid_read_reg_1420_pp0_iter6_reg),
        .Q(outputs_valid),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[0] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_105),
        .Q(\p_0_out_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[0]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_105),
        .Q(\p_0_out[0]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[10] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_95),
        .Q(\p_0_out_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[10]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_95),
        .Q(\p_0_out[10]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[11] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_94),
        .Q(\p_0_out_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[11]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_94),
        .Q(\p_0_out[11]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[12] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_93),
        .Q(\p_0_out_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[12]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_93),
        .Q(\p_0_out[12]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[13] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_92),
        .Q(\p_0_out_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[13]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_92),
        .Q(\p_0_out[13]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[14] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_91),
        .Q(\p_0_out_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[14]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_91),
        .Q(\p_0_out[14]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[15] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_90),
        .Q(\p_0_out_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[15]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_90),
        .Q(\p_0_out[15]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_89),
        .Q(\p_0_out_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_89),
        .Q(\p_0_out[16]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[16]__1 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__1_n_89),
        .Q(\p_0_out[16]__1_n_0 ),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'h08)) 
    \p_0_out[16]_i_1 
       (.I0(p_Val2_4_reg_1510),
        .I1(tmp_3_reg_1602),
        .I2(inputs_current_reset_3_reg_1615),
        .O(tmp_6_reg_16360));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[1] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_104),
        .Q(\p_0_out_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[1]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_104),
        .Q(\p_0_out[1]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[2] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_103),
        .Q(\p_0_out_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[2]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_103),
        .Q(\p_0_out[2]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[3] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_102),
        .Q(\p_0_out_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[3]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_102),
        .Q(\p_0_out[3]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[4] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_101),
        .Q(\p_0_out_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[4]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_101),
        .Q(\p_0_out[4]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[5] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_100),
        .Q(\p_0_out_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[5]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_100),
        .Q(\p_0_out[5]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[6] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_99),
        .Q(\p_0_out_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[6]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_99),
        .Q(\p_0_out[6]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[7] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_98),
        .Q(\p_0_out_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[7]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_98),
        .Q(\p_0_out[7]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[8] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_97),
        .Q(\p_0_out_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[8]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_97),
        .Q(\p_0_out[8]__0_n_0 ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[9] 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2_n_96),
        .Q(\p_0_out_n_0_[9] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_0_out[9]__0 
       (.C(ap_clk),
        .CE(tmp_6_reg_16360),
        .D(p_Val2_19_fu_1151_p2__0_n_96),
        .Q(\p_0_out[9]__0_n_0 ),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 15x16 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__0
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_0_out__0_i_1_n_0,p_0_out__0_i_2_n_0,p_0_out__0_i_3_n_0,p_0_out__0_i_4_n_0,p_0_out__0_i_5_n_0,p_0_out__0_i_6_n_0,p_0_out__0_i_7_n_0,p_0_out__0_i_8_n_0,p_0_out__0_i_9_n_0,p_0_out__0_i_10_n_0,p_0_out__0_i_11_n_0,p_0_out__0_i_12_n_0,p_0_out__0_i_13_n_0,p_0_out__0_i_14_n_0,p_0_out__0_i_15_n_0}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,phase_H1_trunc_V_fu_988_p2[47:45],p_Val2_19_fu_1151_p2_i_5_n_0,phase_H1_trunc_V_fu_988_p2[43:41],p_5_in[40:34]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(tmp_6_reg_16360),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__0_n_58,p_0_out__0_n_59,p_0_out__0_n_60,p_0_out__0_n_61,p_0_out__0_n_62,p_0_out__0_n_63,p_0_out__0_n_64,p_0_out__0_n_65,p_0_out__0_n_66,p_0_out__0_n_67,p_0_out__0_n_68,p_0_out__0_n_69,p_0_out__0_n_70,p_0_out__0_n_71,p_0_out__0_n_72,p_0_out__0_n_73,p_0_out__0_n_74,p_0_out__0_n_75,p_0_out__0_n_76,p_0_out__0_n_77,p_0_out__0_n_78,p_0_out__0_n_79,p_0_out__0_n_80,p_0_out__0_n_81,p_0_out__0_n_82,p_0_out__0_n_83,p_0_out__0_n_84,p_0_out__0_n_85,p_0_out__0_n_86,p_0_out__0_n_87,p_0_out__0_n_88,p_0_out__0_n_89,p_0_out__0_n_90,p_0_out__0_n_91,p_0_out__0_n_92,p_0_out__0_n_93,p_0_out__0_n_94,p_0_out__0_n_95,p_0_out__0_n_96,p_0_out__0_n_97,p_0_out__0_n_98,p_0_out__0_n_99,p_0_out__0_n_100,p_0_out__0_n_101,p_0_out__0_n_102,p_0_out__0_n_103,p_0_out__0_n_104,p_0_out__0_n_105}),
        .PCIN({p_Val2_19_fu_1151_p2_n_106,p_Val2_19_fu_1151_p2_n_107,p_Val2_19_fu_1151_p2_n_108,p_Val2_19_fu_1151_p2_n_109,p_Val2_19_fu_1151_p2_n_110,p_Val2_19_fu_1151_p2_n_111,p_Val2_19_fu_1151_p2_n_112,p_Val2_19_fu_1151_p2_n_113,p_Val2_19_fu_1151_p2_n_114,p_Val2_19_fu_1151_p2_n_115,p_Val2_19_fu_1151_p2_n_116,p_Val2_19_fu_1151_p2_n_117,p_Val2_19_fu_1151_p2_n_118,p_Val2_19_fu_1151_p2_n_119,p_Val2_19_fu_1151_p2_n_120,p_Val2_19_fu_1151_p2_n_121,p_Val2_19_fu_1151_p2_n_122,p_Val2_19_fu_1151_p2_n_123,p_Val2_19_fu_1151_p2_n_124,p_Val2_19_fu_1151_p2_n_125,p_Val2_19_fu_1151_p2_n_126,p_Val2_19_fu_1151_p2_n_127,p_Val2_19_fu_1151_p2_n_128,p_Val2_19_fu_1151_p2_n_129,p_Val2_19_fu_1151_p2_n_130,p_Val2_19_fu_1151_p2_n_131,p_Val2_19_fu_1151_p2_n_132,p_Val2_19_fu_1151_p2_n_133,p_Val2_19_fu_1151_p2_n_134,p_Val2_19_fu_1151_p2_n_135,p_Val2_19_fu_1151_p2_n_136,p_Val2_19_fu_1151_p2_n_137,p_Val2_19_fu_1151_p2_n_138,p_Val2_19_fu_1151_p2_n_139,p_Val2_19_fu_1151_p2_n_140,p_Val2_19_fu_1151_p2_n_141,p_Val2_19_fu_1151_p2_n_142,p_Val2_19_fu_1151_p2_n_143,p_Val2_19_fu_1151_p2_n_144,p_Val2_19_fu_1151_p2_n_145,p_Val2_19_fu_1151_p2_n_146,p_Val2_19_fu_1151_p2_n_147,p_Val2_19_fu_1151_p2_n_148,p_Val2_19_fu_1151_p2_n_149,p_Val2_19_fu_1151_p2_n_150,p_Val2_19_fu_1151_p2_n_151,p_Val2_19_fu_1151_p2_n_152,p_Val2_19_fu_1151_p2_n_153}),
        .RSTA(p_Val2_19_fu_1151_p2_i_1_n_0),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_1
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[31]_i_1_n_0 ),
        .Q(p_0_out__0_i_1_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_10
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[22]_i_1_n_0 ),
        .Q(p_0_out__0_i_10_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_11
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[21]_i_1_n_0 ),
        .Q(p_0_out__0_i_11_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_12
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[20]_i_1_n_0 ),
        .Q(p_0_out__0_i_12_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_13
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[19]_i_1_n_0 ),
        .Q(p_0_out__0_i_13_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_14
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[18]_i_1_n_0 ),
        .Q(p_0_out__0_i_14_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_15
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[17]_i_1_n_0 ),
        .Q(p_0_out__0_i_15_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_2
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[30]_i_1_n_0 ),
        .Q(p_0_out__0_i_2_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_3
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[29]_i_1_n_0 ),
        .Q(p_0_out__0_i_3_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_4
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[28]_i_1_n_0 ),
        .Q(p_0_out__0_i_4_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_5
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[27]_i_1_n_0 ),
        .Q(p_0_out__0_i_5_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_6
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[26]_i_1_n_0 ),
        .Q(p_0_out__0_i_6_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_7
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[25]_i_1_n_0 ),
        .Q(p_0_out__0_i_7_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_8
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[24]_i_1_n_0 ),
        .Q(p_0_out__0_i_8_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_0_out__0_i_9
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[23]_i_1_n_0 ),
        .Q(p_0_out__0_i_9_n_0),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x16 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_5_in[33:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,p_0_out__0_i_1_n_0,p_0_out__0_i_2_n_0,p_0_out__0_i_3_n_0,p_0_out__0_i_4_n_0,p_0_out__0_i_5_n_0,p_0_out__0_i_6_n_0,p_0_out__0_i_7_n_0,p_0_out__0_i_8_n_0,p_0_out__0_i_9_n_0,p_0_out__0_i_10_n_0,p_0_out__0_i_11_n_0,p_0_out__0_i_12_n_0,p_0_out__0_i_13_n_0,p_0_out__0_i_14_n_0,p_0_out__0_i_15_n_0}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(tmp_6_reg_16360),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__2_n_58,p_0_out__2_n_59,p_0_out__2_n_60,p_0_out__2_n_61,p_0_out__2_n_62,p_0_out__2_n_63,p_0_out__2_n_64,p_0_out__2_n_65,p_0_out__2_n_66,p_0_out__2_n_67,p_0_out__2_n_68,p_0_out__2_n_69,p_0_out__2_n_70,p_0_out__2_n_71,p_0_out__2_n_72,p_0_out__2_n_73,p_0_out__2_n_74,p_0_out__2_n_75,p_0_out__2_n_76,p_0_out__2_n_77,p_0_out__2_n_78,p_0_out__2_n_79,p_0_out__2_n_80,p_0_out__2_n_81,p_0_out__2_n_82,p_0_out__2_n_83,p_0_out__2_n_84,p_0_out__2_n_85,p_0_out__2_n_86,p_0_out__2_n_87,p_0_out__2_n_88,p_0_out__2_n_89,p_0_out__2_n_90,p_0_out__2_n_91,p_0_out__2_n_92,p_0_out__2_n_93,p_0_out__2_n_94,p_0_out__2_n_95,p_0_out__2_n_96,p_0_out__2_n_97,p_0_out__2_n_98,p_0_out__2_n_99,p_0_out__2_n_100,p_0_out__2_n_101,p_0_out__2_n_102,p_0_out__2_n_103,p_0_out__2_n_104,p_0_out__2_n_105}),
        .PCIN({p_Val2_19_fu_1151_p2__0_n_106,p_Val2_19_fu_1151_p2__0_n_107,p_Val2_19_fu_1151_p2__0_n_108,p_Val2_19_fu_1151_p2__0_n_109,p_Val2_19_fu_1151_p2__0_n_110,p_Val2_19_fu_1151_p2__0_n_111,p_Val2_19_fu_1151_p2__0_n_112,p_Val2_19_fu_1151_p2__0_n_113,p_Val2_19_fu_1151_p2__0_n_114,p_Val2_19_fu_1151_p2__0_n_115,p_Val2_19_fu_1151_p2__0_n_116,p_Val2_19_fu_1151_p2__0_n_117,p_Val2_19_fu_1151_p2__0_n_118,p_Val2_19_fu_1151_p2__0_n_119,p_Val2_19_fu_1151_p2__0_n_120,p_Val2_19_fu_1151_p2__0_n_121,p_Val2_19_fu_1151_p2__0_n_122,p_Val2_19_fu_1151_p2__0_n_123,p_Val2_19_fu_1151_p2__0_n_124,p_Val2_19_fu_1151_p2__0_n_125,p_Val2_19_fu_1151_p2__0_n_126,p_Val2_19_fu_1151_p2__0_n_127,p_Val2_19_fu_1151_p2__0_n_128,p_Val2_19_fu_1151_p2__0_n_129,p_Val2_19_fu_1151_p2__0_n_130,p_Val2_19_fu_1151_p2__0_n_131,p_Val2_19_fu_1151_p2__0_n_132,p_Val2_19_fu_1151_p2__0_n_133,p_Val2_19_fu_1151_p2__0_n_134,p_Val2_19_fu_1151_p2__0_n_135,p_Val2_19_fu_1151_p2__0_n_136,p_Val2_19_fu_1151_p2__0_n_137,p_Val2_19_fu_1151_p2__0_n_138,p_Val2_19_fu_1151_p2__0_n_139,p_Val2_19_fu_1151_p2__0_n_140,p_Val2_19_fu_1151_p2__0_n_141,p_Val2_19_fu_1151_p2__0_n_142,p_Val2_19_fu_1151_p2__0_n_143,p_Val2_19_fu_1151_p2__0_n_144,p_Val2_19_fu_1151_p2__0_n_145,p_Val2_19_fu_1151_p2__0_n_146,p_Val2_19_fu_1151_p2__0_n_147,p_Val2_19_fu_1151_p2__0_n_148,p_Val2_19_fu_1151_p2__0_n_149,p_Val2_19_fu_1151_p2__0_n_150,p_Val2_19_fu_1151_p2__0_n_151,p_Val2_19_fu_1151_p2__0_n_152,p_Val2_19_fu_1151_p2__0_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(p_Val2_19_fu_1151_p2_i_1_n_0),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x16 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_0_out__3
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_5_in[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,p_0_out__0_i_1_n_0,p_0_out__0_i_2_n_0,p_0_out__0_i_3_n_0,p_0_out__0_i_4_n_0,p_0_out__0_i_5_n_0,p_0_out__0_i_6_n_0,p_0_out__0_i_7_n_0,p_0_out__0_i_8_n_0,p_0_out__0_i_9_n_0,p_0_out__0_i_10_n_0,p_0_out__0_i_11_n_0,p_0_out__0_i_12_n_0,p_0_out__0_i_13_n_0,p_0_out__0_i_14_n_0,p_0_out__0_i_15_n_0}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(tmp_6_reg_16360),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_0_out__3_n_58,p_0_out__3_n_59,p_0_out__3_n_60,p_0_out__3_n_61,p_0_out__3_n_62,p_0_out__3_n_63,p_0_out__3_n_64,p_0_out__3_n_65,p_0_out__3_n_66,p_0_out__3_n_67,p_0_out__3_n_68,p_0_out__3_n_69,p_0_out__3_n_70,p_0_out__3_n_71,p_0_out__3_n_72,p_0_out__3_n_73,p_0_out__3_n_74,p_0_out__3_n_75,p_0_out__3_n_76,p_0_out__3_n_77,p_0_out__3_n_78,p_0_out__3_n_79,p_0_out__3_n_80,p_0_out__3_n_81,p_0_out__3_n_82,p_0_out__3_n_83,p_0_out__3_n_84,p_0_out__3_n_85,p_0_out__3_n_86,p_0_out__3_n_87,p_0_out__3_n_88,p_0_out__3_n_89,p_0_out__3_n_90,p_0_out__3_n_91,p_0_out__3_n_92,p_0_out__3_n_93,p_0_out__3_n_94,p_0_out__3_n_95,p_0_out__3_n_96,p_0_out__3_n_97,p_0_out__3_n_98,p_0_out__3_n_99,p_0_out__3_n_100,p_0_out__3_n_101,p_0_out__3_n_102,p_0_out__3_n_103,p_0_out__3_n_104,p_0_out__3_n_105}),
        .PCIN({p_Val2_19_fu_1151_p2__1_n_106,p_Val2_19_fu_1151_p2__1_n_107,p_Val2_19_fu_1151_p2__1_n_108,p_Val2_19_fu_1151_p2__1_n_109,p_Val2_19_fu_1151_p2__1_n_110,p_Val2_19_fu_1151_p2__1_n_111,p_Val2_19_fu_1151_p2__1_n_112,p_Val2_19_fu_1151_p2__1_n_113,p_Val2_19_fu_1151_p2__1_n_114,p_Val2_19_fu_1151_p2__1_n_115,p_Val2_19_fu_1151_p2__1_n_116,p_Val2_19_fu_1151_p2__1_n_117,p_Val2_19_fu_1151_p2__1_n_118,p_Val2_19_fu_1151_p2__1_n_119,p_Val2_19_fu_1151_p2__1_n_120,p_Val2_19_fu_1151_p2__1_n_121,p_Val2_19_fu_1151_p2__1_n_122,p_Val2_19_fu_1151_p2__1_n_123,p_Val2_19_fu_1151_p2__1_n_124,p_Val2_19_fu_1151_p2__1_n_125,p_Val2_19_fu_1151_p2__1_n_126,p_Val2_19_fu_1151_p2__1_n_127,p_Val2_19_fu_1151_p2__1_n_128,p_Val2_19_fu_1151_p2__1_n_129,p_Val2_19_fu_1151_p2__1_n_130,p_Val2_19_fu_1151_p2__1_n_131,p_Val2_19_fu_1151_p2__1_n_132,p_Val2_19_fu_1151_p2__1_n_133,p_Val2_19_fu_1151_p2__1_n_134,p_Val2_19_fu_1151_p2__1_n_135,p_Val2_19_fu_1151_p2__1_n_136,p_Val2_19_fu_1151_p2__1_n_137,p_Val2_19_fu_1151_p2__1_n_138,p_Val2_19_fu_1151_p2__1_n_139,p_Val2_19_fu_1151_p2__1_n_140,p_Val2_19_fu_1151_p2__1_n_141,p_Val2_19_fu_1151_p2__1_n_142,p_Val2_19_fu_1151_p2__1_n_143,p_Val2_19_fu_1151_p2__1_n_144,p_Val2_19_fu_1151_p2__1_n_145,p_Val2_19_fu_1151_p2__1_n_146,p_Val2_19_fu_1151_p2__1_n_147,p_Val2_19_fu_1151_p2__1_n_148,p_Val2_19_fu_1151_p2__1_n_149,p_Val2_19_fu_1151_p2__1_n_150,p_Val2_19_fu_1151_p2__1_n_151,p_Val2_19_fu_1151_p2__1_n_152,p_Val2_19_fu_1151_p2__1_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(p_Val2_19_fu_1151_p2_i_1_n_0),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[0]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[3]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[10]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[11]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[11]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[11]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[11]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[11]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .O(\p_Val2_12_reg_1560[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[11]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .O(\p_Val2_12_reg_1560[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[11]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .O(\p_Val2_12_reg_1560[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[11]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .O(\p_Val2_12_reg_1560[11]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[12]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[15]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[13]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[15]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[14]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[15]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[15]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[15]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[15]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[15]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .O(\p_Val2_12_reg_1560[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[15]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .O(\p_Val2_12_reg_1560[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[15]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .O(\p_Val2_12_reg_1560[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[15]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .O(\p_Val2_12_reg_1560[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \p_Val2_12_reg_1560[16]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(sel0[2]),
        .I2(sel0[3]),
        .I3(sel0[5]),
        .I4(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[19]_i_2_n_7 ),
        .O(\p_Val2_12_reg_1560[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[17]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[19]_i_2_n_6 ),
        .O(\p_Val2_12_reg_1560[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \p_Val2_12_reg_1560[18]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560_reg[19]_i_2_n_5 ),
        .I2(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .O(\p_Val2_12_reg_1560[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[19]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[19]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[19]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[19]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .O(\p_Val2_12_reg_1560[19]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[19]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .O(\p_Val2_12_reg_1560[19]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[19]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .O(\p_Val2_12_reg_1560[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[19]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .O(\p_Val2_12_reg_1560[19]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[1]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[3]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[20]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[23]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[21]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[23]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[22]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[23]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[23]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[23]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[23]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[23]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .O(\p_Val2_12_reg_1560[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[23]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .O(\p_Val2_12_reg_1560[23]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[23]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .O(\p_Val2_12_reg_1560[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[23]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .O(\p_Val2_12_reg_1560[23]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    \p_Val2_12_reg_1560[24]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(sel0[2]),
        .I2(sel0[3]),
        .I3(sel0[5]),
        .I4(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[27]_i_2_n_7 ),
        .O(\p_Val2_12_reg_1560[24]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \p_Val2_12_reg_1560[24]_i_3 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(sel0[4]),
        .I2(sel0[1]),
        .I3(sel0[0]),
        .O(\p_Val2_12_reg_1560[24]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[24]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .O(\p_Val2_12_reg_1560[24]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[24]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .O(\p_Val2_12_reg_1560[24]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[24]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .O(\p_Val2_12_reg_1560[24]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[24]_i_7 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .O(\p_Val2_12_reg_1560[24]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[25]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[27]_i_2_n_6 ),
        .O(\p_Val2_12_reg_1560[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[26]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[27]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[27]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[27]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[27]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[27]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .O(\p_Val2_12_reg_1560[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[27]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .O(\p_Val2_12_reg_1560[27]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[27]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .O(\p_Val2_12_reg_1560[27]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[27]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .O(\p_Val2_12_reg_1560[27]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[28]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[31]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[29]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[31]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[2]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[3]_i_2_n_5 ),
        .O(\p_Val2_12_reg_1560[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[30]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[31]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[31]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[31]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[31]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[31]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .O(\p_Val2_12_reg_1560[31]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[31]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .O(\p_Val2_12_reg_1560[31]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[31]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .O(\p_Val2_12_reg_1560[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[31]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .O(\p_Val2_12_reg_1560[31]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[32]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[35]_i_2_n_7 ),
        .O(\p_Val2_12_reg_1560[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[33]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[35]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[34]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[35]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[35]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[35]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[35]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[35]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .O(\p_Val2_12_reg_1560[35]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[35]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .O(\p_Val2_12_reg_1560[35]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[35]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .O(\p_Val2_12_reg_1560[35]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[35]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .O(\p_Val2_12_reg_1560[35]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[36]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[39]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[37]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[39]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[38]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[39]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[39]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[39]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[39]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[39]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .O(\p_Val2_12_reg_1560[39]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[39]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .O(\p_Val2_12_reg_1560[39]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[39]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .O(\p_Val2_12_reg_1560[39]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[39]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .O(\p_Val2_12_reg_1560[39]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[3]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[3]_i_2_n_4 ),
        .O(\p_Val2_12_reg_1560[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[3]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .O(\p_Val2_12_reg_1560[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[3]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .O(\p_Val2_12_reg_1560[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[3]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .O(\p_Val2_12_reg_1560[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[3]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .O(\p_Val2_12_reg_1560[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[40]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_4_n_7 ),
        .O(\p_Val2_12_reg_1560[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[41]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_4_n_6 ),
        .O(\p_Val2_12_reg_1560[41]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_Val2_12_reg_1560[41]_i_3 
       (.I0(sel0[2]),
        .I1(sel0[3]),
        .I2(sel0[5]),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .O(\p_Val2_12_reg_1560[41]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[41]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .O(\p_Val2_12_reg_1560[41]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[41]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .O(\p_Val2_12_reg_1560[41]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[41]_i_7 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .O(\p_Val2_12_reg_1560[41]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[41]_i_8 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .O(\p_Val2_12_reg_1560[41]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[4]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[7]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[5]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[7]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[6]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[7]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_12_reg_1560[7]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[7]_i_2_n_4 ),
        .O(\p_Val2_12_reg_1560[7]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[7]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .O(\p_Val2_12_reg_1560[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[7]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .O(\p_Val2_12_reg_1560[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[7]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .O(\p_Val2_12_reg_1560[7]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \p_Val2_12_reg_1560[7]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .O(\p_Val2_12_reg_1560[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[8]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[11]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hE2)) 
    \p_Val2_12_reg_1560[9]_i_1 
       (.I0(\p_Val2_12_reg_1560_reg[11]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .O(\p_Val2_12_reg_1560[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[0]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[10]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[11]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[12]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[13]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[14]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[15]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[16]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[17]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[18]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[19]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[1]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[20]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[21]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[22]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[23]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[24]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[25]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[26]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[27]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[28]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[29]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[2]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[30]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[31]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[32]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[33]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[34]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[35]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[36]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[37]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[38]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[39]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[3]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[40]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[41]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[4]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[5]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[6]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[7]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[8]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_pp0_iter4_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_12_reg_1560[9]),
        .Q(p_Val2_12_reg_1560_pp0_iter4_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[0]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[0]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[10]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[10]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[11]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[11]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[11]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[7]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[11]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[11]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[11]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[11]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11:8]),
        .O({\p_Val2_12_reg_1560_reg[11]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[11]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[11]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[11]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[11]_i_3_n_0 ,\p_Val2_12_reg_1560[11]_i_4_n_0 ,\p_Val2_12_reg_1560[11]_i_5_n_0 ,\p_Val2_12_reg_1560[11]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[12]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[12]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[13]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[13]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[14]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[14]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[15]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[15]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[15]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[11]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[15]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[15]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[15]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[15]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15:12]),
        .O({\p_Val2_12_reg_1560_reg[15]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[15]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[15]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[15]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[15]_i_3_n_0 ,\p_Val2_12_reg_1560[15]_i_4_n_0 ,\p_Val2_12_reg_1560[15]_i_5_n_0 ,\p_Val2_12_reg_1560[15]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[16]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[16]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[17]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[17]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[18]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[18]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[19]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[19]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[19]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[15]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[19]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[19]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[19]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[19]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19:16]),
        .O({\p_Val2_12_reg_1560_reg[19]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[19]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[19]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[19]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[19]_i_3_n_0 ,\p_Val2_12_reg_1560[19]_i_4_n_0 ,\p_Val2_12_reg_1560[19]_i_5_n_0 ,\p_Val2_12_reg_1560[19]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[1]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[1]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[20]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[20]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[21]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[21]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[22]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[22]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[23]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[23]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[23]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[19]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[23]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[23]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[23]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[23]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23:20]),
        .O({\p_Val2_12_reg_1560_reg[23]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[23]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[23]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[23]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[23]_i_3_n_0 ,\p_Val2_12_reg_1560[23]_i_4_n_0 ,\p_Val2_12_reg_1560[23]_i_5_n_0 ,\p_Val2_12_reg_1560[23]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[24]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[24]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[24]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[41]_i_4_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[24]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[24]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[24]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[24]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47:44]),
        .O(sel0[5:2]),
        .S({\p_Val2_12_reg_1560[24]_i_4_n_0 ,\p_Val2_12_reg_1560[24]_i_5_n_0 ,\p_Val2_12_reg_1560[24]_i_6_n_0 ,\p_Val2_12_reg_1560[24]_i_7_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[25]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[25]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[26]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[26]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[27]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[27]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[27]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[23]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[27]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[27]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[27]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[27]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27:24]),
        .O({\p_Val2_12_reg_1560_reg[27]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[27]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[27]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[27]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[27]_i_3_n_0 ,\p_Val2_12_reg_1560[27]_i_4_n_0 ,\p_Val2_12_reg_1560[27]_i_5_n_0 ,\p_Val2_12_reg_1560[27]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[28]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[28]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[29]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[29]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[2]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[2]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[30]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[30]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[31]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[31]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[31]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[27]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[31]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[31]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[31]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[31]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31:28]),
        .O({\p_Val2_12_reg_1560_reg[31]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[31]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[31]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[31]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[31]_i_3_n_0 ,\p_Val2_12_reg_1560[31]_i_4_n_0 ,\p_Val2_12_reg_1560[31]_i_5_n_0 ,\p_Val2_12_reg_1560[31]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[32]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[32]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[33]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[33]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[34]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[34]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[35]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[35]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[35]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[31]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[35]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[35]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[35]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[35]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35:32]),
        .O({\p_Val2_12_reg_1560_reg[35]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[35]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[35]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[35]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[35]_i_3_n_0 ,\p_Val2_12_reg_1560[35]_i_4_n_0 ,\p_Val2_12_reg_1560[35]_i_5_n_0 ,\p_Val2_12_reg_1560[35]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[36]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[36]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[37]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[37]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[38]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[38]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[39]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[39]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[39]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[35]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[39]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[39]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[39]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[39]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39:36]),
        .O({\p_Val2_12_reg_1560_reg[39]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[39]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[39]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[39]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[39]_i_3_n_0 ,\p_Val2_12_reg_1560[39]_i_4_n_0 ,\p_Val2_12_reg_1560[39]_i_5_n_0 ,\p_Val2_12_reg_1560[39]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[3]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[3]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[3]_i_2 
       (.CI(\<const0> ),
        .CO({\p_Val2_12_reg_1560_reg[3]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[3]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[3]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[3]_i_2_n_3 }),
        .CYINIT(\<const1> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3:0]),
        .O({\p_Val2_12_reg_1560_reg[3]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[3]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[3]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[3]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[3]_i_3_n_0 ,\p_Val2_12_reg_1560[3]_i_4_n_0 ,\p_Val2_12_reg_1560[3]_i_5_n_0 ,\p_Val2_12_reg_1560[3]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[40]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[40]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[41]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[41]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  CARRY4 \p_Val2_12_reg_1560_reg[41]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[24]_i_2_n_0 ),
        .CO(\p_Val2_12_reg_1560_reg[41]_i_2_n_3 ),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .S({\<const0> ,\<const0> ,\<const0> ,\<const1> }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[41]_i_4 
       (.CI(\p_Val2_12_reg_1560_reg[39]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[41]_i_4_n_0 ,\p_Val2_12_reg_1560_reg[41]_i_4_n_1 ,\p_Val2_12_reg_1560_reg[41]_i_4_n_2 ,\p_Val2_12_reg_1560_reg[41]_i_4_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43:40]),
        .O({sel0[1:0],\p_Val2_12_reg_1560_reg[41]_i_4_n_6 ,\p_Val2_12_reg_1560_reg[41]_i_4_n_7 }),
        .S({\p_Val2_12_reg_1560[41]_i_5_n_0 ,\p_Val2_12_reg_1560[41]_i_6_n_0 ,\p_Val2_12_reg_1560[41]_i_7_n_0 ,\p_Val2_12_reg_1560[41]_i_8_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[4]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[4]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[5]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[5]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[6]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[6]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[7]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[7]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_12_reg_1560_reg[7]_i_2 
       (.CI(\p_Val2_12_reg_1560_reg[3]_i_2_n_0 ),
        .CO({\p_Val2_12_reg_1560_reg[7]_i_2_n_0 ,\p_Val2_12_reg_1560_reg[7]_i_2_n_1 ,\p_Val2_12_reg_1560_reg[7]_i_2_n_2 ,\p_Val2_12_reg_1560_reg[7]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7:4]),
        .O({\p_Val2_12_reg_1560_reg[7]_i_2_n_4 ,\p_Val2_12_reg_1560_reg[7]_i_2_n_5 ,\p_Val2_12_reg_1560_reg[7]_i_2_n_6 ,\p_Val2_12_reg_1560_reg[7]_i_2_n_7 }),
        .S({\p_Val2_12_reg_1560[7]_i_3_n_0 ,\p_Val2_12_reg_1560[7]_i_4_n_0 ,\p_Val2_12_reg_1560[7]_i_5_n_0 ,\p_Val2_12_reg_1560[7]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[8]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[8]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_12_reg_1560_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_12_reg_1560[9]_i_1_n_0 ),
        .Q(p_Val2_12_reg_1560[9]),
        .R(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[0]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[10]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[11]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[12]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[13]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[14]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[15]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[16]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[17]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[18]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[19]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[1]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[20]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[21]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[22]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[23]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[24]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[25]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[26]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[27]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[28]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[29]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[2]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[30]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[31]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[32]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[33]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[34]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[35]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[36]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[37]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[38]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[39]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[3]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[40]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[41]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[42]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[43]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[44]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[45]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[46]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[47]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[4]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[5]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[6]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[7]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[8]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_13_reg_1576_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_13_reg_1576_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(acc_H1_V_reg[9]),
        .Q(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_13_reg_1576_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate_n_0));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__0
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__1
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__10
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__11
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__12
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__13
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__14
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__14_n_0));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__15
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__16
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__17
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__18
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__19
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__19_n_0));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__2
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__20
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__21
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__22
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__22_n_0));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__23
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__24
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__24_n_0));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__25
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__25_n_0));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__26
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__26_n_0));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__27
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__27_n_0));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__28
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__28_n_0));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__29
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__29_n_0));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__3
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__30
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__31
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__31_n_0));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__32
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__32_n_0));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__33
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__33_n_0));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__34
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__34_n_0));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__35
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__35_n_0));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__36
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__36_n_0));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__37
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__37_n_0));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__38
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__38_n_0));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__39
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__39_n_0));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__4
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__40
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__40_n_0));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__41
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__41_n_0));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__42
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__42_n_0));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__43
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__43_n_0));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__44
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__44_n_0));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__45
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__45_n_0));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__46
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__46_n_0));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__5
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__6
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__7
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__8
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__9
       (.I0(\p_Val2_13_reg_1576_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__9_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__46_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__36_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__35_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__34_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__33_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__32_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__31_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__30_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__29_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__28_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__27_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__45_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__26_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__25_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__24_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__23_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__22_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__21_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__20_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__19_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__18_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__17_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__44_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__16_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__15_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__14_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__13_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__12_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__11_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__10_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__9_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__8_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__7_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__43_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__6_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__5_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__4_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__3_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__2_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__1_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__0_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__42_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__41_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__40_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__39_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__38_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_13_reg_1576_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_13_reg_1576_pp0_iter5_reg_reg_gate__37_n_0),
        .Q(p_Val2_13_reg_1576_pp0_iter6_reg[9]),
        .R(ap_rst));
  (* HLUTNM = "lutpair56" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[11]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[10] ),
        .I1(inputs_current_offse_1[10]),
        .I2(acc_H1_V_reg[10]),
        .O(\p_Val2_15_reg_1581[11]_i_2_n_0 ));
  (* HLUTNM = "lutpair55" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[11]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[9] ),
        .I1(inputs_current_offse_1[9]),
        .I2(acc_H1_V_reg[9]),
        .O(\p_Val2_15_reg_1581[11]_i_3_n_0 ));
  (* HLUTNM = "lutpair54" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[11]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[8] ),
        .I1(inputs_current_offse_1[8]),
        .I2(acc_H1_V_reg[8]),
        .O(\p_Val2_15_reg_1581[11]_i_4_n_0 ));
  (* HLUTNM = "lutpair53" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[11]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[7] ),
        .I1(inputs_current_offse_1[7]),
        .I2(acc_H1_V_reg[7]),
        .O(\p_Val2_15_reg_1581[11]_i_5_n_0 ));
  (* HLUTNM = "lutpair57" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[11]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[11] ),
        .I1(inputs_current_offse_1[11]),
        .I2(acc_H1_V_reg[11]),
        .I3(\p_Val2_15_reg_1581[11]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[11]_i_6_n_0 ));
  (* HLUTNM = "lutpair56" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[11]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[10] ),
        .I1(inputs_current_offse_1[10]),
        .I2(acc_H1_V_reg[10]),
        .I3(\p_Val2_15_reg_1581[11]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[11]_i_7_n_0 ));
  (* HLUTNM = "lutpair55" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[11]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[9] ),
        .I1(inputs_current_offse_1[9]),
        .I2(acc_H1_V_reg[9]),
        .I3(\p_Val2_15_reg_1581[11]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[11]_i_8_n_0 ));
  (* HLUTNM = "lutpair54" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[11]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[8] ),
        .I1(inputs_current_offse_1[8]),
        .I2(acc_H1_V_reg[8]),
        .I3(\p_Val2_15_reg_1581[11]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[11]_i_9_n_0 ));
  (* HLUTNM = "lutpair60" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[15]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[14] ),
        .I1(inputs_current_offse_1[14]),
        .I2(acc_H1_V_reg[14]),
        .O(\p_Val2_15_reg_1581[15]_i_2_n_0 ));
  (* HLUTNM = "lutpair59" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[15]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[13] ),
        .I1(inputs_current_offse_1[13]),
        .I2(acc_H1_V_reg[13]),
        .O(\p_Val2_15_reg_1581[15]_i_3_n_0 ));
  (* HLUTNM = "lutpair58" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[15]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[12] ),
        .I1(inputs_current_offse_1[12]),
        .I2(acc_H1_V_reg[12]),
        .O(\p_Val2_15_reg_1581[15]_i_4_n_0 ));
  (* HLUTNM = "lutpair57" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[15]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[11] ),
        .I1(inputs_current_offse_1[11]),
        .I2(acc_H1_V_reg[11]),
        .O(\p_Val2_15_reg_1581[15]_i_5_n_0 ));
  (* HLUTNM = "lutpair61" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[15]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[15] ),
        .I1(inputs_current_offse_1[15]),
        .I2(acc_H1_V_reg[15]),
        .I3(\p_Val2_15_reg_1581[15]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[15]_i_6_n_0 ));
  (* HLUTNM = "lutpair60" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[15]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[14] ),
        .I1(inputs_current_offse_1[14]),
        .I2(acc_H1_V_reg[14]),
        .I3(\p_Val2_15_reg_1581[15]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[15]_i_7_n_0 ));
  (* HLUTNM = "lutpair59" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[15]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[13] ),
        .I1(inputs_current_offse_1[13]),
        .I2(acc_H1_V_reg[13]),
        .I3(\p_Val2_15_reg_1581[15]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[15]_i_8_n_0 ));
  (* HLUTNM = "lutpair58" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[15]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[12] ),
        .I1(inputs_current_offse_1[12]),
        .I2(acc_H1_V_reg[12]),
        .I3(\p_Val2_15_reg_1581[15]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[15]_i_9_n_0 ));
  (* HLUTNM = "lutpair64" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[19]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[18] ),
        .I1(inputs_current_offse_1[18]),
        .I2(acc_H1_V_reg[18]),
        .O(\p_Val2_15_reg_1581[19]_i_2_n_0 ));
  (* HLUTNM = "lutpair63" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[19]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[17] ),
        .I1(inputs_current_offse_1[17]),
        .I2(acc_H1_V_reg[17]),
        .O(\p_Val2_15_reg_1581[19]_i_3_n_0 ));
  (* HLUTNM = "lutpair62" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[19]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[16] ),
        .I1(inputs_current_offse_1[16]),
        .I2(acc_H1_V_reg[16]),
        .O(\p_Val2_15_reg_1581[19]_i_4_n_0 ));
  (* HLUTNM = "lutpair61" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[19]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[15] ),
        .I1(inputs_current_offse_1[15]),
        .I2(acc_H1_V_reg[15]),
        .O(\p_Val2_15_reg_1581[19]_i_5_n_0 ));
  (* HLUTNM = "lutpair65" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[19]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[19] ),
        .I1(inputs_current_offse_1[19]),
        .I2(acc_H1_V_reg[19]),
        .I3(\p_Val2_15_reg_1581[19]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[19]_i_6_n_0 ));
  (* HLUTNM = "lutpair64" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[19]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[18] ),
        .I1(inputs_current_offse_1[18]),
        .I2(acc_H1_V_reg[18]),
        .I3(\p_Val2_15_reg_1581[19]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[19]_i_7_n_0 ));
  (* HLUTNM = "lutpair63" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[19]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[17] ),
        .I1(inputs_current_offse_1[17]),
        .I2(acc_H1_V_reg[17]),
        .I3(\p_Val2_15_reg_1581[19]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[19]_i_8_n_0 ));
  (* HLUTNM = "lutpair62" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[19]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[16] ),
        .I1(inputs_current_offse_1[16]),
        .I2(acc_H1_V_reg[16]),
        .I3(\p_Val2_15_reg_1581[19]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[19]_i_9_n_0 ));
  (* HLUTNM = "lutpair68" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[23]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[22] ),
        .I1(inputs_current_offse_1[22]),
        .I2(acc_H1_V_reg[22]),
        .O(\p_Val2_15_reg_1581[23]_i_2_n_0 ));
  (* HLUTNM = "lutpair67" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[23]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[21] ),
        .I1(inputs_current_offse_1[21]),
        .I2(acc_H1_V_reg[21]),
        .O(\p_Val2_15_reg_1581[23]_i_3_n_0 ));
  (* HLUTNM = "lutpair66" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[23]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[20] ),
        .I1(inputs_current_offse_1[20]),
        .I2(acc_H1_V_reg[20]),
        .O(\p_Val2_15_reg_1581[23]_i_4_n_0 ));
  (* HLUTNM = "lutpair65" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[23]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[19] ),
        .I1(inputs_current_offse_1[19]),
        .I2(acc_H1_V_reg[19]),
        .O(\p_Val2_15_reg_1581[23]_i_5_n_0 ));
  (* HLUTNM = "lutpair69" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[23]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[23] ),
        .I1(inputs_current_offse_1[23]),
        .I2(acc_H1_V_reg[23]),
        .I3(\p_Val2_15_reg_1581[23]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[23]_i_6_n_0 ));
  (* HLUTNM = "lutpair68" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[23]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[22] ),
        .I1(inputs_current_offse_1[22]),
        .I2(acc_H1_V_reg[22]),
        .I3(\p_Val2_15_reg_1581[23]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[23]_i_7_n_0 ));
  (* HLUTNM = "lutpair67" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[23]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[21] ),
        .I1(inputs_current_offse_1[21]),
        .I2(acc_H1_V_reg[21]),
        .I3(\p_Val2_15_reg_1581[23]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[23]_i_8_n_0 ));
  (* HLUTNM = "lutpair66" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[23]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[20] ),
        .I1(inputs_current_offse_1[20]),
        .I2(acc_H1_V_reg[20]),
        .I3(\p_Val2_15_reg_1581[23]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[23]_i_9_n_0 ));
  (* HLUTNM = "lutpair72" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[27]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[26] ),
        .I1(inputs_current_offse_1[26]),
        .I2(acc_H1_V_reg[26]),
        .O(\p_Val2_15_reg_1581[27]_i_2_n_0 ));
  (* HLUTNM = "lutpair71" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[27]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[25] ),
        .I1(inputs_current_offse_1[25]),
        .I2(acc_H1_V_reg[25]),
        .O(\p_Val2_15_reg_1581[27]_i_3_n_0 ));
  (* HLUTNM = "lutpair70" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[27]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[24] ),
        .I1(inputs_current_offse_1[24]),
        .I2(acc_H1_V_reg[24]),
        .O(\p_Val2_15_reg_1581[27]_i_4_n_0 ));
  (* HLUTNM = "lutpair69" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[27]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[23] ),
        .I1(inputs_current_offse_1[23]),
        .I2(acc_H1_V_reg[23]),
        .O(\p_Val2_15_reg_1581[27]_i_5_n_0 ));
  (* HLUTNM = "lutpair73" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[27]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[27] ),
        .I1(inputs_current_offse_1[27]),
        .I2(acc_H1_V_reg[27]),
        .I3(\p_Val2_15_reg_1581[27]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[27]_i_6_n_0 ));
  (* HLUTNM = "lutpair72" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[27]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[26] ),
        .I1(inputs_current_offse_1[26]),
        .I2(acc_H1_V_reg[26]),
        .I3(\p_Val2_15_reg_1581[27]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[27]_i_7_n_0 ));
  (* HLUTNM = "lutpair71" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[27]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[25] ),
        .I1(inputs_current_offse_1[25]),
        .I2(acc_H1_V_reg[25]),
        .I3(\p_Val2_15_reg_1581[27]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[27]_i_8_n_0 ));
  (* HLUTNM = "lutpair70" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[27]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[24] ),
        .I1(inputs_current_offse_1[24]),
        .I2(acc_H1_V_reg[24]),
        .I3(\p_Val2_15_reg_1581[27]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[27]_i_9_n_0 ));
  (* HLUTNM = "lutpair76" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[31]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[30] ),
        .I1(inputs_current_offse_1[30]),
        .I2(acc_H1_V_reg[30]),
        .O(\p_Val2_15_reg_1581[31]_i_2_n_0 ));
  (* HLUTNM = "lutpair75" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[31]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[29] ),
        .I1(inputs_current_offse_1[29]),
        .I2(acc_H1_V_reg[29]),
        .O(\p_Val2_15_reg_1581[31]_i_3_n_0 ));
  (* HLUTNM = "lutpair74" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[31]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[28] ),
        .I1(inputs_current_offse_1[28]),
        .I2(acc_H1_V_reg[28]),
        .O(\p_Val2_15_reg_1581[31]_i_4_n_0 ));
  (* HLUTNM = "lutpair73" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[31]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[27] ),
        .I1(inputs_current_offse_1[27]),
        .I2(acc_H1_V_reg[27]),
        .O(\p_Val2_15_reg_1581[31]_i_5_n_0 ));
  (* HLUTNM = "lutpair77" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[31]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[31] ),
        .I1(inputs_current_offse_1[31]),
        .I2(acc_H1_V_reg[31]),
        .I3(\p_Val2_15_reg_1581[31]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[31]_i_6_n_0 ));
  (* HLUTNM = "lutpair76" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[31]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[30] ),
        .I1(inputs_current_offse_1[30]),
        .I2(acc_H1_V_reg[30]),
        .I3(\p_Val2_15_reg_1581[31]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[31]_i_7_n_0 ));
  (* HLUTNM = "lutpair75" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[31]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[29] ),
        .I1(inputs_current_offse_1[29]),
        .I2(acc_H1_V_reg[29]),
        .I3(\p_Val2_15_reg_1581[31]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[31]_i_8_n_0 ));
  (* HLUTNM = "lutpair74" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[31]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[28] ),
        .I1(inputs_current_offse_1[28]),
        .I2(acc_H1_V_reg[28]),
        .I3(\p_Val2_15_reg_1581[31]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[31]_i_9_n_0 ));
  (* HLUTNM = "lutpair80" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[35]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[34] ),
        .I1(inputs_current_offse_1[34]),
        .I2(acc_H1_V_reg[34]),
        .O(\p_Val2_15_reg_1581[35]_i_2_n_0 ));
  (* HLUTNM = "lutpair79" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[35]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[33] ),
        .I1(inputs_current_offse_1[33]),
        .I2(acc_H1_V_reg[33]),
        .O(\p_Val2_15_reg_1581[35]_i_3_n_0 ));
  (* HLUTNM = "lutpair78" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[35]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[32] ),
        .I1(inputs_current_offse_1[32]),
        .I2(acc_H1_V_reg[32]),
        .O(\p_Val2_15_reg_1581[35]_i_4_n_0 ));
  (* HLUTNM = "lutpair77" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[35]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[31] ),
        .I1(inputs_current_offse_1[31]),
        .I2(acc_H1_V_reg[31]),
        .O(\p_Val2_15_reg_1581[35]_i_5_n_0 ));
  (* HLUTNM = "lutpair81" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[35]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[35] ),
        .I1(inputs_current_offse_1[35]),
        .I2(acc_H1_V_reg[35]),
        .I3(\p_Val2_15_reg_1581[35]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[35]_i_6_n_0 ));
  (* HLUTNM = "lutpair80" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[35]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[34] ),
        .I1(inputs_current_offse_1[34]),
        .I2(acc_H1_V_reg[34]),
        .I3(\p_Val2_15_reg_1581[35]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[35]_i_7_n_0 ));
  (* HLUTNM = "lutpair79" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[35]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[33] ),
        .I1(inputs_current_offse_1[33]),
        .I2(acc_H1_V_reg[33]),
        .I3(\p_Val2_15_reg_1581[35]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[35]_i_8_n_0 ));
  (* HLUTNM = "lutpair78" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[35]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[32] ),
        .I1(inputs_current_offse_1[32]),
        .I2(acc_H1_V_reg[32]),
        .I3(\p_Val2_15_reg_1581[35]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[35]_i_9_n_0 ));
  (* HLUTNM = "lutpair84" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[39]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[38] ),
        .I1(inputs_current_offse_1[38]),
        .I2(acc_H1_V_reg[38]),
        .O(\p_Val2_15_reg_1581[39]_i_2_n_0 ));
  (* HLUTNM = "lutpair83" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[39]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[37] ),
        .I1(inputs_current_offse_1[37]),
        .I2(acc_H1_V_reg[37]),
        .O(\p_Val2_15_reg_1581[39]_i_3_n_0 ));
  (* HLUTNM = "lutpair82" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[39]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[36] ),
        .I1(inputs_current_offse_1[36]),
        .I2(acc_H1_V_reg[36]),
        .O(\p_Val2_15_reg_1581[39]_i_4_n_0 ));
  (* HLUTNM = "lutpair81" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[39]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[35] ),
        .I1(inputs_current_offse_1[35]),
        .I2(acc_H1_V_reg[35]),
        .O(\p_Val2_15_reg_1581[39]_i_5_n_0 ));
  (* HLUTNM = "lutpair85" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[39]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[39] ),
        .I1(inputs_current_offse_1[39]),
        .I2(acc_H1_V_reg[39]),
        .I3(\p_Val2_15_reg_1581[39]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[39]_i_6_n_0 ));
  (* HLUTNM = "lutpair84" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[39]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[38] ),
        .I1(inputs_current_offse_1[38]),
        .I2(acc_H1_V_reg[38]),
        .I3(\p_Val2_15_reg_1581[39]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[39]_i_7_n_0 ));
  (* HLUTNM = "lutpair83" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[39]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[37] ),
        .I1(inputs_current_offse_1[37]),
        .I2(acc_H1_V_reg[37]),
        .I3(\p_Val2_15_reg_1581[39]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[39]_i_8_n_0 ));
  (* HLUTNM = "lutpair82" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[39]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[36] ),
        .I1(inputs_current_offse_1[36]),
        .I2(acc_H1_V_reg[36]),
        .I3(\p_Val2_15_reg_1581[39]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[39]_i_9_n_0 ));
  (* HLUTNM = "lutpair48" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[3]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[2] ),
        .I1(inputs_current_offse_1[2]),
        .I2(acc_H1_V_reg[2]),
        .O(\p_Val2_15_reg_1581[3]_i_2_n_0 ));
  (* HLUTNM = "lutpair47" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[3]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[1] ),
        .I1(inputs_current_offse_1[1]),
        .I2(acc_H1_V_reg[1]),
        .O(\p_Val2_15_reg_1581[3]_i_3_n_0 ));
  (* HLUTNM = "lutpair46" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[3]_i_4 
       (.I0(inputs_current_offse_1[0]),
        .I1(\p_Val2_4_reg_1510_reg_n_0_[0] ),
        .I2(acc_H1_V_reg[0]),
        .O(\p_Val2_15_reg_1581[3]_i_4_n_0 ));
  (* HLUTNM = "lutpair49" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[3]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[3] ),
        .I1(inputs_current_offse_1[3]),
        .I2(acc_H1_V_reg[3]),
        .I3(\p_Val2_15_reg_1581[3]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[3]_i_5_n_0 ));
  (* HLUTNM = "lutpair48" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[3]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[2] ),
        .I1(inputs_current_offse_1[2]),
        .I2(acc_H1_V_reg[2]),
        .I3(\p_Val2_15_reg_1581[3]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[3]_i_6_n_0 ));
  (* HLUTNM = "lutpair47" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[3]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[1] ),
        .I1(inputs_current_offse_1[1]),
        .I2(acc_H1_V_reg[1]),
        .I3(\p_Val2_15_reg_1581[3]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[3]_i_7_n_0 ));
  (* HLUTNM = "lutpair46" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \p_Val2_15_reg_1581[3]_i_8 
       (.I0(inputs_current_offse_1[0]),
        .I1(\p_Val2_4_reg_1510_reg_n_0_[0] ),
        .I2(acc_H1_V_reg[0]),
        .O(\p_Val2_15_reg_1581[3]_i_8_n_0 ));
  (* HLUTNM = "lutpair88" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[43]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[42] ),
        .I1(inputs_current_offse_1[42]),
        .I2(acc_H1_V_reg[42]),
        .O(\p_Val2_15_reg_1581[43]_i_2_n_0 ));
  (* HLUTNM = "lutpair87" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[43]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[41] ),
        .I1(inputs_current_offse_1[41]),
        .I2(acc_H1_V_reg[41]),
        .O(\p_Val2_15_reg_1581[43]_i_3_n_0 ));
  (* HLUTNM = "lutpair86" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[43]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[40] ),
        .I1(inputs_current_offse_1[40]),
        .I2(acc_H1_V_reg[40]),
        .O(\p_Val2_15_reg_1581[43]_i_4_n_0 ));
  (* HLUTNM = "lutpair85" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[43]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[39] ),
        .I1(inputs_current_offse_1[39]),
        .I2(acc_H1_V_reg[39]),
        .O(\p_Val2_15_reg_1581[43]_i_5_n_0 ));
  (* HLUTNM = "lutpair89" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[43]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[43] ),
        .I1(inputs_current_offse_1[43]),
        .I2(acc_H1_V_reg[43]),
        .I3(\p_Val2_15_reg_1581[43]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[43]_i_6_n_0 ));
  (* HLUTNM = "lutpair88" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[43]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[42] ),
        .I1(inputs_current_offse_1[42]),
        .I2(acc_H1_V_reg[42]),
        .I3(\p_Val2_15_reg_1581[43]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[43]_i_7_n_0 ));
  (* HLUTNM = "lutpair87" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[43]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[41] ),
        .I1(inputs_current_offse_1[41]),
        .I2(acc_H1_V_reg[41]),
        .I3(\p_Val2_15_reg_1581[43]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[43]_i_8_n_0 ));
  (* HLUTNM = "lutpair86" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[43]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[40] ),
        .I1(inputs_current_offse_1[40]),
        .I2(acc_H1_V_reg[40]),
        .I3(\p_Val2_15_reg_1581[43]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[43]_i_9_n_0 ));
  (* HLUTNM = "lutpair91" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[47]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[45] ),
        .I1(inputs_current_offse_1[45]),
        .I2(acc_H1_V_reg[45]),
        .O(\p_Val2_15_reg_1581[47]_i_2_n_0 ));
  (* HLUTNM = "lutpair90" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[47]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[44] ),
        .I1(inputs_current_offse_1[44]),
        .I2(acc_H1_V_reg[44]),
        .O(\p_Val2_15_reg_1581[47]_i_3_n_0 ));
  (* HLUTNM = "lutpair89" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[47]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[43] ),
        .I1(inputs_current_offse_1[43]),
        .I2(acc_H1_V_reg[43]),
        .O(\p_Val2_15_reg_1581[47]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h17E8E817E81717E8)) 
    \p_Val2_15_reg_1581[47]_i_5 
       (.I0(acc_H1_V_reg[46]),
        .I1(inputs_current_offse_1[46]),
        .I2(\p_Val2_4_reg_1510_reg_n_0_[46] ),
        .I3(inputs_current_offse_1[47]),
        .I4(\p_Val2_4_reg_1510_reg_n_0_[47] ),
        .I5(acc_H1_V_reg[47]),
        .O(\p_Val2_15_reg_1581[47]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[47]_i_6 
       (.I0(\p_Val2_15_reg_1581[47]_i_2_n_0 ),
        .I1(inputs_current_offse_1[46]),
        .I2(acc_H1_V_reg[46]),
        .I3(\p_Val2_4_reg_1510_reg_n_0_[46] ),
        .O(\p_Val2_15_reg_1581[47]_i_6_n_0 ));
  (* HLUTNM = "lutpair91" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[47]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[45] ),
        .I1(inputs_current_offse_1[45]),
        .I2(acc_H1_V_reg[45]),
        .I3(\p_Val2_15_reg_1581[47]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[47]_i_7_n_0 ));
  (* HLUTNM = "lutpair90" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[47]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[44] ),
        .I1(inputs_current_offse_1[44]),
        .I2(acc_H1_V_reg[44]),
        .I3(\p_Val2_15_reg_1581[47]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[47]_i_8_n_0 ));
  (* HLUTNM = "lutpair52" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[7]_i_2 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[6] ),
        .I1(inputs_current_offse_1[6]),
        .I2(acc_H1_V_reg[6]),
        .O(\p_Val2_15_reg_1581[7]_i_2_n_0 ));
  (* HLUTNM = "lutpair51" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[7]_i_3 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[5] ),
        .I1(inputs_current_offse_1[5]),
        .I2(acc_H1_V_reg[5]),
        .O(\p_Val2_15_reg_1581[7]_i_3_n_0 ));
  (* HLUTNM = "lutpair50" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[7]_i_4 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[4] ),
        .I1(inputs_current_offse_1[4]),
        .I2(acc_H1_V_reg[4]),
        .O(\p_Val2_15_reg_1581[7]_i_4_n_0 ));
  (* HLUTNM = "lutpair49" *) 
  LUT3 #(
    .INIT(8'hE8)) 
    \p_Val2_15_reg_1581[7]_i_5 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[3] ),
        .I1(inputs_current_offse_1[3]),
        .I2(acc_H1_V_reg[3]),
        .O(\p_Val2_15_reg_1581[7]_i_5_n_0 ));
  (* HLUTNM = "lutpair53" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[7]_i_6 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[7] ),
        .I1(inputs_current_offse_1[7]),
        .I2(acc_H1_V_reg[7]),
        .I3(\p_Val2_15_reg_1581[7]_i_2_n_0 ),
        .O(\p_Val2_15_reg_1581[7]_i_6_n_0 ));
  (* HLUTNM = "lutpair52" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[7]_i_7 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[6] ),
        .I1(inputs_current_offse_1[6]),
        .I2(acc_H1_V_reg[6]),
        .I3(\p_Val2_15_reg_1581[7]_i_3_n_0 ),
        .O(\p_Val2_15_reg_1581[7]_i_7_n_0 ));
  (* HLUTNM = "lutpair51" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[7]_i_8 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[5] ),
        .I1(inputs_current_offse_1[5]),
        .I2(acc_H1_V_reg[5]),
        .I3(\p_Val2_15_reg_1581[7]_i_4_n_0 ),
        .O(\p_Val2_15_reg_1581[7]_i_8_n_0 ));
  (* HLUTNM = "lutpair50" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \p_Val2_15_reg_1581[7]_i_9 
       (.I0(\p_Val2_4_reg_1510_reg_n_0_[4] ),
        .I1(inputs_current_offse_1[4]),
        .I2(acc_H1_V_reg[4]),
        .I3(\p_Val2_15_reg_1581[7]_i_5_n_0 ),
        .O(\p_Val2_15_reg_1581[7]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[0]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[10]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[11]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[12]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[13]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[14]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[15]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[16]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[17]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[18]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[19]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[1]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[20]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[21]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[22]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[23]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[24]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[25]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[26]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[27]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[28]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[29]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[2]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[30]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[31]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[32]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[33]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[34]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[35]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[36]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[37]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[38]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[39]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[3]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[40]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[41]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[42]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[43]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[44]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[45]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[46]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[47]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[4]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[5]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[6]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[7]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[8]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter4_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581[9]),
        .Q(p_Val2_15_reg_1581_pp0_iter4_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[0]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[10]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[11]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[12]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[13]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[14]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[15]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[16]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[17]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[18]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[19]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[1]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[20]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[21]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[22]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[23]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[24]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[25]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[26]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[27]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[28]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[29]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[2]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[30]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[31]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[32]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[33]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[34]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[35]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[36]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[37]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[38]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[39]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[3]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[40]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[41]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[42]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[43]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[44]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[45]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[46]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[47]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[4]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[5]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[6]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[7]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[8]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter5_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter4_reg[9]),
        .Q(p_Val2_15_reg_1581_pp0_iter5_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[0]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[10]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[11]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[12]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[13]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[14]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[15]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[16]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[17]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[18]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[19]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[1]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[20]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[21]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[22]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[23]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[24]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[25]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[26]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[27]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[28]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[29]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[2]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[30]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[31]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[32]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[33]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[34]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[35]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[36]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[37]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[38]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[39]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[3]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[40]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[41]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[42]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[43]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[44]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[45]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[46]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[47]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[4]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[5]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[6]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[7]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[8]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_reg_1581_pp0_iter5_reg[9]),
        .Q(p_Val2_15_reg_1581_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[0]),
        .Q(p_Val2_15_reg_1581[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[10]),
        .Q(p_Val2_15_reg_1581[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[11]),
        .Q(p_Val2_15_reg_1581[11]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[11]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[7]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[11]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[11]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[11]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[11]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[11]_i_2_n_0 ,\p_Val2_15_reg_1581[11]_i_3_n_0 ,\p_Val2_15_reg_1581[11]_i_4_n_0 ,\p_Val2_15_reg_1581[11]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[11:8]),
        .S({\p_Val2_15_reg_1581[11]_i_6_n_0 ,\p_Val2_15_reg_1581[11]_i_7_n_0 ,\p_Val2_15_reg_1581[11]_i_8_n_0 ,\p_Val2_15_reg_1581[11]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[12]),
        .Q(p_Val2_15_reg_1581[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[13]),
        .Q(p_Val2_15_reg_1581[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[14]),
        .Q(p_Val2_15_reg_1581[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[15]),
        .Q(p_Val2_15_reg_1581[15]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[15]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[11]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[15]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[15]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[15]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[15]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[15]_i_2_n_0 ,\p_Val2_15_reg_1581[15]_i_3_n_0 ,\p_Val2_15_reg_1581[15]_i_4_n_0 ,\p_Val2_15_reg_1581[15]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[15:12]),
        .S({\p_Val2_15_reg_1581[15]_i_6_n_0 ,\p_Val2_15_reg_1581[15]_i_7_n_0 ,\p_Val2_15_reg_1581[15]_i_8_n_0 ,\p_Val2_15_reg_1581[15]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[16]),
        .Q(p_Val2_15_reg_1581[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[17]),
        .Q(p_Val2_15_reg_1581[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[18]),
        .Q(p_Val2_15_reg_1581[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[19]),
        .Q(p_Val2_15_reg_1581[19]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[19]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[15]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[19]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[19]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[19]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[19]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[19]_i_2_n_0 ,\p_Val2_15_reg_1581[19]_i_3_n_0 ,\p_Val2_15_reg_1581[19]_i_4_n_0 ,\p_Val2_15_reg_1581[19]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[19:16]),
        .S({\p_Val2_15_reg_1581[19]_i_6_n_0 ,\p_Val2_15_reg_1581[19]_i_7_n_0 ,\p_Val2_15_reg_1581[19]_i_8_n_0 ,\p_Val2_15_reg_1581[19]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[1]),
        .Q(p_Val2_15_reg_1581[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[20]),
        .Q(p_Val2_15_reg_1581[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[21]),
        .Q(p_Val2_15_reg_1581[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[22]),
        .Q(p_Val2_15_reg_1581[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[23]),
        .Q(p_Val2_15_reg_1581[23]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[23]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[19]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[23]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[23]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[23]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[23]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[23]_i_2_n_0 ,\p_Val2_15_reg_1581[23]_i_3_n_0 ,\p_Val2_15_reg_1581[23]_i_4_n_0 ,\p_Val2_15_reg_1581[23]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[23:20]),
        .S({\p_Val2_15_reg_1581[23]_i_6_n_0 ,\p_Val2_15_reg_1581[23]_i_7_n_0 ,\p_Val2_15_reg_1581[23]_i_8_n_0 ,\p_Val2_15_reg_1581[23]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[24]),
        .Q(p_Val2_15_reg_1581[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[25]),
        .Q(p_Val2_15_reg_1581[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[26]),
        .Q(p_Val2_15_reg_1581[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[27]),
        .Q(p_Val2_15_reg_1581[27]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[27]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[23]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[27]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[27]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[27]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[27]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[27]_i_2_n_0 ,\p_Val2_15_reg_1581[27]_i_3_n_0 ,\p_Val2_15_reg_1581[27]_i_4_n_0 ,\p_Val2_15_reg_1581[27]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[27:24]),
        .S({\p_Val2_15_reg_1581[27]_i_6_n_0 ,\p_Val2_15_reg_1581[27]_i_7_n_0 ,\p_Val2_15_reg_1581[27]_i_8_n_0 ,\p_Val2_15_reg_1581[27]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[28]),
        .Q(p_Val2_15_reg_1581[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[29]),
        .Q(p_Val2_15_reg_1581[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[2]),
        .Q(p_Val2_15_reg_1581[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[30]),
        .Q(p_Val2_15_reg_1581[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[31]),
        .Q(p_Val2_15_reg_1581[31]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[31]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[27]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[31]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[31]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[31]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[31]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[31]_i_2_n_0 ,\p_Val2_15_reg_1581[31]_i_3_n_0 ,\p_Val2_15_reg_1581[31]_i_4_n_0 ,\p_Val2_15_reg_1581[31]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[31:28]),
        .S({\p_Val2_15_reg_1581[31]_i_6_n_0 ,\p_Val2_15_reg_1581[31]_i_7_n_0 ,\p_Val2_15_reg_1581[31]_i_8_n_0 ,\p_Val2_15_reg_1581[31]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[32]),
        .Q(p_Val2_15_reg_1581[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[33]),
        .Q(p_Val2_15_reg_1581[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[34]),
        .Q(p_Val2_15_reg_1581[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[35]),
        .Q(p_Val2_15_reg_1581[35]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[35]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[31]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[35]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[35]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[35]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[35]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[35]_i_2_n_0 ,\p_Val2_15_reg_1581[35]_i_3_n_0 ,\p_Val2_15_reg_1581[35]_i_4_n_0 ,\p_Val2_15_reg_1581[35]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[35:32]),
        .S({\p_Val2_15_reg_1581[35]_i_6_n_0 ,\p_Val2_15_reg_1581[35]_i_7_n_0 ,\p_Val2_15_reg_1581[35]_i_8_n_0 ,\p_Val2_15_reg_1581[35]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[36]),
        .Q(p_Val2_15_reg_1581[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[37]),
        .Q(p_Val2_15_reg_1581[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[38]),
        .Q(p_Val2_15_reg_1581[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[39]),
        .Q(p_Val2_15_reg_1581[39]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[39]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[35]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[39]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[39]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[39]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[39]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[39]_i_2_n_0 ,\p_Val2_15_reg_1581[39]_i_3_n_0 ,\p_Val2_15_reg_1581[39]_i_4_n_0 ,\p_Val2_15_reg_1581[39]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[39:36]),
        .S({\p_Val2_15_reg_1581[39]_i_6_n_0 ,\p_Val2_15_reg_1581[39]_i_7_n_0 ,\p_Val2_15_reg_1581[39]_i_8_n_0 ,\p_Val2_15_reg_1581[39]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[3]),
        .Q(p_Val2_15_reg_1581[3]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[3]_i_1 
       (.CI(\<const0> ),
        .CO({\p_Val2_15_reg_1581_reg[3]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[3]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[3]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[3]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[3]_i_2_n_0 ,\p_Val2_15_reg_1581[3]_i_3_n_0 ,\p_Val2_15_reg_1581[3]_i_4_n_0 ,\<const0> }),
        .O(p_Val2_15_fu_962_p2[3:0]),
        .S({\p_Val2_15_reg_1581[3]_i_5_n_0 ,\p_Val2_15_reg_1581[3]_i_6_n_0 ,\p_Val2_15_reg_1581[3]_i_7_n_0 ,\p_Val2_15_reg_1581[3]_i_8_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[40]),
        .Q(p_Val2_15_reg_1581[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[41]),
        .Q(p_Val2_15_reg_1581[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[42]),
        .Q(p_Val2_15_reg_1581[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[43]),
        .Q(p_Val2_15_reg_1581[43]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[43]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[39]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[43]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[43]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[43]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[43]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[43]_i_2_n_0 ,\p_Val2_15_reg_1581[43]_i_3_n_0 ,\p_Val2_15_reg_1581[43]_i_4_n_0 ,\p_Val2_15_reg_1581[43]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[43:40]),
        .S({\p_Val2_15_reg_1581[43]_i_6_n_0 ,\p_Val2_15_reg_1581[43]_i_7_n_0 ,\p_Val2_15_reg_1581[43]_i_8_n_0 ,\p_Val2_15_reg_1581[43]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[44]),
        .Q(p_Val2_15_reg_1581[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[45]),
        .Q(p_Val2_15_reg_1581[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[46]),
        .Q(p_Val2_15_reg_1581[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[47]),
        .Q(p_Val2_15_reg_1581[47]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[47]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[43]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[47]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[47]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[47]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\p_Val2_15_reg_1581[47]_i_2_n_0 ,\p_Val2_15_reg_1581[47]_i_3_n_0 ,\p_Val2_15_reg_1581[47]_i_4_n_0 }),
        .O(p_Val2_15_fu_962_p2[47:44]),
        .S({\p_Val2_15_reg_1581[47]_i_5_n_0 ,\p_Val2_15_reg_1581[47]_i_6_n_0 ,\p_Val2_15_reg_1581[47]_i_7_n_0 ,\p_Val2_15_reg_1581[47]_i_8_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[4]),
        .Q(p_Val2_15_reg_1581[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[5]),
        .Q(p_Val2_15_reg_1581[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[6]),
        .Q(p_Val2_15_reg_1581[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[7]),
        .Q(p_Val2_15_reg_1581[7]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_15_reg_1581_reg[7]_i_1 
       (.CI(\p_Val2_15_reg_1581_reg[3]_i_1_n_0 ),
        .CO({\p_Val2_15_reg_1581_reg[7]_i_1_n_0 ,\p_Val2_15_reg_1581_reg[7]_i_1_n_1 ,\p_Val2_15_reg_1581_reg[7]_i_1_n_2 ,\p_Val2_15_reg_1581_reg[7]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\p_Val2_15_reg_1581[7]_i_2_n_0 ,\p_Val2_15_reg_1581[7]_i_3_n_0 ,\p_Val2_15_reg_1581[7]_i_4_n_0 ,\p_Val2_15_reg_1581[7]_i_5_n_0 }),
        .O(p_Val2_15_fu_962_p2[7:4]),
        .S({\p_Val2_15_reg_1581[7]_i_6_n_0 ,\p_Val2_15_reg_1581[7]_i_7_n_0 ,\p_Val2_15_reg_1581[7]_i_8_n_0 ,\p_Val2_15_reg_1581[7]_i_9_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[8]),
        .Q(p_Val2_15_reg_1581[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_15_reg_1581_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_15_fu_962_p2[9]),
        .Q(p_Val2_15_reg_1581[9]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 15x18 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_19_fu_1151_p2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_Val2_19_fu_1151_p2_i_12_n_0,p_Val2_19_fu_1151_p2_i_13_n_0,p_Val2_19_fu_1151_p2_i_14_n_0,p_Val2_19_fu_1151_p2_i_15_n_0,p_Val2_19_fu_1151_p2_i_16_n_0,p_Val2_19_fu_1151_p2_i_17_n_0,p_Val2_19_fu_1151_p2_i_18_n_0,p_Val2_19_fu_1151_p2_i_19_n_0,p_Val2_19_fu_1151_p2_i_20_n_0,p_Val2_19_fu_1151_p2_i_21_n_0,p_Val2_19_fu_1151_p2_i_22_n_0,p_Val2_19_fu_1151_p2_i_23_n_0,p_Val2_19_fu_1151_p2_i_24_n_0,p_Val2_19_fu_1151_p2_i_25_n_0,p_Val2_19_fu_1151_p2_i_26_n_0,p_Val2_19_fu_1151_p2_i_27_n_0,p_Val2_19_fu_1151_p2_i_28_n_0}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,\<const0> ,\<const0> ,phase_H1_trunc_V_fu_988_p2[47:45],p_Val2_19_fu_1151_p2_i_5_n_0,phase_H1_trunc_V_fu_988_p2[43:41],p_5_in[40:34]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_19_fu_1151_p2_n_58,p_Val2_19_fu_1151_p2_n_59,p_Val2_19_fu_1151_p2_n_60,p_Val2_19_fu_1151_p2_n_61,p_Val2_19_fu_1151_p2_n_62,p_Val2_19_fu_1151_p2_n_63,p_Val2_19_fu_1151_p2_n_64,p_Val2_19_fu_1151_p2_n_65,p_Val2_19_fu_1151_p2_n_66,p_Val2_19_fu_1151_p2_n_67,p_Val2_19_fu_1151_p2_n_68,p_Val2_19_fu_1151_p2_n_69,p_Val2_19_fu_1151_p2_n_70,p_Val2_19_fu_1151_p2_n_71,p_Val2_19_fu_1151_p2_n_72,p_Val2_19_fu_1151_p2_n_73,p_Val2_19_fu_1151_p2_n_74,p_Val2_19_fu_1151_p2_n_75,p_Val2_19_fu_1151_p2_n_76,p_Val2_19_fu_1151_p2_n_77,p_Val2_19_fu_1151_p2_n_78,p_Val2_19_fu_1151_p2_n_79,p_Val2_19_fu_1151_p2_n_80,p_Val2_19_fu_1151_p2_n_81,p_Val2_19_fu_1151_p2_n_82,p_Val2_19_fu_1151_p2_n_83,p_Val2_19_fu_1151_p2_n_84,p_Val2_19_fu_1151_p2_n_85,p_Val2_19_fu_1151_p2_n_86,p_Val2_19_fu_1151_p2_n_87,p_Val2_19_fu_1151_p2_n_88,p_Val2_19_fu_1151_p2_n_89,p_Val2_19_fu_1151_p2_n_90,p_Val2_19_fu_1151_p2_n_91,p_Val2_19_fu_1151_p2_n_92,p_Val2_19_fu_1151_p2_n_93,p_Val2_19_fu_1151_p2_n_94,p_Val2_19_fu_1151_p2_n_95,p_Val2_19_fu_1151_p2_n_96,p_Val2_19_fu_1151_p2_n_97,p_Val2_19_fu_1151_p2_n_98,p_Val2_19_fu_1151_p2_n_99,p_Val2_19_fu_1151_p2_n_100,p_Val2_19_fu_1151_p2_n_101,p_Val2_19_fu_1151_p2_n_102,p_Val2_19_fu_1151_p2_n_103,p_Val2_19_fu_1151_p2_n_104,p_Val2_19_fu_1151_p2_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_19_fu_1151_p2_n_106,p_Val2_19_fu_1151_p2_n_107,p_Val2_19_fu_1151_p2_n_108,p_Val2_19_fu_1151_p2_n_109,p_Val2_19_fu_1151_p2_n_110,p_Val2_19_fu_1151_p2_n_111,p_Val2_19_fu_1151_p2_n_112,p_Val2_19_fu_1151_p2_n_113,p_Val2_19_fu_1151_p2_n_114,p_Val2_19_fu_1151_p2_n_115,p_Val2_19_fu_1151_p2_n_116,p_Val2_19_fu_1151_p2_n_117,p_Val2_19_fu_1151_p2_n_118,p_Val2_19_fu_1151_p2_n_119,p_Val2_19_fu_1151_p2_n_120,p_Val2_19_fu_1151_p2_n_121,p_Val2_19_fu_1151_p2_n_122,p_Val2_19_fu_1151_p2_n_123,p_Val2_19_fu_1151_p2_n_124,p_Val2_19_fu_1151_p2_n_125,p_Val2_19_fu_1151_p2_n_126,p_Val2_19_fu_1151_p2_n_127,p_Val2_19_fu_1151_p2_n_128,p_Val2_19_fu_1151_p2_n_129,p_Val2_19_fu_1151_p2_n_130,p_Val2_19_fu_1151_p2_n_131,p_Val2_19_fu_1151_p2_n_132,p_Val2_19_fu_1151_p2_n_133,p_Val2_19_fu_1151_p2_n_134,p_Val2_19_fu_1151_p2_n_135,p_Val2_19_fu_1151_p2_n_136,p_Val2_19_fu_1151_p2_n_137,p_Val2_19_fu_1151_p2_n_138,p_Val2_19_fu_1151_p2_n_139,p_Val2_19_fu_1151_p2_n_140,p_Val2_19_fu_1151_p2_n_141,p_Val2_19_fu_1151_p2_n_142,p_Val2_19_fu_1151_p2_n_143,p_Val2_19_fu_1151_p2_n_144,p_Val2_19_fu_1151_p2_n_145,p_Val2_19_fu_1151_p2_n_146,p_Val2_19_fu_1151_p2_n_147,p_Val2_19_fu_1151_p2_n_148,p_Val2_19_fu_1151_p2_n_149,p_Val2_19_fu_1151_p2_n_150,p_Val2_19_fu_1151_p2_n_151,p_Val2_19_fu_1151_p2_n_152,p_Val2_19_fu_1151_p2_n_153}),
        .RSTA(p_Val2_19_fu_1151_p2_i_1_n_0),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x18 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_19_fu_1151_p2__0
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_5_in[33:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,p_Val2_19_fu_1151_p2_i_12_n_0,p_Val2_19_fu_1151_p2_i_13_n_0,p_Val2_19_fu_1151_p2_i_14_n_0,p_Val2_19_fu_1151_p2_i_15_n_0,p_Val2_19_fu_1151_p2_i_16_n_0,p_Val2_19_fu_1151_p2_i_17_n_0,p_Val2_19_fu_1151_p2_i_18_n_0,p_Val2_19_fu_1151_p2_i_19_n_0,p_Val2_19_fu_1151_p2_i_20_n_0,p_Val2_19_fu_1151_p2_i_21_n_0,p_Val2_19_fu_1151_p2_i_22_n_0,p_Val2_19_fu_1151_p2_i_23_n_0,p_Val2_19_fu_1151_p2_i_24_n_0,p_Val2_19_fu_1151_p2_i_25_n_0,p_Val2_19_fu_1151_p2_i_26_n_0,p_Val2_19_fu_1151_p2_i_27_n_0,p_Val2_19_fu_1151_p2_i_28_n_0}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_19_fu_1151_p2__0_n_58,p_Val2_19_fu_1151_p2__0_n_59,p_Val2_19_fu_1151_p2__0_n_60,p_Val2_19_fu_1151_p2__0_n_61,p_Val2_19_fu_1151_p2__0_n_62,p_Val2_19_fu_1151_p2__0_n_63,p_Val2_19_fu_1151_p2__0_n_64,p_Val2_19_fu_1151_p2__0_n_65,p_Val2_19_fu_1151_p2__0_n_66,p_Val2_19_fu_1151_p2__0_n_67,p_Val2_19_fu_1151_p2__0_n_68,p_Val2_19_fu_1151_p2__0_n_69,p_Val2_19_fu_1151_p2__0_n_70,p_Val2_19_fu_1151_p2__0_n_71,p_Val2_19_fu_1151_p2__0_n_72,p_Val2_19_fu_1151_p2__0_n_73,p_Val2_19_fu_1151_p2__0_n_74,p_Val2_19_fu_1151_p2__0_n_75,p_Val2_19_fu_1151_p2__0_n_76,p_Val2_19_fu_1151_p2__0_n_77,p_Val2_19_fu_1151_p2__0_n_78,p_Val2_19_fu_1151_p2__0_n_79,p_Val2_19_fu_1151_p2__0_n_80,p_Val2_19_fu_1151_p2__0_n_81,p_Val2_19_fu_1151_p2__0_n_82,p_Val2_19_fu_1151_p2__0_n_83,p_Val2_19_fu_1151_p2__0_n_84,p_Val2_19_fu_1151_p2__0_n_85,p_Val2_19_fu_1151_p2__0_n_86,p_Val2_19_fu_1151_p2__0_n_87,p_Val2_19_fu_1151_p2__0_n_88,p_Val2_19_fu_1151_p2__0_n_89,p_Val2_19_fu_1151_p2__0_n_90,p_Val2_19_fu_1151_p2__0_n_91,p_Val2_19_fu_1151_p2__0_n_92,p_Val2_19_fu_1151_p2__0_n_93,p_Val2_19_fu_1151_p2__0_n_94,p_Val2_19_fu_1151_p2__0_n_95,p_Val2_19_fu_1151_p2__0_n_96,p_Val2_19_fu_1151_p2__0_n_97,p_Val2_19_fu_1151_p2__0_n_98,p_Val2_19_fu_1151_p2__0_n_99,p_Val2_19_fu_1151_p2__0_n_100,p_Val2_19_fu_1151_p2__0_n_101,p_Val2_19_fu_1151_p2__0_n_102,p_Val2_19_fu_1151_p2__0_n_103,p_Val2_19_fu_1151_p2__0_n_104,p_Val2_19_fu_1151_p2__0_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_19_fu_1151_p2__0_n_106,p_Val2_19_fu_1151_p2__0_n_107,p_Val2_19_fu_1151_p2__0_n_108,p_Val2_19_fu_1151_p2__0_n_109,p_Val2_19_fu_1151_p2__0_n_110,p_Val2_19_fu_1151_p2__0_n_111,p_Val2_19_fu_1151_p2__0_n_112,p_Val2_19_fu_1151_p2__0_n_113,p_Val2_19_fu_1151_p2__0_n_114,p_Val2_19_fu_1151_p2__0_n_115,p_Val2_19_fu_1151_p2__0_n_116,p_Val2_19_fu_1151_p2__0_n_117,p_Val2_19_fu_1151_p2__0_n_118,p_Val2_19_fu_1151_p2__0_n_119,p_Val2_19_fu_1151_p2__0_n_120,p_Val2_19_fu_1151_p2__0_n_121,p_Val2_19_fu_1151_p2__0_n_122,p_Val2_19_fu_1151_p2__0_n_123,p_Val2_19_fu_1151_p2__0_n_124,p_Val2_19_fu_1151_p2__0_n_125,p_Val2_19_fu_1151_p2__0_n_126,p_Val2_19_fu_1151_p2__0_n_127,p_Val2_19_fu_1151_p2__0_n_128,p_Val2_19_fu_1151_p2__0_n_129,p_Val2_19_fu_1151_p2__0_n_130,p_Val2_19_fu_1151_p2__0_n_131,p_Val2_19_fu_1151_p2__0_n_132,p_Val2_19_fu_1151_p2__0_n_133,p_Val2_19_fu_1151_p2__0_n_134,p_Val2_19_fu_1151_p2__0_n_135,p_Val2_19_fu_1151_p2__0_n_136,p_Val2_19_fu_1151_p2__0_n_137,p_Val2_19_fu_1151_p2__0_n_138,p_Val2_19_fu_1151_p2__0_n_139,p_Val2_19_fu_1151_p2__0_n_140,p_Val2_19_fu_1151_p2__0_n_141,p_Val2_19_fu_1151_p2__0_n_142,p_Val2_19_fu_1151_p2__0_n_143,p_Val2_19_fu_1151_p2__0_n_144,p_Val2_19_fu_1151_p2__0_n_145,p_Val2_19_fu_1151_p2__0_n_146,p_Val2_19_fu_1151_p2__0_n_147,p_Val2_19_fu_1151_p2__0_n_148,p_Val2_19_fu_1151_p2__0_n_149,p_Val2_19_fu_1151_p2__0_n_150,p_Val2_19_fu_1151_p2__0_n_151,p_Val2_19_fu_1151_p2__0_n_152,p_Val2_19_fu_1151_p2__0_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(p_Val2_19_fu_1151_p2_i_1_n_0),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__0_i_1
       (.CI(p_Val2_19_fu_1151_p2__0_i_2_n_0),
        .CO({p_Val2_19_fu_1151_p2__0_i_1_n_0,p_Val2_19_fu_1151_p2__0_i_1_n_1,p_Val2_19_fu_1151_p2__0_i_1_n_2,p_Val2_19_fu_1151_p2__0_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[31:28]),
        .O(p_5_in[31:28]),
        .S({p_Val2_19_fu_1151_p2__0_i_5_n_0,p_Val2_19_fu_1151_p2__0_i_6_n_0,p_Val2_19_fu_1151_p2__0_i_7_n_0,p_Val2_19_fu_1151_p2__0_i_8_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_10
       (.I0(p_Val2_15_fu_962_p2[26]),
        .I1(inputs_current_offse[26]),
        .O(p_Val2_19_fu_1151_p2__0_i_10_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_11
       (.I0(p_Val2_15_fu_962_p2[25]),
        .I1(inputs_current_offse[25]),
        .O(p_Val2_19_fu_1151_p2__0_i_11_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_12
       (.I0(p_Val2_15_fu_962_p2[24]),
        .I1(inputs_current_offse[24]),
        .O(p_Val2_19_fu_1151_p2__0_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_13
       (.I0(p_Val2_15_fu_962_p2[23]),
        .I1(inputs_current_offse[23]),
        .O(p_Val2_19_fu_1151_p2__0_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_14
       (.I0(p_Val2_15_fu_962_p2[22]),
        .I1(inputs_current_offse[22]),
        .O(p_Val2_19_fu_1151_p2__0_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_15
       (.I0(p_Val2_15_fu_962_p2[21]),
        .I1(inputs_current_offse[21]),
        .O(p_Val2_19_fu_1151_p2__0_i_15_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_16
       (.I0(p_Val2_15_fu_962_p2[20]),
        .I1(inputs_current_offse[20]),
        .O(p_Val2_19_fu_1151_p2__0_i_16_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_17
       (.I0(p_Val2_15_fu_962_p2[19]),
        .I1(inputs_current_offse[19]),
        .O(p_Val2_19_fu_1151_p2__0_i_17_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_18
       (.I0(p_Val2_15_fu_962_p2[18]),
        .I1(inputs_current_offse[18]),
        .O(p_Val2_19_fu_1151_p2__0_i_18_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_19
       (.I0(p_Val2_15_fu_962_p2[17]),
        .I1(inputs_current_offse[17]),
        .O(p_Val2_19_fu_1151_p2__0_i_19_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__0_i_2
       (.CI(p_Val2_19_fu_1151_p2__0_i_3_n_0),
        .CO({p_Val2_19_fu_1151_p2__0_i_2_n_0,p_Val2_19_fu_1151_p2__0_i_2_n_1,p_Val2_19_fu_1151_p2__0_i_2_n_2,p_Val2_19_fu_1151_p2__0_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[27:24]),
        .O(p_5_in[27:24]),
        .S({p_Val2_19_fu_1151_p2__0_i_9_n_0,p_Val2_19_fu_1151_p2__0_i_10_n_0,p_Val2_19_fu_1151_p2__0_i_11_n_0,p_Val2_19_fu_1151_p2__0_i_12_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_20
       (.I0(p_Val2_15_fu_962_p2[16]),
        .I1(inputs_current_offse[16]),
        .O(p_Val2_19_fu_1151_p2__0_i_20_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__0_i_3
       (.CI(p_Val2_19_fu_1151_p2__0_i_4_n_0),
        .CO({p_Val2_19_fu_1151_p2__0_i_3_n_0,p_Val2_19_fu_1151_p2__0_i_3_n_1,p_Val2_19_fu_1151_p2__0_i_3_n_2,p_Val2_19_fu_1151_p2__0_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[23:20]),
        .O(p_5_in[23:20]),
        .S({p_Val2_19_fu_1151_p2__0_i_13_n_0,p_Val2_19_fu_1151_p2__0_i_14_n_0,p_Val2_19_fu_1151_p2__0_i_15_n_0,p_Val2_19_fu_1151_p2__0_i_16_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__0_i_4
       (.CI(p_Val2_19_fu_1151_p2__1_i_1_n_0),
        .CO({p_Val2_19_fu_1151_p2__0_i_4_n_0,p_Val2_19_fu_1151_p2__0_i_4_n_1,p_Val2_19_fu_1151_p2__0_i_4_n_2,p_Val2_19_fu_1151_p2__0_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[19:16]),
        .O(p_5_in[19:16]),
        .S({p_Val2_19_fu_1151_p2__0_i_17_n_0,p_Val2_19_fu_1151_p2__0_i_18_n_0,p_Val2_19_fu_1151_p2__0_i_19_n_0,p_Val2_19_fu_1151_p2__0_i_20_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_5
       (.I0(p_Val2_15_fu_962_p2[31]),
        .I1(inputs_current_offse[31]),
        .O(p_Val2_19_fu_1151_p2__0_i_5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_6
       (.I0(p_Val2_15_fu_962_p2[30]),
        .I1(inputs_current_offse[30]),
        .O(p_Val2_19_fu_1151_p2__0_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_7
       (.I0(p_Val2_15_fu_962_p2[29]),
        .I1(inputs_current_offse[29]),
        .O(p_Val2_19_fu_1151_p2__0_i_7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_8
       (.I0(p_Val2_15_fu_962_p2[28]),
        .I1(inputs_current_offse[28]),
        .O(p_Val2_19_fu_1151_p2__0_i_8_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__0_i_9
       (.I0(p_Val2_15_fu_962_p2[27]),
        .I1(inputs_current_offse[27]),
        .O(p_Val2_19_fu_1151_p2__0_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 18x18 6}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_19_fu_1151_p2__1
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_5_in[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,p_Val2_19_fu_1151_p2_i_12_n_0,p_Val2_19_fu_1151_p2_i_13_n_0,p_Val2_19_fu_1151_p2_i_14_n_0,p_Val2_19_fu_1151_p2_i_15_n_0,p_Val2_19_fu_1151_p2_i_16_n_0,p_Val2_19_fu_1151_p2_i_17_n_0,p_Val2_19_fu_1151_p2_i_18_n_0,p_Val2_19_fu_1151_p2_i_19_n_0,p_Val2_19_fu_1151_p2_i_20_n_0,p_Val2_19_fu_1151_p2_i_21_n_0,p_Val2_19_fu_1151_p2_i_22_n_0,p_Val2_19_fu_1151_p2_i_23_n_0,p_Val2_19_fu_1151_p2_i_24_n_0,p_Val2_19_fu_1151_p2_i_25_n_0,p_Val2_19_fu_1151_p2_i_26_n_0,p_Val2_19_fu_1151_p2_i_27_n_0,p_Val2_19_fu_1151_p2_i_28_n_0}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_19_fu_1151_p2__1_n_58,p_Val2_19_fu_1151_p2__1_n_59,p_Val2_19_fu_1151_p2__1_n_60,p_Val2_19_fu_1151_p2__1_n_61,p_Val2_19_fu_1151_p2__1_n_62,p_Val2_19_fu_1151_p2__1_n_63,p_Val2_19_fu_1151_p2__1_n_64,p_Val2_19_fu_1151_p2__1_n_65,p_Val2_19_fu_1151_p2__1_n_66,p_Val2_19_fu_1151_p2__1_n_67,p_Val2_19_fu_1151_p2__1_n_68,p_Val2_19_fu_1151_p2__1_n_69,p_Val2_19_fu_1151_p2__1_n_70,p_Val2_19_fu_1151_p2__1_n_71,p_Val2_19_fu_1151_p2__1_n_72,p_Val2_19_fu_1151_p2__1_n_73,p_Val2_19_fu_1151_p2__1_n_74,p_Val2_19_fu_1151_p2__1_n_75,p_Val2_19_fu_1151_p2__1_n_76,p_Val2_19_fu_1151_p2__1_n_77,p_Val2_19_fu_1151_p2__1_n_78,p_Val2_19_fu_1151_p2__1_n_79,p_Val2_19_fu_1151_p2__1_n_80,p_Val2_19_fu_1151_p2__1_n_81,p_Val2_19_fu_1151_p2__1_n_82,p_Val2_19_fu_1151_p2__1_n_83,p_Val2_19_fu_1151_p2__1_n_84,p_Val2_19_fu_1151_p2__1_n_85,p_Val2_19_fu_1151_p2__1_n_86,p_Val2_19_fu_1151_p2__1_n_87,p_Val2_19_fu_1151_p2__1_n_88,p_Val2_19_fu_1151_p2__1_n_89,p_Val2_19_fu_1151_p2__1_n_90,p_Val2_19_fu_1151_p2__1_n_91,p_Val2_19_fu_1151_p2__1_n_92,p_Val2_19_fu_1151_p2__1_n_93,p_Val2_19_fu_1151_p2__1_n_94,p_Val2_19_fu_1151_p2__1_n_95,p_Val2_19_fu_1151_p2__1_n_96,p_Val2_19_fu_1151_p2__1_n_97,p_Val2_19_fu_1151_p2__1_n_98,p_Val2_19_fu_1151_p2__1_n_99,p_Val2_19_fu_1151_p2__1_n_100,p_Val2_19_fu_1151_p2__1_n_101,p_Val2_19_fu_1151_p2__1_n_102,p_Val2_19_fu_1151_p2__1_n_103,p_Val2_19_fu_1151_p2__1_n_104,p_Val2_19_fu_1151_p2__1_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_19_fu_1151_p2__1_n_106,p_Val2_19_fu_1151_p2__1_n_107,p_Val2_19_fu_1151_p2__1_n_108,p_Val2_19_fu_1151_p2__1_n_109,p_Val2_19_fu_1151_p2__1_n_110,p_Val2_19_fu_1151_p2__1_n_111,p_Val2_19_fu_1151_p2__1_n_112,p_Val2_19_fu_1151_p2__1_n_113,p_Val2_19_fu_1151_p2__1_n_114,p_Val2_19_fu_1151_p2__1_n_115,p_Val2_19_fu_1151_p2__1_n_116,p_Val2_19_fu_1151_p2__1_n_117,p_Val2_19_fu_1151_p2__1_n_118,p_Val2_19_fu_1151_p2__1_n_119,p_Val2_19_fu_1151_p2__1_n_120,p_Val2_19_fu_1151_p2__1_n_121,p_Val2_19_fu_1151_p2__1_n_122,p_Val2_19_fu_1151_p2__1_n_123,p_Val2_19_fu_1151_p2__1_n_124,p_Val2_19_fu_1151_p2__1_n_125,p_Val2_19_fu_1151_p2__1_n_126,p_Val2_19_fu_1151_p2__1_n_127,p_Val2_19_fu_1151_p2__1_n_128,p_Val2_19_fu_1151_p2__1_n_129,p_Val2_19_fu_1151_p2__1_n_130,p_Val2_19_fu_1151_p2__1_n_131,p_Val2_19_fu_1151_p2__1_n_132,p_Val2_19_fu_1151_p2__1_n_133,p_Val2_19_fu_1151_p2__1_n_134,p_Val2_19_fu_1151_p2__1_n_135,p_Val2_19_fu_1151_p2__1_n_136,p_Val2_19_fu_1151_p2__1_n_137,p_Val2_19_fu_1151_p2__1_n_138,p_Val2_19_fu_1151_p2__1_n_139,p_Val2_19_fu_1151_p2__1_n_140,p_Val2_19_fu_1151_p2__1_n_141,p_Val2_19_fu_1151_p2__1_n_142,p_Val2_19_fu_1151_p2__1_n_143,p_Val2_19_fu_1151_p2__1_n_144,p_Val2_19_fu_1151_p2__1_n_145,p_Val2_19_fu_1151_p2__1_n_146,p_Val2_19_fu_1151_p2__1_n_147,p_Val2_19_fu_1151_p2__1_n_148,p_Val2_19_fu_1151_p2__1_n_149,p_Val2_19_fu_1151_p2__1_n_150,p_Val2_19_fu_1151_p2__1_n_151,p_Val2_19_fu_1151_p2__1_n_152,p_Val2_19_fu_1151_p2__1_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(p_Val2_19_fu_1151_p2_i_1_n_0),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__1_i_1
       (.CI(p_Val2_19_fu_1151_p2__1_i_2_n_0),
        .CO({p_Val2_19_fu_1151_p2__1_i_1_n_0,p_Val2_19_fu_1151_p2__1_i_1_n_1,p_Val2_19_fu_1151_p2__1_i_1_n_2,p_Val2_19_fu_1151_p2__1_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[15:12]),
        .O(p_5_in[15:12]),
        .S({p_Val2_19_fu_1151_p2__1_i_5_n_0,p_Val2_19_fu_1151_p2__1_i_6_n_0,p_Val2_19_fu_1151_p2__1_i_7_n_0,p_Val2_19_fu_1151_p2__1_i_8_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_10
       (.I0(p_Val2_15_fu_962_p2[10]),
        .I1(inputs_current_offse[10]),
        .O(p_Val2_19_fu_1151_p2__1_i_10_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_11
       (.I0(p_Val2_15_fu_962_p2[9]),
        .I1(inputs_current_offse[9]),
        .O(p_Val2_19_fu_1151_p2__1_i_11_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_12
       (.I0(p_Val2_15_fu_962_p2[8]),
        .I1(inputs_current_offse[8]),
        .O(p_Val2_19_fu_1151_p2__1_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_13
       (.I0(p_Val2_15_fu_962_p2[7]),
        .I1(inputs_current_offse[7]),
        .O(p_Val2_19_fu_1151_p2__1_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_14
       (.I0(p_Val2_15_fu_962_p2[6]),
        .I1(inputs_current_offse[6]),
        .O(p_Val2_19_fu_1151_p2__1_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_15
       (.I0(p_Val2_15_fu_962_p2[5]),
        .I1(inputs_current_offse[5]),
        .O(p_Val2_19_fu_1151_p2__1_i_15_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_16
       (.I0(p_Val2_15_fu_962_p2[4]),
        .I1(inputs_current_offse[4]),
        .O(p_Val2_19_fu_1151_p2__1_i_16_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_17
       (.I0(p_Val2_15_fu_962_p2[3]),
        .I1(inputs_current_offse[3]),
        .O(p_Val2_19_fu_1151_p2__1_i_17_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_18
       (.I0(p_Val2_15_fu_962_p2[2]),
        .I1(inputs_current_offse[2]),
        .O(p_Val2_19_fu_1151_p2__1_i_18_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_19
       (.I0(p_Val2_15_fu_962_p2[1]),
        .I1(inputs_current_offse[1]),
        .O(p_Val2_19_fu_1151_p2__1_i_19_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__1_i_2
       (.CI(p_Val2_19_fu_1151_p2__1_i_3_n_0),
        .CO({p_Val2_19_fu_1151_p2__1_i_2_n_0,p_Val2_19_fu_1151_p2__1_i_2_n_1,p_Val2_19_fu_1151_p2__1_i_2_n_2,p_Val2_19_fu_1151_p2__1_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[11:8]),
        .O(p_5_in[11:8]),
        .S({p_Val2_19_fu_1151_p2__1_i_9_n_0,p_Val2_19_fu_1151_p2__1_i_10_n_0,p_Val2_19_fu_1151_p2__1_i_11_n_0,p_Val2_19_fu_1151_p2__1_i_12_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_20
       (.I0(p_Val2_15_fu_962_p2[0]),
        .I1(inputs_current_offse[0]),
        .O(p_Val2_19_fu_1151_p2__1_i_20_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__1_i_3
       (.CI(p_Val2_19_fu_1151_p2__1_i_4_n_0),
        .CO({p_Val2_19_fu_1151_p2__1_i_3_n_0,p_Val2_19_fu_1151_p2__1_i_3_n_1,p_Val2_19_fu_1151_p2__1_i_3_n_2,p_Val2_19_fu_1151_p2__1_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[7:4]),
        .O(p_5_in[7:4]),
        .S({p_Val2_19_fu_1151_p2__1_i_13_n_0,p_Val2_19_fu_1151_p2__1_i_14_n_0,p_Val2_19_fu_1151_p2__1_i_15_n_0,p_Val2_19_fu_1151_p2__1_i_16_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2__1_i_4
       (.CI(\<const0> ),
        .CO({p_Val2_19_fu_1151_p2__1_i_4_n_0,p_Val2_19_fu_1151_p2__1_i_4_n_1,p_Val2_19_fu_1151_p2__1_i_4_n_2,p_Val2_19_fu_1151_p2__1_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[3:0]),
        .O(p_5_in[3:0]),
        .S({p_Val2_19_fu_1151_p2__1_i_17_n_0,p_Val2_19_fu_1151_p2__1_i_18_n_0,p_Val2_19_fu_1151_p2__1_i_19_n_0,p_Val2_19_fu_1151_p2__1_i_20_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_5
       (.I0(p_Val2_15_fu_962_p2[15]),
        .I1(inputs_current_offse[15]),
        .O(p_Val2_19_fu_1151_p2__1_i_5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_6
       (.I0(p_Val2_15_fu_962_p2[14]),
        .I1(inputs_current_offse[14]),
        .O(p_Val2_19_fu_1151_p2__1_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_7
       (.I0(p_Val2_15_fu_962_p2[13]),
        .I1(inputs_current_offse[13]),
        .O(p_Val2_19_fu_1151_p2__1_i_7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_8
       (.I0(p_Val2_15_fu_962_p2[12]),
        .I1(inputs_current_offse[12]),
        .O(p_Val2_19_fu_1151_p2__1_i_8_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2__1_i_9
       (.I0(p_Val2_15_fu_962_p2[11]),
        .I1(inputs_current_offse[11]),
        .O(p_Val2_19_fu_1151_p2__1_i_9_n_0));
  LUT4 #(
    .INIT(16'hFF2A)) 
    p_Val2_19_fu_1151_p2_i_1
       (.I0(p_Val2_4_reg_1510),
        .I1(or_cond_reg_1520),
        .I2(sel_tmp_reg_1527),
        .I3(ap_rst),
        .O(p_Val2_19_fu_1151_p2_i_1_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2_i_10
       (.CI(p_Val2_19_fu_1151_p2_i_11_n_0),
        .CO({p_Val2_19_fu_1151_p2_i_10_n_0,p_Val2_19_fu_1151_p2_i_10_n_1,p_Val2_19_fu_1151_p2_i_10_n_2,p_Val2_19_fu_1151_p2_i_10_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[39:36]),
        .O(p_5_in[39:36]),
        .S({p_Val2_19_fu_1151_p2_i_34_n_0,p_Val2_19_fu_1151_p2_i_35_n_0,p_Val2_19_fu_1151_p2_i_36_n_0,p_Val2_19_fu_1151_p2_i_37_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2_i_11
       (.CI(p_Val2_19_fu_1151_p2__0_i_1_n_0),
        .CO({p_Val2_19_fu_1151_p2_i_11_n_0,p_Val2_19_fu_1151_p2_i_11_n_1,p_Val2_19_fu_1151_p2_i_11_n_2,p_Val2_19_fu_1151_p2_i_11_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[35:32]),
        .O(p_5_in[35:32]),
        .S({p_Val2_19_fu_1151_p2_i_38_n_0,p_Val2_19_fu_1151_p2_i_39_n_0,p_Val2_19_fu_1151_p2_i_40_n_0,p_Val2_19_fu_1151_p2_i_41_n_0}));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_12
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[16]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_12_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_13
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[15]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_13_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_14
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[14]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_14_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_15
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[13]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_15_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_16
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[12]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_16_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_17
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[11]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_17_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_18
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[10]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_18_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_19
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[9]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_19_n_0),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    p_Val2_19_fu_1151_p2_i_2
       (.I0(p_5_in__0[47]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_V_fu_988_p2[47]));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_20
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[8]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_20_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_21
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[7]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_21_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_22
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[6]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_22_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_23
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[5]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_23_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_24
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[4]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_24_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_25
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[3]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_25_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_26
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[2]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_26_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_27
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[1]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_27_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_Val2_19_fu_1151_p2_i_28
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\ap_phi_reg_pp0_iter3_inputs_current_coef_3_reg_496[0]_i_1_n_0 ),
        .Q(p_Val2_19_fu_1151_p2_i_28_n_0),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2_i_29
       (.CI(p_Val2_19_fu_1151_p2_i_9_n_0),
        .CO({p_Val2_19_fu_1151_p2_i_29_n_1,p_Val2_19_fu_1151_p2_i_29_n_2,p_Val2_19_fu_1151_p2_i_29_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_Val2_15_fu_962_p2[46:44]}),
        .O(p_5_in__0[47:44]),
        .S({p_Val2_19_fu_1151_p2_i_42_n_0,p_Val2_19_fu_1151_p2_i_43_n_0,p_Val2_19_fu_1151_p2_i_44_n_0,p_Val2_19_fu_1151_p2_i_45_n_0}));
  LUT5 #(
    .INIT(32'h0028AAAA)) 
    p_Val2_19_fu_1151_p2_i_3
       (.I0(p_5_in__0[46]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_V_fu_988_p2[46]));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_30
       (.I0(p_Val2_15_fu_962_p2[43]),
        .I1(inputs_current_offse[43]),
        .O(p_Val2_19_fu_1151_p2_i_30_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_31
       (.I0(p_Val2_15_fu_962_p2[42]),
        .I1(inputs_current_offse[42]),
        .O(p_Val2_19_fu_1151_p2_i_31_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_32
       (.I0(p_Val2_15_fu_962_p2[41]),
        .I1(inputs_current_offse[41]),
        .O(p_Val2_19_fu_1151_p2_i_32_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_33
       (.I0(p_Val2_15_fu_962_p2[40]),
        .I1(inputs_current_offse[40]),
        .O(p_Val2_19_fu_1151_p2_i_33_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_34
       (.I0(p_Val2_15_fu_962_p2[39]),
        .I1(inputs_current_offse[39]),
        .O(p_Val2_19_fu_1151_p2_i_34_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_35
       (.I0(p_Val2_15_fu_962_p2[38]),
        .I1(inputs_current_offse[38]),
        .O(p_Val2_19_fu_1151_p2_i_35_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_36
       (.I0(p_Val2_15_fu_962_p2[37]),
        .I1(inputs_current_offse[37]),
        .O(p_Val2_19_fu_1151_p2_i_36_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_37
       (.I0(p_Val2_15_fu_962_p2[36]),
        .I1(inputs_current_offse[36]),
        .O(p_Val2_19_fu_1151_p2_i_37_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_38
       (.I0(p_Val2_15_fu_962_p2[35]),
        .I1(inputs_current_offse[35]),
        .O(p_Val2_19_fu_1151_p2_i_38_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_39
       (.I0(p_Val2_15_fu_962_p2[34]),
        .I1(inputs_current_offse[34]),
        .O(p_Val2_19_fu_1151_p2_i_39_n_0));
  LUT5 #(
    .INIT(32'h2220AAAA)) 
    p_Val2_19_fu_1151_p2_i_4
       (.I0(p_5_in__0[45]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_V_fu_988_p2[45]));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_40
       (.I0(p_Val2_15_fu_962_p2[33]),
        .I1(inputs_current_offse[33]),
        .O(p_Val2_19_fu_1151_p2_i_40_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_41
       (.I0(p_Val2_15_fu_962_p2[32]),
        .I1(inputs_current_offse[32]),
        .O(p_Val2_19_fu_1151_p2_i_41_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_42
       (.I0(inputs_current_offse[47]),
        .I1(p_Val2_15_fu_962_p2[47]),
        .O(p_Val2_19_fu_1151_p2_i_42_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_43
       (.I0(p_Val2_15_fu_962_p2[46]),
        .I1(inputs_current_offse[46]),
        .O(p_Val2_19_fu_1151_p2_i_43_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_44
       (.I0(p_Val2_15_fu_962_p2[45]),
        .I1(inputs_current_offse[45]),
        .O(p_Val2_19_fu_1151_p2_i_44_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_19_fu_1151_p2_i_45
       (.I0(p_Val2_15_fu_962_p2[44]),
        .I1(inputs_current_offse[44]),
        .O(p_Val2_19_fu_1151_p2_i_45_n_0));
  LUT5 #(
    .INIT(32'h777D0000)) 
    p_Val2_19_fu_1151_p2_i_5
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(p_5_in__0[44]),
        .O(p_Val2_19_fu_1151_p2_i_5_n_0));
  LUT5 #(
    .INIT(32'h22A8AAAA)) 
    p_Val2_19_fu_1151_p2_i_6
       (.I0(p_5_in__0[43]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_V_fu_988_p2[43]));
  LUT5 #(
    .INIT(32'h2AAAAAA2)) 
    p_Val2_19_fu_1151_p2_i_7
       (.I0(p_5_in__0[42]),
        .I1(or_cond_reg_1520),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(phase_H1_trunc_V_fu_988_p2[42]));
  LUT5 #(
    .INIT(32'hAAA8AAAA)) 
    p_Val2_19_fu_1151_p2_i_8
       (.I0(p_5_in__0[41]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_V_fu_988_p2[41]));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_19_fu_1151_p2_i_9
       (.CI(p_Val2_19_fu_1151_p2_i_10_n_0),
        .CO({p_Val2_19_fu_1151_p2_i_9_n_0,p_Val2_19_fu_1151_p2_i_9_n_1,p_Val2_19_fu_1151_p2_i_9_n_2,p_Val2_19_fu_1151_p2_i_9_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_fu_962_p2[43:40]),
        .O({p_5_in__0[43:41],p_5_in[40]}),
        .S({p_Val2_19_fu_1151_p2_i_30_n_0,p_Val2_19_fu_1151_p2_i_31_n_0,p_Val2_19_fu_1151_p2_i_32_n_0,p_Val2_19_fu_1151_p2_i_33_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 17x18 3}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_26_fu_1377_p2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_Val2_23_fu_1286_p21_out[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,inputs_H_V_read_reg_1490_pp0_iter3_reg}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(p_Val2_4_reg_1510),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_26_fu_1377_p2_n_58,p_Val2_26_fu_1377_p2_n_59,p_Val2_26_fu_1377_p2_n_60,p_Val2_26_fu_1377_p2_n_61,p_Val2_26_fu_1377_p2_n_62,p_Val2_26_fu_1377_p2_n_63,p_Val2_26_fu_1377_p2_n_64,p_Val2_26_fu_1377_p2_n_65,p_Val2_26_fu_1377_p2_n_66,p_Val2_26_fu_1377_p2_n_67,p_Val2_26_fu_1377_p2_n_68,p_Val2_26_fu_1377_p2_n_69,p_Val2_26_fu_1377_p2_n_70,p_Val2_26_fu_1377_p2_n_71,p_Val2_26_fu_1377_p2_n_72,p_Val2_26_fu_1377_p2_n_73,p_Val2_26_fu_1377_p2_n_74,p_Val2_26_fu_1377_p2_n_75,p_Val2_26_fu_1377_p2_n_76,p_Val2_26_fu_1377_p2_n_77,p_Val2_26_fu_1377_p2_n_78,p_Val2_26_fu_1377_p2_n_79,p_Val2_26_fu_1377_p2_n_80,p_Val2_26_fu_1377_p2_n_81,p_Val2_26_fu_1377_p2_n_82,p_Val2_26_fu_1377_p2_n_83,p_Val2_26_fu_1377_p2_n_84,p_Val2_26_fu_1377_p2_n_85,p_Val2_26_fu_1377_p2_n_86,p_Val2_26_fu_1377_p2_n_87,p_Val2_26_fu_1377_p2_n_88,p_Val2_26_fu_1377_p2_n_89,p_Val2_26_fu_1377_p2_n_90,p_Val2_26_fu_1377_p2_n_91,p_Val2_26_fu_1377_p2_n_92,p_Val2_26_fu_1377_p2_n_93,p_Val2_26_fu_1377_p2_n_94,p_Val2_26_fu_1377_p2_n_95,p_Val2_26_fu_1377_p2_n_96,p_Val2_26_fu_1377_p2_n_97,p_Val2_26_fu_1377_p2_n_98,p_Val2_26_fu_1377_p2_n_99,p_Val2_26_fu_1377_p2_n_100,p_Val2_26_fu_1377_p2_n_101,p_Val2_26_fu_1377_p2_n_102,p_Val2_26_fu_1377_p2_n_103,p_Val2_26_fu_1377_p2_n_104,p_Val2_26_fu_1377_p2_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_26_fu_1377_p2_n_106,p_Val2_26_fu_1377_p2_n_107,p_Val2_26_fu_1377_p2_n_108,p_Val2_26_fu_1377_p2_n_109,p_Val2_26_fu_1377_p2_n_110,p_Val2_26_fu_1377_p2_n_111,p_Val2_26_fu_1377_p2_n_112,p_Val2_26_fu_1377_p2_n_113,p_Val2_26_fu_1377_p2_n_114,p_Val2_26_fu_1377_p2_n_115,p_Val2_26_fu_1377_p2_n_116,p_Val2_26_fu_1377_p2_n_117,p_Val2_26_fu_1377_p2_n_118,p_Val2_26_fu_1377_p2_n_119,p_Val2_26_fu_1377_p2_n_120,p_Val2_26_fu_1377_p2_n_121,p_Val2_26_fu_1377_p2_n_122,p_Val2_26_fu_1377_p2_n_123,p_Val2_26_fu_1377_p2_n_124,p_Val2_26_fu_1377_p2_n_125,p_Val2_26_fu_1377_p2_n_126,p_Val2_26_fu_1377_p2_n_127,p_Val2_26_fu_1377_p2_n_128,p_Val2_26_fu_1377_p2_n_129,p_Val2_26_fu_1377_p2_n_130,p_Val2_26_fu_1377_p2_n_131,p_Val2_26_fu_1377_p2_n_132,p_Val2_26_fu_1377_p2_n_133,p_Val2_26_fu_1377_p2_n_134,p_Val2_26_fu_1377_p2_n_135,p_Val2_26_fu_1377_p2_n_136,p_Val2_26_fu_1377_p2_n_137,p_Val2_26_fu_1377_p2_n_138,p_Val2_26_fu_1377_p2_n_139,p_Val2_26_fu_1377_p2_n_140,p_Val2_26_fu_1377_p2_n_141,p_Val2_26_fu_1377_p2_n_142,p_Val2_26_fu_1377_p2_n_143,p_Val2_26_fu_1377_p2_n_144,p_Val2_26_fu_1377_p2_n_145,p_Val2_26_fu_1377_p2_n_146,p_Val2_26_fu_1377_p2_n_147,p_Val2_26_fu_1377_p2_n_148,p_Val2_26_fu_1377_p2_n_149,p_Val2_26_fu_1377_p2_n_150,p_Val2_26_fu_1377_p2_n_151,p_Val2_26_fu_1377_p2_n_152,p_Val2_26_fu_1377_p2_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_fu_1377_p2_i_1
       (.CI(p_Val2_26_fu_1377_p2_i_2_n_0),
        .CO({p_Val2_26_fu_1377_p2_i_1_n_0,p_Val2_26_fu_1377_p2_i_1_n_1,p_Val2_26_fu_1377_p2_i_1_n_2,p_Val2_26_fu_1377_p2_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[19:16]),
        .O(p_Val2_23_fu_1286_p21_out[19:16]),
        .S({p_Val2_26_fu_1377_p2_i_6_n_0,p_Val2_26_fu_1377_p2_i_7_n_0,p_Val2_26_fu_1377_p2_i_8_n_0,p_Val2_26_fu_1377_p2_i_9_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_10
       (.I0(inputs_current_phase[15]),
        .I1(p_Val2_27_fu_1271_p2[15]),
        .O(p_Val2_26_fu_1377_p2_i_10_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_11
       (.I0(inputs_current_phase[14]),
        .I1(p_Val2_27_fu_1271_p2[14]),
        .O(p_Val2_26_fu_1377_p2_i_11_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_12
       (.I0(inputs_current_phase[13]),
        .I1(p_Val2_27_fu_1271_p2[13]),
        .O(p_Val2_26_fu_1377_p2_i_12_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_13
       (.I0(inputs_current_phase[12]),
        .I1(p_Val2_27_fu_1271_p2[12]),
        .O(p_Val2_26_fu_1377_p2_i_13_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_14
       (.I0(inputs_current_phase[11]),
        .I1(p_Val2_27_fu_1271_p2[11]),
        .O(p_Val2_26_fu_1377_p2_i_14_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_15
       (.I0(inputs_current_phase[10]),
        .I1(p_Val2_27_fu_1271_p2[10]),
        .O(p_Val2_26_fu_1377_p2_i_15_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_16
       (.I0(inputs_current_phase[9]),
        .I1(p_Val2_27_fu_1271_p2[9]),
        .O(p_Val2_26_fu_1377_p2_i_16_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_17
       (.I0(inputs_current_phase[8]),
        .I1(p_Val2_27_fu_1271_p2[8]),
        .O(p_Val2_26_fu_1377_p2_i_17_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_18
       (.I0(inputs_current_phase[7]),
        .I1(p_Val2_27_fu_1271_p2[7]),
        .O(p_Val2_26_fu_1377_p2_i_18_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_19
       (.I0(inputs_current_phase[6]),
        .I1(p_Val2_27_fu_1271_p2[6]),
        .O(p_Val2_26_fu_1377_p2_i_19_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_fu_1377_p2_i_2
       (.CI(p_Val2_26_fu_1377_p2_i_3_n_0),
        .CO({p_Val2_26_fu_1377_p2_i_2_n_0,p_Val2_26_fu_1377_p2_i_2_n_1,p_Val2_26_fu_1377_p2_i_2_n_2,p_Val2_26_fu_1377_p2_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[15:12]),
        .O(p_Val2_23_fu_1286_p21_out[15:12]),
        .S({p_Val2_26_fu_1377_p2_i_10_n_0,p_Val2_26_fu_1377_p2_i_11_n_0,p_Val2_26_fu_1377_p2_i_12_n_0,p_Val2_26_fu_1377_p2_i_13_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_20
       (.I0(inputs_current_phase[5]),
        .I1(p_Val2_27_fu_1271_p2[5]),
        .O(p_Val2_26_fu_1377_p2_i_20_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_21
       (.I0(inputs_current_phase[4]),
        .I1(p_Val2_27_fu_1271_p2[4]),
        .O(p_Val2_26_fu_1377_p2_i_21_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_22
       (.I0(inputs_current_phase[3]),
        .I1(p_Val2_27_fu_1271_p2[3]),
        .O(p_Val2_26_fu_1377_p2_i_22_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_23
       (.I0(inputs_current_phase[2]),
        .I1(p_Val2_27_fu_1271_p2[2]),
        .O(p_Val2_26_fu_1377_p2_i_23_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_24
       (.I0(inputs_current_phase[1]),
        .I1(p_Val2_27_fu_1271_p2[1]),
        .O(p_Val2_26_fu_1377_p2_i_24_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_25
       (.I0(inputs_current_phase[0]),
        .I1(p_Val2_27_fu_1271_p2[0]),
        .O(p_Val2_26_fu_1377_p2_i_25_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_fu_1377_p2_i_3
       (.CI(p_Val2_26_fu_1377_p2_i_4_n_0),
        .CO({p_Val2_26_fu_1377_p2_i_3_n_0,p_Val2_26_fu_1377_p2_i_3_n_1,p_Val2_26_fu_1377_p2_i_3_n_2,p_Val2_26_fu_1377_p2_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[11:8]),
        .O(p_Val2_23_fu_1286_p21_out[11:8]),
        .S({p_Val2_26_fu_1377_p2_i_14_n_0,p_Val2_26_fu_1377_p2_i_15_n_0,p_Val2_26_fu_1377_p2_i_16_n_0,p_Val2_26_fu_1377_p2_i_17_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_fu_1377_p2_i_4
       (.CI(p_Val2_26_fu_1377_p2_i_5_n_0),
        .CO({p_Val2_26_fu_1377_p2_i_4_n_0,p_Val2_26_fu_1377_p2_i_4_n_1,p_Val2_26_fu_1377_p2_i_4_n_2,p_Val2_26_fu_1377_p2_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[7:4]),
        .O(p_Val2_23_fu_1286_p21_out[7:4]),
        .S({p_Val2_26_fu_1377_p2_i_18_n_0,p_Val2_26_fu_1377_p2_i_19_n_0,p_Val2_26_fu_1377_p2_i_20_n_0,p_Val2_26_fu_1377_p2_i_21_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_fu_1377_p2_i_5
       (.CI(\<const0> ),
        .CO({p_Val2_26_fu_1377_p2_i_5_n_0,p_Val2_26_fu_1377_p2_i_5_n_1,p_Val2_26_fu_1377_p2_i_5_n_2,p_Val2_26_fu_1377_p2_i_5_n_3}),
        .CYINIT(\<const1> ),
        .DI(p_Val2_27_fu_1271_p2[3:0]),
        .O(p_Val2_23_fu_1286_p21_out[3:0]),
        .S({p_Val2_26_fu_1377_p2_i_22_n_0,p_Val2_26_fu_1377_p2_i_23_n_0,p_Val2_26_fu_1377_p2_i_24_n_0,p_Val2_26_fu_1377_p2_i_25_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_6
       (.I0(inputs_current_phase[19]),
        .I1(p_Val2_27_fu_1271_p2[19]),
        .O(p_Val2_26_fu_1377_p2_i_6_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_7
       (.I0(inputs_current_phase[18]),
        .I1(p_Val2_27_fu_1271_p2[18]),
        .O(p_Val2_26_fu_1377_p2_i_7_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_8
       (.I0(inputs_current_phase[17]),
        .I1(p_Val2_27_fu_1271_p2[17]),
        .O(p_Val2_26_fu_1377_p2_i_8_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_fu_1377_p2_i_9
       (.I0(inputs_current_phase[16]),
        .I1(p_Val2_27_fu_1271_p2[16]),
        .O(p_Val2_26_fu_1377_p2_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 17x14 3}}" *) 
  DSP48E1 #(
    .ACASCREG(2),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(2),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(0),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_26_reg_1683_reg
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,inputs_H_V_read_reg_1490_pp0_iter3_reg}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({p_Val2_23_fu_1286_p21_out[47],p_Val2_23_fu_1286_p21_out[47],p_Val2_23_fu_1286_p21_out[47],p_Val2_23_fu_1286_p21_out[47],p_Val2_23_fu_1286_p21_out[47:34]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(p_Val2_4_reg_1510),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_26_reg_1683_reg_n_58,p_Val2_26_reg_1683_reg_n_59,p_Val2_26_reg_1683_reg_n_60,p_Val2_26_reg_1683_reg_n_61,p_Val2_26_reg_1683_reg_n_62,p_Val2_26_reg_1683_reg_n_63,p_Val2_26_reg_1683_reg_n_64,p_Val2_26_reg_1683_reg_n_65,p_Val2_26_reg_1683_reg_n_66,p_Val2_26_reg_1683_reg_n_67,p_Val2_26_reg_1683_reg_n_68,p_Val2_26_reg_1683_reg_n_69,p_Val2_26_reg_1683_reg_n_70,p_Val2_26_reg_1683_reg_n_71,p_Val2_26_reg_1683_reg_n_72,p_Val2_26_reg_1683_reg_n_73,p_Val2_26_reg_1683_reg_n_74,p_Val2_26_reg_1683_reg_n_75,p_Val2_26_reg_1683_reg_n_76,p_Val2_26_reg_1683_reg_n_77,p_Val2_26_reg_1683_reg_n_78,p_Val2_26_reg_1683_reg_n_79,p_Val2_26_reg_1683_reg_n_80,p_Val2_26_reg_1683_reg_n_81,p_Val2_26_reg_1683_reg_n_82,p_Val2_26_reg_1683_reg_n_83,p_Val2_26_reg_1683_reg_n_84,p_Val2_26_reg_1683_reg_n_85,p_Val2_26_reg_1683_reg_n_86,p_Val2_26_reg_1683_reg_n_87,p_Val2_26_reg_1683_reg_n_88,p_Val2_26_reg_1683_reg_n_89,p_Val2_26_reg_1683_reg_n_90,p_Val2_26_reg_1683_reg_n_91,p_Val2_26_reg_1683_reg_n_92,p_Val2_26_reg_1683_reg_n_93,p_Val2_26_reg_1683_reg_n_94,p_Val2_26_reg_1683_reg_n_95,p_Val2_26_reg_1683_reg_n_96,p_Val2_26_reg_1683_reg_n_97,p_Val2_26_reg_1683_reg_n_98,p_Val2_26_reg_1683_reg_n_99,p_Val2_26_reg_1683_reg_n_100,p_Val2_26_reg_1683_reg_n_101,p_Val2_26_reg_1683_reg_n_102,p_Val2_26_reg_1683_reg_n_103,p_Val2_26_reg_1683_reg_n_104,p_Val2_26_reg_1683_reg_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_105),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_95),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_94),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_93),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_92),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_91),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_90),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_89),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_104),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_103),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_102),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_101),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_100),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_99),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_98),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_97),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_26_reg_1683_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_26_fu_1377_p2_n_96),
        .Q(\p_Val2_26_reg_1683_reg_n_0_[9] ),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 17x18 3}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_26_reg_1683_reg__1
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_Val2_23_fu_1286_p21_out[33:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,inputs_H_V_read_reg_1490_pp0_iter3_reg}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(p_Val2_4_reg_1510),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_26_reg_1683_reg__1_n_58,p_Val2_26_reg_1683_reg__1_n_59,p_Val2_26_reg_1683_reg__1_n_60,p_Val2_26_reg_1683_reg__1_n_61,p_Val2_26_reg_1683_reg__1_n_62,p_Val2_26_reg_1683_reg__1_n_63,p_Val2_26_reg_1683_reg__1_n_64,p_Val2_26_reg_1683_reg__1_n_65,p_Val2_26_reg_1683_reg__1_n_66,p_Val2_26_reg_1683_reg__1_n_67,p_Val2_26_reg_1683_reg__1_n_68,p_Val2_26_reg_1683_reg__1_n_69,p_Val2_26_reg_1683_reg__1_n_70,p_Val2_26_reg_1683_reg__1_n_71,p_Val2_26_reg_1683_reg__1_n_72,p_Val2_26_reg_1683_reg__1_n_73,p_Val2_26_reg_1683_reg__1_n_74,p_Val2_26_reg_1683_reg__1_n_75,p_Val2_26_reg_1683_reg__1_n_76,p_Val2_26_reg_1683_reg__1_n_77,p_Val2_26_reg_1683_reg__1_n_78,p_Val2_26_reg_1683_reg__1_n_79,p_Val2_26_reg_1683_reg__1_n_80,p_Val2_26_reg_1683_reg__1_n_81,p_Val2_26_reg_1683_reg__1_n_82,p_Val2_26_reg_1683_reg__1_n_83,p_Val2_26_reg_1683_reg__1_n_84,p_Val2_26_reg_1683_reg__1_n_85,p_Val2_26_reg_1683_reg__1_n_86,p_Val2_26_reg_1683_reg__1_n_87,p_Val2_26_reg_1683_reg__1_n_88,p_Val2_26_reg_1683_reg__1_n_89,p_Val2_26_reg_1683_reg__1_n_90,p_Val2_26_reg_1683_reg__1_n_91,p_Val2_26_reg_1683_reg__1_n_92,p_Val2_26_reg_1683_reg__1_n_93,p_Val2_26_reg_1683_reg__1_n_94,p_Val2_26_reg_1683_reg__1_n_95,p_Val2_26_reg_1683_reg__1_n_96,p_Val2_26_reg_1683_reg__1_n_97,p_Val2_26_reg_1683_reg__1_n_98,p_Val2_26_reg_1683_reg__1_n_99,p_Val2_26_reg_1683_reg__1_n_100,p_Val2_26_reg_1683_reg__1_n_101,p_Val2_26_reg_1683_reg__1_n_102,p_Val2_26_reg_1683_reg__1_n_103,p_Val2_26_reg_1683_reg__1_n_104,p_Val2_26_reg_1683_reg__1_n_105}),
        .PCIN({p_Val2_26_fu_1377_p2_n_106,p_Val2_26_fu_1377_p2_n_107,p_Val2_26_fu_1377_p2_n_108,p_Val2_26_fu_1377_p2_n_109,p_Val2_26_fu_1377_p2_n_110,p_Val2_26_fu_1377_p2_n_111,p_Val2_26_fu_1377_p2_n_112,p_Val2_26_fu_1377_p2_n_113,p_Val2_26_fu_1377_p2_n_114,p_Val2_26_fu_1377_p2_n_115,p_Val2_26_fu_1377_p2_n_116,p_Val2_26_fu_1377_p2_n_117,p_Val2_26_fu_1377_p2_n_118,p_Val2_26_fu_1377_p2_n_119,p_Val2_26_fu_1377_p2_n_120,p_Val2_26_fu_1377_p2_n_121,p_Val2_26_fu_1377_p2_n_122,p_Val2_26_fu_1377_p2_n_123,p_Val2_26_fu_1377_p2_n_124,p_Val2_26_fu_1377_p2_n_125,p_Val2_26_fu_1377_p2_n_126,p_Val2_26_fu_1377_p2_n_127,p_Val2_26_fu_1377_p2_n_128,p_Val2_26_fu_1377_p2_n_129,p_Val2_26_fu_1377_p2_n_130,p_Val2_26_fu_1377_p2_n_131,p_Val2_26_fu_1377_p2_n_132,p_Val2_26_fu_1377_p2_n_133,p_Val2_26_fu_1377_p2_n_134,p_Val2_26_fu_1377_p2_n_135,p_Val2_26_fu_1377_p2_n_136,p_Val2_26_fu_1377_p2_n_137,p_Val2_26_fu_1377_p2_n_138,p_Val2_26_fu_1377_p2_n_139,p_Val2_26_fu_1377_p2_n_140,p_Val2_26_fu_1377_p2_n_141,p_Val2_26_fu_1377_p2_n_142,p_Val2_26_fu_1377_p2_n_143,p_Val2_26_fu_1377_p2_n_144,p_Val2_26_fu_1377_p2_n_145,p_Val2_26_fu_1377_p2_n_146,p_Val2_26_fu_1377_p2_n_147,p_Val2_26_fu_1377_p2_n_148,p_Val2_26_fu_1377_p2_n_149,p_Val2_26_fu_1377_p2_n_150,p_Val2_26_fu_1377_p2_n_151,p_Val2_26_fu_1377_p2_n_152,p_Val2_26_fu_1377_p2_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg__1_i_1
       (.CI(p_Val2_26_reg_1683_reg__1_i_2_n_0),
        .CO({p_Val2_26_reg_1683_reg__1_i_1_n_0,p_Val2_26_reg_1683_reg__1_i_1_n_1,p_Val2_26_reg_1683_reg__1_i_1_n_2,p_Val2_26_reg_1683_reg__1_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[31:28]),
        .O(p_Val2_23_fu_1286_p21_out[31:28]),
        .S({p_Val2_26_reg_1683_reg__1_i_4_n_0,p_Val2_26_reg_1683_reg__1_i_5_n_0,p_Val2_26_reg_1683_reg__1_i_6_n_0,p_Val2_26_reg_1683_reg__1_i_7_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_10
       (.I0(inputs_current_phase[25]),
        .I1(p_Val2_27_fu_1271_p2[25]),
        .O(p_Val2_26_reg_1683_reg__1_i_10_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_11
       (.I0(inputs_current_phase[24]),
        .I1(p_Val2_27_fu_1271_p2[24]),
        .O(p_Val2_26_reg_1683_reg__1_i_11_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_12
       (.I0(inputs_current_phase[23]),
        .I1(p_Val2_27_fu_1271_p2[23]),
        .O(p_Val2_26_reg_1683_reg__1_i_12_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_13
       (.I0(inputs_current_phase[22]),
        .I1(p_Val2_27_fu_1271_p2[22]),
        .O(p_Val2_26_reg_1683_reg__1_i_13_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_14
       (.I0(inputs_current_phase[21]),
        .I1(p_Val2_27_fu_1271_p2[21]),
        .O(p_Val2_26_reg_1683_reg__1_i_14_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_15
       (.I0(inputs_current_phase[20]),
        .I1(p_Val2_27_fu_1271_p2[20]),
        .O(p_Val2_26_reg_1683_reg__1_i_15_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg__1_i_2
       (.CI(p_Val2_26_reg_1683_reg__1_i_3_n_0),
        .CO({p_Val2_26_reg_1683_reg__1_i_2_n_0,p_Val2_26_reg_1683_reg__1_i_2_n_1,p_Val2_26_reg_1683_reg__1_i_2_n_2,p_Val2_26_reg_1683_reg__1_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[27:24]),
        .O(p_Val2_23_fu_1286_p21_out[27:24]),
        .S({p_Val2_26_reg_1683_reg__1_i_8_n_0,p_Val2_26_reg_1683_reg__1_i_9_n_0,p_Val2_26_reg_1683_reg__1_i_10_n_0,p_Val2_26_reg_1683_reg__1_i_11_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg__1_i_3
       (.CI(p_Val2_26_fu_1377_p2_i_1_n_0),
        .CO({p_Val2_26_reg_1683_reg__1_i_3_n_0,p_Val2_26_reg_1683_reg__1_i_3_n_1,p_Val2_26_reg_1683_reg__1_i_3_n_2,p_Val2_26_reg_1683_reg__1_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[23:20]),
        .O(p_Val2_23_fu_1286_p21_out[23:20]),
        .S({p_Val2_26_reg_1683_reg__1_i_12_n_0,p_Val2_26_reg_1683_reg__1_i_13_n_0,p_Val2_26_reg_1683_reg__1_i_14_n_0,p_Val2_26_reg_1683_reg__1_i_15_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_4
       (.I0(inputs_current_phase[31]),
        .I1(p_Val2_27_fu_1271_p2[31]),
        .O(p_Val2_26_reg_1683_reg__1_i_4_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_5
       (.I0(inputs_current_phase[30]),
        .I1(p_Val2_27_fu_1271_p2[30]),
        .O(p_Val2_26_reg_1683_reg__1_i_5_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_6
       (.I0(inputs_current_phase[29]),
        .I1(p_Val2_27_fu_1271_p2[29]),
        .O(p_Val2_26_reg_1683_reg__1_i_6_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_7
       (.I0(inputs_current_phase[28]),
        .I1(p_Val2_27_fu_1271_p2[28]),
        .O(p_Val2_26_reg_1683_reg__1_i_7_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_8
       (.I0(inputs_current_phase[27]),
        .I1(p_Val2_27_fu_1271_p2[27]),
        .O(p_Val2_26_reg_1683_reg__1_i_8_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg__1_i_9
       (.I0(inputs_current_phase[26]),
        .I1(p_Val2_27_fu_1271_p2[26]),
        .O(p_Val2_26_reg_1683_reg__1_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg_i_1
       (.CI(p_Val2_26_reg_1683_reg_i_2_n_0),
        .CO({p_Val2_26_reg_1683_reg_i_1_n_1,p_Val2_26_reg_1683_reg_i_1_n_2,p_Val2_26_reg_1683_reg_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_Val2_27_fu_1271_p2[46:44]}),
        .O(p_Val2_23_fu_1286_p21_out[47:44]),
        .S({p_Val2_26_reg_1683_reg_i_5_n_0,p_Val2_26_reg_1683_reg_i_6_n_0,p_Val2_26_reg_1683_reg_i_7_n_0,p_Val2_26_reg_1683_reg_i_8_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_10
       (.I0(inputs_current_phase[42]),
        .I1(p_Val2_27_fu_1271_p2[42]),
        .O(p_Val2_26_reg_1683_reg_i_10_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_11
       (.I0(inputs_current_phase[41]),
        .I1(p_Val2_27_fu_1271_p2[41]),
        .O(p_Val2_26_reg_1683_reg_i_11_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_12
       (.I0(inputs_current_phase[40]),
        .I1(p_Val2_27_fu_1271_p2[40]),
        .O(p_Val2_26_reg_1683_reg_i_12_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_13
       (.I0(inputs_current_phase[39]),
        .I1(p_Val2_27_fu_1271_p2[39]),
        .O(p_Val2_26_reg_1683_reg_i_13_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_14
       (.I0(inputs_current_phase[38]),
        .I1(p_Val2_27_fu_1271_p2[38]),
        .O(p_Val2_26_reg_1683_reg_i_14_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_15
       (.I0(inputs_current_phase[37]),
        .I1(p_Val2_27_fu_1271_p2[37]),
        .O(p_Val2_26_reg_1683_reg_i_15_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_16
       (.I0(inputs_current_phase[36]),
        .I1(p_Val2_27_fu_1271_p2[36]),
        .O(p_Val2_26_reg_1683_reg_i_16_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_17
       (.I0(inputs_current_phase[35]),
        .I1(p_Val2_27_fu_1271_p2[35]),
        .O(p_Val2_26_reg_1683_reg_i_17_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_18
       (.I0(inputs_current_phase[34]),
        .I1(p_Val2_27_fu_1271_p2[34]),
        .O(p_Val2_26_reg_1683_reg_i_18_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_19
       (.I0(inputs_current_phase[33]),
        .I1(p_Val2_27_fu_1271_p2[33]),
        .O(p_Val2_26_reg_1683_reg_i_19_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg_i_2
       (.CI(p_Val2_26_reg_1683_reg_i_3_n_0),
        .CO({p_Val2_26_reg_1683_reg_i_2_n_0,p_Val2_26_reg_1683_reg_i_2_n_1,p_Val2_26_reg_1683_reg_i_2_n_2,p_Val2_26_reg_1683_reg_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[43:40]),
        .O(p_Val2_23_fu_1286_p21_out[43:40]),
        .S({p_Val2_26_reg_1683_reg_i_9_n_0,p_Val2_26_reg_1683_reg_i_10_n_0,p_Val2_26_reg_1683_reg_i_11_n_0,p_Val2_26_reg_1683_reg_i_12_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_20
       (.I0(inputs_current_phase[32]),
        .I1(p_Val2_27_fu_1271_p2[32]),
        .O(p_Val2_26_reg_1683_reg_i_20_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg_i_3
       (.CI(p_Val2_26_reg_1683_reg_i_4_n_0),
        .CO({p_Val2_26_reg_1683_reg_i_3_n_0,p_Val2_26_reg_1683_reg_i_3_n_1,p_Val2_26_reg_1683_reg_i_3_n_2,p_Val2_26_reg_1683_reg_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[39:36]),
        .O(p_Val2_23_fu_1286_p21_out[39:36]),
        .S({p_Val2_26_reg_1683_reg_i_13_n_0,p_Val2_26_reg_1683_reg_i_14_n_0,p_Val2_26_reg_1683_reg_i_15_n_0,p_Val2_26_reg_1683_reg_i_16_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_26_reg_1683_reg_i_4
       (.CI(p_Val2_26_reg_1683_reg__1_i_1_n_0),
        .CO({p_Val2_26_reg_1683_reg_i_4_n_0,p_Val2_26_reg_1683_reg_i_4_n_1,p_Val2_26_reg_1683_reg_i_4_n_2,p_Val2_26_reg_1683_reg_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[35:32]),
        .O(p_Val2_23_fu_1286_p21_out[35:32]),
        .S({p_Val2_26_reg_1683_reg_i_17_n_0,p_Val2_26_reg_1683_reg_i_18_n_0,p_Val2_26_reg_1683_reg_i_19_n_0,p_Val2_26_reg_1683_reg_i_20_n_0}));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_5
       (.I0(inputs_current_phase[47]),
        .I1(p_Val2_27_fu_1271_p2[47]),
        .O(p_Val2_26_reg_1683_reg_i_5_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_6
       (.I0(inputs_current_phase[46]),
        .I1(p_Val2_27_fu_1271_p2[46]),
        .O(p_Val2_26_reg_1683_reg_i_6_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_7
       (.I0(inputs_current_phase[45]),
        .I1(p_Val2_27_fu_1271_p2[45]),
        .O(p_Val2_26_reg_1683_reg_i_7_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_8
       (.I0(inputs_current_phase[44]),
        .I1(p_Val2_27_fu_1271_p2[44]),
        .O(p_Val2_26_reg_1683_reg_i_8_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    p_Val2_26_reg_1683_reg_i_9
       (.I0(inputs_current_phase[43]),
        .I1(p_Val2_27_fu_1271_p2[43]),
        .O(p_Val2_26_reg_1683_reg_i_9_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[11]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[11]),
        .I1(p_1_in[11]),
        .O(\p_Val2_27_reg_1649[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[11]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[10]),
        .I1(p_1_in[10]),
        .O(\p_Val2_27_reg_1649[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[11]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[9]),
        .I1(p_1_in[9]),
        .O(\p_Val2_27_reg_1649[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[11]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[8]),
        .I1(p_1_in[8]),
        .O(\p_Val2_27_reg_1649[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[15]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[15]),
        .I1(p_1_in[15]),
        .O(\p_Val2_27_reg_1649[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[15]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[14]),
        .I1(p_1_in[14]),
        .O(\p_Val2_27_reg_1649[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[15]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[13]),
        .I1(p_1_in[13]),
        .O(\p_Val2_27_reg_1649[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[15]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[12]),
        .I1(p_1_in[12]),
        .O(\p_Val2_27_reg_1649[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[19]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[19]),
        .I1(p_1_in[19]),
        .O(\p_Val2_27_reg_1649[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[19]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[18]),
        .I1(p_1_in[18]),
        .O(\p_Val2_27_reg_1649[19]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[19]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[17]),
        .I1(p_1_in[17]),
        .O(\p_Val2_27_reg_1649[19]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[19]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[16]),
        .I1(p_1_in[16]),
        .O(\p_Val2_27_reg_1649[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[23]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[23]),
        .I1(p_1_in[23]),
        .O(\p_Val2_27_reg_1649[23]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[23]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[22]),
        .I1(p_1_in[22]),
        .O(\p_Val2_27_reg_1649[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[23]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[21]),
        .I1(p_1_in[21]),
        .O(\p_Val2_27_reg_1649[23]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[23]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[20]),
        .I1(p_1_in[20]),
        .O(\p_Val2_27_reg_1649[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[27]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[27]),
        .I1(p_1_in[27]),
        .O(\p_Val2_27_reg_1649[27]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[27]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[26]),
        .I1(p_1_in[26]),
        .O(\p_Val2_27_reg_1649[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[27]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[25]),
        .I1(p_1_in[25]),
        .O(\p_Val2_27_reg_1649[27]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[27]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[24]),
        .I1(p_1_in[24]),
        .O(\p_Val2_27_reg_1649[27]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[31]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[31]),
        .I1(p_1_in[31]),
        .O(\p_Val2_27_reg_1649[31]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[31]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[30]),
        .I1(p_1_in[30]),
        .O(\p_Val2_27_reg_1649[31]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[31]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[29]),
        .I1(p_1_in[29]),
        .O(\p_Val2_27_reg_1649[31]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[31]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[28]),
        .I1(p_1_in[28]),
        .O(\p_Val2_27_reg_1649[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[35]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[35]),
        .I1(p_1_in[35]),
        .O(\p_Val2_27_reg_1649[35]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[35]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[34]),
        .I1(p_1_in[34]),
        .O(\p_Val2_27_reg_1649[35]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[35]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[33]),
        .I1(p_1_in[33]),
        .O(\p_Val2_27_reg_1649[35]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[35]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[32]),
        .I1(p_1_in[32]),
        .O(\p_Val2_27_reg_1649[35]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[39]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[39]),
        .I1(p_1_in[39]),
        .O(\p_Val2_27_reg_1649[39]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[39]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[38]),
        .I1(p_1_in[38]),
        .O(\p_Val2_27_reg_1649[39]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[39]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[37]),
        .I1(p_1_in[37]),
        .O(\p_Val2_27_reg_1649[39]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[39]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[36]),
        .I1(p_1_in[36]),
        .O(\p_Val2_27_reg_1649[39]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[3]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[3]),
        .I1(p_1_in[3]),
        .O(\p_Val2_27_reg_1649[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[3]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[2]),
        .I1(p_1_in[2]),
        .O(\p_Val2_27_reg_1649[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[3]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[1]),
        .I1(p_1_in[1]),
        .O(\p_Val2_27_reg_1649[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[3]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[0]),
        .I1(p_1_in[0]),
        .O(\p_Val2_27_reg_1649[3]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \p_Val2_27_reg_1649[43]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[43]),
        .I1(\acc_H1_FSK_V[43]_i_2_n_0 ),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(\p_Val2_27_reg_1649[43]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \p_Val2_27_reg_1649[43]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[42]),
        .I1(\acc_H1_FSK_V[42]_i_2_n_0 ),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(\p_Val2_27_reg_1649[43]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[43]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[41]),
        .I1(p_1_in[41]),
        .O(\p_Val2_27_reg_1649[43]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[43]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[40]),
        .I1(p_1_in[40]),
        .O(\p_Val2_27_reg_1649[43]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \p_Val2_27_reg_1649[47]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[47]),
        .I1(\acc_H1_FSK_V[47]_i_5_n_0 ),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(\p_Val2_27_reg_1649[47]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \p_Val2_27_reg_1649[47]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[46]),
        .I1(\acc_H1_FSK_V[46]_i_2_n_0 ),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(\p_Val2_27_reg_1649[47]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \p_Val2_27_reg_1649[47]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[45]),
        .I1(\acc_H1_FSK_V[45]_i_2_n_0 ),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(\p_Val2_27_reg_1649[47]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \p_Val2_27_reg_1649[47]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[44]),
        .I1(\acc_H1_FSK_V[44]_i_2_n_0 ),
        .I2(inputs_current_reset_3_reg_1615_pp0_iter4_reg),
        .O(\p_Val2_27_reg_1649[47]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[7]_i_2 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[7]),
        .I1(p_1_in[7]),
        .O(\p_Val2_27_reg_1649[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[7]_i_3 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[6]),
        .I1(p_1_in[6]),
        .O(\p_Val2_27_reg_1649[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[7]_i_4 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[5]),
        .I1(p_1_in[5]),
        .O(\p_Val2_27_reg_1649[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \p_Val2_27_reg_1649[7]_i_5 
       (.I0(p_Val2_15_reg_1581_pp0_iter4_reg[4]),
        .I1(p_1_in[4]),
        .O(\p_Val2_27_reg_1649[7]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[0]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[10]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[11]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[12]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[13]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[14]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[15]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[16]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[17]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[18]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[19]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[1]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[20]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[21]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[22]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[23]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[24]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[25]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[26]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[27]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[28]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[29]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[2]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[30]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[31]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[32]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[33]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[34]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[35]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[36]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[37]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[38]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[39]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[3]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[40]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[41]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[42]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[43]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[44]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[45]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[46]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[47]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[4]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[5]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[6]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[7]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[8]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_reg_1649[9]),
        .Q(p_Val2_27_reg_1649_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[0]),
        .Q(p_Val2_27_reg_1649[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[10]),
        .Q(p_Val2_27_reg_1649[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[11]),
        .Q(p_Val2_27_reg_1649[11]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[11]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[7]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[11]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[11]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[11]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[11]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[11:8]),
        .O(p_Val2_27_fu_1271_p2[11:8]),
        .S({\p_Val2_27_reg_1649[11]_i_2_n_0 ,\p_Val2_27_reg_1649[11]_i_3_n_0 ,\p_Val2_27_reg_1649[11]_i_4_n_0 ,\p_Val2_27_reg_1649[11]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[12]),
        .Q(p_Val2_27_reg_1649[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[13]),
        .Q(p_Val2_27_reg_1649[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[14]),
        .Q(p_Val2_27_reg_1649[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[15]),
        .Q(p_Val2_27_reg_1649[15]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[15]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[11]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[15]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[15]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[15]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[15]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[15:12]),
        .O(p_Val2_27_fu_1271_p2[15:12]),
        .S({\p_Val2_27_reg_1649[15]_i_2_n_0 ,\p_Val2_27_reg_1649[15]_i_3_n_0 ,\p_Val2_27_reg_1649[15]_i_4_n_0 ,\p_Val2_27_reg_1649[15]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[16]),
        .Q(p_Val2_27_reg_1649[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[17]),
        .Q(p_Val2_27_reg_1649[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[18]),
        .Q(p_Val2_27_reg_1649[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[19]),
        .Q(p_Val2_27_reg_1649[19]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[19]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[15]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[19]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[19]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[19]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[19]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[19:16]),
        .O(p_Val2_27_fu_1271_p2[19:16]),
        .S({\p_Val2_27_reg_1649[19]_i_2_n_0 ,\p_Val2_27_reg_1649[19]_i_3_n_0 ,\p_Val2_27_reg_1649[19]_i_4_n_0 ,\p_Val2_27_reg_1649[19]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[1]),
        .Q(p_Val2_27_reg_1649[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[20]),
        .Q(p_Val2_27_reg_1649[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[21]),
        .Q(p_Val2_27_reg_1649[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[22]),
        .Q(p_Val2_27_reg_1649[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[23]),
        .Q(p_Val2_27_reg_1649[23]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[23]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[19]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[23]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[23]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[23]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[23]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[23:20]),
        .O(p_Val2_27_fu_1271_p2[23:20]),
        .S({\p_Val2_27_reg_1649[23]_i_2_n_0 ,\p_Val2_27_reg_1649[23]_i_3_n_0 ,\p_Val2_27_reg_1649[23]_i_4_n_0 ,\p_Val2_27_reg_1649[23]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[24]),
        .Q(p_Val2_27_reg_1649[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[25]),
        .Q(p_Val2_27_reg_1649[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[26]),
        .Q(p_Val2_27_reg_1649[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[27]),
        .Q(p_Val2_27_reg_1649[27]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[27]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[23]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[27]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[27]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[27]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[27]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[27:24]),
        .O(p_Val2_27_fu_1271_p2[27:24]),
        .S({\p_Val2_27_reg_1649[27]_i_2_n_0 ,\p_Val2_27_reg_1649[27]_i_3_n_0 ,\p_Val2_27_reg_1649[27]_i_4_n_0 ,\p_Val2_27_reg_1649[27]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[28]),
        .Q(p_Val2_27_reg_1649[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[29]),
        .Q(p_Val2_27_reg_1649[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[2]),
        .Q(p_Val2_27_reg_1649[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[30]),
        .Q(p_Val2_27_reg_1649[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[31]),
        .Q(p_Val2_27_reg_1649[31]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[31]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[27]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[31]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[31]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[31]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[31]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[31:28]),
        .O(p_Val2_27_fu_1271_p2[31:28]),
        .S({\p_Val2_27_reg_1649[31]_i_2_n_0 ,\p_Val2_27_reg_1649[31]_i_3_n_0 ,\p_Val2_27_reg_1649[31]_i_4_n_0 ,\p_Val2_27_reg_1649[31]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[32]),
        .Q(p_Val2_27_reg_1649[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[33]),
        .Q(p_Val2_27_reg_1649[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[34]),
        .Q(p_Val2_27_reg_1649[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[35]),
        .Q(p_Val2_27_reg_1649[35]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[35]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[31]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[35]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[35]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[35]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[35]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[35:32]),
        .O(p_Val2_27_fu_1271_p2[35:32]),
        .S({\p_Val2_27_reg_1649[35]_i_2_n_0 ,\p_Val2_27_reg_1649[35]_i_3_n_0 ,\p_Val2_27_reg_1649[35]_i_4_n_0 ,\p_Val2_27_reg_1649[35]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[36]),
        .Q(p_Val2_27_reg_1649[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[37]),
        .Q(p_Val2_27_reg_1649[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[38]),
        .Q(p_Val2_27_reg_1649[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[39]),
        .Q(p_Val2_27_reg_1649[39]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[39]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[35]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[39]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[39]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[39]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[39]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[39:36]),
        .O(p_Val2_27_fu_1271_p2[39:36]),
        .S({\p_Val2_27_reg_1649[39]_i_2_n_0 ,\p_Val2_27_reg_1649[39]_i_3_n_0 ,\p_Val2_27_reg_1649[39]_i_4_n_0 ,\p_Val2_27_reg_1649[39]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[3]),
        .Q(p_Val2_27_reg_1649[3]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[3]_i_1 
       (.CI(\<const0> ),
        .CO({\p_Val2_27_reg_1649_reg[3]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[3]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[3]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[3]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[3:0]),
        .O(p_Val2_27_fu_1271_p2[3:0]),
        .S({\p_Val2_27_reg_1649[3]_i_2_n_0 ,\p_Val2_27_reg_1649[3]_i_3_n_0 ,\p_Val2_27_reg_1649[3]_i_4_n_0 ,\p_Val2_27_reg_1649[3]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[40]),
        .Q(p_Val2_27_reg_1649[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[41]),
        .Q(p_Val2_27_reg_1649[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[42]),
        .Q(p_Val2_27_reg_1649[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[43]),
        .Q(p_Val2_27_reg_1649[43]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[43]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[39]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[43]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[43]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[43]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[43]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[43:40]),
        .O(p_Val2_27_fu_1271_p2[43:40]),
        .S({\p_Val2_27_reg_1649[43]_i_2_n_0 ,\p_Val2_27_reg_1649[43]_i_3_n_0 ,\p_Val2_27_reg_1649[43]_i_4_n_0 ,\p_Val2_27_reg_1649[43]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[44]),
        .Q(p_Val2_27_reg_1649[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[45]),
        .Q(p_Val2_27_reg_1649[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[46]),
        .Q(p_Val2_27_reg_1649[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[47]),
        .Q(p_Val2_27_reg_1649[47]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[47]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[43]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[47]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[47]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[47]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_Val2_15_reg_1581_pp0_iter4_reg[46:44]}),
        .O(p_Val2_27_fu_1271_p2[47:44]),
        .S({\p_Val2_27_reg_1649[47]_i_2_n_0 ,\p_Val2_27_reg_1649[47]_i_3_n_0 ,\p_Val2_27_reg_1649[47]_i_4_n_0 ,\p_Val2_27_reg_1649[47]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[4]),
        .Q(p_Val2_27_reg_1649[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[5]),
        .Q(p_Val2_27_reg_1649[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[6]),
        .Q(p_Val2_27_reg_1649[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[7]),
        .Q(p_Val2_27_reg_1649[7]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \p_Val2_27_reg_1649_reg[7]_i_1 
       (.CI(\p_Val2_27_reg_1649_reg[3]_i_1_n_0 ),
        .CO({\p_Val2_27_reg_1649_reg[7]_i_1_n_0 ,\p_Val2_27_reg_1649_reg[7]_i_1_n_1 ,\p_Val2_27_reg_1649_reg[7]_i_1_n_2 ,\p_Val2_27_reg_1649_reg[7]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_Val2_15_reg_1581_pp0_iter4_reg[7:4]),
        .O(p_Val2_27_fu_1271_p2[7:4]),
        .S({\p_Val2_27_reg_1649[7]_i_2_n_0 ,\p_Val2_27_reg_1649[7]_i_3_n_0 ,\p_Val2_27_reg_1649[7]_i_4_n_0 ,\p_Val2_27_reg_1649[7]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[8]),
        .Q(p_Val2_27_reg_1649[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_27_reg_1649_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_27_fu_1271_p2[9]),
        .Q(p_Val2_27_reg_1649[9]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 17x18 3}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(0),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_30_fu_1372_p2
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_Val2_29_fu_1280_p2[16:0]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,inputs_H_V_read_reg_1490_pp0_iter3_reg}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(p_Val2_4_reg_1510),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(\<const0> ),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_30_fu_1372_p2_n_58,p_Val2_30_fu_1372_p2_n_59,p_Val2_30_fu_1372_p2_n_60,p_Val2_30_fu_1372_p2_n_61,p_Val2_30_fu_1372_p2_n_62,p_Val2_30_fu_1372_p2_n_63,p_Val2_30_fu_1372_p2_n_64,p_Val2_30_fu_1372_p2_n_65,p_Val2_30_fu_1372_p2_n_66,p_Val2_30_fu_1372_p2_n_67,p_Val2_30_fu_1372_p2_n_68,p_Val2_30_fu_1372_p2_n_69,p_Val2_30_fu_1372_p2_n_70,p_Val2_30_fu_1372_p2_n_71,p_Val2_30_fu_1372_p2_n_72,p_Val2_30_fu_1372_p2_n_73,p_Val2_30_fu_1372_p2_n_74,p_Val2_30_fu_1372_p2_n_75,p_Val2_30_fu_1372_p2_n_76,p_Val2_30_fu_1372_p2_n_77,p_Val2_30_fu_1372_p2_n_78,p_Val2_30_fu_1372_p2_n_79,p_Val2_30_fu_1372_p2_n_80,p_Val2_30_fu_1372_p2_n_81,p_Val2_30_fu_1372_p2_n_82,p_Val2_30_fu_1372_p2_n_83,p_Val2_30_fu_1372_p2_n_84,p_Val2_30_fu_1372_p2_n_85,p_Val2_30_fu_1372_p2_n_86,p_Val2_30_fu_1372_p2_n_87,p_Val2_30_fu_1372_p2_n_88,p_Val2_30_fu_1372_p2_n_89,p_Val2_30_fu_1372_p2_n_90,p_Val2_30_fu_1372_p2_n_91,p_Val2_30_fu_1372_p2_n_92,p_Val2_30_fu_1372_p2_n_93,p_Val2_30_fu_1372_p2_n_94,p_Val2_30_fu_1372_p2_n_95,p_Val2_30_fu_1372_p2_n_96,p_Val2_30_fu_1372_p2_n_97,p_Val2_30_fu_1372_p2_n_98,p_Val2_30_fu_1372_p2_n_99,p_Val2_30_fu_1372_p2_n_100,p_Val2_30_fu_1372_p2_n_101,p_Val2_30_fu_1372_p2_n_102,p_Val2_30_fu_1372_p2_n_103,p_Val2_30_fu_1372_p2_n_104,p_Val2_30_fu_1372_p2_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .PCOUT({p_Val2_30_fu_1372_p2_n_106,p_Val2_30_fu_1372_p2_n_107,p_Val2_30_fu_1372_p2_n_108,p_Val2_30_fu_1372_p2_n_109,p_Val2_30_fu_1372_p2_n_110,p_Val2_30_fu_1372_p2_n_111,p_Val2_30_fu_1372_p2_n_112,p_Val2_30_fu_1372_p2_n_113,p_Val2_30_fu_1372_p2_n_114,p_Val2_30_fu_1372_p2_n_115,p_Val2_30_fu_1372_p2_n_116,p_Val2_30_fu_1372_p2_n_117,p_Val2_30_fu_1372_p2_n_118,p_Val2_30_fu_1372_p2_n_119,p_Val2_30_fu_1372_p2_n_120,p_Val2_30_fu_1372_p2_n_121,p_Val2_30_fu_1372_p2_n_122,p_Val2_30_fu_1372_p2_n_123,p_Val2_30_fu_1372_p2_n_124,p_Val2_30_fu_1372_p2_n_125,p_Val2_30_fu_1372_p2_n_126,p_Val2_30_fu_1372_p2_n_127,p_Val2_30_fu_1372_p2_n_128,p_Val2_30_fu_1372_p2_n_129,p_Val2_30_fu_1372_p2_n_130,p_Val2_30_fu_1372_p2_n_131,p_Val2_30_fu_1372_p2_n_132,p_Val2_30_fu_1372_p2_n_133,p_Val2_30_fu_1372_p2_n_134,p_Val2_30_fu_1372_p2_n_135,p_Val2_30_fu_1372_p2_n_136,p_Val2_30_fu_1372_p2_n_137,p_Val2_30_fu_1372_p2_n_138,p_Val2_30_fu_1372_p2_n_139,p_Val2_30_fu_1372_p2_n_140,p_Val2_30_fu_1372_p2_n_141,p_Val2_30_fu_1372_p2_n_142,p_Val2_30_fu_1372_p2_n_143,p_Val2_30_fu_1372_p2_n_144,p_Val2_30_fu_1372_p2_n_145,p_Val2_30_fu_1372_p2_n_146,p_Val2_30_fu_1372_p2_n_147,p_Val2_30_fu_1372_p2_n_148,p_Val2_30_fu_1372_p2_n_149,p_Val2_30_fu_1372_p2_n_150,p_Val2_30_fu_1372_p2_n_151,p_Val2_30_fu_1372_p2_n_152,p_Val2_30_fu_1372_p2_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(\<const0> ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_fu_1372_p2_i_1
       (.CI(p_Val2_30_fu_1372_p2_i_2_n_0),
        .CO({p_Val2_30_fu_1372_p2_i_1_n_0,p_Val2_30_fu_1372_p2_i_1_n_1,p_Val2_30_fu_1372_p2_i_1_n_2,p_Val2_30_fu_1372_p2_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[19:16]),
        .O(p_Val2_29_fu_1280_p2[19:16]),
        .S({p_Val2_30_fu_1372_p2_i_6_n_0,p_Val2_30_fu_1372_p2_i_7_n_0,p_Val2_30_fu_1372_p2_i_8_n_0,p_Val2_30_fu_1372_p2_i_9_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_10
       (.I0(p_Val2_27_fu_1271_p2[15]),
        .I1(inputs_current_phase[15]),
        .O(p_Val2_30_fu_1372_p2_i_10_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_11
       (.I0(p_Val2_27_fu_1271_p2[14]),
        .I1(inputs_current_phase[14]),
        .O(p_Val2_30_fu_1372_p2_i_11_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_12
       (.I0(p_Val2_27_fu_1271_p2[13]),
        .I1(inputs_current_phase[13]),
        .O(p_Val2_30_fu_1372_p2_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_13
       (.I0(p_Val2_27_fu_1271_p2[12]),
        .I1(inputs_current_phase[12]),
        .O(p_Val2_30_fu_1372_p2_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_14
       (.I0(p_Val2_27_fu_1271_p2[11]),
        .I1(inputs_current_phase[11]),
        .O(p_Val2_30_fu_1372_p2_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_15
       (.I0(p_Val2_27_fu_1271_p2[10]),
        .I1(inputs_current_phase[10]),
        .O(p_Val2_30_fu_1372_p2_i_15_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_16
       (.I0(p_Val2_27_fu_1271_p2[9]),
        .I1(inputs_current_phase[9]),
        .O(p_Val2_30_fu_1372_p2_i_16_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_17
       (.I0(p_Val2_27_fu_1271_p2[8]),
        .I1(inputs_current_phase[8]),
        .O(p_Val2_30_fu_1372_p2_i_17_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_18
       (.I0(p_Val2_27_fu_1271_p2[7]),
        .I1(inputs_current_phase[7]),
        .O(p_Val2_30_fu_1372_p2_i_18_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_19
       (.I0(p_Val2_27_fu_1271_p2[6]),
        .I1(inputs_current_phase[6]),
        .O(p_Val2_30_fu_1372_p2_i_19_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_fu_1372_p2_i_2
       (.CI(p_Val2_30_fu_1372_p2_i_3_n_0),
        .CO({p_Val2_30_fu_1372_p2_i_2_n_0,p_Val2_30_fu_1372_p2_i_2_n_1,p_Val2_30_fu_1372_p2_i_2_n_2,p_Val2_30_fu_1372_p2_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[15:12]),
        .O(p_Val2_29_fu_1280_p2[15:12]),
        .S({p_Val2_30_fu_1372_p2_i_10_n_0,p_Val2_30_fu_1372_p2_i_11_n_0,p_Val2_30_fu_1372_p2_i_12_n_0,p_Val2_30_fu_1372_p2_i_13_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_20
       (.I0(p_Val2_27_fu_1271_p2[5]),
        .I1(inputs_current_phase[5]),
        .O(p_Val2_30_fu_1372_p2_i_20_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_21
       (.I0(p_Val2_27_fu_1271_p2[4]),
        .I1(inputs_current_phase[4]),
        .O(p_Val2_30_fu_1372_p2_i_21_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_22
       (.I0(p_Val2_27_fu_1271_p2[3]),
        .I1(inputs_current_phase[3]),
        .O(p_Val2_30_fu_1372_p2_i_22_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_23
       (.I0(p_Val2_27_fu_1271_p2[2]),
        .I1(inputs_current_phase[2]),
        .O(p_Val2_30_fu_1372_p2_i_23_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_24
       (.I0(p_Val2_27_fu_1271_p2[1]),
        .I1(inputs_current_phase[1]),
        .O(p_Val2_30_fu_1372_p2_i_24_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_25
       (.I0(p_Val2_27_fu_1271_p2[0]),
        .I1(inputs_current_phase[0]),
        .O(p_Val2_30_fu_1372_p2_i_25_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_fu_1372_p2_i_3
       (.CI(p_Val2_30_fu_1372_p2_i_4_n_0),
        .CO({p_Val2_30_fu_1372_p2_i_3_n_0,p_Val2_30_fu_1372_p2_i_3_n_1,p_Val2_30_fu_1372_p2_i_3_n_2,p_Val2_30_fu_1372_p2_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[11:8]),
        .O(p_Val2_29_fu_1280_p2[11:8]),
        .S({p_Val2_30_fu_1372_p2_i_14_n_0,p_Val2_30_fu_1372_p2_i_15_n_0,p_Val2_30_fu_1372_p2_i_16_n_0,p_Val2_30_fu_1372_p2_i_17_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_fu_1372_p2_i_4
       (.CI(p_Val2_30_fu_1372_p2_i_5_n_0),
        .CO({p_Val2_30_fu_1372_p2_i_4_n_0,p_Val2_30_fu_1372_p2_i_4_n_1,p_Val2_30_fu_1372_p2_i_4_n_2,p_Val2_30_fu_1372_p2_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[7:4]),
        .O(p_Val2_29_fu_1280_p2[7:4]),
        .S({p_Val2_30_fu_1372_p2_i_18_n_0,p_Val2_30_fu_1372_p2_i_19_n_0,p_Val2_30_fu_1372_p2_i_20_n_0,p_Val2_30_fu_1372_p2_i_21_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_fu_1372_p2_i_5
       (.CI(\<const0> ),
        .CO({p_Val2_30_fu_1372_p2_i_5_n_0,p_Val2_30_fu_1372_p2_i_5_n_1,p_Val2_30_fu_1372_p2_i_5_n_2,p_Val2_30_fu_1372_p2_i_5_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[3:0]),
        .O(p_Val2_29_fu_1280_p2[3:0]),
        .S({p_Val2_30_fu_1372_p2_i_22_n_0,p_Val2_30_fu_1372_p2_i_23_n_0,p_Val2_30_fu_1372_p2_i_24_n_0,p_Val2_30_fu_1372_p2_i_25_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_6
       (.I0(p_Val2_27_fu_1271_p2[19]),
        .I1(inputs_current_phase[19]),
        .O(p_Val2_30_fu_1372_p2_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_7
       (.I0(p_Val2_27_fu_1271_p2[18]),
        .I1(inputs_current_phase[18]),
        .O(p_Val2_30_fu_1372_p2_i_7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_8
       (.I0(p_Val2_27_fu_1271_p2[17]),
        .I1(inputs_current_phase[17]),
        .O(p_Val2_30_fu_1372_p2_i_8_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_fu_1372_p2_i_9
       (.I0(p_Val2_27_fu_1271_p2[16]),
        .I1(inputs_current_phase[16]),
        .O(p_Val2_30_fu_1372_p2_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 17x14 3}}" *) 
  DSP48E1 #(
    .ACASCREG(2),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(2),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(1),
    .BREG(1),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(0),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_30_reg_1678_reg
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,inputs_H_V_read_reg_1490_pp0_iter3_reg}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({p_Val2_29_fu_1280_p2[47],p_Val2_29_fu_1280_p2[47],p_Val2_29_fu_1280_p2[47],p_Val2_29_fu_1280_p2[47],p_Val2_29_fu_1280_p2[47:34]}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(p_Val2_4_reg_1510),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(\<const0> ),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_30_reg_1678_reg_n_58,p_Val2_30_reg_1678_reg_n_59,p_Val2_30_reg_1678_reg_n_60,p_Val2_30_reg_1678_reg_n_61,p_Val2_30_reg_1678_reg_n_62,p_Val2_30_reg_1678_reg_n_63,p_Val2_30_reg_1678_reg_n_64,p_Val2_30_reg_1678_reg_n_65,p_Val2_30_reg_1678_reg_n_66,p_Val2_30_reg_1678_reg_n_67,p_Val2_30_reg_1678_reg_n_68,p_Val2_30_reg_1678_reg_n_69,p_Val2_30_reg_1678_reg_n_70,p_Val2_30_reg_1678_reg_n_71,p_Val2_30_reg_1678_reg_n_72,p_Val2_30_reg_1678_reg_n_73,p_Val2_30_reg_1678_reg_n_74,p_Val2_30_reg_1678_reg_n_75,p_Val2_30_reg_1678_reg_n_76,p_Val2_30_reg_1678_reg_n_77,p_Val2_30_reg_1678_reg_n_78,p_Val2_30_reg_1678_reg_n_79,p_Val2_30_reg_1678_reg_n_80,p_Val2_30_reg_1678_reg_n_81,p_Val2_30_reg_1678_reg_n_82,p_Val2_30_reg_1678_reg_n_83,p_Val2_30_reg_1678_reg_n_84,p_Val2_30_reg_1678_reg_n_85,p_Val2_30_reg_1678_reg_n_86,p_Val2_30_reg_1678_reg_n_87,p_Val2_30_reg_1678_reg_n_88,p_Val2_30_reg_1678_reg_n_89,p_Val2_30_reg_1678_reg_n_90,p_Val2_30_reg_1678_reg_n_91,p_Val2_30_reg_1678_reg_n_92,p_Val2_30_reg_1678_reg_n_93,p_Val2_30_reg_1678_reg_n_94,p_Val2_30_reg_1678_reg_n_95,p_Val2_30_reg_1678_reg_n_96,p_Val2_30_reg_1678_reg_n_97,p_Val2_30_reg_1678_reg_n_98,p_Val2_30_reg_1678_reg_n_99,p_Val2_30_reg_1678_reg_n_100,p_Val2_30_reg_1678_reg_n_101,p_Val2_30_reg_1678_reg_n_102,p_Val2_30_reg_1678_reg_n_103,p_Val2_30_reg_1678_reg_n_104,p_Val2_30_reg_1678_reg_n_105}),
        .PCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_105),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_95),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_94),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_93),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_92),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_91),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_90),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_89),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_104),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_103),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_102),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_101),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_100),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_99),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_98),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_97),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_30_reg_1678_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_30_fu_1372_p2_n_96),
        .Q(\p_Val2_30_reg_1678_reg_n_0_[9] ),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-10 {cell *THIS*} {string 17x18 3}}" *) 
  DSP48E1 #(
    .ACASCREG(1),
    .ADREG(1),
    .ALUMODEREG(0),
    .AREG(1),
    .AUTORESET_PATDET("NO_RESET"),
    .A_INPUT("DIRECT"),
    .BCASCREG(2),
    .BREG(2),
    .B_INPUT("DIRECT"),
    .CARRYINREG(0),
    .CARRYINSELREG(0),
    .CREG(1),
    .DREG(1),
    .INMODEREG(0),
    .MASK(48'h3FFFFFFFFFFF),
    .MREG(0),
    .OPMODEREG(0),
    .PATTERN(48'h000000000000),
    .PREG(1),
    .SEL_MASK("MASK"),
    .SEL_PATTERN("PATTERN"),
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_PATTERN_DETECT("NO_PATDET"),
    .USE_SIMD("ONE48")) 
    p_Val2_30_reg_1678_reg__1
       (.A({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,p_Val2_29_fu_1280_p2[33:17]}),
        .ACIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .ALUMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .B({\<const0> ,\<const0> ,inputs_H_V_read_reg_1490_pp0_iter3_reg}),
        .BCIN({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .C({VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2,VCC_2}),
        .CARRYCASCIN(\<const0> ),
        .CARRYIN(\<const0> ),
        .CARRYINSEL({\<const0> ,\<const0> ,\<const0> }),
        .CEA1(\<const0> ),
        .CEA2(p_Val2_4_reg_1510),
        .CEAD(\<const0> ),
        .CEALUMODE(\<const0> ),
        .CEB1(p_Val2_4_reg_1510),
        .CEB2(p_Val2_4_reg_1510),
        .CEC(\<const0> ),
        .CECARRYIN(\<const0> ),
        .CECTRL(\<const0> ),
        .CED(\<const0> ),
        .CEINMODE(\<const0> ),
        .CEM(\<const0> ),
        .CEP(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D({GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2,GND_2}),
        .INMODE({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .MULTSIGNIN(\<const0> ),
        .OPMODE({\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> ,\<const0> ,\<const1> }),
        .P({p_Val2_30_reg_1678_reg__1_n_58,p_Val2_30_reg_1678_reg__1_n_59,p_Val2_30_reg_1678_reg__1_n_60,p_Val2_30_reg_1678_reg__1_n_61,p_Val2_30_reg_1678_reg__1_n_62,p_Val2_30_reg_1678_reg__1_n_63,p_Val2_30_reg_1678_reg__1_n_64,p_Val2_30_reg_1678_reg__1_n_65,p_Val2_30_reg_1678_reg__1_n_66,p_Val2_30_reg_1678_reg__1_n_67,p_Val2_30_reg_1678_reg__1_n_68,p_Val2_30_reg_1678_reg__1_n_69,p_Val2_30_reg_1678_reg__1_n_70,p_Val2_30_reg_1678_reg__1_n_71,p_Val2_30_reg_1678_reg__1_n_72,p_Val2_30_reg_1678_reg__1_n_73,p_Val2_30_reg_1678_reg__1_n_74,p_Val2_30_reg_1678_reg__1_n_75,p_Val2_30_reg_1678_reg__1_n_76,p_Val2_30_reg_1678_reg__1_n_77,p_Val2_30_reg_1678_reg__1_n_78,p_Val2_30_reg_1678_reg__1_n_79,p_Val2_30_reg_1678_reg__1_n_80,p_Val2_30_reg_1678_reg__1_n_81,p_Val2_30_reg_1678_reg__1_n_82,p_Val2_30_reg_1678_reg__1_n_83,p_Val2_30_reg_1678_reg__1_n_84,p_Val2_30_reg_1678_reg__1_n_85,p_Val2_30_reg_1678_reg__1_n_86,p_Val2_30_reg_1678_reg__1_n_87,p_Val2_30_reg_1678_reg__1_n_88,p_Val2_30_reg_1678_reg__1_n_89,p_Val2_30_reg_1678_reg__1_n_90,p_Val2_30_reg_1678_reg__1_n_91,p_Val2_30_reg_1678_reg__1_n_92,p_Val2_30_reg_1678_reg__1_n_93,p_Val2_30_reg_1678_reg__1_n_94,p_Val2_30_reg_1678_reg__1_n_95,p_Val2_30_reg_1678_reg__1_n_96,p_Val2_30_reg_1678_reg__1_n_97,p_Val2_30_reg_1678_reg__1_n_98,p_Val2_30_reg_1678_reg__1_n_99,p_Val2_30_reg_1678_reg__1_n_100,p_Val2_30_reg_1678_reg__1_n_101,p_Val2_30_reg_1678_reg__1_n_102,p_Val2_30_reg_1678_reg__1_n_103,p_Val2_30_reg_1678_reg__1_n_104,p_Val2_30_reg_1678_reg__1_n_105}),
        .PCIN({p_Val2_30_fu_1372_p2_n_106,p_Val2_30_fu_1372_p2_n_107,p_Val2_30_fu_1372_p2_n_108,p_Val2_30_fu_1372_p2_n_109,p_Val2_30_fu_1372_p2_n_110,p_Val2_30_fu_1372_p2_n_111,p_Val2_30_fu_1372_p2_n_112,p_Val2_30_fu_1372_p2_n_113,p_Val2_30_fu_1372_p2_n_114,p_Val2_30_fu_1372_p2_n_115,p_Val2_30_fu_1372_p2_n_116,p_Val2_30_fu_1372_p2_n_117,p_Val2_30_fu_1372_p2_n_118,p_Val2_30_fu_1372_p2_n_119,p_Val2_30_fu_1372_p2_n_120,p_Val2_30_fu_1372_p2_n_121,p_Val2_30_fu_1372_p2_n_122,p_Val2_30_fu_1372_p2_n_123,p_Val2_30_fu_1372_p2_n_124,p_Val2_30_fu_1372_p2_n_125,p_Val2_30_fu_1372_p2_n_126,p_Val2_30_fu_1372_p2_n_127,p_Val2_30_fu_1372_p2_n_128,p_Val2_30_fu_1372_p2_n_129,p_Val2_30_fu_1372_p2_n_130,p_Val2_30_fu_1372_p2_n_131,p_Val2_30_fu_1372_p2_n_132,p_Val2_30_fu_1372_p2_n_133,p_Val2_30_fu_1372_p2_n_134,p_Val2_30_fu_1372_p2_n_135,p_Val2_30_fu_1372_p2_n_136,p_Val2_30_fu_1372_p2_n_137,p_Val2_30_fu_1372_p2_n_138,p_Val2_30_fu_1372_p2_n_139,p_Val2_30_fu_1372_p2_n_140,p_Val2_30_fu_1372_p2_n_141,p_Val2_30_fu_1372_p2_n_142,p_Val2_30_fu_1372_p2_n_143,p_Val2_30_fu_1372_p2_n_144,p_Val2_30_fu_1372_p2_n_145,p_Val2_30_fu_1372_p2_n_146,p_Val2_30_fu_1372_p2_n_147,p_Val2_30_fu_1372_p2_n_148,p_Val2_30_fu_1372_p2_n_149,p_Val2_30_fu_1372_p2_n_150,p_Val2_30_fu_1372_p2_n_151,p_Val2_30_fu_1372_p2_n_152,p_Val2_30_fu_1372_p2_n_153}),
        .RSTA(ap_rst),
        .RSTALLCARRYIN(\<const0> ),
        .RSTALUMODE(\<const0> ),
        .RSTB(ap_rst),
        .RSTC(\<const0> ),
        .RSTCTRL(\<const0> ),
        .RSTD(\<const0> ),
        .RSTINMODE(\<const0> ),
        .RSTM(\<const0> ),
        .RSTP(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg__1_i_1
       (.CI(p_Val2_30_reg_1678_reg__1_i_2_n_0),
        .CO({p_Val2_30_reg_1678_reg__1_i_1_n_0,p_Val2_30_reg_1678_reg__1_i_1_n_1,p_Val2_30_reg_1678_reg__1_i_1_n_2,p_Val2_30_reg_1678_reg__1_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[31:28]),
        .O(p_Val2_29_fu_1280_p2[31:28]),
        .S({p_Val2_30_reg_1678_reg__1_i_4_n_0,p_Val2_30_reg_1678_reg__1_i_5_n_0,p_Val2_30_reg_1678_reg__1_i_6_n_0,p_Val2_30_reg_1678_reg__1_i_7_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_10
       (.I0(p_Val2_27_fu_1271_p2[25]),
        .I1(inputs_current_phase[25]),
        .O(p_Val2_30_reg_1678_reg__1_i_10_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_11
       (.I0(p_Val2_27_fu_1271_p2[24]),
        .I1(inputs_current_phase[24]),
        .O(p_Val2_30_reg_1678_reg__1_i_11_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_12
       (.I0(p_Val2_27_fu_1271_p2[23]),
        .I1(inputs_current_phase[23]),
        .O(p_Val2_30_reg_1678_reg__1_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_13
       (.I0(p_Val2_27_fu_1271_p2[22]),
        .I1(inputs_current_phase[22]),
        .O(p_Val2_30_reg_1678_reg__1_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_14
       (.I0(p_Val2_27_fu_1271_p2[21]),
        .I1(inputs_current_phase[21]),
        .O(p_Val2_30_reg_1678_reg__1_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_15
       (.I0(p_Val2_27_fu_1271_p2[20]),
        .I1(inputs_current_phase[20]),
        .O(p_Val2_30_reg_1678_reg__1_i_15_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg__1_i_2
       (.CI(p_Val2_30_reg_1678_reg__1_i_3_n_0),
        .CO({p_Val2_30_reg_1678_reg__1_i_2_n_0,p_Val2_30_reg_1678_reg__1_i_2_n_1,p_Val2_30_reg_1678_reg__1_i_2_n_2,p_Val2_30_reg_1678_reg__1_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[27:24]),
        .O(p_Val2_29_fu_1280_p2[27:24]),
        .S({p_Val2_30_reg_1678_reg__1_i_8_n_0,p_Val2_30_reg_1678_reg__1_i_9_n_0,p_Val2_30_reg_1678_reg__1_i_10_n_0,p_Val2_30_reg_1678_reg__1_i_11_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg__1_i_3
       (.CI(p_Val2_30_fu_1372_p2_i_1_n_0),
        .CO({p_Val2_30_reg_1678_reg__1_i_3_n_0,p_Val2_30_reg_1678_reg__1_i_3_n_1,p_Val2_30_reg_1678_reg__1_i_3_n_2,p_Val2_30_reg_1678_reg__1_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[23:20]),
        .O(p_Val2_29_fu_1280_p2[23:20]),
        .S({p_Val2_30_reg_1678_reg__1_i_12_n_0,p_Val2_30_reg_1678_reg__1_i_13_n_0,p_Val2_30_reg_1678_reg__1_i_14_n_0,p_Val2_30_reg_1678_reg__1_i_15_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_4
       (.I0(p_Val2_27_fu_1271_p2[31]),
        .I1(inputs_current_phase[31]),
        .O(p_Val2_30_reg_1678_reg__1_i_4_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_5
       (.I0(p_Val2_27_fu_1271_p2[30]),
        .I1(inputs_current_phase[30]),
        .O(p_Val2_30_reg_1678_reg__1_i_5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_6
       (.I0(p_Val2_27_fu_1271_p2[29]),
        .I1(inputs_current_phase[29]),
        .O(p_Val2_30_reg_1678_reg__1_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_7
       (.I0(p_Val2_27_fu_1271_p2[28]),
        .I1(inputs_current_phase[28]),
        .O(p_Val2_30_reg_1678_reg__1_i_7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_8
       (.I0(p_Val2_27_fu_1271_p2[27]),
        .I1(inputs_current_phase[27]),
        .O(p_Val2_30_reg_1678_reg__1_i_8_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg__1_i_9
       (.I0(p_Val2_27_fu_1271_p2[26]),
        .I1(inputs_current_phase[26]),
        .O(p_Val2_30_reg_1678_reg__1_i_9_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg_i_1
       (.CI(p_Val2_30_reg_1678_reg_i_2_n_0),
        .CO({p_Val2_30_reg_1678_reg_i_1_n_1,p_Val2_30_reg_1678_reg_i_1_n_2,p_Val2_30_reg_1678_reg_i_1_n_3}),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_Val2_27_fu_1271_p2[46:44]}),
        .O(p_Val2_29_fu_1280_p2[47:44]),
        .S({p_Val2_30_reg_1678_reg_i_5_n_0,p_Val2_30_reg_1678_reg_i_6_n_0,p_Val2_30_reg_1678_reg_i_7_n_0,p_Val2_30_reg_1678_reg_i_8_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_10
       (.I0(p_Val2_27_fu_1271_p2[42]),
        .I1(inputs_current_phase[42]),
        .O(p_Val2_30_reg_1678_reg_i_10_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_11
       (.I0(p_Val2_27_fu_1271_p2[41]),
        .I1(inputs_current_phase[41]),
        .O(p_Val2_30_reg_1678_reg_i_11_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_12
       (.I0(p_Val2_27_fu_1271_p2[40]),
        .I1(inputs_current_phase[40]),
        .O(p_Val2_30_reg_1678_reg_i_12_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_13
       (.I0(p_Val2_27_fu_1271_p2[39]),
        .I1(inputs_current_phase[39]),
        .O(p_Val2_30_reg_1678_reg_i_13_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_14
       (.I0(p_Val2_27_fu_1271_p2[38]),
        .I1(inputs_current_phase[38]),
        .O(p_Val2_30_reg_1678_reg_i_14_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_15
       (.I0(p_Val2_27_fu_1271_p2[37]),
        .I1(inputs_current_phase[37]),
        .O(p_Val2_30_reg_1678_reg_i_15_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_16
       (.I0(p_Val2_27_fu_1271_p2[36]),
        .I1(inputs_current_phase[36]),
        .O(p_Val2_30_reg_1678_reg_i_16_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_17
       (.I0(p_Val2_27_fu_1271_p2[35]),
        .I1(inputs_current_phase[35]),
        .O(p_Val2_30_reg_1678_reg_i_17_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_18
       (.I0(p_Val2_27_fu_1271_p2[34]),
        .I1(inputs_current_phase[34]),
        .O(p_Val2_30_reg_1678_reg_i_18_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_19
       (.I0(p_Val2_27_fu_1271_p2[33]),
        .I1(inputs_current_phase[33]),
        .O(p_Val2_30_reg_1678_reg_i_19_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg_i_2
       (.CI(p_Val2_30_reg_1678_reg_i_3_n_0),
        .CO({p_Val2_30_reg_1678_reg_i_2_n_0,p_Val2_30_reg_1678_reg_i_2_n_1,p_Val2_30_reg_1678_reg_i_2_n_2,p_Val2_30_reg_1678_reg_i_2_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[43:40]),
        .O(p_Val2_29_fu_1280_p2[43:40]),
        .S({p_Val2_30_reg_1678_reg_i_9_n_0,p_Val2_30_reg_1678_reg_i_10_n_0,p_Val2_30_reg_1678_reg_i_11_n_0,p_Val2_30_reg_1678_reg_i_12_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_20
       (.I0(p_Val2_27_fu_1271_p2[32]),
        .I1(inputs_current_phase[32]),
        .O(p_Val2_30_reg_1678_reg_i_20_n_0));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg_i_3
       (.CI(p_Val2_30_reg_1678_reg_i_4_n_0),
        .CO({p_Val2_30_reg_1678_reg_i_3_n_0,p_Val2_30_reg_1678_reg_i_3_n_1,p_Val2_30_reg_1678_reg_i_3_n_2,p_Val2_30_reg_1678_reg_i_3_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[39:36]),
        .O(p_Val2_29_fu_1280_p2[39:36]),
        .S({p_Val2_30_reg_1678_reg_i_13_n_0,p_Val2_30_reg_1678_reg_i_14_n_0,p_Val2_30_reg_1678_reg_i_15_n_0,p_Val2_30_reg_1678_reg_i_16_n_0}));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 p_Val2_30_reg_1678_reg_i_4
       (.CI(p_Val2_30_reg_1678_reg__1_i_1_n_0),
        .CO({p_Val2_30_reg_1678_reg_i_4_n_0,p_Val2_30_reg_1678_reg_i_4_n_1,p_Val2_30_reg_1678_reg_i_4_n_2,p_Val2_30_reg_1678_reg_i_4_n_3}),
        .CYINIT(\<const0> ),
        .DI(p_Val2_27_fu_1271_p2[35:32]),
        .O(p_Val2_29_fu_1280_p2[35:32]),
        .S({p_Val2_30_reg_1678_reg_i_17_n_0,p_Val2_30_reg_1678_reg_i_18_n_0,p_Val2_30_reg_1678_reg_i_19_n_0,p_Val2_30_reg_1678_reg_i_20_n_0}));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_5
       (.I0(p_Val2_27_fu_1271_p2[47]),
        .I1(inputs_current_phase[47]),
        .O(p_Val2_30_reg_1678_reg_i_5_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_6
       (.I0(p_Val2_27_fu_1271_p2[46]),
        .I1(inputs_current_phase[46]),
        .O(p_Val2_30_reg_1678_reg_i_6_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_7
       (.I0(p_Val2_27_fu_1271_p2[45]),
        .I1(inputs_current_phase[45]),
        .O(p_Val2_30_reg_1678_reg_i_7_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_8
       (.I0(p_Val2_27_fu_1271_p2[44]),
        .I1(inputs_current_phase[44]),
        .O(p_Val2_30_reg_1678_reg_i_8_n_0));
  LUT2 #(
    .INIT(4'h6)) 
    p_Val2_30_reg_1678_reg_i_9
       (.I0(p_Val2_27_fu_1271_p2[43]),
        .I1(inputs_current_phase[43]),
        .O(p_Val2_30_reg_1678_reg_i_9_n_0));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[0]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[0]),
        .O(p_Val2_33_fu_1080_p3[0]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[10]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[10]),
        .O(p_Val2_33_fu_1080_p3[10]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[11]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[11]),
        .O(p_Val2_33_fu_1080_p3[11]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[12]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[12]),
        .O(p_Val2_33_fu_1080_p3[12]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[13]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[13]),
        .O(p_Val2_33_fu_1080_p3[13]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[14]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[14]),
        .O(p_Val2_33_fu_1080_p3[14]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[15]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[15]),
        .O(p_Val2_33_fu_1080_p3[15]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[16]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[16]),
        .O(p_Val2_33_fu_1080_p3[16]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[17]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[17]),
        .O(p_Val2_33_fu_1080_p3[17]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[18]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[18]),
        .O(p_Val2_33_fu_1080_p3[18]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[19]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[19]),
        .O(p_Val2_33_fu_1080_p3[19]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[1]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[1]),
        .O(p_Val2_33_fu_1080_p3[1]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[20]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[20]),
        .O(p_Val2_33_fu_1080_p3[20]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[21]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[21]),
        .O(p_Val2_33_fu_1080_p3[21]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[22]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[22]),
        .O(p_Val2_33_fu_1080_p3[22]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[23]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[23]),
        .O(p_Val2_33_fu_1080_p3[23]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[24]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[24]),
        .O(p_Val2_33_fu_1080_p3[24]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[25]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[25]),
        .O(p_Val2_33_fu_1080_p3[25]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[26]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[26]),
        .O(p_Val2_33_fu_1080_p3[26]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[27]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[27]),
        .O(p_Val2_33_fu_1080_p3[27]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[28]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[28]),
        .O(p_Val2_33_fu_1080_p3[28]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[29]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[29]),
        .O(p_Val2_33_fu_1080_p3[29]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[2]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[2]),
        .O(p_Val2_33_fu_1080_p3[2]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[30]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[30]),
        .O(p_Val2_33_fu_1080_p3[30]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[31]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[31]),
        .O(p_Val2_33_fu_1080_p3[31]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[32]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[32]),
        .O(p_Val2_33_fu_1080_p3[32]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[33]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[33]),
        .O(p_Val2_33_fu_1080_p3[33]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[34]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[34]),
        .O(p_Val2_33_fu_1080_p3[34]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[35]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[35]),
        .O(p_Val2_33_fu_1080_p3[35]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[36]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[36]),
        .O(p_Val2_33_fu_1080_p3[36]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[37]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[37]),
        .O(p_Val2_33_fu_1080_p3[37]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[38]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[38]),
        .O(p_Val2_33_fu_1080_p3[38]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[39]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[39]),
        .O(p_Val2_33_fu_1080_p3[39]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[3]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[3]),
        .O(p_Val2_33_fu_1080_p3[3]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[40]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[40]),
        .O(p_Val2_33_fu_1080_p3[40]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[41]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[41]),
        .O(p_Val2_33_fu_1080_p3[41]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[42]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[42]),
        .O(p_Val2_33_fu_1080_p3[42]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[43]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[43]),
        .O(p_Val2_33_fu_1080_p3[43]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[44]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[44]),
        .O(p_Val2_33_fu_1080_p3[44]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[45]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[45]),
        .O(p_Val2_33_fu_1080_p3[45]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[46]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[46]),
        .O(p_Val2_33_fu_1080_p3[46]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[47]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[47]),
        .O(p_Val2_33_fu_1080_p3[47]));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(\sel_tmp3_reg_1566[0]_i_9_n_0 ),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_8_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ),
        .O(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000005051)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ),
        .I1(\p_Val2_12_reg_1560_reg[19]_i_2_n_5 ),
        .I2(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I3(\p_Val2_12_reg_1560_reg[3]_i_2_n_6 ),
        .I4(\sel_tmp3_reg_1566[0]_i_13_n_0 ),
        .I5(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ),
        .O(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(\p_Val2_12_reg_1560_reg[31]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560_reg[15]_i_2_n_4 ),
        .I2(\p_Val2_12_reg_1560_reg[15]_i_2_n_5 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[19]_i_2_n_4 ),
        .O(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(\p_Val2_12_reg_1560_reg[35]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560_reg[11]_i_2_n_6 ),
        .I2(\p_Val2_12_reg_1560_reg[31]_i_2_n_4 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[35]_i_2_n_5 ),
        .O(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000300000002)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6 
       (.I0(\p_Val2_12_reg_1560_reg[7]_i_2_n_6 ),
        .I1(sel0[2]),
        .I2(sel0[3]),
        .I3(sel0[5]),
        .I4(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[35]_i_2_n_4 ),
        .O(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7 
       (.I0(\p_Val2_12_reg_1560_reg[11]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560_reg[39]_i_2_n_4 ),
        .I2(\p_Val2_12_reg_1560_reg[27]_i_2_n_4 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[23]_i_2_n_7 ),
        .O(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[4]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[4]),
        .O(p_Val2_33_fu_1080_p3[4]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[5]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[5]),
        .O(p_Val2_33_fu_1080_p3[5]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[6]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[6]),
        .O(p_Val2_33_fu_1080_p3[6]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[7]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[7]),
        .O(p_Val2_33_fu_1080_p3[7]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[8]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[8]),
        .O(p_Val2_33_fu_1080_p3[8]));
  (* srl_bus_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_Val2_33_reg_1631_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_Val2_33_fu_1080_p3[9]),
        .Q(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFAAAA0200AAAA)) 
    \p_Val2_33_reg_1631_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I1(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ),
        .I4(sel_tmp_reg_1527),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_7_reg_487[9]),
        .O(p_Val2_33_fu_1080_p3[9]));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_33_reg_1631_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate_n_0));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__0
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__1
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__10
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__11
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__12
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__13
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__14
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__14_n_0));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__15
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__16
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__17
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__18
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__19
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__19_n_0));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__2
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__20
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__21
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__22
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__22_n_0));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__23
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__24
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__24_n_0));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__25
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__25_n_0));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__26
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__26_n_0));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__27
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__27_n_0));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__28
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__28_n_0));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__29
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__29_n_0));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__3
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__30
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__31
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__31_n_0));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__32
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__32_n_0));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__33
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__33_n_0));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__34
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__34_n_0));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__35
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__35_n_0));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__36
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__36_n_0));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__37
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__37_n_0));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__38
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__38_n_0));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__39
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__39_n_0));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__4
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__40
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__40_n_0));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__41
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__41_n_0));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__42
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__42_n_0));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__43
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__43_n_0));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__44
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__44_n_0));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__45
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__45_n_0));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__46
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__46_n_0));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__5
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__6
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__7
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__8
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__9
       (.I0(\p_Val2_33_reg_1631_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__9_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__46_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__36_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__35_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__34_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__33_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__32_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__31_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__30_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__29_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__28_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__27_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__45_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__26_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__25_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__24_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__23_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__22_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__21_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__20_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__19_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__18_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__17_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__44_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__16_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__15_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__14_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__13_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__12_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__11_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__10_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__9_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__8_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__7_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__43_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__6_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__5_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__4_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__3_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__2_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__1_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__0_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__42_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__41_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__40_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__39_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__38_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_33_reg_1631_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_33_reg_1631_pp0_iter5_reg_reg_gate__37_n_0),
        .Q(p_Val2_33_reg_1631_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[0]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[10]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[11]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[12]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[13]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[14]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[15]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[16]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[17]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[18]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[19]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[1]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[20]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[21]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[22]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[23]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[24]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[25]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[26]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[27]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[28]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[29]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[2]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[30]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[31]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[32]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[33]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[34]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[35]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[36]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[37]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[38]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[39]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[3]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[40]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[41]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[42]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[43]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[44]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[45]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[46]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[47]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[4]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[5]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[6]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[7]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[8]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_38_reg_1664[9]),
        .Q(p_Val2_38_reg_1664_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[0]),
        .Q(p_Val2_38_reg_1664[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[10]),
        .Q(p_Val2_38_reg_1664[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[11]),
        .Q(p_Val2_38_reg_1664[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[12]),
        .Q(p_Val2_38_reg_1664[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[13]),
        .Q(p_Val2_38_reg_1664[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[14]),
        .Q(p_Val2_38_reg_1664[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[15]),
        .Q(p_Val2_38_reg_1664[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[16]),
        .Q(p_Val2_38_reg_1664[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[17]),
        .Q(p_Val2_38_reg_1664[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[18]),
        .Q(p_Val2_38_reg_1664[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[19]),
        .Q(p_Val2_38_reg_1664[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[1]),
        .Q(p_Val2_38_reg_1664[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[20]),
        .Q(p_Val2_38_reg_1664[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[21]),
        .Q(p_Val2_38_reg_1664[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[22]),
        .Q(p_Val2_38_reg_1664[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[23]),
        .Q(p_Val2_38_reg_1664[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[24]),
        .Q(p_Val2_38_reg_1664[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[25]),
        .Q(p_Val2_38_reg_1664[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[26]),
        .Q(p_Val2_38_reg_1664[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[27]),
        .Q(p_Val2_38_reg_1664[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[28]),
        .Q(p_Val2_38_reg_1664[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[29]),
        .Q(p_Val2_38_reg_1664[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[2]),
        .Q(p_Val2_38_reg_1664[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[30]),
        .Q(p_Val2_38_reg_1664[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[31]),
        .Q(p_Val2_38_reg_1664[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[32]),
        .Q(p_Val2_38_reg_1664[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[33]),
        .Q(p_Val2_38_reg_1664[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[34]),
        .Q(p_Val2_38_reg_1664[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[35]),
        .Q(p_Val2_38_reg_1664[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[36]),
        .Q(p_Val2_38_reg_1664[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[37]),
        .Q(p_Val2_38_reg_1664[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[38]),
        .Q(p_Val2_38_reg_1664[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[39]),
        .Q(p_Val2_38_reg_1664[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[3]),
        .Q(p_Val2_38_reg_1664[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[40]),
        .Q(p_Val2_38_reg_1664[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[41]),
        .Q(p_Val2_38_reg_1664[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[42]),
        .Q(p_Val2_38_reg_1664[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[43]),
        .Q(p_Val2_38_reg_1664[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[44]),
        .Q(p_Val2_38_reg_1664[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[45]),
        .Q(p_Val2_38_reg_1664[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[46]),
        .Q(p_Val2_38_reg_1664[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[47]),
        .Q(p_Val2_38_reg_1664[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[4]),
        .Q(p_Val2_38_reg_1664[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[5]),
        .Q(p_Val2_38_reg_1664[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[6]),
        .Q(p_Val2_38_reg_1664[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[7]),
        .Q(p_Val2_38_reg_1664[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[8]),
        .Q(p_Val2_38_reg_1664[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_38_reg_1664_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_0_V_reg[9]),
        .Q(p_Val2_38_reg_1664[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[0]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[10]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[11]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[12]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[13]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[14]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[15]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[16]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[17]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[18]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[19]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[1]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[20]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[21]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[22]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[23]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[24]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[25]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[26]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[27]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[28]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[29]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[2]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[30]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[31]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[32]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[33]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[34]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[35]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[36]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[37]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[38]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[39]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[3]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[40]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[41]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[42]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[43]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[44]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[45]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[46]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[47]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[4]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[5]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[6]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[7]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[8]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_Val2_39_reg_1669[9]),
        .Q(p_Val2_39_reg_1669_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[0]),
        .Q(p_Val2_39_reg_1669[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[10]),
        .Q(p_Val2_39_reg_1669[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[11]),
        .Q(p_Val2_39_reg_1669[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[12]),
        .Q(p_Val2_39_reg_1669[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[13]),
        .Q(p_Val2_39_reg_1669[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[14]),
        .Q(p_Val2_39_reg_1669[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[15]),
        .Q(p_Val2_39_reg_1669[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[16]),
        .Q(p_Val2_39_reg_1669[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[17]),
        .Q(p_Val2_39_reg_1669[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[18]),
        .Q(p_Val2_39_reg_1669[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[19]),
        .Q(p_Val2_39_reg_1669[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[1]),
        .Q(p_Val2_39_reg_1669[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[20]),
        .Q(p_Val2_39_reg_1669[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[21]),
        .Q(p_Val2_39_reg_1669[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[22]),
        .Q(p_Val2_39_reg_1669[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[23]),
        .Q(p_Val2_39_reg_1669[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[24]),
        .Q(p_Val2_39_reg_1669[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[25]),
        .Q(p_Val2_39_reg_1669[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[26]),
        .Q(p_Val2_39_reg_1669[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[27]),
        .Q(p_Val2_39_reg_1669[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[28]),
        .Q(p_Val2_39_reg_1669[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[29]),
        .Q(p_Val2_39_reg_1669[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[2]),
        .Q(p_Val2_39_reg_1669[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[30]),
        .Q(p_Val2_39_reg_1669[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[31]),
        .Q(p_Val2_39_reg_1669[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[32]),
        .Q(p_Val2_39_reg_1669[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[33]),
        .Q(p_Val2_39_reg_1669[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[34]),
        .Q(p_Val2_39_reg_1669[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[35]),
        .Q(p_Val2_39_reg_1669[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[36]),
        .Q(p_Val2_39_reg_1669[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[37]),
        .Q(p_Val2_39_reg_1669[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[38]),
        .Q(p_Val2_39_reg_1669[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[39]),
        .Q(p_Val2_39_reg_1669[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[3]),
        .Q(p_Val2_39_reg_1669[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[40]),
        .Q(p_Val2_39_reg_1669[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[41]),
        .Q(p_Val2_39_reg_1669[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[42]),
        .Q(p_Val2_39_reg_1669[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[43]),
        .Q(p_Val2_39_reg_1669[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[44]),
        .Q(p_Val2_39_reg_1669[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[45]),
        .Q(p_Val2_39_reg_1669[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[46]),
        .Q(p_Val2_39_reg_1669[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[47]),
        .Q(p_Val2_39_reg_1669[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[4]),
        .Q(p_Val2_39_reg_1669[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[5]),
        .Q(p_Val2_39_reg_1669[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[6]),
        .Q(p_Val2_39_reg_1669[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[7]),
        .Q(p_Val2_39_reg_1669[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[8]),
        .Q(p_Val2_39_reg_1669[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_39_reg_1669_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(acc_LO_1_V_reg[9]),
        .Q(p_Val2_39_reg_1669[9]),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_3_reg_440[0]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[0]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_rate_s[0]),
        .O(\p_Val2_3_reg_440[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_3_reg_440[1]_i_1 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[1]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_rate_s[1]),
        .O(\p_Val2_3_reg_440[1]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_3_reg_440[2]_i_1 
       (.I0(p_Val2_4_reg_1510),
        .I1(ap_enable_reg_pp0_iter2),
        .O(acc_H1_slip_V0));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \p_Val2_3_reg_440[2]_i_2 
       (.I0(ap_phi_reg_pp0_iter2_p_Val2_3_reg_440[2]),
        .I1(inputs_valid_read_reg_1420),
        .I2(inputs_current_rate_s[2]),
        .O(\p_Val2_3_reg_440[2]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_3_reg_440_reg[0] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\p_Val2_3_reg_440[0]_i_1_n_0 ),
        .Q(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_3_reg_440_reg[1] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\p_Val2_3_reg_440[1]_i_1_n_0 ),
        .Q(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_3_reg_440_reg[2] 
       (.C(ap_clk),
        .CE(acc_H1_slip_V0),
        .D(\p_Val2_3_reg_440[2]_i_2_n_0 ),
        .Q(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[0]_i_1 
       (.I0(tmp_8_fu_673_p3[0]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[10]_i_1 
       (.I0(tmp_8_fu_673_p3[10]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[11]_i_1 
       (.I0(tmp_8_fu_673_p3[11]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[12]_i_1 
       (.I0(tmp_8_fu_673_p3[12]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[13]_i_1 
       (.I0(tmp_8_fu_673_p3[13]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[14]_i_1 
       (.I0(tmp_8_fu_673_p3[14]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[15]_i_1 
       (.I0(tmp_8_fu_673_p3[15]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[16]_i_1 
       (.I0(tmp_8_fu_673_p3[16]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[16]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[17]_i_1 
       (.I0(tmp_8_fu_673_p3[17]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[17]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[18]_i_1 
       (.I0(tmp_8_fu_673_p3[18]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[18]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[19]_i_1 
       (.I0(tmp_8_fu_673_p3[19]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[19]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[1]_i_1 
       (.I0(tmp_8_fu_673_p3[1]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[20]_i_1 
       (.I0(tmp_8_fu_673_p3[20]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[20]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[21]_i_1 
       (.I0(tmp_8_fu_673_p3[21]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[22]_i_1 
       (.I0(tmp_8_fu_673_p3[22]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[23]_i_1 
       (.I0(tmp_8_fu_673_p3[23]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[23]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[24]_i_1 
       (.I0(tmp_8_fu_673_p3[24]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[24]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[25]_i_1 
       (.I0(tmp_8_fu_673_p3[25]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[25]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[26]_i_1 
       (.I0(tmp_8_fu_673_p3[26]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[26]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[27]_i_1 
       (.I0(tmp_8_fu_673_p3[27]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[27]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[28]_i_1 
       (.I0(tmp_8_fu_673_p3[28]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[28]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[29]_i_1 
       (.I0(tmp_8_fu_673_p3[29]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[29]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[2]_i_1 
       (.I0(tmp_8_fu_673_p3[2]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[30]_i_1 
       (.I0(tmp_8_fu_673_p3[30]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[30]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[31]_i_1 
       (.I0(tmp_8_fu_673_p3[31]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[32]_i_1 
       (.I0(tmp_8_fu_673_p3[32]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[32]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[33]_i_1 
       (.I0(tmp_8_fu_673_p3[33]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[33]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[34]_i_1 
       (.I0(tmp_8_fu_673_p3[34]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[34]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[35]_i_1 
       (.I0(tmp_8_fu_673_p3[35]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[35]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[36]_i_1 
       (.I0(tmp_8_fu_673_p3[36]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[36]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[37]_i_1 
       (.I0(tmp_8_fu_673_p3[37]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[37]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[38]_i_1 
       (.I0(tmp_8_fu_673_p3[38]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[38]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[39]_i_1 
       (.I0(tmp_8_fu_673_p3[39]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[39]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[3]_i_1 
       (.I0(tmp_8_fu_673_p3[3]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[40]_i_1 
       (.I0(tmp_8_fu_673_p3[40]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[40]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[41]_i_1 
       (.I0(tmp_8_fu_673_p3[41]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[41]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[42]_i_1 
       (.I0(tmp_8_fu_673_p3[42]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[42]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[43]_i_1 
       (.I0(tmp_8_fu_673_p3[43]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[43]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[44]_i_1 
       (.I0(tmp_8_fu_673_p3[44]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[44]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[45]_i_1 
       (.I0(tmp_8_fu_673_p3[45]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[45]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[46]_i_1 
       (.I0(tmp_8_fu_673_p3[46]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[46]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[47]_i_1 
       (.I0(tmp_8_fu_673_p3[47]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[4]_i_1 
       (.I0(tmp_8_fu_673_p3[4]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[5]_i_1 
       (.I0(tmp_8_fu_673_p3[5]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[6]_i_1 
       (.I0(tmp_8_fu_673_p3[6]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[7]_i_1 
       (.I0(tmp_8_fu_673_p3[7]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[8]_i_1 
       (.I0(tmp_8_fu_673_p3[8]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \p_Val2_4_reg_1510[9]_i_1 
       (.I0(tmp_8_fu_673_p3[9]),
        .I1(inputs_current_enabl),
        .O(\p_Val2_4_reg_1510[9]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[0]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[0] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[10]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[10] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[11]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[11] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[12]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[12] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[13]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[13] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[14]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[14] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[15]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[15] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[16]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[16] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[17]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[17] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[18]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[18] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[19]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[19] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[1]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[1] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[20]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[20] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[21]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[21] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[22]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[22] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[23]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[23] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[24]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[24] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[25]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[25] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[26]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[26] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[27]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[27] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[28]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[28] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[29]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[29] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[2]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[2] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[30]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[30] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[31]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[31] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[32]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[32] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[33]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[33] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[34]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[34] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[35]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[35] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[36]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[36] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[37]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[37] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[38]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[38] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[39]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[39] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[3]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[3] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[40]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[40] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[41]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[41] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[42]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[42] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[43]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[43] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[44]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[44] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[45]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[45] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[46]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[46] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[47]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[47] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[4]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[4] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[5]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[5] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[6]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[6] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[7]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[7] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[8]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[8] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_Val2_4_reg_1510_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_Val2_4_reg_1510[9]_i_1_n_0 ),
        .Q(\p_Val2_4_reg_1510_reg_n_0_[9] ),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_tmp_8_reg_1515_pp0_iter3_reg_reg_r
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_reg_r_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0),
        .R(ap_rst));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[0]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[0]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[0]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[0]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[10]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[10]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[10]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[10]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[11]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[11]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[11]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[11]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[12]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[12]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[12]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[12]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[13]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[13]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[13]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[13]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[14]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[14]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[14]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[14]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[15]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[15]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[15]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[15]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[16]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[16]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[16]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[16]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[17]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[17]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[17]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[17]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[18]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[18]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[18]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[18]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[19]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[19]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[19]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[19]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[1]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[1]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[1]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[1]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[20]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[20]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[20]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[20]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[21]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[21]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[21]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[21]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[22]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[22]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[22]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[22]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[23]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[23]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[23]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[23]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[24]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[24]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[24]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[24]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[25]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[25]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[25]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[25]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[26]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[26]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[26]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[26]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[27]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[27]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[27]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[27]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[28]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[28]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[28]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[28]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[29]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[29]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[29]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[29]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[2]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[2]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[2]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[2]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[30]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[30]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[30]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[30]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[31]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[31]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[31]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[31]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[32]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[32]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[32]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[32]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[33]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[33]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[33]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[33]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[34]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[34]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[34]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[34]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[35]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[35]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[35]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[35]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[36]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[36]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[36]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[36]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[37]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[37]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[37]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[37]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[38]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[38]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[38]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[38]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[39]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[39]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[39]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[39]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[3]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[3]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[3]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[3]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[40]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[40]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[40]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[40]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[41]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[41]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[41]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[41]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[42]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[42]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[42]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[42]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[43]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[43]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[43]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[43]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[44]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[44]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[44]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[44]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[45]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[45]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[45]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[45]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[46]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[46]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[46]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[46]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[47]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[47]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[47]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[47]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[4]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[4]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[4]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[4]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[5]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[5]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[5]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[5]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[6]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[6]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[6]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[6]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[7]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[7]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[7]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[7]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[8]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[8]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[8]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[8]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\p_tmp_8_reg_1515_pp0_iter4_reg_reg[9]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \p_tmp_8_reg_1515_pp0_iter4_reg_reg[9]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.A0(\<const0> ),
        .A1(\<const1> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(p_tmp_8_fu_693_p3[9]),
        .Q(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[9]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    p_tmp_8_reg_1515_pp0_iter4_reg_reg_r
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[0]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[10]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[11]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[12]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[13]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[14]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[15]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[16]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[17]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[18]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[19]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[1]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[20]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[21]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[22]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[23]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[24]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[25]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[26]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[27]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[28]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[29]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[2]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[30]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[31]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[32]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[33]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[34]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[35]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[36]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[37]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[38]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[39]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[3]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[40]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[41]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[42]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[43]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[44]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[45]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[46]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[47]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[4]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[5]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[6]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[7]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[8]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\p_tmp_8_reg_1515_pp0_iter4_reg_reg[9]_srl3___p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .Q(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate_n_0));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__0
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__1
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__10
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__11
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__12
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__13
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__14
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__14_n_0));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__15
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__16
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__17
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__18
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__19
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__19_n_0));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__2
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__20
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__21
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__22
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__22_n_0));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__23
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__24
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__24_n_0));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__25
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__25_n_0));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__26
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__26_n_0));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__27
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__27_n_0));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__28
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__28_n_0));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__29
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__29_n_0));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__3
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__30
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__31
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__31_n_0));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__32
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__32_n_0));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__33
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__33_n_0));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__34
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__34_n_0));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__35
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__35_n_0));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__36
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__36_n_0));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__37
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__37_n_0));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__38
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__38_n_0));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__39
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__39_n_0));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__4
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__40
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__40_n_0));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__41
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__41_n_0));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__42
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__42_n_0));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__43
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__43_n_0));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__44
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__44_n_0));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__45
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__45_n_0));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__46
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__46_n_0));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__5
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__6
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__7
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__8
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT2 #(
    .INIT(4'h8)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__9
       (.I0(\p_tmp_8_reg_1515_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .O(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__9_n_0));
  FDRE #(
    .INIT(1'b0)) 
    p_tmp_8_reg_1515_pp0_iter5_reg_reg_r
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter5_reg_reg_r_n_0),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__46_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__36_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__35_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__34_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__33_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__32_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__31_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__30_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__29_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__28_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__27_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__45_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__26_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__25_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__24_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__23_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__22_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__21_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__20_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__19_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__18_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__17_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__44_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__16_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__15_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__14_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__13_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__12_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__11_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__10_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__9_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__8_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__7_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__43_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__6_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__5_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__4_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__3_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__2_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__1_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__0_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__42_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__41_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__40_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__39_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__38_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \p_tmp_8_reg_1515_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_tmp_8_reg_1515_pp0_iter5_reg_reg_gate__37_n_0),
        .Q(p_tmp_8_reg_1515_pp0_iter6_reg[9]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    p_tmp_8_reg_1515_reg_r
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\<const1> ),
        .Q(p_tmp_8_reg_1515_reg_r_n_0),
        .R(ap_rst));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[0]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[10]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[11]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[11:8]),
        .O(phase_H1_prog_offset_fu_972_p2[11:8]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[11]),
        .I1(acc_H1_prog_V_reg[11]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[10]),
        .I1(acc_H1_prog_V_reg[10]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[9]),
        .I1(acc_H1_prog_V_reg[9]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[8]),
        .I1(acc_H1_prog_V_reg[8]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[12]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[13]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[14]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[15]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[15:12]),
        .O(phase_H1_prog_offset_fu_972_p2[15:12]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[15]),
        .I1(acc_H1_prog_V_reg[15]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[14]),
        .I1(acc_H1_prog_V_reg[14]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[13]),
        .I1(acc_H1_prog_V_reg[13]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[12]),
        .I1(acc_H1_prog_V_reg[12]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[16]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[17]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[18]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[19]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[19:16]),
        .O(phase_H1_prog_offset_fu_972_p2[19:16]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[19]),
        .I1(acc_H1_prog_V_reg[19]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[18]),
        .I1(acc_H1_prog_V_reg[18]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[17]),
        .I1(acc_H1_prog_V_reg[17]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[16]),
        .I1(acc_H1_prog_V_reg[16]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[1]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[20]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[21]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[22]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[23]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[23:20]),
        .O(phase_H1_prog_offset_fu_972_p2[23:20]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[23]),
        .I1(acc_H1_prog_V_reg[23]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[22]),
        .I1(acc_H1_prog_V_reg[22]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[21]),
        .I1(acc_H1_prog_V_reg[21]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[20]),
        .I1(acc_H1_prog_V_reg[20]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[24]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[25]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[26]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[27]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[27:24]),
        .O(phase_H1_prog_offset_fu_972_p2[27:24]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[27]),
        .I1(acc_H1_prog_V_reg[27]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[26]),
        .I1(acc_H1_prog_V_reg[26]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[25]),
        .I1(acc_H1_prog_V_reg[25]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[24]),
        .I1(acc_H1_prog_V_reg[24]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[28]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[29]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[2]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[30]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[31]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[31:28]),
        .O(phase_H1_prog_offset_fu_972_p2[31:28]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[31]),
        .I1(acc_H1_prog_V_reg[31]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[30]),
        .I1(acc_H1_prog_V_reg[30]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[29]),
        .I1(acc_H1_prog_V_reg[29]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[28]),
        .I1(acc_H1_prog_V_reg[28]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[32]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[33]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[34]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[35]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[35:32]),
        .O(phase_H1_prog_offset_fu_972_p2[35:32]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[35]),
        .I1(acc_H1_prog_V_reg[35]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[34]),
        .I1(acc_H1_prog_V_reg[34]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[33]),
        .I1(acc_H1_prog_V_reg[33]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[32]),
        .I1(acc_H1_prog_V_reg[32]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[36]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[37]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[38]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[39]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[39:36]),
        .O(phase_H1_prog_offset_fu_972_p2[39:36]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[39]),
        .I1(acc_H1_prog_V_reg[39]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[38]),
        .I1(acc_H1_prog_V_reg[38]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[37]),
        .I1(acc_H1_prog_V_reg[37]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[36]),
        .I1(acc_H1_prog_V_reg[36]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[3]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\<const0> ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[3:0]),
        .O(phase_H1_prog_offset_fu_972_p2[3:0]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[3]),
        .I1(acc_H1_prog_V_reg[3]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[2]),
        .I1(acc_H1_prog_V_reg[2]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[1]),
        .I1(acc_H1_prog_V_reg[1]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[0]),
        .I1(acc_H1_prog_V_reg[0]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[40]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[41]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[42]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[43]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[43:40]),
        .O(phase_H1_prog_offset_fu_972_p2[43:40]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[43]),
        .I1(acc_H1_prog_V_reg[43]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[42]),
        .I1(acc_H1_prog_V_reg[42]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[41]),
        .I1(acc_H1_prog_V_reg[41]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[40]),
        .I1(acc_H1_prog_V_reg[40]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[44]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[45]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[46]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[47]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,inputs_current_offse_1[46:44]}),
        .O(phase_H1_prog_offset_fu_972_p2[47:44]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[47]),
        .I1(acc_H1_prog_V_reg[47]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[46]),
        .I1(acc_H1_prog_V_reg[46]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[45]),
        .I1(acc_H1_prog_V_reg[45]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[44]),
        .I1(acc_H1_prog_V_reg[44]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[4]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[5]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[6]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[7]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ),
        .CO({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(inputs_current_offse_1[7:4]),
        .O(phase_H1_prog_offset_fu_972_p2[7:4]),
        .S({\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.I0(inputs_current_offse_1[7]),
        .I1(acc_H1_prog_V_reg[7]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(inputs_current_offse_1[6]),
        .I1(acc_H1_prog_V_reg[6]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(inputs_current_offse_1[5]),
        .I1(acc_H1_prog_V_reg[5]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(inputs_current_offse_1[4]),
        .I1(acc_H1_prog_V_reg[4]),
        .O(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[8]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* srl_bus_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(phase_H1_prog_offset_fu_972_p2[9]),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[10]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[11]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[12]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[13]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[14]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[15]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[16]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[17]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[18]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[19]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[1]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[20]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[21]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[22]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[23]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[24]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[25]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[26]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[27]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[28]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[29]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[2]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[30]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[31]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[32]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[33]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[34]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[35]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[36]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[37]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[38]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[39]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[3]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[40]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[41]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[42]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[43]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[44]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[45]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[46]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[47]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[4]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[5]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[6]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[7]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[8]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\phase_H1_prog_offset_reg_1587_pp0_iter4_reg_reg[9]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[47]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate_n_0));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__0
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[46]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__1
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[45]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__10
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[36]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__10_n_0));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__11
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[35]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__12
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[34]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__13
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[33]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__13_n_0));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__14
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[32]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__14_n_0));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__15
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[31]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__15_n_0));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__16
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[30]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__17
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[29]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__17_n_0));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__18
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[28]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__19
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[27]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__19_n_0));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__2
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[44]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__20
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[26]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__21
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[25]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__22
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[24]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__22_n_0));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__23
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[23]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__24
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[22]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__24_n_0));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__25
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[21]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__25_n_0));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__26
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[20]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__26_n_0));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__27
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[19]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__27_n_0));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__28
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[18]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__28_n_0));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__29
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[17]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__29_n_0));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__3
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[43]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__30
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[16]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__31
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[15]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__31_n_0));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__32
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[14]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__32_n_0));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__33
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[13]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__33_n_0));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__34
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[12]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__34_n_0));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__35
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[11]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__35_n_0));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__36
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[10]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__36_n_0));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__37
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[9]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__37_n_0));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__38
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[8]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__38_n_0));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__39
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[7]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__39_n_0));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__4
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[42]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__40
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[6]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__40_n_0));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__41
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[5]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__41_n_0));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__42
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[4]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__42_n_0));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__43
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[3]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__43_n_0));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__44
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[2]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__44_n_0));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__45
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[1]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__45_n_0));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__46
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__46_n_0));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__5
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[41]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__6
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[40]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__7
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[39]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__8
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[38]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__9
       (.I0(\phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg[37]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__9_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__46_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__36_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__35_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__34_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__33_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__32_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__31_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__30_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__29_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__28_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__27_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__45_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__26_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__25_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__24_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__23_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__22_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__21_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__20_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__19_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__18_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__17_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__44_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__16_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__15_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__14_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__13_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__12_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__11_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__10_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__9_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__8_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__7_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__43_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__6_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[40]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__5_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__4_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__3_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__2_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__1_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__0_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__42_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__41_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__40_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__39_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__38_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_prog_offset_reg_1587_pp0_iter6_reg_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_prog_offset_reg_1587_pp0_iter5_reg_reg_gate__37_n_0),
        .Q(phase_H1_prog_offset_reg_1587_pp0_iter6_reg[9]),
        .R(ap_rst));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[11]_i_2 
       (.I0(p_5_in[11]),
        .I1(inputs_current_offse_4[11]),
        .O(\phase_H1_trunc_AM_on_reg_1597[11]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[11]_i_3 
       (.I0(p_5_in[10]),
        .I1(inputs_current_offse_4[10]),
        .O(\phase_H1_trunc_AM_on_reg_1597[11]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[11]_i_4 
       (.I0(p_5_in[9]),
        .I1(inputs_current_offse_4[9]),
        .O(\phase_H1_trunc_AM_on_reg_1597[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[11]_i_5 
       (.I0(p_5_in[8]),
        .I1(inputs_current_offse_4[8]),
        .O(\phase_H1_trunc_AM_on_reg_1597[11]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[15]_i_2 
       (.I0(p_5_in[15]),
        .I1(inputs_current_offse_4[15]),
        .O(\phase_H1_trunc_AM_on_reg_1597[15]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[15]_i_3 
       (.I0(p_5_in[14]),
        .I1(inputs_current_offse_4[14]),
        .O(\phase_H1_trunc_AM_on_reg_1597[15]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[15]_i_4 
       (.I0(p_5_in[13]),
        .I1(inputs_current_offse_4[13]),
        .O(\phase_H1_trunc_AM_on_reg_1597[15]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[15]_i_5 
       (.I0(p_5_in[12]),
        .I1(inputs_current_offse_4[12]),
        .O(\phase_H1_trunc_AM_on_reg_1597[15]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[19]_i_2 
       (.I0(p_5_in[19]),
        .I1(inputs_current_offse_4[19]),
        .O(\phase_H1_trunc_AM_on_reg_1597[19]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[19]_i_3 
       (.I0(p_5_in[18]),
        .I1(inputs_current_offse_4[18]),
        .O(\phase_H1_trunc_AM_on_reg_1597[19]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[19]_i_4 
       (.I0(p_5_in[17]),
        .I1(inputs_current_offse_4[17]),
        .O(\phase_H1_trunc_AM_on_reg_1597[19]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[19]_i_5 
       (.I0(p_5_in[16]),
        .I1(inputs_current_offse_4[16]),
        .O(\phase_H1_trunc_AM_on_reg_1597[19]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[23]_i_2 
       (.I0(p_5_in[23]),
        .I1(inputs_current_offse_4[23]),
        .O(\phase_H1_trunc_AM_on_reg_1597[23]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[23]_i_3 
       (.I0(p_5_in[22]),
        .I1(inputs_current_offse_4[22]),
        .O(\phase_H1_trunc_AM_on_reg_1597[23]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[23]_i_4 
       (.I0(p_5_in[21]),
        .I1(inputs_current_offse_4[21]),
        .O(\phase_H1_trunc_AM_on_reg_1597[23]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[23]_i_5 
       (.I0(p_5_in[20]),
        .I1(inputs_current_offse_4[20]),
        .O(\phase_H1_trunc_AM_on_reg_1597[23]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[27]_i_2 
       (.I0(p_5_in[27]),
        .I1(inputs_current_offse_4[27]),
        .O(\phase_H1_trunc_AM_on_reg_1597[27]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[27]_i_3 
       (.I0(p_5_in[26]),
        .I1(inputs_current_offse_4[26]),
        .O(\phase_H1_trunc_AM_on_reg_1597[27]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[27]_i_4 
       (.I0(p_5_in[25]),
        .I1(inputs_current_offse_4[25]),
        .O(\phase_H1_trunc_AM_on_reg_1597[27]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[27]_i_5 
       (.I0(p_5_in[24]),
        .I1(inputs_current_offse_4[24]),
        .O(\phase_H1_trunc_AM_on_reg_1597[27]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[31]_i_2 
       (.I0(p_5_in[31]),
        .I1(inputs_current_offse_4[31]),
        .O(\phase_H1_trunc_AM_on_reg_1597[31]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[31]_i_3 
       (.I0(p_5_in[30]),
        .I1(inputs_current_offse_4[30]),
        .O(\phase_H1_trunc_AM_on_reg_1597[31]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[31]_i_4 
       (.I0(p_5_in[29]),
        .I1(inputs_current_offse_4[29]),
        .O(\phase_H1_trunc_AM_on_reg_1597[31]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[31]_i_5 
       (.I0(p_5_in[28]),
        .I1(inputs_current_offse_4[28]),
        .O(\phase_H1_trunc_AM_on_reg_1597[31]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[35]_i_2 
       (.I0(p_5_in[35]),
        .I1(inputs_current_offse_4[35]),
        .O(\phase_H1_trunc_AM_on_reg_1597[35]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[35]_i_3 
       (.I0(p_5_in[34]),
        .I1(inputs_current_offse_4[34]),
        .O(\phase_H1_trunc_AM_on_reg_1597[35]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[35]_i_4 
       (.I0(p_5_in[33]),
        .I1(inputs_current_offse_4[33]),
        .O(\phase_H1_trunc_AM_on_reg_1597[35]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[35]_i_5 
       (.I0(p_5_in[32]),
        .I1(inputs_current_offse_4[32]),
        .O(\phase_H1_trunc_AM_on_reg_1597[35]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[39]_i_2 
       (.I0(p_5_in[39]),
        .I1(inputs_current_offse_4[39]),
        .O(\phase_H1_trunc_AM_on_reg_1597[39]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[39]_i_3 
       (.I0(p_5_in[38]),
        .I1(inputs_current_offse_4[38]),
        .O(\phase_H1_trunc_AM_on_reg_1597[39]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[39]_i_4 
       (.I0(p_5_in[37]),
        .I1(inputs_current_offse_4[37]),
        .O(\phase_H1_trunc_AM_on_reg_1597[39]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[39]_i_5 
       (.I0(p_5_in[36]),
        .I1(inputs_current_offse_4[36]),
        .O(\phase_H1_trunc_AM_on_reg_1597[39]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[3]_i_2 
       (.I0(p_5_in[3]),
        .I1(inputs_current_offse_4[3]),
        .O(\phase_H1_trunc_AM_on_reg_1597[3]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[3]_i_3 
       (.I0(p_5_in[2]),
        .I1(inputs_current_offse_4[2]),
        .O(\phase_H1_trunc_AM_on_reg_1597[3]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[3]_i_4 
       (.I0(p_5_in[1]),
        .I1(inputs_current_offse_4[1]),
        .O(\phase_H1_trunc_AM_on_reg_1597[3]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[3]_i_5 
       (.I0(p_5_in[0]),
        .I1(inputs_current_offse_4[0]),
        .O(\phase_H1_trunc_AM_on_reg_1597[3]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[40]_i_2 
       (.I0(p_5_in__0[43]),
        .I1(inputs_current_offse_4[43]),
        .O(\phase_H1_trunc_AM_on_reg_1597[40]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[40]_i_3 
       (.I0(p_5_in__0[42]),
        .I1(inputs_current_offse_4[42]),
        .O(\phase_H1_trunc_AM_on_reg_1597[40]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[40]_i_4 
       (.I0(p_5_in__0[41]),
        .I1(inputs_current_offse_4[41]),
        .O(\phase_H1_trunc_AM_on_reg_1597[40]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[40]_i_5 
       (.I0(p_5_in[40]),
        .I1(inputs_current_offse_4[40]),
        .O(\phase_H1_trunc_AM_on_reg_1597[40]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT5 #(
    .INIT(32'hAAA8AAAA)) 
    \phase_H1_trunc_AM_on_reg_1597[41]_i_1 
       (.I0(r_V_6_fu_998_p2__0[41]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[41]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h2AAAAAA2)) 
    \phase_H1_trunc_AM_on_reg_1597[42]_i_1 
       (.I0(r_V_6_fu_998_p2__0[42]),
        .I1(or_cond_reg_1520),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[42]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h22A8AAAA)) 
    \phase_H1_trunc_AM_on_reg_1597[43]_i_1 
       (.I0(r_V_6_fu_998_p2__0[43]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[43]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'h2A2A2AA2)) 
    \phase_H1_trunc_AM_on_reg_1597[44]_i_1 
       (.I0(r_V_6_fu_998_p2__0[44]),
        .I1(or_cond_reg_1520),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[44]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h2220AAAA)) 
    \phase_H1_trunc_AM_on_reg_1597[45]_i_1 
       (.I0(r_V_6_fu_998_p2__0[45]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[45]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT5 #(
    .INIT(32'h0028AAAA)) 
    \phase_H1_trunc_AM_on_reg_1597[46]_i_1 
       (.I0(r_V_6_fu_998_p2__0[46]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[46]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'h0020AAAA)) 
    \phase_H1_trunc_AM_on_reg_1597[47]_i_1 
       (.I0(r_V_6_fu_998_p2__0[47]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .O(phase_H1_trunc_AM_on_fu_1004_p2[47]));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[47]_i_3 
       (.I0(inputs_current_offse_4[47]),
        .I1(p_5_in__0[47]),
        .O(\phase_H1_trunc_AM_on_reg_1597[47]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[47]_i_4 
       (.I0(p_5_in__0[46]),
        .I1(inputs_current_offse_4[46]),
        .O(\phase_H1_trunc_AM_on_reg_1597[47]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[47]_i_5 
       (.I0(p_5_in__0[45]),
        .I1(inputs_current_offse_4[45]),
        .O(\phase_H1_trunc_AM_on_reg_1597[47]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[47]_i_6 
       (.I0(p_5_in__0[44]),
        .I1(inputs_current_offse_4[44]),
        .O(\phase_H1_trunc_AM_on_reg_1597[47]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[7]_i_2 
       (.I0(p_5_in[7]),
        .I1(inputs_current_offse_4[7]),
        .O(\phase_H1_trunc_AM_on_reg_1597[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[7]_i_3 
       (.I0(p_5_in[6]),
        .I1(inputs_current_offse_4[6]),
        .O(\phase_H1_trunc_AM_on_reg_1597[7]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[7]_i_4 
       (.I0(p_5_in[5]),
        .I1(inputs_current_offse_4[5]),
        .O(\phase_H1_trunc_AM_on_reg_1597[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \phase_H1_trunc_AM_on_reg_1597[7]_i_5 
       (.I0(p_5_in[4]),
        .I1(inputs_current_offse_4[4]),
        .O(\phase_H1_trunc_AM_on_reg_1597[7]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[0]),
        .Q(phase_H1_trunc_AM_on_reg_1597[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[10]),
        .Q(phase_H1_trunc_AM_on_reg_1597[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[11]),
        .Q(phase_H1_trunc_AM_on_reg_1597[11]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[11:8]),
        .O(r_V_6_fu_998_p2[11:8]),
        .S({\phase_H1_trunc_AM_on_reg_1597[11]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[11]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[11]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[11]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[12]),
        .Q(phase_H1_trunc_AM_on_reg_1597[12]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[13]),
        .Q(phase_H1_trunc_AM_on_reg_1597[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[14]),
        .Q(phase_H1_trunc_AM_on_reg_1597[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[15]),
        .Q(phase_H1_trunc_AM_on_reg_1597[15]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[11]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[15:12]),
        .O(r_V_6_fu_998_p2[15:12]),
        .S({\phase_H1_trunc_AM_on_reg_1597[15]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[15]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[15]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[15]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[16]),
        .Q(phase_H1_trunc_AM_on_reg_1597[16]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[17]),
        .Q(phase_H1_trunc_AM_on_reg_1597[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[18]),
        .Q(phase_H1_trunc_AM_on_reg_1597[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[19]),
        .Q(phase_H1_trunc_AM_on_reg_1597[19]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[15]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[19:16]),
        .O(r_V_6_fu_998_p2[19:16]),
        .S({\phase_H1_trunc_AM_on_reg_1597[19]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[19]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[19]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[19]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[1]),
        .Q(phase_H1_trunc_AM_on_reg_1597[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[20]),
        .Q(phase_H1_trunc_AM_on_reg_1597[20]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[21]),
        .Q(phase_H1_trunc_AM_on_reg_1597[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[22]),
        .Q(phase_H1_trunc_AM_on_reg_1597[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[23]),
        .Q(phase_H1_trunc_AM_on_reg_1597[23]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[19]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[23:20]),
        .O(r_V_6_fu_998_p2[23:20]),
        .S({\phase_H1_trunc_AM_on_reg_1597[23]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[23]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[23]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[23]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[24]),
        .Q(phase_H1_trunc_AM_on_reg_1597[24]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[25]),
        .Q(phase_H1_trunc_AM_on_reg_1597[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[26]),
        .Q(phase_H1_trunc_AM_on_reg_1597[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[27]),
        .Q(phase_H1_trunc_AM_on_reg_1597[27]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[23]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[27:24]),
        .O(r_V_6_fu_998_p2[27:24]),
        .S({\phase_H1_trunc_AM_on_reg_1597[27]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[27]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[27]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[27]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[28]),
        .Q(phase_H1_trunc_AM_on_reg_1597[28]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[29]),
        .Q(phase_H1_trunc_AM_on_reg_1597[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[2]),
        .Q(phase_H1_trunc_AM_on_reg_1597[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[30]),
        .Q(phase_H1_trunc_AM_on_reg_1597[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[31]),
        .Q(phase_H1_trunc_AM_on_reg_1597[31]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[27]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[31:28]),
        .O(r_V_6_fu_998_p2[31:28]),
        .S({\phase_H1_trunc_AM_on_reg_1597[31]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[31]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[31]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[31]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[32]),
        .Q(phase_H1_trunc_AM_on_reg_1597[32]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[33]),
        .Q(phase_H1_trunc_AM_on_reg_1597[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[34]),
        .Q(phase_H1_trunc_AM_on_reg_1597[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[35]),
        .Q(phase_H1_trunc_AM_on_reg_1597[35]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[31]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[35:32]),
        .O(r_V_6_fu_998_p2[35:32]),
        .S({\phase_H1_trunc_AM_on_reg_1597[35]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[35]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[35]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[35]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[36]),
        .Q(phase_H1_trunc_AM_on_reg_1597[36]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[37]),
        .Q(phase_H1_trunc_AM_on_reg_1597[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[38]),
        .Q(phase_H1_trunc_AM_on_reg_1597[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[39]),
        .Q(phase_H1_trunc_AM_on_reg_1597[39]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[35]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[39:36]),
        .O(r_V_6_fu_998_p2[39:36]),
        .S({\phase_H1_trunc_AM_on_reg_1597[39]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[39]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[39]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[39]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[3]),
        .Q(phase_H1_trunc_AM_on_reg_1597[3]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1 
       (.CI(\<const0> ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[3:0]),
        .O(r_V_6_fu_998_p2[3:0]),
        .S({\phase_H1_trunc_AM_on_reg_1597[3]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[3]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[3]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[3]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[40]),
        .Q(phase_H1_trunc_AM_on_reg_1597[40]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[39]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_5_in__0[43:41],p_5_in[40]}),
        .O({r_V_6_fu_998_p2__0[43:41],r_V_6_fu_998_p2[40]}),
        .S({\phase_H1_trunc_AM_on_reg_1597[40]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[40]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[40]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[40]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[41]),
        .Q(phase_H1_trunc_AM_on_reg_1597[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[42]),
        .Q(phase_H1_trunc_AM_on_reg_1597[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[43]),
        .Q(phase_H1_trunc_AM_on_reg_1597[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[44]),
        .Q(phase_H1_trunc_AM_on_reg_1597[44]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[45]),
        .Q(phase_H1_trunc_AM_on_reg_1597[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[46]),
        .Q(phase_H1_trunc_AM_on_reg_1597[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(phase_H1_trunc_AM_on_fu_1004_p2[47]),
        .Q(phase_H1_trunc_AM_on_reg_1597[47]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[40]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[47]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,p_5_in__0[46:44]}),
        .O(r_V_6_fu_998_p2__0[47:44]),
        .S({\phase_H1_trunc_AM_on_reg_1597[47]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[47]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[47]_i_5_n_0 ,\phase_H1_trunc_AM_on_reg_1597[47]_i_6_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[4]),
        .Q(phase_H1_trunc_AM_on_reg_1597[4]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[5]),
        .Q(phase_H1_trunc_AM_on_reg_1597[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[6]),
        .Q(phase_H1_trunc_AM_on_reg_1597[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[7]),
        .Q(phase_H1_trunc_AM_on_reg_1597[7]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1 
       (.CI(\phase_H1_trunc_AM_on_reg_1597_reg[3]_i_1_n_0 ),
        .CO({\phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_0 ,\phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_1 ,\phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_2 ,\phase_H1_trunc_AM_on_reg_1597_reg[7]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(p_5_in[7:4]),
        .O(r_V_6_fu_998_p2[7:4]),
        .S({\phase_H1_trunc_AM_on_reg_1597[7]_i_2_n_0 ,\phase_H1_trunc_AM_on_reg_1597[7]_i_3_n_0 ,\phase_H1_trunc_AM_on_reg_1597[7]_i_4_n_0 ,\phase_H1_trunc_AM_on_reg_1597[7]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[8]),
        .Q(phase_H1_trunc_AM_on_reg_1597[8]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \phase_H1_trunc_AM_on_reg_1597_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_6_fu_998_p2[9]),
        .Q(phase_H1_trunc_AM_on_reg_1597[9]),
        .R(ap_rst));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[0]_i_1 
       (.I0(inputs_current_offse_3[0]),
        .O(r_V_fu_1058_p2[0]));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[12]_i_2 
       (.I0(inputs_current_offse_3[12]),
        .O(\r_V_reg_1610[12]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[12]_i_3 
       (.I0(inputs_current_offse_3[11]),
        .O(\r_V_reg_1610[12]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[12]_i_4 
       (.I0(inputs_current_offse_3[10]),
        .O(\r_V_reg_1610[12]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[12]_i_5 
       (.I0(inputs_current_offse_3[9]),
        .O(\r_V_reg_1610[12]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[16]_i_2 
       (.I0(inputs_current_offse_3[16]),
        .O(\r_V_reg_1610[16]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[16]_i_3 
       (.I0(inputs_current_offse_3[15]),
        .O(\r_V_reg_1610[16]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[16]_i_4 
       (.I0(inputs_current_offse_3[14]),
        .O(\r_V_reg_1610[16]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[16]_i_5 
       (.I0(inputs_current_offse_3[13]),
        .O(\r_V_reg_1610[16]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[20]_i_2 
       (.I0(inputs_current_offse_3[20]),
        .O(\r_V_reg_1610[20]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[20]_i_3 
       (.I0(inputs_current_offse_3[19]),
        .O(\r_V_reg_1610[20]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[20]_i_4 
       (.I0(inputs_current_offse_3[18]),
        .O(\r_V_reg_1610[20]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[20]_i_5 
       (.I0(inputs_current_offse_3[17]),
        .O(\r_V_reg_1610[20]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[24]_i_2 
       (.I0(inputs_current_offse_3[24]),
        .O(\r_V_reg_1610[24]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[24]_i_3 
       (.I0(inputs_current_offse_3[23]),
        .O(\r_V_reg_1610[24]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[24]_i_4 
       (.I0(inputs_current_offse_3[22]),
        .O(\r_V_reg_1610[24]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[24]_i_5 
       (.I0(inputs_current_offse_3[21]),
        .O(\r_V_reg_1610[24]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[28]_i_2 
       (.I0(inputs_current_offse_3[28]),
        .O(\r_V_reg_1610[28]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[28]_i_3 
       (.I0(inputs_current_offse_3[27]),
        .O(\r_V_reg_1610[28]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[28]_i_4 
       (.I0(inputs_current_offse_3[26]),
        .O(\r_V_reg_1610[28]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[28]_i_5 
       (.I0(inputs_current_offse_3[25]),
        .O(\r_V_reg_1610[28]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[32]_i_2 
       (.I0(inputs_current_offse_3[32]),
        .O(\r_V_reg_1610[32]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[32]_i_3 
       (.I0(inputs_current_offse_3[31]),
        .O(\r_V_reg_1610[32]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[32]_i_4 
       (.I0(inputs_current_offse_3[30]),
        .O(\r_V_reg_1610[32]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[32]_i_5 
       (.I0(inputs_current_offse_3[29]),
        .O(\r_V_reg_1610[32]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[36]_i_2 
       (.I0(inputs_current_offse_3[36]),
        .O(\r_V_reg_1610[36]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[36]_i_3 
       (.I0(inputs_current_offse_3[35]),
        .O(\r_V_reg_1610[36]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[36]_i_4 
       (.I0(inputs_current_offse_3[34]),
        .O(\r_V_reg_1610[36]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[36]_i_5 
       (.I0(inputs_current_offse_3[33]),
        .O(\r_V_reg_1610[36]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h0100FEFF)) 
    \r_V_reg_1610[40]_i_2 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .I4(inputs_current_offse_3[40]),
        .O(\r_V_reg_1610[40]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[40]_i_3 
       (.I0(inputs_current_offse_3[39]),
        .O(\r_V_reg_1610[40]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[40]_i_4 
       (.I0(inputs_current_offse_3[38]),
        .O(\r_V_reg_1610[40]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[40]_i_5 
       (.I0(inputs_current_offse_3[37]),
        .O(\r_V_reg_1610[40]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h54FF)) 
    \r_V_reg_1610[44]_i_2 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I3(or_cond_reg_1520),
        .O(p_Val2_22_fu_1036_p4[44]));
  LUT4 #(
    .INIT(16'h77FD)) 
    \r_V_reg_1610[44]_i_3 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(\r_V_reg_1610[44]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hAB0054FF)) 
    \r_V_reg_1610[44]_i_4 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I3(or_cond_reg_1520),
        .I4(inputs_current_offse_3[44]),
        .O(\r_V_reg_1610[44]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h8882777D)) 
    \r_V_reg_1610[44]_i_5 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(inputs_current_offse_3[43]),
        .O(\r_V_reg_1610[44]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hA1005EFF)) 
    \r_V_reg_1610[44]_i_6 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .I4(inputs_current_offse_3[42]),
        .O(\r_V_reg_1610[44]_i_6_n_0 ));
  LUT5 #(
    .INIT(32'h80027FFD)) 
    \r_V_reg_1610[44]_i_7 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(inputs_current_offse_3[41]),
        .O(\r_V_reg_1610[44]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h06FF)) 
    \r_V_reg_1610[48]_i_2 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .O(p_Val2_22_fu_1036_p4[45]));
  LUT5 #(
    .INIT(32'hFB0004FF)) 
    \r_V_reg_1610[48]_i_3 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .I4(inputs_current_offse_3[46]),
        .O(\r_V_reg_1610[48]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hF90006FF)) 
    \r_V_reg_1610[48]_i_4 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .I4(inputs_current_offse_3[45]),
        .O(\r_V_reg_1610[48]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[4]_i_2 
       (.I0(inputs_current_offse_3[4]),
        .O(\r_V_reg_1610[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[4]_i_3 
       (.I0(inputs_current_offse_3[3]),
        .O(\r_V_reg_1610[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[4]_i_4 
       (.I0(inputs_current_offse_3[2]),
        .O(\r_V_reg_1610[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[4]_i_5 
       (.I0(inputs_current_offse_3[1]),
        .O(\r_V_reg_1610[4]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[8]_i_2 
       (.I0(inputs_current_offse_3[8]),
        .O(\r_V_reg_1610[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[8]_i_3 
       (.I0(inputs_current_offse_3[7]),
        .O(\r_V_reg_1610[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[8]_i_4 
       (.I0(inputs_current_offse_3[6]),
        .O(\r_V_reg_1610[8]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \r_V_reg_1610[8]_i_5 
       (.I0(inputs_current_offse_3[5]),
        .O(\r_V_reg_1610[8]_i_5_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[0]),
        .Q(r_V_reg_1610[0]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[10] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[10]),
        .Q(r_V_reg_1610[10]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[11] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[11]),
        .Q(r_V_reg_1610[11]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[12] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[12]),
        .Q(r_V_reg_1610[12]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[12]_i_1 
       (.CI(\r_V_reg_1610_reg[8]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[12]_i_1_n_0 ,\r_V_reg_1610_reg[12]_i_1_n_1 ,\r_V_reg_1610_reg[12]_i_1_n_2 ,\r_V_reg_1610_reg[12]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[12:9]),
        .S({\r_V_reg_1610[12]_i_2_n_0 ,\r_V_reg_1610[12]_i_3_n_0 ,\r_V_reg_1610[12]_i_4_n_0 ,\r_V_reg_1610[12]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[13] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[13]),
        .Q(r_V_reg_1610[13]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[14] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[14]),
        .Q(r_V_reg_1610[14]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[15] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[15]),
        .Q(r_V_reg_1610[15]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[16] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[16]),
        .Q(r_V_reg_1610[16]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[16]_i_1 
       (.CI(\r_V_reg_1610_reg[12]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[16]_i_1_n_0 ,\r_V_reg_1610_reg[16]_i_1_n_1 ,\r_V_reg_1610_reg[16]_i_1_n_2 ,\r_V_reg_1610_reg[16]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[16:13]),
        .S({\r_V_reg_1610[16]_i_2_n_0 ,\r_V_reg_1610[16]_i_3_n_0 ,\r_V_reg_1610[16]_i_4_n_0 ,\r_V_reg_1610[16]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[17] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[17]),
        .Q(r_V_reg_1610[17]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[18] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[18]),
        .Q(r_V_reg_1610[18]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[19] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[19]),
        .Q(r_V_reg_1610[19]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[1] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[1]),
        .Q(r_V_reg_1610[1]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[20] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[20]),
        .Q(r_V_reg_1610[20]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[20]_i_1 
       (.CI(\r_V_reg_1610_reg[16]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[20]_i_1_n_0 ,\r_V_reg_1610_reg[20]_i_1_n_1 ,\r_V_reg_1610_reg[20]_i_1_n_2 ,\r_V_reg_1610_reg[20]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[20:17]),
        .S({\r_V_reg_1610[20]_i_2_n_0 ,\r_V_reg_1610[20]_i_3_n_0 ,\r_V_reg_1610[20]_i_4_n_0 ,\r_V_reg_1610[20]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[21] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[21]),
        .Q(r_V_reg_1610[21]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[22] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[22]),
        .Q(r_V_reg_1610[22]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[23] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[23]),
        .Q(r_V_reg_1610[23]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[24] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[24]),
        .Q(r_V_reg_1610[24]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[24]_i_1 
       (.CI(\r_V_reg_1610_reg[20]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[24]_i_1_n_0 ,\r_V_reg_1610_reg[24]_i_1_n_1 ,\r_V_reg_1610_reg[24]_i_1_n_2 ,\r_V_reg_1610_reg[24]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[24:21]),
        .S({\r_V_reg_1610[24]_i_2_n_0 ,\r_V_reg_1610[24]_i_3_n_0 ,\r_V_reg_1610[24]_i_4_n_0 ,\r_V_reg_1610[24]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[25] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[25]),
        .Q(r_V_reg_1610[25]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[26] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[26]),
        .Q(r_V_reg_1610[26]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[27] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[27]),
        .Q(r_V_reg_1610[27]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[28] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[28]),
        .Q(r_V_reg_1610[28]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[28]_i_1 
       (.CI(\r_V_reg_1610_reg[24]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[28]_i_1_n_0 ,\r_V_reg_1610_reg[28]_i_1_n_1 ,\r_V_reg_1610_reg[28]_i_1_n_2 ,\r_V_reg_1610_reg[28]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[28:25]),
        .S({\r_V_reg_1610[28]_i_2_n_0 ,\r_V_reg_1610[28]_i_3_n_0 ,\r_V_reg_1610[28]_i_4_n_0 ,\r_V_reg_1610[28]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[29] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[29]),
        .Q(r_V_reg_1610[29]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[2] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[2]),
        .Q(r_V_reg_1610[2]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[30] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[30]),
        .Q(r_V_reg_1610[30]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[31] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[31]),
        .Q(r_V_reg_1610[31]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[32] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[32]),
        .Q(r_V_reg_1610[32]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[32]_i_1 
       (.CI(\r_V_reg_1610_reg[28]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[32]_i_1_n_0 ,\r_V_reg_1610_reg[32]_i_1_n_1 ,\r_V_reg_1610_reg[32]_i_1_n_2 ,\r_V_reg_1610_reg[32]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[32:29]),
        .S({\r_V_reg_1610[32]_i_2_n_0 ,\r_V_reg_1610[32]_i_3_n_0 ,\r_V_reg_1610[32]_i_4_n_0 ,\r_V_reg_1610[32]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[33] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[33]),
        .Q(r_V_reg_1610[33]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[34] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[34]),
        .Q(r_V_reg_1610[34]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[35] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[35]),
        .Q(r_V_reg_1610[35]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[36] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[36]),
        .Q(r_V_reg_1610[36]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[36]_i_1 
       (.CI(\r_V_reg_1610_reg[32]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[36]_i_1_n_0 ,\r_V_reg_1610_reg[36]_i_1_n_1 ,\r_V_reg_1610_reg[36]_i_1_n_2 ,\r_V_reg_1610_reg[36]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[36:33]),
        .S({\r_V_reg_1610[36]_i_2_n_0 ,\r_V_reg_1610[36]_i_3_n_0 ,\r_V_reg_1610[36]_i_4_n_0 ,\r_V_reg_1610[36]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[37] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[37]),
        .Q(r_V_reg_1610[37]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[38] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[38]),
        .Q(r_V_reg_1610[38]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[39] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[39]),
        .Q(r_V_reg_1610[39]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[3] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[3]),
        .Q(r_V_reg_1610[3]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[40] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[40]),
        .Q(r_V_reg_1610[40]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[40]_i_1 
       (.CI(\r_V_reg_1610_reg[36]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[40]_i_1_n_0 ,\r_V_reg_1610_reg[40]_i_1_n_1 ,\r_V_reg_1610_reg[40]_i_1_n_2 ,\r_V_reg_1610_reg[40]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({inputs_current_offse_3[40],\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[40:37]),
        .S({\r_V_reg_1610[40]_i_2_n_0 ,\r_V_reg_1610[40]_i_3_n_0 ,\r_V_reg_1610[40]_i_4_n_0 ,\r_V_reg_1610[40]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[41] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[41]),
        .Q(r_V_reg_1610[41]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[42] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[42]),
        .Q(r_V_reg_1610[42]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[43] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[43]),
        .Q(r_V_reg_1610[43]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[44] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[44]),
        .Q(r_V_reg_1610[44]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[44]_i_1 
       (.CI(\r_V_reg_1610_reg[40]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[44]_i_1_n_0 ,\r_V_reg_1610_reg[44]_i_1_n_1 ,\r_V_reg_1610_reg[44]_i_1_n_2 ,\r_V_reg_1610_reg[44]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({p_Val2_22_fu_1036_p4[44],inputs_current_offse_3[43],\r_V_reg_1610[44]_i_3_n_0 ,inputs_current_offse_3[41]}),
        .O(r_V_fu_1058_p2[44:41]),
        .S({\r_V_reg_1610[44]_i_4_n_0 ,\r_V_reg_1610[44]_i_5_n_0 ,\r_V_reg_1610[44]_i_6_n_0 ,\r_V_reg_1610[44]_i_7_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[45] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[45]),
        .Q(r_V_reg_1610[45]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[46] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[46]),
        .Q(r_V_reg_1610[46]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[47] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[47]),
        .Q(r_V_reg_1610[47]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[48] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[48]),
        .Q(r_V_reg_1610[48]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[48]_i_1 
       (.CI(\r_V_reg_1610_reg[44]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[48]_i_1_n_1 ,\r_V_reg_1610_reg[48]_i_1_n_2 ,\r_V_reg_1610_reg[48]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const1> ,inputs_current_offse_3[46],p_Val2_22_fu_1036_p4[45]}),
        .O(r_V_fu_1058_p2[48:45]),
        .S({\<const1> ,inputs_current_offse_3[47],\r_V_reg_1610[48]_i_3_n_0 ,\r_V_reg_1610[48]_i_4_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[4] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[4]),
        .Q(r_V_reg_1610[4]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[4]_i_1 
       (.CI(\<const0> ),
        .CO({\r_V_reg_1610_reg[4]_i_1_n_0 ,\r_V_reg_1610_reg[4]_i_1_n_1 ,\r_V_reg_1610_reg[4]_i_1_n_2 ,\r_V_reg_1610_reg[4]_i_1_n_3 }),
        .CYINIT(inputs_current_offse_3[0]),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[4:1]),
        .S({\r_V_reg_1610[4]_i_2_n_0 ,\r_V_reg_1610[4]_i_3_n_0 ,\r_V_reg_1610[4]_i_4_n_0 ,\r_V_reg_1610[4]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[5] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[5]),
        .Q(r_V_reg_1610[5]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[6] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[6]),
        .Q(r_V_reg_1610[6]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[7] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[7]),
        .Q(r_V_reg_1610[7]),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[8] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[8]),
        .Q(r_V_reg_1610[8]),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \r_V_reg_1610_reg[8]_i_1 
       (.CI(\r_V_reg_1610_reg[4]_i_1_n_0 ),
        .CO({\r_V_reg_1610_reg[8]_i_1_n_0 ,\r_V_reg_1610_reg[8]_i_1_n_1 ,\r_V_reg_1610_reg[8]_i_1_n_2 ,\r_V_reg_1610_reg[8]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const1> ,\<const1> ,\<const1> ,\<const1> }),
        .O(r_V_fu_1058_p2[8:5]),
        .S({\r_V_reg_1610[8]_i_2_n_0 ,\r_V_reg_1610[8]_i_3_n_0 ,\r_V_reg_1610[8]_i_4_n_0 ,\r_V_reg_1610[8]_i_5_n_0 }));
  FDRE #(
    .INIT(1'b0)) 
    \r_V_reg_1610_reg[9] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(r_V_fu_1058_p2[9]),
        .Q(r_V_reg_1610[9]),
        .R(ap_rst));
  LUT6 #(
    .INIT(64'h00440347FFFFFFFF)) 
    \sel_tmp2_reg_1535[0]_i_1 
       (.I0(inputs_current_force),
        .I1(\or_cond_reg_1520[0]_i_2_n_0 ),
        .I2(ap_phi_reg_pp0_iter2_inputs_current_force_2_reg_468),
        .I3(inputs_current_enabl_1),
        .I4(ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450),
        .I5(\or_cond_reg_1520[0]_i_3_n_0 ),
        .O(sel_tmp2_fu_731_p2));
  FDRE #(
    .INIT(1'b0)) 
    \sel_tmp2_reg_1535_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(sel_tmp2_reg_1535),
        .Q(sel_tmp2_reg_1535_pp0_iter3_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \sel_tmp2_reg_1535_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(sel_tmp2_fu_731_p2),
        .Q(sel_tmp2_reg_1535),
        .R(ap_rst));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \sel_tmp3_reg_1566[0]_i_1 
       (.I0(\sel_tmp3_reg_1566[0]_i_2_n_0 ),
        .I1(\sel_tmp3_reg_1566[0]_i_3_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_4_n_0 ),
        .I3(\sel_tmp3_reg_1566[0]_i_5_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_6_n_0 ),
        .I5(\sel_tmp3_reg_1566[0]_i_7_n_0 ),
        .O(sel_tmp3_fu_938_p2));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \sel_tmp3_reg_1566[0]_i_10 
       (.I0(\p_Val2_12_reg_1560_reg[11]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560_reg[31]_i_2_n_7 ),
        .I2(\p_Val2_12_reg_1560_reg[3]_i_2_n_7 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[23]_i_2_n_5 ),
        .O(\sel_tmp3_reg_1566[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \sel_tmp3_reg_1566[0]_i_11 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_4_n_6 ),
        .I1(\p_Val2_12_reg_1560_reg[3]_i_2_n_5 ),
        .I2(\p_Val2_12_reg_1560_reg[27]_i_2_n_6 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[19]_i_2_n_6 ),
        .O(\sel_tmp3_reg_1566[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \sel_tmp3_reg_1566[0]_i_12 
       (.I0(\p_Val2_12_reg_1560_reg[41]_i_4_n_7 ),
        .I1(\p_Val2_12_reg_1560_reg[3]_i_2_n_4 ),
        .I2(\p_Val2_12_reg_1560_reg[35]_i_2_n_7 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[7]_i_2_n_4 ),
        .O(\sel_tmp3_reg_1566[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \sel_tmp3_reg_1566[0]_i_13 
       (.I0(\p_Val2_12_reg_1560_reg[7]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560_reg[11]_i_2_n_4 ),
        .I2(\p_Val2_12_reg_1560_reg[27]_i_2_n_5 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[7]_i_2_n_7 ),
        .O(\sel_tmp3_reg_1566[0]_i_13_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \sel_tmp3_reg_1566[0]_i_14 
       (.I0(sel0[5]),
        .I1(sel0[3]),
        .I2(sel0[2]),
        .O(\sel_tmp3_reg_1566[0]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF33333332)) 
    \sel_tmp3_reg_1566[0]_i_2 
       (.I0(\p_Val2_12_reg_1560_reg[35]_i_2_n_5 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[31]_i_2_n_4 ),
        .I3(\p_Val2_12_reg_1560_reg[11]_i_2_n_6 ),
        .I4(\p_Val2_12_reg_1560_reg[35]_i_2_n_6 ),
        .I5(\sel_tmp3_reg_1566[0]_i_8_n_0 ),
        .O(\sel_tmp3_reg_1566[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF33333332)) 
    \sel_tmp3_reg_1566[0]_i_3 
       (.I0(\p_Val2_12_reg_1560_reg[19]_i_2_n_4 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[15]_i_2_n_5 ),
        .I3(\p_Val2_12_reg_1560_reg[15]_i_2_n_4 ),
        .I4(\p_Val2_12_reg_1560_reg[31]_i_2_n_5 ),
        .I5(\sel_tmp3_reg_1566[0]_i_9_n_0 ),
        .O(\sel_tmp3_reg_1566[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \sel_tmp3_reg_1566[0]_i_4 
       (.I0(\p_Val2_12_reg_1560[24]_i_1_n_0 ),
        .I1(\p_Val2_12_reg_1560[16]_i_1_n_0 ),
        .I2(\sel_tmp3_reg_1566[0]_i_10_n_0 ),
        .I3(\sel_tmp3_reg_1566[0]_i_11_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_12_n_0 ),
        .O(\sel_tmp3_reg_1566[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFF00FF01)) 
    \sel_tmp3_reg_1566[0]_i_5 
       (.I0(\p_Val2_12_reg_1560_reg[3]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560_reg[19]_i_2_n_5 ),
        .I2(\p_Val2_12_reg_1560_reg[35]_i_2_n_4 ),
        .I3(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I4(\p_Val2_12_reg_1560_reg[7]_i_2_n_6 ),
        .O(\sel_tmp3_reg_1566[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF33333332)) 
    \sel_tmp3_reg_1566[0]_i_6 
       (.I0(\p_Val2_12_reg_1560_reg[23]_i_2_n_7 ),
        .I1(\p_Val2_12_reg_1560[41]_i_3_n_0 ),
        .I2(\p_Val2_12_reg_1560_reg[27]_i_2_n_4 ),
        .I3(\p_Val2_12_reg_1560_reg[39]_i_2_n_4 ),
        .I4(\p_Val2_12_reg_1560_reg[11]_i_2_n_7 ),
        .I5(\sel_tmp3_reg_1566[0]_i_13_n_0 ),
        .O(\sel_tmp3_reg_1566[0]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \sel_tmp3_reg_1566[0]_i_7 
       (.I0(inputs_current_force_2_reg_468),
        .I1(sel_tmp_reg_1527),
        .O(\sel_tmp3_reg_1566[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \sel_tmp3_reg_1566[0]_i_8 
       (.I0(\p_Val2_12_reg_1560_reg[15]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560_reg[15]_i_2_n_7 ),
        .I2(\p_Val2_12_reg_1560_reg[23]_i_2_n_4 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[39]_i_2_n_5 ),
        .O(\sel_tmp3_reg_1566[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h000000FF000000FE)) 
    \sel_tmp3_reg_1566[0]_i_9 
       (.I0(\p_Val2_12_reg_1560_reg[39]_i_2_n_6 ),
        .I1(\p_Val2_12_reg_1560_reg[23]_i_2_n_6 ),
        .I2(\p_Val2_12_reg_1560_reg[39]_i_2_n_7 ),
        .I3(\p_Val2_12_reg_1560[24]_i_3_n_0 ),
        .I4(\sel_tmp3_reg_1566[0]_i_14_n_0 ),
        .I5(\p_Val2_12_reg_1560_reg[31]_i_2_n_6 ),
        .O(\sel_tmp3_reg_1566[0]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sel_tmp3_reg_1566_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(sel_tmp3_fu_938_p2),
        .Q(sel_tmp3_reg_1566),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h8A888088)) 
    \sel_tmp_reg_1527[0]_i_1 
       (.I0(\or_cond_reg_1520[0]_i_3_n_0 ),
        .I1(ap_phi_reg_pp0_iter2_inputs_current_enabl_4_reg_450),
        .I2(inputs_valid_read_reg_1420),
        .I3(ap_enable_reg_pp0_iter2),
        .I4(inputs_current_enabl_1),
        .O(p_0_in47_out));
  FDRE #(
    .INIT(1'b0)) 
    \sel_tmp_reg_1527_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_0_in47_out),
        .Q(sel_tmp_reg_1527),
        .R(ap_rst));
  LUT3 #(
    .INIT(8'hFE)) 
    \storemerge_reg_1641[0]_i_1 
       (.I0(tmp_18_fu_1170_p2),
        .I1(sel_tmp2_reg_1535_pp0_iter3_reg),
        .I2(sel_tmp3_reg_1566),
        .O(storemerge_fu_1180_p2));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_10 
       (.I0(r_V_reg_1610[46]),
        .I1(phase_H1_trunc_AM_on_reg_1597[46]),
        .I2(r_V_reg_1610[47]),
        .I3(phase_H1_trunc_AM_on_reg_1597[47]),
        .O(\storemerge_reg_1641[0]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_11 
       (.I0(r_V_reg_1610[44]),
        .I1(phase_H1_trunc_AM_on_reg_1597[44]),
        .I2(r_V_reg_1610[45]),
        .I3(phase_H1_trunc_AM_on_reg_1597[45]),
        .O(\storemerge_reg_1641[0]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_12 
       (.I0(r_V_reg_1610[42]),
        .I1(phase_H1_trunc_AM_on_reg_1597[42]),
        .I2(r_V_reg_1610[43]),
        .I3(phase_H1_trunc_AM_on_reg_1597[43]),
        .O(\storemerge_reg_1641[0]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_13 
       (.I0(r_V_reg_1610[40]),
        .I1(phase_H1_trunc_AM_on_reg_1597[40]),
        .I2(r_V_reg_1610[41]),
        .I3(phase_H1_trunc_AM_on_reg_1597[41]),
        .O(\storemerge_reg_1641[0]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_15 
       (.I0(r_V_reg_1610[38]),
        .I1(phase_H1_trunc_AM_on_reg_1597[38]),
        .I2(phase_H1_trunc_AM_on_reg_1597[39]),
        .I3(r_V_reg_1610[39]),
        .O(\storemerge_reg_1641[0]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_16 
       (.I0(r_V_reg_1610[36]),
        .I1(phase_H1_trunc_AM_on_reg_1597[36]),
        .I2(phase_H1_trunc_AM_on_reg_1597[37]),
        .I3(r_V_reg_1610[37]),
        .O(\storemerge_reg_1641[0]_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_17 
       (.I0(r_V_reg_1610[34]),
        .I1(phase_H1_trunc_AM_on_reg_1597[34]),
        .I2(phase_H1_trunc_AM_on_reg_1597[35]),
        .I3(r_V_reg_1610[35]),
        .O(\storemerge_reg_1641[0]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_18 
       (.I0(r_V_reg_1610[32]),
        .I1(phase_H1_trunc_AM_on_reg_1597[32]),
        .I2(phase_H1_trunc_AM_on_reg_1597[33]),
        .I3(r_V_reg_1610[33]),
        .O(\storemerge_reg_1641[0]_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_19 
       (.I0(r_V_reg_1610[38]),
        .I1(phase_H1_trunc_AM_on_reg_1597[38]),
        .I2(r_V_reg_1610[39]),
        .I3(phase_H1_trunc_AM_on_reg_1597[39]),
        .O(\storemerge_reg_1641[0]_i_19_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_20 
       (.I0(r_V_reg_1610[36]),
        .I1(phase_H1_trunc_AM_on_reg_1597[36]),
        .I2(r_V_reg_1610[37]),
        .I3(phase_H1_trunc_AM_on_reg_1597[37]),
        .O(\storemerge_reg_1641[0]_i_20_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_21 
       (.I0(r_V_reg_1610[34]),
        .I1(phase_H1_trunc_AM_on_reg_1597[34]),
        .I2(r_V_reg_1610[35]),
        .I3(phase_H1_trunc_AM_on_reg_1597[35]),
        .O(\storemerge_reg_1641[0]_i_21_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_22 
       (.I0(r_V_reg_1610[32]),
        .I1(phase_H1_trunc_AM_on_reg_1597[32]),
        .I2(r_V_reg_1610[33]),
        .I3(phase_H1_trunc_AM_on_reg_1597[33]),
        .O(\storemerge_reg_1641[0]_i_22_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_24 
       (.I0(r_V_reg_1610[30]),
        .I1(phase_H1_trunc_AM_on_reg_1597[30]),
        .I2(phase_H1_trunc_AM_on_reg_1597[31]),
        .I3(r_V_reg_1610[31]),
        .O(\storemerge_reg_1641[0]_i_24_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_25 
       (.I0(r_V_reg_1610[28]),
        .I1(phase_H1_trunc_AM_on_reg_1597[28]),
        .I2(phase_H1_trunc_AM_on_reg_1597[29]),
        .I3(r_V_reg_1610[29]),
        .O(\storemerge_reg_1641[0]_i_25_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_26 
       (.I0(r_V_reg_1610[26]),
        .I1(phase_H1_trunc_AM_on_reg_1597[26]),
        .I2(phase_H1_trunc_AM_on_reg_1597[27]),
        .I3(r_V_reg_1610[27]),
        .O(\storemerge_reg_1641[0]_i_26_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_27 
       (.I0(r_V_reg_1610[24]),
        .I1(phase_H1_trunc_AM_on_reg_1597[24]),
        .I2(phase_H1_trunc_AM_on_reg_1597[25]),
        .I3(r_V_reg_1610[25]),
        .O(\storemerge_reg_1641[0]_i_27_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_28 
       (.I0(r_V_reg_1610[30]),
        .I1(phase_H1_trunc_AM_on_reg_1597[30]),
        .I2(r_V_reg_1610[31]),
        .I3(phase_H1_trunc_AM_on_reg_1597[31]),
        .O(\storemerge_reg_1641[0]_i_28_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_29 
       (.I0(r_V_reg_1610[28]),
        .I1(phase_H1_trunc_AM_on_reg_1597[28]),
        .I2(r_V_reg_1610[29]),
        .I3(phase_H1_trunc_AM_on_reg_1597[29]),
        .O(\storemerge_reg_1641[0]_i_29_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_30 
       (.I0(r_V_reg_1610[26]),
        .I1(phase_H1_trunc_AM_on_reg_1597[26]),
        .I2(r_V_reg_1610[27]),
        .I3(phase_H1_trunc_AM_on_reg_1597[27]),
        .O(\storemerge_reg_1641[0]_i_30_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_31 
       (.I0(r_V_reg_1610[24]),
        .I1(phase_H1_trunc_AM_on_reg_1597[24]),
        .I2(r_V_reg_1610[25]),
        .I3(phase_H1_trunc_AM_on_reg_1597[25]),
        .O(\storemerge_reg_1641[0]_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_33 
       (.I0(r_V_reg_1610[22]),
        .I1(phase_H1_trunc_AM_on_reg_1597[22]),
        .I2(phase_H1_trunc_AM_on_reg_1597[23]),
        .I3(r_V_reg_1610[23]),
        .O(\storemerge_reg_1641[0]_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_34 
       (.I0(r_V_reg_1610[20]),
        .I1(phase_H1_trunc_AM_on_reg_1597[20]),
        .I2(phase_H1_trunc_AM_on_reg_1597[21]),
        .I3(r_V_reg_1610[21]),
        .O(\storemerge_reg_1641[0]_i_34_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_35 
       (.I0(r_V_reg_1610[18]),
        .I1(phase_H1_trunc_AM_on_reg_1597[18]),
        .I2(phase_H1_trunc_AM_on_reg_1597[19]),
        .I3(r_V_reg_1610[19]),
        .O(\storemerge_reg_1641[0]_i_35_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_36 
       (.I0(r_V_reg_1610[16]),
        .I1(phase_H1_trunc_AM_on_reg_1597[16]),
        .I2(phase_H1_trunc_AM_on_reg_1597[17]),
        .I3(r_V_reg_1610[17]),
        .O(\storemerge_reg_1641[0]_i_36_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_37 
       (.I0(r_V_reg_1610[22]),
        .I1(phase_H1_trunc_AM_on_reg_1597[22]),
        .I2(r_V_reg_1610[23]),
        .I3(phase_H1_trunc_AM_on_reg_1597[23]),
        .O(\storemerge_reg_1641[0]_i_37_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_38 
       (.I0(r_V_reg_1610[20]),
        .I1(phase_H1_trunc_AM_on_reg_1597[20]),
        .I2(r_V_reg_1610[21]),
        .I3(phase_H1_trunc_AM_on_reg_1597[21]),
        .O(\storemerge_reg_1641[0]_i_38_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_39 
       (.I0(r_V_reg_1610[18]),
        .I1(phase_H1_trunc_AM_on_reg_1597[18]),
        .I2(r_V_reg_1610[19]),
        .I3(phase_H1_trunc_AM_on_reg_1597[19]),
        .O(\storemerge_reg_1641[0]_i_39_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \storemerge_reg_1641[0]_i_4 
       (.I0(r_V_reg_1610[48]),
        .O(\storemerge_reg_1641[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_40 
       (.I0(r_V_reg_1610[16]),
        .I1(phase_H1_trunc_AM_on_reg_1597[16]),
        .I2(r_V_reg_1610[17]),
        .I3(phase_H1_trunc_AM_on_reg_1597[17]),
        .O(\storemerge_reg_1641[0]_i_40_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_42 
       (.I0(r_V_reg_1610[14]),
        .I1(phase_H1_trunc_AM_on_reg_1597[14]),
        .I2(phase_H1_trunc_AM_on_reg_1597[15]),
        .I3(r_V_reg_1610[15]),
        .O(\storemerge_reg_1641[0]_i_42_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_43 
       (.I0(r_V_reg_1610[12]),
        .I1(phase_H1_trunc_AM_on_reg_1597[12]),
        .I2(phase_H1_trunc_AM_on_reg_1597[13]),
        .I3(r_V_reg_1610[13]),
        .O(\storemerge_reg_1641[0]_i_43_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_44 
       (.I0(r_V_reg_1610[10]),
        .I1(phase_H1_trunc_AM_on_reg_1597[10]),
        .I2(phase_H1_trunc_AM_on_reg_1597[11]),
        .I3(r_V_reg_1610[11]),
        .O(\storemerge_reg_1641[0]_i_44_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_45 
       (.I0(r_V_reg_1610[8]),
        .I1(phase_H1_trunc_AM_on_reg_1597[8]),
        .I2(phase_H1_trunc_AM_on_reg_1597[9]),
        .I3(r_V_reg_1610[9]),
        .O(\storemerge_reg_1641[0]_i_45_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_46 
       (.I0(r_V_reg_1610[14]),
        .I1(phase_H1_trunc_AM_on_reg_1597[14]),
        .I2(r_V_reg_1610[15]),
        .I3(phase_H1_trunc_AM_on_reg_1597[15]),
        .O(\storemerge_reg_1641[0]_i_46_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_47 
       (.I0(r_V_reg_1610[12]),
        .I1(phase_H1_trunc_AM_on_reg_1597[12]),
        .I2(r_V_reg_1610[13]),
        .I3(phase_H1_trunc_AM_on_reg_1597[13]),
        .O(\storemerge_reg_1641[0]_i_47_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_48 
       (.I0(r_V_reg_1610[10]),
        .I1(phase_H1_trunc_AM_on_reg_1597[10]),
        .I2(r_V_reg_1610[11]),
        .I3(phase_H1_trunc_AM_on_reg_1597[11]),
        .O(\storemerge_reg_1641[0]_i_48_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_49 
       (.I0(r_V_reg_1610[8]),
        .I1(phase_H1_trunc_AM_on_reg_1597[8]),
        .I2(r_V_reg_1610[9]),
        .I3(phase_H1_trunc_AM_on_reg_1597[9]),
        .O(\storemerge_reg_1641[0]_i_49_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_50 
       (.I0(r_V_reg_1610[6]),
        .I1(phase_H1_trunc_AM_on_reg_1597[6]),
        .I2(phase_H1_trunc_AM_on_reg_1597[7]),
        .I3(r_V_reg_1610[7]),
        .O(\storemerge_reg_1641[0]_i_50_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_51 
       (.I0(r_V_reg_1610[4]),
        .I1(phase_H1_trunc_AM_on_reg_1597[4]),
        .I2(phase_H1_trunc_AM_on_reg_1597[5]),
        .I3(r_V_reg_1610[5]),
        .O(\storemerge_reg_1641[0]_i_51_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_52 
       (.I0(r_V_reg_1610[2]),
        .I1(phase_H1_trunc_AM_on_reg_1597[2]),
        .I2(phase_H1_trunc_AM_on_reg_1597[3]),
        .I3(r_V_reg_1610[3]),
        .O(\storemerge_reg_1641[0]_i_52_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_53 
       (.I0(r_V_reg_1610[0]),
        .I1(phase_H1_trunc_AM_on_reg_1597[0]),
        .I2(phase_H1_trunc_AM_on_reg_1597[1]),
        .I3(r_V_reg_1610[1]),
        .O(\storemerge_reg_1641[0]_i_53_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_54 
       (.I0(r_V_reg_1610[6]),
        .I1(phase_H1_trunc_AM_on_reg_1597[6]),
        .I2(r_V_reg_1610[7]),
        .I3(phase_H1_trunc_AM_on_reg_1597[7]),
        .O(\storemerge_reg_1641[0]_i_54_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_55 
       (.I0(r_V_reg_1610[4]),
        .I1(phase_H1_trunc_AM_on_reg_1597[4]),
        .I2(r_V_reg_1610[5]),
        .I3(phase_H1_trunc_AM_on_reg_1597[5]),
        .O(\storemerge_reg_1641[0]_i_55_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_56 
       (.I0(r_V_reg_1610[2]),
        .I1(phase_H1_trunc_AM_on_reg_1597[2]),
        .I2(r_V_reg_1610[3]),
        .I3(phase_H1_trunc_AM_on_reg_1597[3]),
        .O(\storemerge_reg_1641[0]_i_56_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \storemerge_reg_1641[0]_i_57 
       (.I0(r_V_reg_1610[0]),
        .I1(phase_H1_trunc_AM_on_reg_1597[0]),
        .I2(r_V_reg_1610[1]),
        .I3(phase_H1_trunc_AM_on_reg_1597[1]),
        .O(\storemerge_reg_1641[0]_i_57_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_6 
       (.I0(r_V_reg_1610[46]),
        .I1(phase_H1_trunc_AM_on_reg_1597[46]),
        .I2(phase_H1_trunc_AM_on_reg_1597[47]),
        .I3(r_V_reg_1610[47]),
        .O(\storemerge_reg_1641[0]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_7 
       (.I0(r_V_reg_1610[44]),
        .I1(phase_H1_trunc_AM_on_reg_1597[44]),
        .I2(phase_H1_trunc_AM_on_reg_1597[45]),
        .I3(r_V_reg_1610[45]),
        .O(\storemerge_reg_1641[0]_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_8 
       (.I0(r_V_reg_1610[42]),
        .I1(phase_H1_trunc_AM_on_reg_1597[42]),
        .I2(phase_H1_trunc_AM_on_reg_1597[43]),
        .I3(r_V_reg_1610[43]),
        .O(\storemerge_reg_1641[0]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    \storemerge_reg_1641[0]_i_9 
       (.I0(r_V_reg_1610[40]),
        .I1(phase_H1_trunc_AM_on_reg_1597[40]),
        .I2(phase_H1_trunc_AM_on_reg_1597[41]),
        .I3(r_V_reg_1610[41]),
        .O(\storemerge_reg_1641[0]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \storemerge_reg_1641_pp0_iter5_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(storemerge_reg_1641),
        .Q(storemerge_reg_1641_pp0_iter5_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \storemerge_reg_1641_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(storemerge_reg_1641_pp0_iter5_reg),
        .Q(storemerge_reg_1641_pp0_iter6_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \storemerge_reg_1641_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(storemerge_fu_1180_p2),
        .Q(storemerge_reg_1641),
        .R(ap_rst));
  CARRY4 \storemerge_reg_1641_reg[0]_i_14 
       (.CI(\storemerge_reg_1641_reg[0]_i_23_n_0 ),
        .CO({\storemerge_reg_1641_reg[0]_i_14_n_0 ,\storemerge_reg_1641_reg[0]_i_14_n_1 ,\storemerge_reg_1641_reg[0]_i_14_n_2 ,\storemerge_reg_1641_reg[0]_i_14_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\storemerge_reg_1641[0]_i_24_n_0 ,\storemerge_reg_1641[0]_i_25_n_0 ,\storemerge_reg_1641[0]_i_26_n_0 ,\storemerge_reg_1641[0]_i_27_n_0 }),
        .S({\storemerge_reg_1641[0]_i_28_n_0 ,\storemerge_reg_1641[0]_i_29_n_0 ,\storemerge_reg_1641[0]_i_30_n_0 ,\storemerge_reg_1641[0]_i_31_n_0 }));
  CARRY4 \storemerge_reg_1641_reg[0]_i_2 
       (.CI(\storemerge_reg_1641_reg[0]_i_3_n_0 ),
        .CO(tmp_18_fu_1170_p2),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .S({\<const0> ,\<const0> ,\<const0> ,\storemerge_reg_1641[0]_i_4_n_0 }));
  CARRY4 \storemerge_reg_1641_reg[0]_i_23 
       (.CI(\storemerge_reg_1641_reg[0]_i_32_n_0 ),
        .CO({\storemerge_reg_1641_reg[0]_i_23_n_0 ,\storemerge_reg_1641_reg[0]_i_23_n_1 ,\storemerge_reg_1641_reg[0]_i_23_n_2 ,\storemerge_reg_1641_reg[0]_i_23_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\storemerge_reg_1641[0]_i_33_n_0 ,\storemerge_reg_1641[0]_i_34_n_0 ,\storemerge_reg_1641[0]_i_35_n_0 ,\storemerge_reg_1641[0]_i_36_n_0 }),
        .S({\storemerge_reg_1641[0]_i_37_n_0 ,\storemerge_reg_1641[0]_i_38_n_0 ,\storemerge_reg_1641[0]_i_39_n_0 ,\storemerge_reg_1641[0]_i_40_n_0 }));
  CARRY4 \storemerge_reg_1641_reg[0]_i_3 
       (.CI(\storemerge_reg_1641_reg[0]_i_5_n_0 ),
        .CO({\storemerge_reg_1641_reg[0]_i_3_n_0 ,\storemerge_reg_1641_reg[0]_i_3_n_1 ,\storemerge_reg_1641_reg[0]_i_3_n_2 ,\storemerge_reg_1641_reg[0]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\storemerge_reg_1641[0]_i_6_n_0 ,\storemerge_reg_1641[0]_i_7_n_0 ,\storemerge_reg_1641[0]_i_8_n_0 ,\storemerge_reg_1641[0]_i_9_n_0 }),
        .S({\storemerge_reg_1641[0]_i_10_n_0 ,\storemerge_reg_1641[0]_i_11_n_0 ,\storemerge_reg_1641[0]_i_12_n_0 ,\storemerge_reg_1641[0]_i_13_n_0 }));
  CARRY4 \storemerge_reg_1641_reg[0]_i_32 
       (.CI(\storemerge_reg_1641_reg[0]_i_41_n_0 ),
        .CO({\storemerge_reg_1641_reg[0]_i_32_n_0 ,\storemerge_reg_1641_reg[0]_i_32_n_1 ,\storemerge_reg_1641_reg[0]_i_32_n_2 ,\storemerge_reg_1641_reg[0]_i_32_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\storemerge_reg_1641[0]_i_42_n_0 ,\storemerge_reg_1641[0]_i_43_n_0 ,\storemerge_reg_1641[0]_i_44_n_0 ,\storemerge_reg_1641[0]_i_45_n_0 }),
        .S({\storemerge_reg_1641[0]_i_46_n_0 ,\storemerge_reg_1641[0]_i_47_n_0 ,\storemerge_reg_1641[0]_i_48_n_0 ,\storemerge_reg_1641[0]_i_49_n_0 }));
  CARRY4 \storemerge_reg_1641_reg[0]_i_41 
       (.CI(\<const0> ),
        .CO({\storemerge_reg_1641_reg[0]_i_41_n_0 ,\storemerge_reg_1641_reg[0]_i_41_n_1 ,\storemerge_reg_1641_reg[0]_i_41_n_2 ,\storemerge_reg_1641_reg[0]_i_41_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\storemerge_reg_1641[0]_i_50_n_0 ,\storemerge_reg_1641[0]_i_51_n_0 ,\storemerge_reg_1641[0]_i_52_n_0 ,\storemerge_reg_1641[0]_i_53_n_0 }),
        .S({\storemerge_reg_1641[0]_i_54_n_0 ,\storemerge_reg_1641[0]_i_55_n_0 ,\storemerge_reg_1641[0]_i_56_n_0 ,\storemerge_reg_1641[0]_i_57_n_0 }));
  CARRY4 \storemerge_reg_1641_reg[0]_i_5 
       (.CI(\storemerge_reg_1641_reg[0]_i_14_n_0 ),
        .CO({\storemerge_reg_1641_reg[0]_i_5_n_0 ,\storemerge_reg_1641_reg[0]_i_5_n_1 ,\storemerge_reg_1641_reg[0]_i_5_n_2 ,\storemerge_reg_1641_reg[0]_i_5_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\storemerge_reg_1641[0]_i_15_n_0 ,\storemerge_reg_1641[0]_i_16_n_0 ,\storemerge_reg_1641[0]_i_17_n_0 ,\storemerge_reg_1641[0]_i_18_n_0 }),
        .S({\storemerge_reg_1641[0]_i_19_n_0 ,\storemerge_reg_1641[0]_i_20_n_0 ,\storemerge_reg_1641[0]_i_21_n_0 ,\storemerge_reg_1641[0]_i_22_n_0 }));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'hFB08)) 
    \tmp_12_reg_1606[0]_i_1 
       (.I0(tmp_12_fu_1030_p2),
        .I1(p_Val2_4_reg_1510),
        .I2(tmp_3_fu_1010_p2),
        .I3(tmp_12_reg_1606),
        .O(\tmp_12_reg_1606[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF8883888488888F8)) 
    \tmp_12_reg_1606[0]_i_10 
       (.I0(p_5_in__0[43]),
        .I1(p_5_in__0[42]),
        .I2(or_cond_reg_1520),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I5(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(\tmp_12_reg_1606[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAA20000000C)) 
    \tmp_12_reg_1606[0]_i_11 
       (.I0(p_5_in__0[41]),
        .I1(or_cond_reg_1520),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I5(p_5_in[40]),
        .O(\tmp_12_reg_1606[0]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_13 
       (.I0(p_5_in[38]),
        .I1(p_5_in[39]),
        .O(\tmp_12_reg_1606[0]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_14 
       (.I0(p_5_in[36]),
        .I1(p_5_in[37]),
        .O(\tmp_12_reg_1606[0]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_15 
       (.I0(p_5_in[34]),
        .I1(p_5_in[35]),
        .O(\tmp_12_reg_1606[0]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_16 
       (.I0(p_5_in[32]),
        .I1(p_5_in[33]),
        .O(\tmp_12_reg_1606[0]_i_16_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_17 
       (.I0(p_5_in[39]),
        .I1(p_5_in[38]),
        .O(\tmp_12_reg_1606[0]_i_17_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_18 
       (.I0(p_5_in[37]),
        .I1(p_5_in[36]),
        .O(\tmp_12_reg_1606[0]_i_18_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_19 
       (.I0(p_5_in[35]),
        .I1(p_5_in[34]),
        .O(\tmp_12_reg_1606[0]_i_19_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_20 
       (.I0(p_5_in[33]),
        .I1(p_5_in[32]),
        .O(\tmp_12_reg_1606[0]_i_20_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_22 
       (.I0(p_5_in[30]),
        .I1(p_5_in[31]),
        .O(\tmp_12_reg_1606[0]_i_22_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_23 
       (.I0(p_5_in[28]),
        .I1(p_5_in[29]),
        .O(\tmp_12_reg_1606[0]_i_23_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_24 
       (.I0(p_5_in[26]),
        .I1(p_5_in[27]),
        .O(\tmp_12_reg_1606[0]_i_24_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_25 
       (.I0(p_5_in[24]),
        .I1(p_5_in[25]),
        .O(\tmp_12_reg_1606[0]_i_25_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_26 
       (.I0(p_5_in[31]),
        .I1(p_5_in[30]),
        .O(\tmp_12_reg_1606[0]_i_26_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_27 
       (.I0(p_5_in[29]),
        .I1(p_5_in[28]),
        .O(\tmp_12_reg_1606[0]_i_27_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_28 
       (.I0(p_5_in[27]),
        .I1(p_5_in[26]),
        .O(\tmp_12_reg_1606[0]_i_28_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_29 
       (.I0(p_5_in[25]),
        .I1(p_5_in[24]),
        .O(\tmp_12_reg_1606[0]_i_29_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_31 
       (.I0(p_5_in[22]),
        .I1(p_5_in[23]),
        .O(\tmp_12_reg_1606[0]_i_31_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_32 
       (.I0(p_5_in[20]),
        .I1(p_5_in[21]),
        .O(\tmp_12_reg_1606[0]_i_32_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_33 
       (.I0(p_5_in[18]),
        .I1(p_5_in[19]),
        .O(\tmp_12_reg_1606[0]_i_33_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_34 
       (.I0(p_5_in[16]),
        .I1(p_5_in[17]),
        .O(\tmp_12_reg_1606[0]_i_34_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_35 
       (.I0(p_5_in[23]),
        .I1(p_5_in[22]),
        .O(\tmp_12_reg_1606[0]_i_35_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_36 
       (.I0(p_5_in[21]),
        .I1(p_5_in[20]),
        .O(\tmp_12_reg_1606[0]_i_36_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_37 
       (.I0(p_5_in[19]),
        .I1(p_5_in[18]),
        .O(\tmp_12_reg_1606[0]_i_37_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_38 
       (.I0(p_5_in[17]),
        .I1(p_5_in[16]),
        .O(\tmp_12_reg_1606[0]_i_38_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000005575)) 
    \tmp_12_reg_1606[0]_i_4 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(p_5_in__0[47]),
        .I5(p_5_in__0[46]),
        .O(\tmp_12_reg_1606[0]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_40 
       (.I0(p_5_in[14]),
        .I1(p_5_in[15]),
        .O(\tmp_12_reg_1606[0]_i_40_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_41 
       (.I0(p_5_in[12]),
        .I1(p_5_in[13]),
        .O(\tmp_12_reg_1606[0]_i_41_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_42 
       (.I0(p_5_in[10]),
        .I1(p_5_in[11]),
        .O(\tmp_12_reg_1606[0]_i_42_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_43 
       (.I0(p_5_in[8]),
        .I1(p_5_in[9]),
        .O(\tmp_12_reg_1606[0]_i_43_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_44 
       (.I0(p_5_in[15]),
        .I1(p_5_in[14]),
        .O(\tmp_12_reg_1606[0]_i_44_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_45 
       (.I0(p_5_in[13]),
        .I1(p_5_in[12]),
        .O(\tmp_12_reg_1606[0]_i_45_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_46 
       (.I0(p_5_in[11]),
        .I1(p_5_in[10]),
        .O(\tmp_12_reg_1606[0]_i_46_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_47 
       (.I0(p_5_in[9]),
        .I1(p_5_in[8]),
        .O(\tmp_12_reg_1606[0]_i_47_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_48 
       (.I0(p_5_in[6]),
        .I1(p_5_in[7]),
        .O(\tmp_12_reg_1606[0]_i_48_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_49 
       (.I0(p_5_in[4]),
        .I1(p_5_in[5]),
        .O(\tmp_12_reg_1606[0]_i_49_n_0 ));
  LUT6 #(
    .INIT(64'h0000557D557D55FD)) 
    \tmp_12_reg_1606[0]_i_5 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(p_5_in__0[45]),
        .I5(p_5_in__0[44]),
        .O(\tmp_12_reg_1606[0]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_50 
       (.I0(p_5_in[2]),
        .I1(p_5_in[3]),
        .O(\tmp_12_reg_1606[0]_i_50_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \tmp_12_reg_1606[0]_i_51 
       (.I0(p_5_in[0]),
        .I1(p_5_in[1]),
        .O(\tmp_12_reg_1606[0]_i_51_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_52 
       (.I0(p_5_in[7]),
        .I1(p_5_in[6]),
        .O(\tmp_12_reg_1606[0]_i_52_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_53 
       (.I0(p_5_in[5]),
        .I1(p_5_in[4]),
        .O(\tmp_12_reg_1606[0]_i_53_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_54 
       (.I0(p_5_in[3]),
        .I1(p_5_in[2]),
        .O(\tmp_12_reg_1606[0]_i_54_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_12_reg_1606[0]_i_55 
       (.I0(p_5_in[1]),
        .I1(p_5_in[0]),
        .O(\tmp_12_reg_1606[0]_i_55_n_0 ));
  LUT6 #(
    .INIT(64'h0154555513FCFFFF)) 
    \tmp_12_reg_1606[0]_i_6 
       (.I0(p_5_in__0[43]),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I4(or_cond_reg_1520),
        .I5(p_5_in__0[42]),
        .O(\tmp_12_reg_1606[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00007FFD7FFDFFFD)) 
    \tmp_12_reg_1606[0]_i_7 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(p_5_in__0[41]),
        .I5(p_5_in[40]),
        .O(\tmp_12_reg_1606[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFF34F44444444)) 
    \tmp_12_reg_1606[0]_i_8 
       (.I0(p_5_in__0[47]),
        .I1(p_5_in__0[46]),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I5(or_cond_reg_1520),
        .O(\tmp_12_reg_1606[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hE6EAEA2EC0C0C0CC)) 
    \tmp_12_reg_1606[0]_i_9 
       (.I0(p_5_in__0[45]),
        .I1(or_cond_reg_1520),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I4(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I5(p_5_in__0[44]),
        .O(\tmp_12_reg_1606[0]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_12_reg_1606_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_12_reg_1606),
        .Q(tmp_12_reg_1606_pp0_iter4_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_12_reg_1606_reg[0] 
       (.C(ap_clk),
        .CE(\<const1> ),
        .D(\tmp_12_reg_1606[0]_i_1_n_0 ),
        .Q(tmp_12_reg_1606),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_12_reg_1606_reg[0]_i_12 
       (.CI(\tmp_12_reg_1606_reg[0]_i_21_n_0 ),
        .CO({\tmp_12_reg_1606_reg[0]_i_12_n_0 ,\tmp_12_reg_1606_reg[0]_i_12_n_1 ,\tmp_12_reg_1606_reg[0]_i_12_n_2 ,\tmp_12_reg_1606_reg[0]_i_12_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_12_reg_1606[0]_i_22_n_0 ,\tmp_12_reg_1606[0]_i_23_n_0 ,\tmp_12_reg_1606[0]_i_24_n_0 ,\tmp_12_reg_1606[0]_i_25_n_0 }),
        .S({\tmp_12_reg_1606[0]_i_26_n_0 ,\tmp_12_reg_1606[0]_i_27_n_0 ,\tmp_12_reg_1606[0]_i_28_n_0 ,\tmp_12_reg_1606[0]_i_29_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_12_reg_1606_reg[0]_i_2 
       (.CI(\tmp_12_reg_1606_reg[0]_i_3_n_0 ),
        .CO({tmp_12_fu_1030_p2,\tmp_12_reg_1606_reg[0]_i_2_n_1 ,\tmp_12_reg_1606_reg[0]_i_2_n_2 ,\tmp_12_reg_1606_reg[0]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_12_reg_1606[0]_i_4_n_0 ,\tmp_12_reg_1606[0]_i_5_n_0 ,\tmp_12_reg_1606[0]_i_6_n_0 ,\tmp_12_reg_1606[0]_i_7_n_0 }),
        .S({\tmp_12_reg_1606[0]_i_8_n_0 ,\tmp_12_reg_1606[0]_i_9_n_0 ,\tmp_12_reg_1606[0]_i_10_n_0 ,\tmp_12_reg_1606[0]_i_11_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_12_reg_1606_reg[0]_i_21 
       (.CI(\tmp_12_reg_1606_reg[0]_i_30_n_0 ),
        .CO({\tmp_12_reg_1606_reg[0]_i_21_n_0 ,\tmp_12_reg_1606_reg[0]_i_21_n_1 ,\tmp_12_reg_1606_reg[0]_i_21_n_2 ,\tmp_12_reg_1606_reg[0]_i_21_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_12_reg_1606[0]_i_31_n_0 ,\tmp_12_reg_1606[0]_i_32_n_0 ,\tmp_12_reg_1606[0]_i_33_n_0 ,\tmp_12_reg_1606[0]_i_34_n_0 }),
        .S({\tmp_12_reg_1606[0]_i_35_n_0 ,\tmp_12_reg_1606[0]_i_36_n_0 ,\tmp_12_reg_1606[0]_i_37_n_0 ,\tmp_12_reg_1606[0]_i_38_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_12_reg_1606_reg[0]_i_3 
       (.CI(\tmp_12_reg_1606_reg[0]_i_12_n_0 ),
        .CO({\tmp_12_reg_1606_reg[0]_i_3_n_0 ,\tmp_12_reg_1606_reg[0]_i_3_n_1 ,\tmp_12_reg_1606_reg[0]_i_3_n_2 ,\tmp_12_reg_1606_reg[0]_i_3_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_12_reg_1606[0]_i_13_n_0 ,\tmp_12_reg_1606[0]_i_14_n_0 ,\tmp_12_reg_1606[0]_i_15_n_0 ,\tmp_12_reg_1606[0]_i_16_n_0 }),
        .S({\tmp_12_reg_1606[0]_i_17_n_0 ,\tmp_12_reg_1606[0]_i_18_n_0 ,\tmp_12_reg_1606[0]_i_19_n_0 ,\tmp_12_reg_1606[0]_i_20_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_12_reg_1606_reg[0]_i_30 
       (.CI(\tmp_12_reg_1606_reg[0]_i_39_n_0 ),
        .CO({\tmp_12_reg_1606_reg[0]_i_30_n_0 ,\tmp_12_reg_1606_reg[0]_i_30_n_1 ,\tmp_12_reg_1606_reg[0]_i_30_n_2 ,\tmp_12_reg_1606_reg[0]_i_30_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_12_reg_1606[0]_i_40_n_0 ,\tmp_12_reg_1606[0]_i_41_n_0 ,\tmp_12_reg_1606[0]_i_42_n_0 ,\tmp_12_reg_1606[0]_i_43_n_0 }),
        .S({\tmp_12_reg_1606[0]_i_44_n_0 ,\tmp_12_reg_1606[0]_i_45_n_0 ,\tmp_12_reg_1606[0]_i_46_n_0 ,\tmp_12_reg_1606[0]_i_47_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_12_reg_1606_reg[0]_i_39 
       (.CI(\<const0> ),
        .CO({\tmp_12_reg_1606_reg[0]_i_39_n_0 ,\tmp_12_reg_1606_reg[0]_i_39_n_1 ,\tmp_12_reg_1606_reg[0]_i_39_n_2 ,\tmp_12_reg_1606_reg[0]_i_39_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_12_reg_1606[0]_i_48_n_0 ,\tmp_12_reg_1606[0]_i_49_n_0 ,\tmp_12_reg_1606[0]_i_50_n_0 ,\tmp_12_reg_1606[0]_i_51_n_0 }),
        .S({\tmp_12_reg_1606[0]_i_52_n_0 ,\tmp_12_reg_1606[0]_i_53_n_0 ,\tmp_12_reg_1606[0]_i_54_n_0 ,\tmp_12_reg_1606[0]_i_55_n_0 }));
  (* srl_bus_name = "U0/\tmp_19_reg_1621_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(tmp_19_fu_1068_p2),
        .Q(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .CO({tmp_19_fu_1068_p2,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 }),
        .S({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10_n_0 }));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10 
       (.I0(p_Val2_15_fu_962_p2[41]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I2(p_Val2_15_fu_962_p2[40]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11 
       (.CI(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_0 ),
        .CO({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_1 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_2 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24_n_0 }),
        .S({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I1(p_Val2_15_fu_962_p2[39]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .I3(p_Val2_15_fu_962_p2[38]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I1(p_Val2_15_fu_962_p2[37]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .I3(p_Val2_15_fu_962_p2[36]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I1(p_Val2_15_fu_962_p2[35]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .I3(p_Val2_15_fu_962_p2[34]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I1(p_Val2_15_fu_962_p2[33]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .I3(p_Val2_15_fu_962_p2[32]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16 
       (.I0(p_Val2_15_fu_962_p2[39]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I2(p_Val2_15_fu_962_p2[38]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17 
       (.I0(p_Val2_15_fu_962_p2[37]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I2(p_Val2_15_fu_962_p2[36]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18 
       (.I0(p_Val2_15_fu_962_p2[35]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I2(p_Val2_15_fu_962_p2[34]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19 
       (.I0(p_Val2_15_fu_962_p2[33]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I2(p_Val2_15_fu_962_p2[32]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.CI(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_0 ),
        .CO({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_1 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_2 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15_n_0 }),
        .S({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20 
       (.CI(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_0 ),
        .CO({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_1 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_2 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33_n_0 }),
        .S({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I1(p_Val2_15_fu_962_p2[31]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .I3(p_Val2_15_fu_962_p2[30]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I1(p_Val2_15_fu_962_p2[29]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .I3(p_Val2_15_fu_962_p2[28]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I1(p_Val2_15_fu_962_p2[27]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .I3(p_Val2_15_fu_962_p2[26]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I1(p_Val2_15_fu_962_p2[25]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .I3(p_Val2_15_fu_962_p2[24]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25 
       (.I0(p_Val2_15_fu_962_p2[31]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I2(p_Val2_15_fu_962_p2[30]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26 
       (.I0(p_Val2_15_fu_962_p2[29]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I2(p_Val2_15_fu_962_p2[28]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27 
       (.I0(p_Val2_15_fu_962_p2[27]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I2(p_Val2_15_fu_962_p2[26]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28 
       (.I0(p_Val2_15_fu_962_p2[25]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I2(p_Val2_15_fu_962_p2[24]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29 
       (.CI(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_0 ),
        .CO({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_1 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_2 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42_n_0 }),
        .S({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I1(p_Val2_15_fu_962_p2[47]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .I3(p_Val2_15_fu_962_p2[46]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I1(p_Val2_15_fu_962_p2[23]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .I3(p_Val2_15_fu_962_p2[22]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I1(p_Val2_15_fu_962_p2[21]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .I3(p_Val2_15_fu_962_p2[20]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I1(p_Val2_15_fu_962_p2[19]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .I3(p_Val2_15_fu_962_p2[18]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I1(p_Val2_15_fu_962_p2[17]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .I3(p_Val2_15_fu_962_p2[16]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34 
       (.I0(p_Val2_15_fu_962_p2[23]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I2(p_Val2_15_fu_962_p2[22]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35 
       (.I0(p_Val2_15_fu_962_p2[21]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I2(p_Val2_15_fu_962_p2[20]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36 
       (.I0(p_Val2_15_fu_962_p2[19]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I2(p_Val2_15_fu_962_p2[18]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37 
       (.I0(p_Val2_15_fu_962_p2[17]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I2(p_Val2_15_fu_962_p2[16]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38 
       (.CI(\<const0> ),
        .CO({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_1 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_2 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50_n_0 }),
        .S({\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53_n_0 ,\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I1(p_Val2_15_fu_962_p2[15]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .I3(p_Val2_15_fu_962_p2[14]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I1(p_Val2_15_fu_962_p2[45]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .I3(p_Val2_15_fu_962_p2[44]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I1(p_Val2_15_fu_962_p2[13]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .I3(p_Val2_15_fu_962_p2[12]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I1(p_Val2_15_fu_962_p2[11]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .I3(p_Val2_15_fu_962_p2[10]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I1(p_Val2_15_fu_962_p2[9]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .I3(p_Val2_15_fu_962_p2[8]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43 
       (.I0(p_Val2_15_fu_962_p2[15]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I2(p_Val2_15_fu_962_p2[14]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44 
       (.I0(p_Val2_15_fu_962_p2[13]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I2(p_Val2_15_fu_962_p2[12]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45 
       (.I0(p_Val2_15_fu_962_p2[11]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I2(p_Val2_15_fu_962_p2[10]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46 
       (.I0(p_Val2_15_fu_962_p2[9]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I2(p_Val2_15_fu_962_p2[8]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I1(p_Val2_15_fu_962_p2[7]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .I3(p_Val2_15_fu_962_p2[6]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I1(p_Val2_15_fu_962_p2[5]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .I3(p_Val2_15_fu_962_p2[4]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I1(p_Val2_15_fu_962_p2[3]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .I3(p_Val2_15_fu_962_p2[2]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I1(p_Val2_15_fu_962_p2[43]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .I3(p_Val2_15_fu_962_p2[42]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I1(p_Val2_15_fu_962_p2[1]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .I3(p_Val2_15_fu_962_p2[0]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51 
       (.I0(p_Val2_15_fu_962_p2[7]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I2(p_Val2_15_fu_962_p2[6]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52 
       (.I0(p_Val2_15_fu_962_p2[5]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I2(p_Val2_15_fu_962_p2[4]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53 
       (.I0(p_Val2_15_fu_962_p2[3]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I2(p_Val2_15_fu_962_p2[2]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54 
       (.I0(p_Val2_15_fu_962_p2[1]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I2(p_Val2_15_fu_962_p2[0]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I1(p_Val2_15_fu_962_p2[41]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .I3(p_Val2_15_fu_962_p2[40]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7 
       (.I0(p_Val2_15_fu_962_p2[47]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I2(p_Val2_15_fu_962_p2[46]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8 
       (.I0(p_Val2_15_fu_962_p2[45]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I2(p_Val2_15_fu_962_p2[44]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9 
       (.I0(p_Val2_15_fu_962_p2[43]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I2(p_Val2_15_fu_962_p2[42]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .O(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_19_reg_1621_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\tmp_19_reg_1621_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\tmp_19_reg_1621_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT2 #(
    .INIT(4'h8)) 
    tmp_19_reg_1621_pp0_iter5_reg_reg_gate
       (.I0(\tmp_19_reg_1621_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(tmp_19_reg_1621_pp0_iter5_reg_reg_gate_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_19_reg_1621_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_19_reg_1621_pp0_iter5_reg_reg_gate_n_0),
        .Q(tmp_19_reg_1621_pp0_iter6_reg),
        .R(ap_rst));
  (* srl_bus_name = "U0/\tmp_20_reg_1626_pp0_iter4_reg_reg " *) 
  (* srl_name = "U0/\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r " *) 
  SRL16E #(
    .INIT(16'h0000)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r 
       (.A0(\<const1> ),
        .A1(\<const0> ),
        .A2(\<const0> ),
        .A3(\<const0> ),
        .CE(p_Val2_4_reg_1510),
        .CLK(ap_clk),
        .D(tmp_20_fu_1074_p2),
        .Q(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1 
       (.CI(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ),
        .CO({tmp_20_fu_1074_p2,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_1 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_2 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 }),
        .S({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10_n_0 }));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10 
       (.I0(acc_H1_V_reg[41]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I2(acc_H1_V_reg[40]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_10_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11 
       (.CI(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_0 ),
        .CO({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_1 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_2 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24_n_0 }),
        .S({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I1(acc_H1_V_reg[39]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .I3(acc_H1_V_reg[38]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I1(acc_H1_V_reg[37]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .I3(acc_H1_V_reg[36]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I1(acc_H1_V_reg[35]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .I3(acc_H1_V_reg[34]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I1(acc_H1_V_reg[33]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .I3(acc_H1_V_reg[32]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16 
       (.I0(acc_H1_V_reg[39]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I2(acc_H1_V_reg[38]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17 
       (.I0(acc_H1_V_reg[37]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I2(acc_H1_V_reg[36]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18 
       (.I0(acc_H1_V_reg[35]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I2(acc_H1_V_reg[34]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19 
       (.I0(acc_H1_V_reg[33]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I2(acc_H1_V_reg[32]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2 
       (.CI(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_11_n_0 ),
        .CO({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_1 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_2 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_12_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_13_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_14_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_15_n_0 }),
        .S({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_16_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_17_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_18_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_19_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20 
       (.CI(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_0 ),
        .CO({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_1 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_2 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_20_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33_n_0 }),
        .S({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I1(acc_H1_V_reg[31]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .I3(acc_H1_V_reg[30]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_21_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I1(acc_H1_V_reg[29]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .I3(acc_H1_V_reg[28]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_22_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I1(acc_H1_V_reg[27]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .I3(acc_H1_V_reg[26]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_23_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I1(acc_H1_V_reg[25]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .I3(acc_H1_V_reg[24]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_24_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25 
       (.I0(acc_H1_V_reg[31]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I2(acc_H1_V_reg[30]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_25_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26 
       (.I0(acc_H1_V_reg[29]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I2(acc_H1_V_reg[28]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_26_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27 
       (.I0(acc_H1_V_reg[27]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I2(acc_H1_V_reg[26]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_27_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28 
       (.I0(acc_H1_V_reg[25]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I2(acc_H1_V_reg[24]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_28_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29 
       (.CI(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_0 ),
        .CO({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_1 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_2 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_29_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42_n_0 }),
        .S({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46_n_0 }));
  LUT4 #(
    .INIT(16'h40F4)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3 
       (.I0(acc_H1_V_reg[46]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I3(acc_H1_V_reg[47]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I1(acc_H1_V_reg[23]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .I3(acc_H1_V_reg[22]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_30_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I1(acc_H1_V_reg[21]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .I3(acc_H1_V_reg[20]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I1(acc_H1_V_reg[19]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .I3(acc_H1_V_reg[18]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_32_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I1(acc_H1_V_reg[17]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .I3(acc_H1_V_reg[16]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34 
       (.I0(acc_H1_V_reg[23]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I2(acc_H1_V_reg[22]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_34_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35 
       (.I0(acc_H1_V_reg[21]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I2(acc_H1_V_reg[20]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_35_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36 
       (.I0(acc_H1_V_reg[19]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I2(acc_H1_V_reg[18]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_36_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37 
       (.I0(acc_H1_V_reg[17]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I2(acc_H1_V_reg[16]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_37_n_0 ));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38 
       (.CI(\<const0> ),
        .CO({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_1 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_2 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_38_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50_n_0 }),
        .S({\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53_n_0 ,\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54_n_0 }));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I1(acc_H1_V_reg[15]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .I3(acc_H1_V_reg[14]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_39_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I1(acc_H1_V_reg[45]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .I3(acc_H1_V_reg[44]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I1(acc_H1_V_reg[13]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .I3(acc_H1_V_reg[12]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_40_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I1(acc_H1_V_reg[11]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .I3(acc_H1_V_reg[10]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_41_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I1(acc_H1_V_reg[9]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .I3(acc_H1_V_reg[8]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_42_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43 
       (.I0(acc_H1_V_reg[15]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I2(acc_H1_V_reg[14]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_43_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44 
       (.I0(acc_H1_V_reg[13]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I2(acc_H1_V_reg[12]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_44_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45 
       (.I0(acc_H1_V_reg[11]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I2(acc_H1_V_reg[10]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_45_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46 
       (.I0(acc_H1_V_reg[9]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I2(acc_H1_V_reg[8]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_46_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I1(acc_H1_V_reg[7]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .I3(acc_H1_V_reg[6]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_47_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I1(acc_H1_V_reg[5]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .I3(acc_H1_V_reg[4]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_48_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I1(acc_H1_V_reg[3]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .I3(acc_H1_V_reg[2]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_49_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I1(acc_H1_V_reg[43]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .I3(acc_H1_V_reg[42]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I1(acc_H1_V_reg[1]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .I3(acc_H1_V_reg[0]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_50_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51 
       (.I0(acc_H1_V_reg[7]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I2(acc_H1_V_reg[6]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_51_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52 
       (.I0(acc_H1_V_reg[5]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I2(acc_H1_V_reg[4]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_52_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53 
       (.I0(acc_H1_V_reg[3]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I2(acc_H1_V_reg[2]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_53_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54 
       (.I0(acc_H1_V_reg[1]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I2(acc_H1_V_reg[0]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_54_n_0 ));
  LUT4 #(
    .INIT(16'h22B2)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I1(acc_H1_V_reg[41]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .I3(acc_H1_V_reg[40]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7 
       (.I0(acc_H1_V_reg[46]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .I2(acc_H1_V_reg[47]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_7_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8 
       (.I0(acc_H1_V_reg[45]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I2(acc_H1_V_reg[44]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9 
       (.I0(acc_H1_V_reg[43]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I2(acc_H1_V_reg[42]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .O(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_20_reg_1626_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(\tmp_20_reg_1626_pp0_iter4_reg_reg[0]_srl2___p_tmp_8_reg_1515_pp0_iter3_reg_reg_r_n_0 ),
        .Q(\tmp_20_reg_1626_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT2 #(
    .INIT(4'h8)) 
    tmp_20_reg_1626_pp0_iter5_reg_reg_gate
       (.I0(\tmp_20_reg_1626_pp0_iter5_reg_reg[0]_p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0 ),
        .I1(p_tmp_8_reg_1515_pp0_iter4_reg_reg_r_n_0),
        .O(tmp_20_reg_1626_pp0_iter5_reg_reg_gate_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_20_reg_1626_pp0_iter6_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_20_reg_1626_pp0_iter5_reg_reg_gate_n_0),
        .Q(tmp_20_reg_1626_pp0_iter6_reg),
        .R(ap_rst));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tmp_22_reg_1544[0]_i_1 
       (.I0(inputs_valid_read_reg_1420),
        .I1(inputs_reset_NCO_rea_reg_1398),
        .O(p_1_in49_out));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_22_reg_1544_pp0_iter3_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_22_reg_1544),
        .Q(tmp_22_reg_1544_pp0_iter3_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_22_reg_1544_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_22_reg_1544_pp0_iter3_reg),
        .Q(tmp_22_reg_1544_pp0_iter4_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_22_reg_1544_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(p_1_in49_out),
        .Q(tmp_22_reg_1544),
        .R(ap_rst));
  LUT5 #(
    .INIT(32'h2D00002D)) 
    \tmp_3_reg_1602[0]_i_10 
       (.I0(p_5_in__0[41]),
        .I1(\tmp_3_reg_1602[0]_i_26_n_0 ),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .I4(p_5_in[40]),
        .O(\tmp_3_reg_1602[0]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_12 
       (.I0(p_5_in[39]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .I3(p_5_in[38]),
        .O(\tmp_3_reg_1602[0]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_13 
       (.I0(p_5_in[37]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .I3(p_5_in[36]),
        .O(\tmp_3_reg_1602[0]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_14 
       (.I0(p_5_in[35]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .I3(p_5_in[34]),
        .O(\tmp_3_reg_1602[0]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_15 
       (.I0(p_5_in[33]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .I3(p_5_in[32]),
        .O(\tmp_3_reg_1602[0]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_16 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[39]),
        .I1(p_5_in[39]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[38]),
        .I3(p_5_in[38]),
        .O(\tmp_3_reg_1602[0]_i_16_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_17 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[37]),
        .I1(p_5_in[37]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[36]),
        .I3(p_5_in[36]),
        .O(\tmp_3_reg_1602[0]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_18 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[35]),
        .I1(p_5_in[35]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[34]),
        .I3(p_5_in[34]),
        .O(\tmp_3_reg_1602[0]_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_19 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[33]),
        .I1(p_5_in[33]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[32]),
        .I3(p_5_in[32]),
        .O(\tmp_3_reg_1602[0]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'hAA8A)) 
    \tmp_3_reg_1602[0]_i_20 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(\tmp_3_reg_1602[0]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'hA88A)) 
    \tmp_3_reg_1602[0]_i_21 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .O(\tmp_3_reg_1602[0]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT4 #(
    .INIT(16'hAA02)) 
    \tmp_3_reg_1602[0]_i_22 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .O(\tmp_3_reg_1602[0]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT4 #(
    .INIT(16'h1EFF)) 
    \tmp_3_reg_1602[0]_i_23 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .O(p_Val2_22_fu_1036_p4[43]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h77FD)) 
    \tmp_3_reg_1602[0]_i_24 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(p_Val2_22_fu_1036_p4[42]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h8100)) 
    \tmp_3_reg_1602[0]_i_25 
       (.I0(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .I1(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I3(or_cond_reg_1520),
        .O(\tmp_3_reg_1602[0]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \tmp_3_reg_1602[0]_i_26 
       (.I0(or_cond_reg_1520),
        .I1(\p_Val2_3_reg_440_reg_n_0_[2] ),
        .I2(\p_Val2_3_reg_440_reg_n_0_[0] ),
        .I3(\p_Val2_3_reg_440_reg_n_0_[1] ),
        .O(\tmp_3_reg_1602[0]_i_26_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_28 
       (.I0(p_5_in[31]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .I3(p_5_in[30]),
        .O(\tmp_3_reg_1602[0]_i_28_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_29 
       (.I0(p_5_in[29]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .I3(p_5_in[28]),
        .O(\tmp_3_reg_1602[0]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hEF8A8A8AEF8AEF8A)) 
    \tmp_3_reg_1602[0]_i_3 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I1(\tmp_3_reg_1602[0]_i_20_n_0 ),
        .I2(p_5_in__0[47]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .I4(\tmp_3_reg_1602[0]_i_21_n_0 ),
        .I5(p_5_in__0[46]),
        .O(\tmp_3_reg_1602[0]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_30 
       (.I0(p_5_in[27]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .I3(p_5_in[26]),
        .O(\tmp_3_reg_1602[0]_i_30_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_31 
       (.I0(p_5_in[25]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .I3(p_5_in[24]),
        .O(\tmp_3_reg_1602[0]_i_31_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_32 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[31]),
        .I1(p_5_in[31]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[30]),
        .I3(p_5_in[30]),
        .O(\tmp_3_reg_1602[0]_i_32_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_33 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[29]),
        .I1(p_5_in[29]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[28]),
        .I3(p_5_in[28]),
        .O(\tmp_3_reg_1602[0]_i_33_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_34 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[27]),
        .I1(p_5_in[27]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[26]),
        .I3(p_5_in[26]),
        .O(\tmp_3_reg_1602[0]_i_34_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_35 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[25]),
        .I1(p_5_in[25]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[24]),
        .I3(p_5_in[24]),
        .O(\tmp_3_reg_1602[0]_i_35_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_37 
       (.I0(p_5_in[23]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .I3(p_5_in[22]),
        .O(\tmp_3_reg_1602[0]_i_37_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_38 
       (.I0(p_5_in[21]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .I3(p_5_in[20]),
        .O(\tmp_3_reg_1602[0]_i_38_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_39 
       (.I0(p_5_in[19]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .I3(p_5_in[18]),
        .O(\tmp_3_reg_1602[0]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h8A8AEF8AEF8AEF8A)) 
    \tmp_3_reg_1602[0]_i_4 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I1(\tmp_3_reg_1602[0]_i_22_n_0 ),
        .I2(p_5_in__0[45]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .I4(p_5_in__0[44]),
        .I5(p_Val2_22_fu_1036_p4[43]),
        .O(\tmp_3_reg_1602[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_40 
       (.I0(p_5_in[17]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .I3(p_5_in[16]),
        .O(\tmp_3_reg_1602[0]_i_40_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_41 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[23]),
        .I1(p_5_in[23]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[22]),
        .I3(p_5_in[22]),
        .O(\tmp_3_reg_1602[0]_i_41_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_42 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[21]),
        .I1(p_5_in[21]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[20]),
        .I3(p_5_in[20]),
        .O(\tmp_3_reg_1602[0]_i_42_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_43 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[19]),
        .I1(p_5_in[19]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[18]),
        .I3(p_5_in[18]),
        .O(\tmp_3_reg_1602[0]_i_43_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_44 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[17]),
        .I1(p_5_in[17]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[16]),
        .I3(p_5_in[16]),
        .O(\tmp_3_reg_1602[0]_i_44_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_46 
       (.I0(p_5_in[15]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .I3(p_5_in[14]),
        .O(\tmp_3_reg_1602[0]_i_46_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_47 
       (.I0(p_5_in[13]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .I3(p_5_in[12]),
        .O(\tmp_3_reg_1602[0]_i_47_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_48 
       (.I0(p_5_in[11]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .I3(p_5_in[10]),
        .O(\tmp_3_reg_1602[0]_i_48_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_49 
       (.I0(p_5_in[9]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .I3(p_5_in[8]),
        .O(\tmp_3_reg_1602[0]_i_49_n_0 ));
  LUT6 #(
    .INIT(64'hBF2A2A2ABF2ABF2A)) 
    \tmp_3_reg_1602[0]_i_5 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I1(p_Val2_22_fu_1036_p4[42]),
        .I2(p_5_in__0[43]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .I4(\tmp_3_reg_1602[0]_i_25_n_0 ),
        .I5(p_5_in__0[42]),
        .O(\tmp_3_reg_1602[0]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_50 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[15]),
        .I1(p_5_in[15]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[14]),
        .I3(p_5_in[14]),
        .O(\tmp_3_reg_1602[0]_i_50_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_51 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[13]),
        .I1(p_5_in[13]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[12]),
        .I3(p_5_in[12]),
        .O(\tmp_3_reg_1602[0]_i_51_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_52 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[11]),
        .I1(p_5_in[11]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[10]),
        .I3(p_5_in[10]),
        .O(\tmp_3_reg_1602[0]_i_52_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_53 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[9]),
        .I1(p_5_in[9]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[8]),
        .I3(p_5_in[8]),
        .O(\tmp_3_reg_1602[0]_i_53_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_54 
       (.I0(p_5_in[7]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .I3(p_5_in[6]),
        .O(\tmp_3_reg_1602[0]_i_54_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_55 
       (.I0(p_5_in[5]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .I3(p_5_in[4]),
        .O(\tmp_3_reg_1602[0]_i_55_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_56 
       (.I0(p_5_in[3]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .I3(p_5_in[2]),
        .O(\tmp_3_reg_1602[0]_i_56_n_0 ));
  LUT4 #(
    .INIT(16'h44D4)) 
    \tmp_3_reg_1602[0]_i_57 
       (.I0(p_5_in[1]),
        .I1(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .I3(p_5_in[0]),
        .O(\tmp_3_reg_1602[0]_i_57_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_58 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[7]),
        .I1(p_5_in[7]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[6]),
        .I3(p_5_in[6]),
        .O(\tmp_3_reg_1602[0]_i_58_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_59 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[5]),
        .I1(p_5_in[5]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[4]),
        .I3(p_5_in[4]),
        .O(\tmp_3_reg_1602[0]_i_59_n_0 ));
  LUT5 #(
    .INIT(32'h8A8AEF8A)) 
    \tmp_3_reg_1602[0]_i_6 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[41]),
        .I1(\tmp_3_reg_1602[0]_i_26_n_0 ),
        .I2(p_5_in__0[41]),
        .I3(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[40]),
        .I4(p_5_in[40]),
        .O(\tmp_3_reg_1602[0]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_60 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[3]),
        .I1(p_5_in[3]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[2]),
        .I3(p_5_in[2]),
        .O(\tmp_3_reg_1602[0]_i_60_n_0 ));
  LUT4 #(
    .INIT(16'h9009)) 
    \tmp_3_reg_1602[0]_i_61 
       (.I0(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[1]),
        .I1(p_5_in[1]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[0]),
        .I3(p_5_in[0]),
        .O(\tmp_3_reg_1602[0]_i_61_n_0 ));
  LUT6 #(
    .INIT(64'h00002D002D2D002D)) 
    \tmp_3_reg_1602[0]_i_7 
       (.I0(p_5_in__0[47]),
        .I1(\tmp_3_reg_1602[0]_i_20_n_0 ),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[47]),
        .I3(p_5_in__0[46]),
        .I4(\tmp_3_reg_1602[0]_i_21_n_0 ),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[46]),
        .O(\tmp_3_reg_1602[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h2D000000002D2D2D)) 
    \tmp_3_reg_1602[0]_i_8 
       (.I0(p_5_in__0[45]),
        .I1(\tmp_3_reg_1602[0]_i_22_n_0 ),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[45]),
        .I3(p_Val2_22_fu_1036_p4[43]),
        .I4(p_5_in__0[44]),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[44]),
        .O(\tmp_3_reg_1602[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000870087870087)) 
    \tmp_3_reg_1602[0]_i_9 
       (.I0(p_5_in__0[43]),
        .I1(p_Val2_22_fu_1036_p4[42]),
        .I2(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[43]),
        .I3(p_5_in__0[42]),
        .I4(\tmp_3_reg_1602[0]_i_25_n_0 ),
        .I5(ap_phi_reg_pp0_iter3_p_Val2_8_reg_478[42]),
        .O(\tmp_3_reg_1602[0]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_3_reg_1602_pp0_iter4_reg_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_3_reg_1602),
        .Q(tmp_3_reg_1602_pp0_iter4_reg),
        .R(ap_rst));
  FDRE #(
    .INIT(1'b0)) 
    \tmp_3_reg_1602_reg[0] 
       (.C(ap_clk),
        .CE(p_Val2_4_reg_1510),
        .D(tmp_3_fu_1010_p2),
        .Q(tmp_3_reg_1602),
        .R(ap_rst));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_3_reg_1602_reg[0]_i_1 
       (.CI(\tmp_3_reg_1602_reg[0]_i_2_n_0 ),
        .CO({tmp_3_fu_1010_p2,\tmp_3_reg_1602_reg[0]_i_1_n_1 ,\tmp_3_reg_1602_reg[0]_i_1_n_2 ,\tmp_3_reg_1602_reg[0]_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_3_reg_1602[0]_i_3_n_0 ,\tmp_3_reg_1602[0]_i_4_n_0 ,\tmp_3_reg_1602[0]_i_5_n_0 ,\tmp_3_reg_1602[0]_i_6_n_0 }),
        .S({\tmp_3_reg_1602[0]_i_7_n_0 ,\tmp_3_reg_1602[0]_i_8_n_0 ,\tmp_3_reg_1602[0]_i_9_n_0 ,\tmp_3_reg_1602[0]_i_10_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_3_reg_1602_reg[0]_i_11 
       (.CI(\tmp_3_reg_1602_reg[0]_i_27_n_0 ),
        .CO({\tmp_3_reg_1602_reg[0]_i_11_n_0 ,\tmp_3_reg_1602_reg[0]_i_11_n_1 ,\tmp_3_reg_1602_reg[0]_i_11_n_2 ,\tmp_3_reg_1602_reg[0]_i_11_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_3_reg_1602[0]_i_28_n_0 ,\tmp_3_reg_1602[0]_i_29_n_0 ,\tmp_3_reg_1602[0]_i_30_n_0 ,\tmp_3_reg_1602[0]_i_31_n_0 }),
        .S({\tmp_3_reg_1602[0]_i_32_n_0 ,\tmp_3_reg_1602[0]_i_33_n_0 ,\tmp_3_reg_1602[0]_i_34_n_0 ,\tmp_3_reg_1602[0]_i_35_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_3_reg_1602_reg[0]_i_2 
       (.CI(\tmp_3_reg_1602_reg[0]_i_11_n_0 ),
        .CO({\tmp_3_reg_1602_reg[0]_i_2_n_0 ,\tmp_3_reg_1602_reg[0]_i_2_n_1 ,\tmp_3_reg_1602_reg[0]_i_2_n_2 ,\tmp_3_reg_1602_reg[0]_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_3_reg_1602[0]_i_12_n_0 ,\tmp_3_reg_1602[0]_i_13_n_0 ,\tmp_3_reg_1602[0]_i_14_n_0 ,\tmp_3_reg_1602[0]_i_15_n_0 }),
        .S({\tmp_3_reg_1602[0]_i_16_n_0 ,\tmp_3_reg_1602[0]_i_17_n_0 ,\tmp_3_reg_1602[0]_i_18_n_0 ,\tmp_3_reg_1602[0]_i_19_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_3_reg_1602_reg[0]_i_27 
       (.CI(\tmp_3_reg_1602_reg[0]_i_36_n_0 ),
        .CO({\tmp_3_reg_1602_reg[0]_i_27_n_0 ,\tmp_3_reg_1602_reg[0]_i_27_n_1 ,\tmp_3_reg_1602_reg[0]_i_27_n_2 ,\tmp_3_reg_1602_reg[0]_i_27_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_3_reg_1602[0]_i_37_n_0 ,\tmp_3_reg_1602[0]_i_38_n_0 ,\tmp_3_reg_1602[0]_i_39_n_0 ,\tmp_3_reg_1602[0]_i_40_n_0 }),
        .S({\tmp_3_reg_1602[0]_i_41_n_0 ,\tmp_3_reg_1602[0]_i_42_n_0 ,\tmp_3_reg_1602[0]_i_43_n_0 ,\tmp_3_reg_1602[0]_i_44_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_3_reg_1602_reg[0]_i_36 
       (.CI(\tmp_3_reg_1602_reg[0]_i_45_n_0 ),
        .CO({\tmp_3_reg_1602_reg[0]_i_36_n_0 ,\tmp_3_reg_1602_reg[0]_i_36_n_1 ,\tmp_3_reg_1602_reg[0]_i_36_n_2 ,\tmp_3_reg_1602_reg[0]_i_36_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_3_reg_1602[0]_i_46_n_0 ,\tmp_3_reg_1602[0]_i_47_n_0 ,\tmp_3_reg_1602[0]_i_48_n_0 ,\tmp_3_reg_1602[0]_i_49_n_0 }),
        .S({\tmp_3_reg_1602[0]_i_50_n_0 ,\tmp_3_reg_1602[0]_i_51_n_0 ,\tmp_3_reg_1602[0]_i_52_n_0 ,\tmp_3_reg_1602[0]_i_53_n_0 }));
  (* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *) 
  CARRY4 \tmp_3_reg_1602_reg[0]_i_45 
       (.CI(\<const0> ),
        .CO({\tmp_3_reg_1602_reg[0]_i_45_n_0 ,\tmp_3_reg_1602_reg[0]_i_45_n_1 ,\tmp_3_reg_1602_reg[0]_i_45_n_2 ,\tmp_3_reg_1602_reg[0]_i_45_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\tmp_3_reg_1602[0]_i_54_n_0 ,\tmp_3_reg_1602[0]_i_55_n_0 ,\tmp_3_reg_1602[0]_i_56_n_0 ,\tmp_3_reg_1602[0]_i_57_n_0 }),
        .S({\tmp_3_reg_1602[0]_i_58_n_0 ,\tmp_3_reg_1602[0]_i_59_n_0 ,\tmp_3_reg_1602[0]_i_60_n_0 ,\tmp_3_reg_1602[0]_i_61_n_0 }));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_RFNCO_veto_0,RFNCO_veto,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_RFNCO_veto_0,RFNCO_veto,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=RFNCO_veto,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "RFNCO_veto,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_RFNCO_veto_0
   (NCO_rst_i,
    phase_valid_i,
    sel_H1_i,
    sel_H1on_i,
    sel_load_i,
    interlock_o);
  input NCO_rst_i;
  input phase_valid_i;
  input sel_H1_i;
  input sel_H1on_i;
  input sel_load_i;
  output interlock_o;

  wire NCO_rst_i;
  wire interlock_o;
  wire phase_valid_i;
  wire sel_H1_i;
  wire sel_H1on_i;
  wire sel_load_i;

  RFNCO_cmp_RFNCO_veto_0_RFNCO_veto U0
       (.NCO_rst_i(NCO_rst_i),
        .interlock_o(interlock_o),
        .phase_valid_i(phase_valid_i),
        .sel_H1_i(sel_H1_i),
        .sel_H1on_i(sel_H1on_i),
        .sel_load_i(sel_load_i));
endmodule

(* ORIG_REF_NAME = "RFNCO_veto" *) 
module RFNCO_cmp_RFNCO_veto_0_RFNCO_veto
   (interlock_o,
    NCO_rst_i,
    sel_H1_i,
    phase_valid_i,
    sel_load_i,
    sel_H1on_i);
  output interlock_o;
  input NCO_rst_i;
  input sel_H1_i;
  input phase_valid_i;
  input sel_load_i;
  input sel_H1on_i;

  wire NCO_rst_i;
  wire interlock_o;
  wire phase_valid_i;
  wire sel_H1_i;
  wire sel_H1on_i;
  wire sel_load_i;

  LUT5 #(
    .INIT(32'h00000002)) 
    interlock_o__0
       (.I0(NCO_rst_i),
        .I1(sel_H1_i),
        .I2(phase_valid_i),
        .I3(sel_load_i),
        .I4(sel_H1on_i),
        .O(interlock_o));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_WRFrameBusSlave_0,WRFrameBusSlave,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_WRFrameBusSlave_0,WRFrameBusSlave,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=WRFrameBusSlave,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,FTW_LENGTH=48,OFFSET_LENGTH=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "WRFrameBusSlave,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_WRFrameBusSlave_0
   (slave_FTW_H1_main,
    slave_FTW_H1_prog,
    slave_FTW_H1_on,
    slave_rate,
    slave_dFTW_H1_slip0,
    slave_dFTW_H1_slip1,
    slave_inputs_valid,
    slave_reset_NCO,
    slave_reset_slip,
    slave_reset_FSK,
    master_FTW_H1_main,
    master_FTW_H1_prog,
    master_FTW_H1_on,
    master_rate,
    master_dFTW_H1_slip0,
    master_dFTW_H1_slip1,
    master_inputs_valid,
    master_reset_NCO,
    master_reset_slip,
    master_reset_FSK);
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave FTW_H1_main" *) output [47:0]slave_FTW_H1_main;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave FTW_H1_prog" *) output [47:0]slave_FTW_H1_prog;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave FTW_H1_on" *) output [47:0]slave_FTW_H1_on;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave rate" *) output [2:0]slave_rate;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave dFTW_H1_slip0" *) output [31:0]slave_dFTW_H1_slip0;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave dFTW_H1_slip1" *) output [31:0]slave_dFTW_H1_slip1;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave inputs_valid" *) output slave_inputs_valid;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave reset_NCO" *) output slave_reset_NCO;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave reset_slip" *) output slave_reset_slip;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 slave reset_FSK" *) output slave_reset_FSK;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus FTW_H1_main" *) input [47:0]master_FTW_H1_main;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus FTW_H1_prog" *) input [47:0]master_FTW_H1_prog;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus FTW_H1_on" *) input [47:0]master_FTW_H1_on;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus rate" *) input [2:0]master_rate;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus dFTW_H1_slip0" *) input [31:0]master_dFTW_H1_slip0;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus dFTW_H1_slip1" *) input [31:0]master_dFTW_H1_slip1;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus inputs_valid" *) input master_inputs_valid;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus reset_NCO" *) input master_reset_NCO;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus reset_slip" *) input master_reset_slip;
  (* X_INTERFACE_INFO = "cern.ch:interface:wr_frame:1.0 wr_frame_bus reset_FSK" *) input master_reset_FSK;

  wire [47:0]master_FTW_H1_main;
  wire [47:0]master_FTW_H1_on;
  wire [47:0]master_FTW_H1_prog;
  wire [31:0]master_dFTW_H1_slip0;
  wire [31:0]master_dFTW_H1_slip1;
  wire master_inputs_valid;
  wire [2:0]master_rate;
  wire master_reset_FSK;
  wire master_reset_NCO;
  wire master_reset_slip;

  assign slave_FTW_H1_main[47:0] = master_FTW_H1_main;
  assign slave_FTW_H1_on[47:0] = master_FTW_H1_on;
  assign slave_FTW_H1_prog[47:0] = master_FTW_H1_prog;
  assign slave_dFTW_H1_slip0[31:0] = master_dFTW_H1_slip0;
  assign slave_dFTW_H1_slip1[31:0] = master_dFTW_H1_slip1;
  assign slave_inputs_valid = master_inputs_valid;
  assign slave_rate[2:0] = master_rate;
  assign slave_reset_FSK = master_reset_FSK;
  assign slave_reset_NCO = master_reset_NCO;
  assign slave_reset_slip = master_reset_slip;
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_and_reset_enable_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_and_reset_enable_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=and,C_SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
module RFNCO_cmp_and_reset_enable_0
   (Op1,
    Op2,
    Res);
  input [0:0]Op1;
  input [0:0]Op2;
  output [0:0]Res;

  wire [0:0]Op1;
  wire [0:0]Op2;
  wire [0:0]Res;

  LUT2 #(
    .INIT(4'h8)) 
    \Res[0]_INST_0 
       (.I0(Op1),
        .I1(Op2),
        .O(Res));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_and_reset_enable_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_and_reset_enable_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=and,C_SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
module RFNCO_cmp_and_rstnco_valid_0
   (Op1,
    Op2,
    Res);
  input [0:0]Op1;
  input [0:0]Op2;
  output [0:0]Res;

  wire [0:0]Op1;
  wire [0:0]Op2;
  wire [0:0]Res;

  LUT2 #(
    .INIT(4'h8)) 
    \Res[0]_INST_0 
       (.I0(Op1),
        .I1(Op2),
        .O(Res));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_bit_shift_0,bit_shift,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_bit_shift_0,bit_shift,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=bit_shift,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "bit_shift,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_bit_shift_0
   (data_i,
    enable_i,
    data_o);
  input [47:0]data_i;
  input enable_i;
  output [47:0]data_o;

  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;

  RFNCO_cmp_bit_shift_0_bit_shift U0
       (.data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i));
endmodule

(* ORIG_REF_NAME = "bit_shift" *) 
module RFNCO_cmp_bit_shift_0_bit_shift
   (data_o,
    data_i,
    enable_i);
  output [47:0]data_o;
  input [47:0]data_i;
  input enable_i;

  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \data_o[0]_INST_0 
       (.I0(data_i[0]),
        .I1(enable_i),
        .O(data_o[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[10]_INST_0 
       (.I0(data_i[9]),
        .I1(enable_i),
        .I2(data_i[10]),
        .O(data_o[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[11]_INST_0 
       (.I0(data_i[10]),
        .I1(enable_i),
        .I2(data_i[11]),
        .O(data_o[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[12]_INST_0 
       (.I0(data_i[11]),
        .I1(enable_i),
        .I2(data_i[12]),
        .O(data_o[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[13]_INST_0 
       (.I0(data_i[12]),
        .I1(enable_i),
        .I2(data_i[13]),
        .O(data_o[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[14]_INST_0 
       (.I0(data_i[13]),
        .I1(enable_i),
        .I2(data_i[14]),
        .O(data_o[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[15]_INST_0 
       (.I0(data_i[14]),
        .I1(enable_i),
        .I2(data_i[15]),
        .O(data_o[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[16]_INST_0 
       (.I0(data_i[15]),
        .I1(enable_i),
        .I2(data_i[16]),
        .O(data_o[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[17]_INST_0 
       (.I0(data_i[16]),
        .I1(enable_i),
        .I2(data_i[17]),
        .O(data_o[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[18]_INST_0 
       (.I0(data_i[17]),
        .I1(enable_i),
        .I2(data_i[18]),
        .O(data_o[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[19]_INST_0 
       (.I0(data_i[18]),
        .I1(enable_i),
        .I2(data_i[19]),
        .O(data_o[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[1]_INST_0 
       (.I0(data_i[0]),
        .I1(enable_i),
        .I2(data_i[1]),
        .O(data_o[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[20]_INST_0 
       (.I0(data_i[19]),
        .I1(enable_i),
        .I2(data_i[20]),
        .O(data_o[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[21]_INST_0 
       (.I0(data_i[20]),
        .I1(enable_i),
        .I2(data_i[21]),
        .O(data_o[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[22]_INST_0 
       (.I0(data_i[21]),
        .I1(enable_i),
        .I2(data_i[22]),
        .O(data_o[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[23]_INST_0 
       (.I0(data_i[22]),
        .I1(enable_i),
        .I2(data_i[23]),
        .O(data_o[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[24]_INST_0 
       (.I0(data_i[23]),
        .I1(enable_i),
        .I2(data_i[24]),
        .O(data_o[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[25]_INST_0 
       (.I0(data_i[24]),
        .I1(enable_i),
        .I2(data_i[25]),
        .O(data_o[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[26]_INST_0 
       (.I0(data_i[25]),
        .I1(enable_i),
        .I2(data_i[26]),
        .O(data_o[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[27]_INST_0 
       (.I0(data_i[26]),
        .I1(enable_i),
        .I2(data_i[27]),
        .O(data_o[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[28]_INST_0 
       (.I0(data_i[27]),
        .I1(enable_i),
        .I2(data_i[28]),
        .O(data_o[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[29]_INST_0 
       (.I0(data_i[28]),
        .I1(enable_i),
        .I2(data_i[29]),
        .O(data_o[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[2]_INST_0 
       (.I0(data_i[1]),
        .I1(enable_i),
        .I2(data_i[2]),
        .O(data_o[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[30]_INST_0 
       (.I0(data_i[29]),
        .I1(enable_i),
        .I2(data_i[30]),
        .O(data_o[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[31]_INST_0 
       (.I0(data_i[30]),
        .I1(enable_i),
        .I2(data_i[31]),
        .O(data_o[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[32]_INST_0 
       (.I0(data_i[31]),
        .I1(enable_i),
        .I2(data_i[32]),
        .O(data_o[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[33]_INST_0 
       (.I0(data_i[32]),
        .I1(enable_i),
        .I2(data_i[33]),
        .O(data_o[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[34]_INST_0 
       (.I0(data_i[33]),
        .I1(enable_i),
        .I2(data_i[34]),
        .O(data_o[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[35]_INST_0 
       (.I0(data_i[34]),
        .I1(enable_i),
        .I2(data_i[35]),
        .O(data_o[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[36]_INST_0 
       (.I0(data_i[35]),
        .I1(enable_i),
        .I2(data_i[36]),
        .O(data_o[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[37]_INST_0 
       (.I0(data_i[36]),
        .I1(enable_i),
        .I2(data_i[37]),
        .O(data_o[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[38]_INST_0 
       (.I0(data_i[37]),
        .I1(enable_i),
        .I2(data_i[38]),
        .O(data_o[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[39]_INST_0 
       (.I0(data_i[38]),
        .I1(enable_i),
        .I2(data_i[39]),
        .O(data_o[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[3]_INST_0 
       (.I0(data_i[2]),
        .I1(enable_i),
        .I2(data_i[3]),
        .O(data_o[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[40]_INST_0 
       (.I0(data_i[39]),
        .I1(enable_i),
        .I2(data_i[40]),
        .O(data_o[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[41]_INST_0 
       (.I0(data_i[40]),
        .I1(enable_i),
        .I2(data_i[41]),
        .O(data_o[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[42]_INST_0 
       (.I0(data_i[41]),
        .I1(enable_i),
        .I2(data_i[42]),
        .O(data_o[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[43]_INST_0 
       (.I0(data_i[42]),
        .I1(enable_i),
        .I2(data_i[43]),
        .O(data_o[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[44]_INST_0 
       (.I0(data_i[43]),
        .I1(enable_i),
        .I2(data_i[44]),
        .O(data_o[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[45]_INST_0 
       (.I0(data_i[44]),
        .I1(enable_i),
        .I2(data_i[45]),
        .O(data_o[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[46]_INST_0 
       (.I0(data_i[45]),
        .I1(enable_i),
        .I2(data_i[46]),
        .O(data_o[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[47]_INST_0 
       (.I0(data_i[46]),
        .I1(enable_i),
        .I2(data_i[47]),
        .O(data_o[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[4]_INST_0 
       (.I0(data_i[3]),
        .I1(enable_i),
        .I2(data_i[4]),
        .O(data_o[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[5]_INST_0 
       (.I0(data_i[4]),
        .I1(enable_i),
        .I2(data_i[5]),
        .O(data_o[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[6]_INST_0 
       (.I0(data_i[5]),
        .I1(enable_i),
        .I2(data_i[6]),
        .O(data_o[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[7]_INST_0 
       (.I0(data_i[6]),
        .I1(enable_i),
        .I2(data_i[7]),
        .O(data_o[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[8]_INST_0 
       (.I0(data_i[7]),
        .I1(enable_i),
        .I2(data_i[8]),
        .O(data_o[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_o[9]_INST_0 
       (.I0(data_i[8]),
        .I1(enable_i),
        .I2(data_i[9]),
        .O(data_o[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_concat_phase_IF0_0,xlconcat_v2_1_1_xlconcat,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_concat_phase_IF0_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=25,IN1_WIDTH=7,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=32,NUM_PORTS=2}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2018.2" *) 
module RFNCO_cmp_concat_phase_IF0_0
   (In0,
    In1,
    dout);
  input [24:0]In0;
  input [6:0]In1;
  output [31:0]dout;

  wire [24:0]In0;
  wire [6:0]In1;

  assign dout[31:25] = In1;
  assign dout[24:0] = In0;
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_concat_phase_IF0_0,xlconcat_v2_1_1_xlconcat,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_concat_phase_IF0_0,xlconcat_v2_1_1_xlconcat,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=25,IN1_WIDTH=7,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=32,NUM_PORTS=2}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlconcat_v2_1_1_xlconcat,Vivado 2018.2" *) 
module RFNCO_cmp_concat_phase_IF1_0
   (In0,
    In1,
    dout);
  input [24:0]In0;
  input [6:0]In1;
  output [31:0]dout;

  wire [24:0]In0;
  wire [6:0]In1;

  assign dout[31:25] = In1;
  assign dout[24:0] = In0;
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_dds_IF0_0,dds_compiler_v6_0_16,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_dds_IF0_0,dds_compiler_v6_0_16,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=16,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=kintex7,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=25,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=0,C_HAS_SINCOS=1,C_LATENCY=9,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=2,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=25,C_PHASE_ANGLE_WIDTH=11,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=2,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=32,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=64,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "dds_compiler_v6_0_16,Vivado 2018.2" *) 
module RFNCO_cmp_dds_IF0_0
   (aclk,
    s_axis_phase_tvalid,
    s_axis_phase_tdata,
    s_axis_phase_tlast,
    m_axis_data_tvalid,
    m_axis_data_tdata,
    m_axis_data_tlast);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input aclk;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_PHASE, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i, LAYERED_METADATA undef" *) input s_axis_phase_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA" *) input [31:0]s_axis_phase_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TLAST" *) input s_axis_phase_tlast;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 57} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 64} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 57} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_cosine {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cosine} enabled {attribs {resolve_type generated dependency cosine_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency cosine_width format long minimum {} maximum {}} value 25} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency cosine_fractwidth format long minimum {} maximum {}} value 24} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}} field_sine {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value sine} enabled {attribs {resolve_type generated dependency sine_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency sine_width format long minimum {} maximum {}} value 25} bitoffset {attribs {resolve_type generated dependency sine_offset format long minimum {} maximum {}} value 32} real {fixed {fractwidth {attribs {resolve_type generated dependency sine_fractwidth format long minimum {} maximum {}} value 24} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}} TDATA_WIDTH 64 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated dependency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_offset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}" *) output m_axis_data_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [63:0]m_axis_data_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST" *) output m_axis_data_tlast;

  wire \<const0> ;
  wire \<const1> ;
  wire aclk;
  wire [63:0]m_axis_data_tdata;
  wire m_axis_data_tlast;
  wire m_axis_data_tvalid;
  wire [31:0]s_axis_phase_tdata;
  wire s_axis_phase_tlast;
  wire s_axis_phase_tvalid;

  GND GND
       (.G(\<const0> ));
  (* C_ACCUMULATOR_WIDTH = "25" *) 
  (* C_AMPLITUDE = "0" *) 
  (* C_CHANNELS = "1" *) 
  (* C_CHAN_WIDTH = "1" *) 
  (* C_DEBUG_INTERFACE = "0" *) 
  (* C_HAS_ACLKEN = "0" *) 
  (* C_HAS_ARESETN = "0" *) 
  (* C_HAS_M_DATA = "1" *) 
  (* C_HAS_M_PHASE = "0" *) 
  (* C_HAS_PHASEGEN = "0" *) 
  (* C_HAS_PHASE_OUT = "0" *) 
  (* C_HAS_SINCOS = "1" *) 
  (* C_HAS_S_CONFIG = "0" *) 
  (* C_HAS_S_PHASE = "1" *) 
  (* C_HAS_TLAST = "2" *) 
  (* C_HAS_TREADY = "0" *) 
  (* C_LATENCY = "9" *) 
  (* C_MEM_TYPE = "1" *) 
  (* C_MODE_OF_OPERATION = "0" *) 
  (* C_MODULUS = "9" *) 
  (* C_M_DATA_HAS_TUSER = "0" *) 
  (* C_M_DATA_TDATA_WIDTH = "64" *) 
  (* C_M_DATA_TUSER_WIDTH = "1" *) 
  (* C_M_PHASE_HAS_TUSER = "0" *) 
  (* C_M_PHASE_TDATA_WIDTH = "1" *) 
  (* C_M_PHASE_TUSER_WIDTH = "1" *) 
  (* C_NEGATIVE_COSINE = "0" *) 
  (* C_NEGATIVE_SINE = "0" *) 
  (* C_NOISE_SHAPING = "2" *) 
  (* C_OPTIMISE_GOAL = "0" *) 
  (* C_OUTPUTS_REQUIRED = "2" *) 
  (* C_OUTPUT_FORM = "0" *) 
  (* C_OUTPUT_WIDTH = "25" *) 
  (* C_PHASE_ANGLE_WIDTH = "11" *) 
  (* C_PHASE_INCREMENT = "2" *) 
  (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_PHASE_OFFSET = "0" *) 
  (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_POR_MODE = "0" *) 
  (* C_RESYNC = "0" *) 
  (* C_S_CONFIG_SYNC_MODE = "0" *) 
  (* C_S_CONFIG_TDATA_WIDTH = "1" *) 
  (* C_S_PHASE_HAS_TUSER = "0" *) 
  (* C_S_PHASE_TDATA_WIDTH = "32" *) 
  (* C_S_PHASE_TUSER_WIDTH = "1" *) 
  (* C_USE_DSP48 = "0" *) 
  (* C_XDEVICEFAMILY = "kintex7" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  RFNCO_cmp_dds_IF0_0_dds_compiler_v6_0_16 U0
       (.aclk(aclk),
        .aclken(\<const1> ),
        .aresetn(\<const1> ),
        .m_axis_data_tdata(m_axis_data_tdata),
        .m_axis_data_tlast(m_axis_data_tlast),
        .m_axis_data_tready(\<const0> ),
        .m_axis_data_tvalid(m_axis_data_tvalid),
        .m_axis_phase_tready(\<const0> ),
        .s_axis_config_tdata(\<const0> ),
        .s_axis_config_tlast(\<const0> ),
        .s_axis_config_tvalid(\<const0> ),
        .s_axis_phase_tdata(s_axis_phase_tdata),
        .s_axis_phase_tlast(s_axis_phase_tlast),
        .s_axis_phase_tuser(\<const0> ),
        .s_axis_phase_tvalid(s_axis_phase_tvalid));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_dds_IF1_0,dds_compiler_v6_0_16,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_dds_IF1_0,dds_compiler_v6_0_16,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=16,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=kintex7,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=25,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=0,C_HAS_SINCOS=1,C_LATENCY=9,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=2,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=25,C_PHASE_ANGLE_WIDTH=11,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=32,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=64,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "dds_compiler_v6_0_16,Vivado 2018.2" *) 
module RFNCO_cmp_dds_IF1_0
   (aclk,
    s_axis_phase_tvalid,
    s_axis_phase_tdata,
    m_axis_data_tvalid,
    m_axis_data_tdata);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF M_AXIS_PHASE:S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_PHASE, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input aclk;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXIS_PHASE, TDATA_NUM_BYTES 4, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i, LAYERED_METADATA undef" *) input s_axis_phase_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA" *) input [31:0]s_axis_phase_tdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 0, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 57} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 1} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 64} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 57} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_cosine {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value cosine} enabled {attribs {resolve_type generated dependency cosine_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency cosine_width format long minimum {} maximum {}} value 25} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency cosine_fractwidth format long minimum {} maximum {}} value 24} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}} field_sine {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value sine} enabled {attribs {resolve_type generated dependency sine_enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency sine_width format long minimum {} maximum {}} value 25} bitoffset {attribs {resolve_type generated dependency sine_offset format long minimum {} maximum {}} value 32} real {fixed {fractwidth {attribs {resolve_type generated dependency sine_fractwidth format long minimum {} maximum {}} value 24} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}}}}} TDATA_WIDTH 64 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chanid {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chanid} enabled {attribs {resolve_type generated dependency chanid_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chanid_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_user {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value user} enabled {attribs {resolve_type generated dependency user_enabled format bool minimum {} maximum {}} value false} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency user_width format long minimum {} maximum {}} value 0} bitoffset {attribs {resolve_type generated dependency user_offset format long minimum {} maximum {}} value 0}}}}}} TUSER_WIDTH 0}" *) output m_axis_data_tvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) output [63:0]m_axis_data_tdata;

  wire \<const0> ;
  wire \<const1> ;
  wire aclk;
  wire [63:0]m_axis_data_tdata;
  wire m_axis_data_tvalid;
  wire [31:0]s_axis_phase_tdata;
  wire s_axis_phase_tvalid;

  GND GND
       (.G(\<const0> ));
  (* C_ACCUMULATOR_WIDTH = "25" *) 
  (* C_AMPLITUDE = "0" *) 
  (* C_CHANNELS = "1" *) 
  (* C_CHAN_WIDTH = "1" *) 
  (* C_DEBUG_INTERFACE = "0" *) 
  (* C_HAS_ACLKEN = "0" *) 
  (* C_HAS_ARESETN = "0" *) 
  (* C_HAS_M_DATA = "1" *) 
  (* C_HAS_M_PHASE = "0" *) 
  (* C_HAS_PHASEGEN = "0" *) 
  (* C_HAS_PHASE_OUT = "0" *) 
  (* C_HAS_SINCOS = "1" *) 
  (* C_HAS_S_CONFIG = "0" *) 
  (* C_HAS_S_PHASE = "1" *) 
  (* C_HAS_TLAST = "0" *) 
  (* C_HAS_TREADY = "0" *) 
  (* C_LATENCY = "9" *) 
  (* C_MEM_TYPE = "1" *) 
  (* C_MODE_OF_OPERATION = "0" *) 
  (* C_MODULUS = "9" *) 
  (* C_M_DATA_HAS_TUSER = "0" *) 
  (* C_M_DATA_TDATA_WIDTH = "64" *) 
  (* C_M_DATA_TUSER_WIDTH = "1" *) 
  (* C_M_PHASE_HAS_TUSER = "0" *) 
  (* C_M_PHASE_TDATA_WIDTH = "1" *) 
  (* C_M_PHASE_TUSER_WIDTH = "1" *) 
  (* C_NEGATIVE_COSINE = "0" *) 
  (* C_NEGATIVE_SINE = "0" *) 
  (* C_NOISE_SHAPING = "2" *) 
  (* C_OPTIMISE_GOAL = "0" *) 
  (* C_OUTPUTS_REQUIRED = "2" *) 
  (* C_OUTPUT_FORM = "0" *) 
  (* C_OUTPUT_WIDTH = "25" *) 
  (* C_PHASE_ANGLE_WIDTH = "11" *) 
  (* C_PHASE_INCREMENT = "2" *) 
  (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_PHASE_OFFSET = "0" *) 
  (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_POR_MODE = "0" *) 
  (* C_RESYNC = "0" *) 
  (* C_S_CONFIG_SYNC_MODE = "0" *) 
  (* C_S_CONFIG_TDATA_WIDTH = "1" *) 
  (* C_S_PHASE_HAS_TUSER = "0" *) 
  (* C_S_PHASE_TDATA_WIDTH = "32" *) 
  (* C_S_PHASE_TUSER_WIDTH = "1" *) 
  (* C_USE_DSP48 = "0" *) 
  (* C_XDEVICEFAMILY = "kintex7" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  RFNCO_cmp_dds_IF1_0_dds_compiler_v6_0_16 U0
       (.aclk(aclk),
        .aclken(\<const1> ),
        .aresetn(\<const1> ),
        .m_axis_data_tdata(m_axis_data_tdata),
        .m_axis_data_tready(\<const0> ),
        .m_axis_data_tvalid(m_axis_data_tvalid),
        .m_axis_phase_tready(\<const0> ),
        .s_axis_config_tdata(\<const0> ),
        .s_axis_config_tlast(\<const0> ),
        .s_axis_config_tvalid(\<const0> ),
        .s_axis_phase_tdata(s_axis_phase_tdata),
        .s_axis_phase_tlast(\<const0> ),
        .s_axis_phase_tuser(\<const0> ),
        .s_axis_phase_tvalid(s_axis_phase_tvalid));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_dftw_slip_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_dftw_slip_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=32}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_dftw_slip_mux_0
   (A,
    B,
    C,
    sel);
  input [31:0]A;
  input [31:0]B;
  output [31:0]C;
  input sel;

  wire [31:0]A;
  wire [31:0]B;
  wire [31:0]C;
  wire sel;

  RFNCO_cmp_dftw_slip_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_dftw_slip_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [31:0]C;
  input [31:0]A;
  input [31:0]B;
  input sel;

  wire [31:0]A;
  wire [31:0]B;
  wire [31:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_cos_IF0_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_cos_IF0_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=25,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_cos_IF0_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  output [24:0]data_o;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_cos_IF0_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_cos_IF0_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [24:0]data_o;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  input clk_i;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_cos_IF1_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_cos_IF1_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=25,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_cos_IF1_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  output [24:0]data_o;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_cos_IF1_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_cos_IF1_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [24:0]data_o;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  input clk_i;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_ftw_H1_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_ftw_H1_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_ftw_H1_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_ftw_H1_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_ftw_H1_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_ftw_H1_on_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_ftw_H1_on_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_ftw_H1_on_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_ftw_H1_on_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_ftw_H1_on_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_ftw_H1_vld_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_ftw_H1_vld_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=1,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_ftw_H1_vld_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [0:0]data_i;
  output [0:0]data_o;

  wire clk_i;
  wire [0:0]data_i;
  wire [0:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_ftw_H1_vld_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_ftw_H1_vld_0_enable_ff
   (data_o,
    clk_i,
    enable_i,
    data_i,
    rst_i);
  output [0:0]data_o;
  input clk_i;
  input enable_i;
  input [0:0]data_i;
  input rst_i;

  wire \<const0> ;
  wire \<const1> ;
  wire clk_i;
  wire [0:0]data_i;
  wire [0:0]data_o;
  wire enable_i;
  wire rst_i;
  wire \s_data[0]_i_1_n_0 ;

  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \s_data[0]_i_1 
       (.I0(data_o),
        .I1(enable_i),
        .I2(data_i),
        .I3(rst_i),
        .O(\s_data[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(\<const1> ),
        .D(\s_data[0]_i_1_n_0 ),
        .Q(data_o),
        .R(\<const0> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_phaseIf0_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_phaseIf0_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_phaseIf0_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_phaseIf0_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_phaseIf0_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_phaseIf1_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_phaseIf1_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_phaseIf1_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_phaseIf1_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_phaseIf1_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_phase_H1_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_phase_H1_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_phase_H1_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_phase_H1_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_phase_H1_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_phase_H1main_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_phase_H1main_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_phase_H1main_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_phase_H1main_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_phase_H1main_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_phase_H1slip_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_phase_H1slip_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=48,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_phase_H1slip_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  output [47:0]data_o;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_phase_H1slip_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_phase_H1slip_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [47:0]data_o;
  input rst_i;
  input enable_i;
  input [47:0]data_i;
  input clk_i;

  wire clk_i;
  wire [47:0]data_i;
  wire [47:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[25] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[25]),
        .Q(data_o[25]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[26] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[26]),
        .Q(data_o[26]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[27] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[27]),
        .Q(data_o[27]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[28] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[28]),
        .Q(data_o[28]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[29] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[29]),
        .Q(data_o[29]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[30] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[30]),
        .Q(data_o[30]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[31] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[31]),
        .Q(data_o[31]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[32] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[32]),
        .Q(data_o[32]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[33] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[33]),
        .Q(data_o[33]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[34] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[34]),
        .Q(data_o[34]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[35] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[35]),
        .Q(data_o[35]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[36] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[36]),
        .Q(data_o[36]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[37] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[37]),
        .Q(data_o[37]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[38] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[38]),
        .Q(data_o[38]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[39] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[39]),
        .Q(data_o[39]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[40] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[40]),
        .Q(data_o[40]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[41] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[41]),
        .Q(data_o[41]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[42] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[42]),
        .Q(data_o[42]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[43] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[43]),
        .Q(data_o[43]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[44] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[44]),
        .Q(data_o[44]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[45] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[45]),
        .Q(data_o[45]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[46] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[46]),
        .Q(data_o[46]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[47] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[47]),
        .Q(data_o[47]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_sin_IF0_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_sin_IF0_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=25,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_sin_IF0_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  output [24:0]data_o;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_sin_IF0_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_sin_IF0_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [24:0]data_o;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  input clk_i;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_sin_IF1_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_sin_IF1_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=25,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_sin_IF1_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  output [24:0]data_o;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_sin_IF1_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_sin_IF1_0_enable_ff
   (data_o,
    rst_i,
    enable_i,
    data_i,
    clk_i);
  output [24:0]data_o;
  input rst_i;
  input enable_i;
  input [24:0]data_i;
  input clk_i;

  wire clk_i;
  wire [24:0]data_i;
  wire [24:0]data_o;
  wire enable_i;
  wire rst_i;

  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[0]),
        .Q(data_o[0]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[10] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[10]),
        .Q(data_o[10]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[11] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[11]),
        .Q(data_o[11]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[12] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[12]),
        .Q(data_o[12]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[13] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[13]),
        .Q(data_o[13]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[14] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[14]),
        .Q(data_o[14]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[15] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[15]),
        .Q(data_o[15]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[16] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[16]),
        .Q(data_o[16]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[17] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[17]),
        .Q(data_o[17]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[18] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[18]),
        .Q(data_o[18]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[19] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[19]),
        .Q(data_o[19]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[1] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[1]),
        .Q(data_o[1]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[20] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[20]),
        .Q(data_o[20]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[21] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[21]),
        .Q(data_o[21]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[22] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[22]),
        .Q(data_o[22]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[23] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[23]),
        .Q(data_o[23]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[24] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[24]),
        .Q(data_o[24]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[2] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[2]),
        .Q(data_o[2]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[3] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[3]),
        .Q(data_o[3]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[4] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[4]),
        .Q(data_o[4]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[5] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[5]),
        .Q(data_o[5]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[6] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[6]),
        .Q(data_o[6]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[7] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[7]),
        .Q(data_o[7]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[8] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[8]),
        .Q(data_o[8]),
        .R(rst_i));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[9] 
       (.C(clk_i),
        .CE(enable_i),
        .D(data_i[9]),
        .Q(data_o[9]),
        .R(rst_i));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ff_sincos_vld_0,enable_ff,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ff_sincos_vld_0,enable_ff,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=enable_ff,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,RES=1,RST_N=false}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "enable_ff,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ff_sincos_vld_0
   (clk_i,
    rst_i,
    enable_i,
    data_i,
    data_o);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst_i, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input clk_i;
  input rst_i;
  input enable_i;
  input [0:0]data_i;
  output [0:0]data_o;

  wire clk_i;
  wire [0:0]data_i;
  wire [0:0]data_o;
  wire enable_i;
  wire rst_i;

  RFNCO_cmp_ff_sincos_vld_0_enable_ff U0
       (.clk_i(clk_i),
        .data_i(data_i),
        .data_o(data_o),
        .enable_i(enable_i),
        .rst_i(rst_i));
endmodule

(* ORIG_REF_NAME = "enable_ff" *) 
module RFNCO_cmp_ff_sincos_vld_0_enable_ff
   (data_o,
    clk_i,
    enable_i,
    data_i,
    rst_i);
  output [0:0]data_o;
  input clk_i;
  input enable_i;
  input [0:0]data_i;
  input rst_i;

  wire \<const0> ;
  wire \<const1> ;
  wire clk_i;
  wire [0:0]data_i;
  wire [0:0]data_o;
  wire enable_i;
  wire rst_i;
  wire \s_data[0]_i_1_n_0 ;

  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \s_data[0]_i_1 
       (.I0(data_o),
        .I1(enable_i),
        .I2(data_i),
        .I3(rst_i),
        .O(\s_data[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \s_data_reg[0] 
       (.C(clk_i),
        .CE(\<const1> ),
        .D(\s_data[0]_i_1_n_0 ),
        .Q(data_o),
        .R(\<const0> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_ftw_slip_adder_0,ftw_slip_adder,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_ftw_slip_adder_0,ftw_slip_adder,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=ftw_slip_adder,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "ftw_slip_adder,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_ftw_slip_adder_0
   (slip_sign_i,
    slip_enable_i,
    ftw_slip_i,
    ftw_H1_i,
    ftw_H1_o);
  input slip_sign_i;
  input slip_enable_i;
  input [31:0]ftw_slip_i;
  input [47:0]ftw_H1_i;
  output [47:0]ftw_H1_o;

  wire [47:0]ftw_H1_i;
  wire [47:0]ftw_H1_o;
  wire [31:0]ftw_slip_i;
  wire slip_enable_i;
  wire slip_sign_i;

  RFNCO_cmp_ftw_slip_adder_0_ftw_slip_adder U0
       (.ftw_H1_i(ftw_H1_i),
        .ftw_H1_o(ftw_H1_o),
        .ftw_slip_i(ftw_slip_i),
        .slip_enable_i(slip_enable_i),
        .slip_sign_i(slip_sign_i));
endmodule

(* ORIG_REF_NAME = "ftw_slip_adder" *) 
module RFNCO_cmp_ftw_slip_adder_0_ftw_slip_adder
   (ftw_H1_o,
    ftw_H1_i,
    ftw_slip_i,
    slip_enable_i,
    slip_sign_i);
  output [47:0]ftw_H1_o;
  input [47:0]ftw_H1_i;
  input [31:0]ftw_slip_i;
  input slip_enable_i;
  input slip_sign_i;

  wire \<const0> ;
  wire \<const1> ;
  wire [47:0]ftw_H1_i;
  wire [47:0]ftw_H1_o;
  wire [47:0]ftw_H1_o0;
  wire [47:0]ftw_H1_o00_in;
  wire \ftw_H1_o[11]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[11]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[11]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[11]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[11]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[11]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[11]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[11]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[15]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[15]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[15]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[15]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[15]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[15]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[15]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[19]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[19]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[19]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[19]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[19]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[19]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[19]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[23]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[23]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[23]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[23]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[23]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[23]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[23]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[27]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[27]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[27]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[27]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[27]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[27]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[27]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[31]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[31]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[31]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[31]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[31]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[31]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[31]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_11_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[35]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[35]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[35]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[35]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[35]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[35]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[35]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[39]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[39]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[39]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[39]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[39]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[39]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[39]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[3]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[3]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[3]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[3]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[3]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[3]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[3]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[43]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[43]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[43]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[43]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[43]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[43]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[43]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[47]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[47]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[47]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[47]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[47]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[47]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[47]_INST_0_i_9_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_10_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_1_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_1_n_1 ;
  wire \ftw_H1_o[7]_INST_0_i_1_n_2 ;
  wire \ftw_H1_o[7]_INST_0_i_1_n_3 ;
  wire \ftw_H1_o[7]_INST_0_i_2_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_2_n_1 ;
  wire \ftw_H1_o[7]_INST_0_i_2_n_2 ;
  wire \ftw_H1_o[7]_INST_0_i_2_n_3 ;
  wire \ftw_H1_o[7]_INST_0_i_3_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_4_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_5_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_6_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_7_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_8_n_0 ;
  wire \ftw_H1_o[7]_INST_0_i_9_n_0 ;
  wire [31:0]ftw_slip_i;
  wire slip_enable_i;
  wire slip_sign_i;

  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[0]_INST_0 
       (.I0(ftw_H1_o00_in[0]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[0]),
        .I4(ftw_H1_i[0]),
        .O(ftw_H1_o[0]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[10]_INST_0 
       (.I0(ftw_H1_o00_in[10]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[10]),
        .I4(ftw_H1_i[10]),
        .O(ftw_H1_o[10]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[11]_INST_0 
       (.I0(ftw_H1_o00_in[11]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[11]),
        .I4(ftw_H1_i[11]),
        .O(ftw_H1_o[11]));
  CARRY4 \ftw_H1_o[11]_INST_0_i_1 
       (.CI(\ftw_H1_o[7]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[11]_INST_0_i_1_n_0 ,\ftw_H1_o[11]_INST_0_i_1_n_1 ,\ftw_H1_o[11]_INST_0_i_1_n_2 ,\ftw_H1_o[11]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[11:8]),
        .O(ftw_H1_o00_in[11:8]),
        .S({\ftw_H1_o[11]_INST_0_i_3_n_0 ,\ftw_H1_o[11]_INST_0_i_4_n_0 ,\ftw_H1_o[11]_INST_0_i_5_n_0 ,\ftw_H1_o[11]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[11]_INST_0_i_10 
       (.I0(ftw_H1_i[8]),
        .I1(ftw_slip_i[8]),
        .O(\ftw_H1_o[11]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[11]_INST_0_i_2 
       (.CI(\ftw_H1_o[7]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[11]_INST_0_i_2_n_0 ,\ftw_H1_o[11]_INST_0_i_2_n_1 ,\ftw_H1_o[11]_INST_0_i_2_n_2 ,\ftw_H1_o[11]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[11:8]),
        .O(ftw_H1_o0[11:8]),
        .S({\ftw_H1_o[11]_INST_0_i_7_n_0 ,\ftw_H1_o[11]_INST_0_i_8_n_0 ,\ftw_H1_o[11]_INST_0_i_9_n_0 ,\ftw_H1_o[11]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[11]_INST_0_i_3 
       (.I0(ftw_slip_i[11]),
        .I1(ftw_H1_i[11]),
        .O(\ftw_H1_o[11]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[11]_INST_0_i_4 
       (.I0(ftw_slip_i[10]),
        .I1(ftw_H1_i[10]),
        .O(\ftw_H1_o[11]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[11]_INST_0_i_5 
       (.I0(ftw_slip_i[9]),
        .I1(ftw_H1_i[9]),
        .O(\ftw_H1_o[11]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[11]_INST_0_i_6 
       (.I0(ftw_slip_i[8]),
        .I1(ftw_H1_i[8]),
        .O(\ftw_H1_o[11]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[11]_INST_0_i_7 
       (.I0(ftw_H1_i[11]),
        .I1(ftw_slip_i[11]),
        .O(\ftw_H1_o[11]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[11]_INST_0_i_8 
       (.I0(ftw_H1_i[10]),
        .I1(ftw_slip_i[10]),
        .O(\ftw_H1_o[11]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[11]_INST_0_i_9 
       (.I0(ftw_H1_i[9]),
        .I1(ftw_slip_i[9]),
        .O(\ftw_H1_o[11]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[12]_INST_0 
       (.I0(ftw_H1_o00_in[12]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[12]),
        .I4(ftw_H1_i[12]),
        .O(ftw_H1_o[12]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[13]_INST_0 
       (.I0(ftw_H1_o00_in[13]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[13]),
        .I4(ftw_H1_i[13]),
        .O(ftw_H1_o[13]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[14]_INST_0 
       (.I0(ftw_H1_o00_in[14]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[14]),
        .I4(ftw_H1_i[14]),
        .O(ftw_H1_o[14]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[15]_INST_0 
       (.I0(ftw_H1_o00_in[15]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[15]),
        .I4(ftw_H1_i[15]),
        .O(ftw_H1_o[15]));
  CARRY4 \ftw_H1_o[15]_INST_0_i_1 
       (.CI(\ftw_H1_o[11]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[15]_INST_0_i_1_n_0 ,\ftw_H1_o[15]_INST_0_i_1_n_1 ,\ftw_H1_o[15]_INST_0_i_1_n_2 ,\ftw_H1_o[15]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[15:12]),
        .O(ftw_H1_o00_in[15:12]),
        .S({\ftw_H1_o[15]_INST_0_i_3_n_0 ,\ftw_H1_o[15]_INST_0_i_4_n_0 ,\ftw_H1_o[15]_INST_0_i_5_n_0 ,\ftw_H1_o[15]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[15]_INST_0_i_10 
       (.I0(ftw_H1_i[12]),
        .I1(ftw_slip_i[12]),
        .O(\ftw_H1_o[15]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[15]_INST_0_i_2 
       (.CI(\ftw_H1_o[11]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[15]_INST_0_i_2_n_0 ,\ftw_H1_o[15]_INST_0_i_2_n_1 ,\ftw_H1_o[15]_INST_0_i_2_n_2 ,\ftw_H1_o[15]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[15:12]),
        .O(ftw_H1_o0[15:12]),
        .S({\ftw_H1_o[15]_INST_0_i_7_n_0 ,\ftw_H1_o[15]_INST_0_i_8_n_0 ,\ftw_H1_o[15]_INST_0_i_9_n_0 ,\ftw_H1_o[15]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[15]_INST_0_i_3 
       (.I0(ftw_slip_i[15]),
        .I1(ftw_H1_i[15]),
        .O(\ftw_H1_o[15]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[15]_INST_0_i_4 
       (.I0(ftw_slip_i[14]),
        .I1(ftw_H1_i[14]),
        .O(\ftw_H1_o[15]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[15]_INST_0_i_5 
       (.I0(ftw_slip_i[13]),
        .I1(ftw_H1_i[13]),
        .O(\ftw_H1_o[15]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[15]_INST_0_i_6 
       (.I0(ftw_slip_i[12]),
        .I1(ftw_H1_i[12]),
        .O(\ftw_H1_o[15]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[15]_INST_0_i_7 
       (.I0(ftw_H1_i[15]),
        .I1(ftw_slip_i[15]),
        .O(\ftw_H1_o[15]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[15]_INST_0_i_8 
       (.I0(ftw_H1_i[14]),
        .I1(ftw_slip_i[14]),
        .O(\ftw_H1_o[15]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[15]_INST_0_i_9 
       (.I0(ftw_H1_i[13]),
        .I1(ftw_slip_i[13]),
        .O(\ftw_H1_o[15]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[16]_INST_0 
       (.I0(ftw_H1_o00_in[16]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[16]),
        .I4(ftw_H1_i[16]),
        .O(ftw_H1_o[16]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[17]_INST_0 
       (.I0(ftw_H1_o00_in[17]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[17]),
        .I4(ftw_H1_i[17]),
        .O(ftw_H1_o[17]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[18]_INST_0 
       (.I0(ftw_H1_o00_in[18]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[18]),
        .I4(ftw_H1_i[18]),
        .O(ftw_H1_o[18]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[19]_INST_0 
       (.I0(ftw_H1_o00_in[19]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[19]),
        .I4(ftw_H1_i[19]),
        .O(ftw_H1_o[19]));
  CARRY4 \ftw_H1_o[19]_INST_0_i_1 
       (.CI(\ftw_H1_o[15]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[19]_INST_0_i_1_n_0 ,\ftw_H1_o[19]_INST_0_i_1_n_1 ,\ftw_H1_o[19]_INST_0_i_1_n_2 ,\ftw_H1_o[19]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[19:16]),
        .O(ftw_H1_o00_in[19:16]),
        .S({\ftw_H1_o[19]_INST_0_i_3_n_0 ,\ftw_H1_o[19]_INST_0_i_4_n_0 ,\ftw_H1_o[19]_INST_0_i_5_n_0 ,\ftw_H1_o[19]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[19]_INST_0_i_10 
       (.I0(ftw_H1_i[16]),
        .I1(ftw_slip_i[16]),
        .O(\ftw_H1_o[19]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[19]_INST_0_i_2 
       (.CI(\ftw_H1_o[15]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[19]_INST_0_i_2_n_0 ,\ftw_H1_o[19]_INST_0_i_2_n_1 ,\ftw_H1_o[19]_INST_0_i_2_n_2 ,\ftw_H1_o[19]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[19:16]),
        .O(ftw_H1_o0[19:16]),
        .S({\ftw_H1_o[19]_INST_0_i_7_n_0 ,\ftw_H1_o[19]_INST_0_i_8_n_0 ,\ftw_H1_o[19]_INST_0_i_9_n_0 ,\ftw_H1_o[19]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[19]_INST_0_i_3 
       (.I0(ftw_slip_i[19]),
        .I1(ftw_H1_i[19]),
        .O(\ftw_H1_o[19]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[19]_INST_0_i_4 
       (.I0(ftw_slip_i[18]),
        .I1(ftw_H1_i[18]),
        .O(\ftw_H1_o[19]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[19]_INST_0_i_5 
       (.I0(ftw_slip_i[17]),
        .I1(ftw_H1_i[17]),
        .O(\ftw_H1_o[19]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[19]_INST_0_i_6 
       (.I0(ftw_slip_i[16]),
        .I1(ftw_H1_i[16]),
        .O(\ftw_H1_o[19]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[19]_INST_0_i_7 
       (.I0(ftw_H1_i[19]),
        .I1(ftw_slip_i[19]),
        .O(\ftw_H1_o[19]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[19]_INST_0_i_8 
       (.I0(ftw_H1_i[18]),
        .I1(ftw_slip_i[18]),
        .O(\ftw_H1_o[19]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[19]_INST_0_i_9 
       (.I0(ftw_H1_i[17]),
        .I1(ftw_slip_i[17]),
        .O(\ftw_H1_o[19]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[1]_INST_0 
       (.I0(ftw_H1_o00_in[1]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[1]),
        .I4(ftw_H1_i[1]),
        .O(ftw_H1_o[1]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[20]_INST_0 
       (.I0(ftw_H1_o00_in[20]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[20]),
        .I4(ftw_H1_i[20]),
        .O(ftw_H1_o[20]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[21]_INST_0 
       (.I0(ftw_H1_o00_in[21]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[21]),
        .I4(ftw_H1_i[21]),
        .O(ftw_H1_o[21]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[22]_INST_0 
       (.I0(ftw_H1_o00_in[22]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[22]),
        .I4(ftw_H1_i[22]),
        .O(ftw_H1_o[22]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[23]_INST_0 
       (.I0(ftw_H1_o00_in[23]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[23]),
        .I4(ftw_H1_i[23]),
        .O(ftw_H1_o[23]));
  CARRY4 \ftw_H1_o[23]_INST_0_i_1 
       (.CI(\ftw_H1_o[19]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[23]_INST_0_i_1_n_0 ,\ftw_H1_o[23]_INST_0_i_1_n_1 ,\ftw_H1_o[23]_INST_0_i_1_n_2 ,\ftw_H1_o[23]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[23:20]),
        .O(ftw_H1_o00_in[23:20]),
        .S({\ftw_H1_o[23]_INST_0_i_3_n_0 ,\ftw_H1_o[23]_INST_0_i_4_n_0 ,\ftw_H1_o[23]_INST_0_i_5_n_0 ,\ftw_H1_o[23]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[23]_INST_0_i_10 
       (.I0(ftw_H1_i[20]),
        .I1(ftw_slip_i[20]),
        .O(\ftw_H1_o[23]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[23]_INST_0_i_2 
       (.CI(\ftw_H1_o[19]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[23]_INST_0_i_2_n_0 ,\ftw_H1_o[23]_INST_0_i_2_n_1 ,\ftw_H1_o[23]_INST_0_i_2_n_2 ,\ftw_H1_o[23]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[23:20]),
        .O(ftw_H1_o0[23:20]),
        .S({\ftw_H1_o[23]_INST_0_i_7_n_0 ,\ftw_H1_o[23]_INST_0_i_8_n_0 ,\ftw_H1_o[23]_INST_0_i_9_n_0 ,\ftw_H1_o[23]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[23]_INST_0_i_3 
       (.I0(ftw_slip_i[23]),
        .I1(ftw_H1_i[23]),
        .O(\ftw_H1_o[23]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[23]_INST_0_i_4 
       (.I0(ftw_slip_i[22]),
        .I1(ftw_H1_i[22]),
        .O(\ftw_H1_o[23]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[23]_INST_0_i_5 
       (.I0(ftw_slip_i[21]),
        .I1(ftw_H1_i[21]),
        .O(\ftw_H1_o[23]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[23]_INST_0_i_6 
       (.I0(ftw_slip_i[20]),
        .I1(ftw_H1_i[20]),
        .O(\ftw_H1_o[23]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[23]_INST_0_i_7 
       (.I0(ftw_H1_i[23]),
        .I1(ftw_slip_i[23]),
        .O(\ftw_H1_o[23]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[23]_INST_0_i_8 
       (.I0(ftw_H1_i[22]),
        .I1(ftw_slip_i[22]),
        .O(\ftw_H1_o[23]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[23]_INST_0_i_9 
       (.I0(ftw_H1_i[21]),
        .I1(ftw_slip_i[21]),
        .O(\ftw_H1_o[23]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[24]_INST_0 
       (.I0(ftw_H1_o00_in[24]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[24]),
        .I4(ftw_H1_i[24]),
        .O(ftw_H1_o[24]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[25]_INST_0 
       (.I0(ftw_H1_o00_in[25]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[25]),
        .I4(ftw_H1_i[25]),
        .O(ftw_H1_o[25]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[26]_INST_0 
       (.I0(ftw_H1_o00_in[26]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[26]),
        .I4(ftw_H1_i[26]),
        .O(ftw_H1_o[26]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[27]_INST_0 
       (.I0(ftw_H1_o00_in[27]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[27]),
        .I4(ftw_H1_i[27]),
        .O(ftw_H1_o[27]));
  CARRY4 \ftw_H1_o[27]_INST_0_i_1 
       (.CI(\ftw_H1_o[23]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[27]_INST_0_i_1_n_0 ,\ftw_H1_o[27]_INST_0_i_1_n_1 ,\ftw_H1_o[27]_INST_0_i_1_n_2 ,\ftw_H1_o[27]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[27:24]),
        .O(ftw_H1_o00_in[27:24]),
        .S({\ftw_H1_o[27]_INST_0_i_3_n_0 ,\ftw_H1_o[27]_INST_0_i_4_n_0 ,\ftw_H1_o[27]_INST_0_i_5_n_0 ,\ftw_H1_o[27]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[27]_INST_0_i_10 
       (.I0(ftw_H1_i[24]),
        .I1(ftw_slip_i[24]),
        .O(\ftw_H1_o[27]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[27]_INST_0_i_2 
       (.CI(\ftw_H1_o[23]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[27]_INST_0_i_2_n_0 ,\ftw_H1_o[27]_INST_0_i_2_n_1 ,\ftw_H1_o[27]_INST_0_i_2_n_2 ,\ftw_H1_o[27]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[27:24]),
        .O(ftw_H1_o0[27:24]),
        .S({\ftw_H1_o[27]_INST_0_i_7_n_0 ,\ftw_H1_o[27]_INST_0_i_8_n_0 ,\ftw_H1_o[27]_INST_0_i_9_n_0 ,\ftw_H1_o[27]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[27]_INST_0_i_3 
       (.I0(ftw_slip_i[27]),
        .I1(ftw_H1_i[27]),
        .O(\ftw_H1_o[27]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[27]_INST_0_i_4 
       (.I0(ftw_slip_i[26]),
        .I1(ftw_H1_i[26]),
        .O(\ftw_H1_o[27]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[27]_INST_0_i_5 
       (.I0(ftw_slip_i[25]),
        .I1(ftw_H1_i[25]),
        .O(\ftw_H1_o[27]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[27]_INST_0_i_6 
       (.I0(ftw_slip_i[24]),
        .I1(ftw_H1_i[24]),
        .O(\ftw_H1_o[27]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[27]_INST_0_i_7 
       (.I0(ftw_H1_i[27]),
        .I1(ftw_slip_i[27]),
        .O(\ftw_H1_o[27]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[27]_INST_0_i_8 
       (.I0(ftw_H1_i[26]),
        .I1(ftw_slip_i[26]),
        .O(\ftw_H1_o[27]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[27]_INST_0_i_9 
       (.I0(ftw_H1_i[25]),
        .I1(ftw_slip_i[25]),
        .O(\ftw_H1_o[27]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[28]_INST_0 
       (.I0(ftw_H1_o00_in[28]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[28]),
        .I4(ftw_H1_i[28]),
        .O(ftw_H1_o[28]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[29]_INST_0 
       (.I0(ftw_H1_o00_in[29]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[29]),
        .I4(ftw_H1_i[29]),
        .O(ftw_H1_o[29]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[2]_INST_0 
       (.I0(ftw_H1_o00_in[2]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[2]),
        .I4(ftw_H1_i[2]),
        .O(ftw_H1_o[2]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[30]_INST_0 
       (.I0(ftw_H1_o00_in[30]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[30]),
        .I4(ftw_H1_i[30]),
        .O(ftw_H1_o[30]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[31]_INST_0 
       (.I0(ftw_H1_o00_in[31]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[31]),
        .I4(ftw_H1_i[31]),
        .O(ftw_H1_o[31]));
  CARRY4 \ftw_H1_o[31]_INST_0_i_1 
       (.CI(\ftw_H1_o[27]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[31]_INST_0_i_1_n_0 ,\ftw_H1_o[31]_INST_0_i_1_n_1 ,\ftw_H1_o[31]_INST_0_i_1_n_2 ,\ftw_H1_o[31]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({ftw_slip_i[31],ftw_H1_i[30:28]}),
        .O(ftw_H1_o00_in[31:28]),
        .S({\ftw_H1_o[31]_INST_0_i_3_n_0 ,\ftw_H1_o[31]_INST_0_i_4_n_0 ,\ftw_H1_o[31]_INST_0_i_5_n_0 ,\ftw_H1_o[31]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[31]_INST_0_i_10 
       (.I0(ftw_H1_i[28]),
        .I1(ftw_slip_i[28]),
        .O(\ftw_H1_o[31]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[31]_INST_0_i_2 
       (.CI(\ftw_H1_o[27]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[31]_INST_0_i_2_n_0 ,\ftw_H1_o[31]_INST_0_i_2_n_1 ,\ftw_H1_o[31]_INST_0_i_2_n_2 ,\ftw_H1_o[31]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[31:28]),
        .O(ftw_H1_o0[31:28]),
        .S({\ftw_H1_o[31]_INST_0_i_7_n_0 ,\ftw_H1_o[31]_INST_0_i_8_n_0 ,\ftw_H1_o[31]_INST_0_i_9_n_0 ,\ftw_H1_o[31]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[31]_INST_0_i_3 
       (.I0(ftw_H1_i[31]),
        .I1(ftw_slip_i[31]),
        .O(\ftw_H1_o[31]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[31]_INST_0_i_4 
       (.I0(ftw_slip_i[30]),
        .I1(ftw_H1_i[30]),
        .O(\ftw_H1_o[31]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[31]_INST_0_i_5 
       (.I0(ftw_slip_i[29]),
        .I1(ftw_H1_i[29]),
        .O(\ftw_H1_o[31]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[31]_INST_0_i_6 
       (.I0(ftw_slip_i[28]),
        .I1(ftw_H1_i[28]),
        .O(\ftw_H1_o[31]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[31]_INST_0_i_7 
       (.I0(ftw_slip_i[31]),
        .I1(ftw_H1_i[31]),
        .O(\ftw_H1_o[31]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[31]_INST_0_i_8 
       (.I0(ftw_H1_i[30]),
        .I1(ftw_slip_i[30]),
        .O(\ftw_H1_o[31]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[31]_INST_0_i_9 
       (.I0(ftw_H1_i[29]),
        .I1(ftw_slip_i[29]),
        .O(\ftw_H1_o[31]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[32]_INST_0 
       (.I0(ftw_H1_o00_in[32]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[32]),
        .I4(ftw_H1_i[32]),
        .O(ftw_H1_o[32]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[33]_INST_0 
       (.I0(ftw_H1_o00_in[33]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[33]),
        .I4(ftw_H1_i[33]),
        .O(ftw_H1_o[33]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[34]_INST_0 
       (.I0(ftw_H1_o00_in[34]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[34]),
        .I4(ftw_H1_i[34]),
        .O(ftw_H1_o[34]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[35]_INST_0 
       (.I0(ftw_H1_o00_in[35]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[35]),
        .I4(ftw_H1_i[35]),
        .O(ftw_H1_o[35]));
  CARRY4 \ftw_H1_o[35]_INST_0_i_1 
       (.CI(\ftw_H1_o[31]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[35]_INST_0_i_1_n_0 ,\ftw_H1_o[35]_INST_0_i_1_n_1 ,\ftw_H1_o[35]_INST_0_i_1_n_2 ,\ftw_H1_o[35]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({ftw_H1_i[34:32],\ftw_H1_o[35]_INST_0_i_3_n_0 }),
        .O(ftw_H1_o00_in[35:32]),
        .S({\ftw_H1_o[35]_INST_0_i_4_n_0 ,\ftw_H1_o[35]_INST_0_i_5_n_0 ,\ftw_H1_o[35]_INST_0_i_6_n_0 ,\ftw_H1_o[35]_INST_0_i_7_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_10 
       (.I0(ftw_H1_i[32]),
        .I1(ftw_H1_i[33]),
        .O(\ftw_H1_o[35]_INST_0_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_11 
       (.I0(ftw_slip_i[31]),
        .I1(ftw_H1_i[32]),
        .O(\ftw_H1_o[35]_INST_0_i_11_n_0 ));
  CARRY4 \ftw_H1_o[35]_INST_0_i_2 
       (.CI(\ftw_H1_o[31]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[35]_INST_0_i_2_n_0 ,\ftw_H1_o[35]_INST_0_i_2_n_1 ,\ftw_H1_o[35]_INST_0_i_2_n_2 ,\ftw_H1_o[35]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({ftw_H1_i[34:32],ftw_slip_i[31]}),
        .O(ftw_H1_o0[35:32]),
        .S({\ftw_H1_o[35]_INST_0_i_8_n_0 ,\ftw_H1_o[35]_INST_0_i_9_n_0 ,\ftw_H1_o[35]_INST_0_i_10_n_0 ,\ftw_H1_o[35]_INST_0_i_11_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \ftw_H1_o[35]_INST_0_i_3 
       (.I0(ftw_slip_i[31]),
        .O(\ftw_H1_o[35]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_4 
       (.I0(ftw_H1_i[34]),
        .I1(ftw_H1_i[35]),
        .O(\ftw_H1_o[35]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_5 
       (.I0(ftw_H1_i[33]),
        .I1(ftw_H1_i[34]),
        .O(\ftw_H1_o[35]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_6 
       (.I0(ftw_H1_i[32]),
        .I1(ftw_H1_i[33]),
        .O(\ftw_H1_o[35]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[35]_INST_0_i_7 
       (.I0(ftw_H1_i[32]),
        .I1(ftw_slip_i[31]),
        .O(\ftw_H1_o[35]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_8 
       (.I0(ftw_H1_i[34]),
        .I1(ftw_H1_i[35]),
        .O(\ftw_H1_o[35]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[35]_INST_0_i_9 
       (.I0(ftw_H1_i[33]),
        .I1(ftw_H1_i[34]),
        .O(\ftw_H1_o[35]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[36]_INST_0 
       (.I0(ftw_H1_o00_in[36]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[36]),
        .I4(ftw_H1_i[36]),
        .O(ftw_H1_o[36]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[37]_INST_0 
       (.I0(ftw_H1_o00_in[37]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[37]),
        .I4(ftw_H1_i[37]),
        .O(ftw_H1_o[37]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[38]_INST_0 
       (.I0(ftw_H1_o00_in[38]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[38]),
        .I4(ftw_H1_i[38]),
        .O(ftw_H1_o[38]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[39]_INST_0 
       (.I0(ftw_H1_o00_in[39]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[39]),
        .I4(ftw_H1_i[39]),
        .O(ftw_H1_o[39]));
  CARRY4 \ftw_H1_o[39]_INST_0_i_1 
       (.CI(\ftw_H1_o[35]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[39]_INST_0_i_1_n_0 ,\ftw_H1_o[39]_INST_0_i_1_n_1 ,\ftw_H1_o[39]_INST_0_i_1_n_2 ,\ftw_H1_o[39]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[38:35]),
        .O(ftw_H1_o00_in[39:36]),
        .S({\ftw_H1_o[39]_INST_0_i_3_n_0 ,\ftw_H1_o[39]_INST_0_i_4_n_0 ,\ftw_H1_o[39]_INST_0_i_5_n_0 ,\ftw_H1_o[39]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_10 
       (.I0(ftw_H1_i[35]),
        .I1(ftw_H1_i[36]),
        .O(\ftw_H1_o[39]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[39]_INST_0_i_2 
       (.CI(\ftw_H1_o[35]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[39]_INST_0_i_2_n_0 ,\ftw_H1_o[39]_INST_0_i_2_n_1 ,\ftw_H1_o[39]_INST_0_i_2_n_2 ,\ftw_H1_o[39]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[38:35]),
        .O(ftw_H1_o0[39:36]),
        .S({\ftw_H1_o[39]_INST_0_i_7_n_0 ,\ftw_H1_o[39]_INST_0_i_8_n_0 ,\ftw_H1_o[39]_INST_0_i_9_n_0 ,\ftw_H1_o[39]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_3 
       (.I0(ftw_H1_i[38]),
        .I1(ftw_H1_i[39]),
        .O(\ftw_H1_o[39]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_4 
       (.I0(ftw_H1_i[37]),
        .I1(ftw_H1_i[38]),
        .O(\ftw_H1_o[39]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_5 
       (.I0(ftw_H1_i[36]),
        .I1(ftw_H1_i[37]),
        .O(\ftw_H1_o[39]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_6 
       (.I0(ftw_H1_i[35]),
        .I1(ftw_H1_i[36]),
        .O(\ftw_H1_o[39]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_7 
       (.I0(ftw_H1_i[38]),
        .I1(ftw_H1_i[39]),
        .O(\ftw_H1_o[39]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_8 
       (.I0(ftw_H1_i[37]),
        .I1(ftw_H1_i[38]),
        .O(\ftw_H1_o[39]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[39]_INST_0_i_9 
       (.I0(ftw_H1_i[36]),
        .I1(ftw_H1_i[37]),
        .O(\ftw_H1_o[39]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[3]_INST_0 
       (.I0(ftw_H1_o00_in[3]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[3]),
        .I4(ftw_H1_i[3]),
        .O(ftw_H1_o[3]));
  CARRY4 \ftw_H1_o[3]_INST_0_i_1 
       (.CI(\<const0> ),
        .CO({\ftw_H1_o[3]_INST_0_i_1_n_0 ,\ftw_H1_o[3]_INST_0_i_1_n_1 ,\ftw_H1_o[3]_INST_0_i_1_n_2 ,\ftw_H1_o[3]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[3:0]),
        .O(ftw_H1_o00_in[3:0]),
        .S({\ftw_H1_o[3]_INST_0_i_3_n_0 ,\ftw_H1_o[3]_INST_0_i_4_n_0 ,\ftw_H1_o[3]_INST_0_i_5_n_0 ,\ftw_H1_o[3]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[3]_INST_0_i_10 
       (.I0(ftw_H1_i[0]),
        .I1(ftw_slip_i[0]),
        .O(\ftw_H1_o[3]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[3]_INST_0_i_2 
       (.CI(\<const0> ),
        .CO({\ftw_H1_o[3]_INST_0_i_2_n_0 ,\ftw_H1_o[3]_INST_0_i_2_n_1 ,\ftw_H1_o[3]_INST_0_i_2_n_2 ,\ftw_H1_o[3]_INST_0_i_2_n_3 }),
        .CYINIT(\<const1> ),
        .DI(ftw_H1_i[3:0]),
        .O(ftw_H1_o0[3:0]),
        .S({\ftw_H1_o[3]_INST_0_i_7_n_0 ,\ftw_H1_o[3]_INST_0_i_8_n_0 ,\ftw_H1_o[3]_INST_0_i_9_n_0 ,\ftw_H1_o[3]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[3]_INST_0_i_3 
       (.I0(ftw_slip_i[3]),
        .I1(ftw_H1_i[3]),
        .O(\ftw_H1_o[3]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[3]_INST_0_i_4 
       (.I0(ftw_slip_i[2]),
        .I1(ftw_H1_i[2]),
        .O(\ftw_H1_o[3]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[3]_INST_0_i_5 
       (.I0(ftw_slip_i[1]),
        .I1(ftw_H1_i[1]),
        .O(\ftw_H1_o[3]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[3]_INST_0_i_6 
       (.I0(ftw_slip_i[0]),
        .I1(ftw_H1_i[0]),
        .O(\ftw_H1_o[3]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[3]_INST_0_i_7 
       (.I0(ftw_H1_i[3]),
        .I1(ftw_slip_i[3]),
        .O(\ftw_H1_o[3]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[3]_INST_0_i_8 
       (.I0(ftw_H1_i[2]),
        .I1(ftw_slip_i[2]),
        .O(\ftw_H1_o[3]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[3]_INST_0_i_9 
       (.I0(ftw_H1_i[1]),
        .I1(ftw_slip_i[1]),
        .O(\ftw_H1_o[3]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[40]_INST_0 
       (.I0(ftw_H1_o00_in[40]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[40]),
        .I4(ftw_H1_i[40]),
        .O(ftw_H1_o[40]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[41]_INST_0 
       (.I0(ftw_H1_o00_in[41]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[41]),
        .I4(ftw_H1_i[41]),
        .O(ftw_H1_o[41]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[42]_INST_0 
       (.I0(ftw_H1_o00_in[42]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[42]),
        .I4(ftw_H1_i[42]),
        .O(ftw_H1_o[42]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[43]_INST_0 
       (.I0(ftw_H1_o00_in[43]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[43]),
        .I4(ftw_H1_i[43]),
        .O(ftw_H1_o[43]));
  CARRY4 \ftw_H1_o[43]_INST_0_i_1 
       (.CI(\ftw_H1_o[39]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[43]_INST_0_i_1_n_0 ,\ftw_H1_o[43]_INST_0_i_1_n_1 ,\ftw_H1_o[43]_INST_0_i_1_n_2 ,\ftw_H1_o[43]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[42:39]),
        .O(ftw_H1_o00_in[43:40]),
        .S({\ftw_H1_o[43]_INST_0_i_3_n_0 ,\ftw_H1_o[43]_INST_0_i_4_n_0 ,\ftw_H1_o[43]_INST_0_i_5_n_0 ,\ftw_H1_o[43]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_10 
       (.I0(ftw_H1_i[39]),
        .I1(ftw_H1_i[40]),
        .O(\ftw_H1_o[43]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[43]_INST_0_i_2 
       (.CI(\ftw_H1_o[39]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[43]_INST_0_i_2_n_0 ,\ftw_H1_o[43]_INST_0_i_2_n_1 ,\ftw_H1_o[43]_INST_0_i_2_n_2 ,\ftw_H1_o[43]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[42:39]),
        .O(ftw_H1_o0[43:40]),
        .S({\ftw_H1_o[43]_INST_0_i_7_n_0 ,\ftw_H1_o[43]_INST_0_i_8_n_0 ,\ftw_H1_o[43]_INST_0_i_9_n_0 ,\ftw_H1_o[43]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_3 
       (.I0(ftw_H1_i[42]),
        .I1(ftw_H1_i[43]),
        .O(\ftw_H1_o[43]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_4 
       (.I0(ftw_H1_i[41]),
        .I1(ftw_H1_i[42]),
        .O(\ftw_H1_o[43]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_5 
       (.I0(ftw_H1_i[40]),
        .I1(ftw_H1_i[41]),
        .O(\ftw_H1_o[43]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_6 
       (.I0(ftw_H1_i[39]),
        .I1(ftw_H1_i[40]),
        .O(\ftw_H1_o[43]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_7 
       (.I0(ftw_H1_i[42]),
        .I1(ftw_H1_i[43]),
        .O(\ftw_H1_o[43]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_8 
       (.I0(ftw_H1_i[41]),
        .I1(ftw_H1_i[42]),
        .O(\ftw_H1_o[43]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[43]_INST_0_i_9 
       (.I0(ftw_H1_i[40]),
        .I1(ftw_H1_i[41]),
        .O(\ftw_H1_o[43]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[44]_INST_0 
       (.I0(ftw_H1_o00_in[44]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[44]),
        .I4(ftw_H1_i[44]),
        .O(ftw_H1_o[44]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[45]_INST_0 
       (.I0(ftw_H1_o00_in[45]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[45]),
        .I4(ftw_H1_i[45]),
        .O(ftw_H1_o[45]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[46]_INST_0 
       (.I0(ftw_H1_o00_in[46]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[46]),
        .I4(ftw_H1_i[46]),
        .O(ftw_H1_o[46]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[47]_INST_0 
       (.I0(ftw_H1_o00_in[47]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[47]),
        .I4(ftw_H1_i[47]),
        .O(ftw_H1_o[47]));
  CARRY4 \ftw_H1_o[47]_INST_0_i_1 
       (.CI(\ftw_H1_o[43]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[47]_INST_0_i_1_n_1 ,\ftw_H1_o[47]_INST_0_i_1_n_2 ,\ftw_H1_o[47]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,ftw_H1_i[45:43]}),
        .O(ftw_H1_o00_in[47:44]),
        .S({\ftw_H1_o[47]_INST_0_i_3_n_0 ,\ftw_H1_o[47]_INST_0_i_4_n_0 ,\ftw_H1_o[47]_INST_0_i_5_n_0 ,\ftw_H1_o[47]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_10 
       (.I0(ftw_H1_i[43]),
        .I1(ftw_H1_i[44]),
        .O(\ftw_H1_o[47]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[47]_INST_0_i_2 
       (.CI(\ftw_H1_o[43]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[47]_INST_0_i_2_n_1 ,\ftw_H1_o[47]_INST_0_i_2_n_2 ,\ftw_H1_o[47]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,ftw_H1_i[45:43]}),
        .O(ftw_H1_o0[47:44]),
        .S({\ftw_H1_o[47]_INST_0_i_7_n_0 ,\ftw_H1_o[47]_INST_0_i_8_n_0 ,\ftw_H1_o[47]_INST_0_i_9_n_0 ,\ftw_H1_o[47]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_3 
       (.I0(ftw_H1_i[46]),
        .I1(ftw_H1_i[47]),
        .O(\ftw_H1_o[47]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_4 
       (.I0(ftw_H1_i[45]),
        .I1(ftw_H1_i[46]),
        .O(\ftw_H1_o[47]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_5 
       (.I0(ftw_H1_i[44]),
        .I1(ftw_H1_i[45]),
        .O(\ftw_H1_o[47]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_6 
       (.I0(ftw_H1_i[43]),
        .I1(ftw_H1_i[44]),
        .O(\ftw_H1_o[47]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_7 
       (.I0(ftw_H1_i[46]),
        .I1(ftw_H1_i[47]),
        .O(\ftw_H1_o[47]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_8 
       (.I0(ftw_H1_i[45]),
        .I1(ftw_H1_i[46]),
        .O(\ftw_H1_o[47]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[47]_INST_0_i_9 
       (.I0(ftw_H1_i[44]),
        .I1(ftw_H1_i[45]),
        .O(\ftw_H1_o[47]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[4]_INST_0 
       (.I0(ftw_H1_o00_in[4]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[4]),
        .I4(ftw_H1_i[4]),
        .O(ftw_H1_o[4]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[5]_INST_0 
       (.I0(ftw_H1_o00_in[5]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[5]),
        .I4(ftw_H1_i[5]),
        .O(ftw_H1_o[5]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[6]_INST_0 
       (.I0(ftw_H1_o00_in[6]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[6]),
        .I4(ftw_H1_i[6]),
        .O(ftw_H1_o[6]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[7]_INST_0 
       (.I0(ftw_H1_o00_in[7]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[7]),
        .I4(ftw_H1_i[7]),
        .O(ftw_H1_o[7]));
  CARRY4 \ftw_H1_o[7]_INST_0_i_1 
       (.CI(\ftw_H1_o[3]_INST_0_i_1_n_0 ),
        .CO({\ftw_H1_o[7]_INST_0_i_1_n_0 ,\ftw_H1_o[7]_INST_0_i_1_n_1 ,\ftw_H1_o[7]_INST_0_i_1_n_2 ,\ftw_H1_o[7]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[7:4]),
        .O(ftw_H1_o00_in[7:4]),
        .S({\ftw_H1_o[7]_INST_0_i_3_n_0 ,\ftw_H1_o[7]_INST_0_i_4_n_0 ,\ftw_H1_o[7]_INST_0_i_5_n_0 ,\ftw_H1_o[7]_INST_0_i_6_n_0 }));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[7]_INST_0_i_10 
       (.I0(ftw_H1_i[4]),
        .I1(ftw_slip_i[4]),
        .O(\ftw_H1_o[7]_INST_0_i_10_n_0 ));
  CARRY4 \ftw_H1_o[7]_INST_0_i_2 
       (.CI(\ftw_H1_o[3]_INST_0_i_2_n_0 ),
        .CO({\ftw_H1_o[7]_INST_0_i_2_n_0 ,\ftw_H1_o[7]_INST_0_i_2_n_1 ,\ftw_H1_o[7]_INST_0_i_2_n_2 ,\ftw_H1_o[7]_INST_0_i_2_n_3 }),
        .CYINIT(\<const0> ),
        .DI(ftw_H1_i[7:4]),
        .O(ftw_H1_o0[7:4]),
        .S({\ftw_H1_o[7]_INST_0_i_7_n_0 ,\ftw_H1_o[7]_INST_0_i_8_n_0 ,\ftw_H1_o[7]_INST_0_i_9_n_0 ,\ftw_H1_o[7]_INST_0_i_10_n_0 }));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[7]_INST_0_i_3 
       (.I0(ftw_slip_i[7]),
        .I1(ftw_H1_i[7]),
        .O(\ftw_H1_o[7]_INST_0_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[7]_INST_0_i_4 
       (.I0(ftw_slip_i[6]),
        .I1(ftw_H1_i[6]),
        .O(\ftw_H1_o[7]_INST_0_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[7]_INST_0_i_5 
       (.I0(ftw_slip_i[5]),
        .I1(ftw_H1_i[5]),
        .O(\ftw_H1_o[7]_INST_0_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \ftw_H1_o[7]_INST_0_i_6 
       (.I0(ftw_slip_i[4]),
        .I1(ftw_H1_i[4]),
        .O(\ftw_H1_o[7]_INST_0_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[7]_INST_0_i_7 
       (.I0(ftw_H1_i[7]),
        .I1(ftw_slip_i[7]),
        .O(\ftw_H1_o[7]_INST_0_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[7]_INST_0_i_8 
       (.I0(ftw_H1_i[6]),
        .I1(ftw_slip_i[6]),
        .O(\ftw_H1_o[7]_INST_0_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \ftw_H1_o[7]_INST_0_i_9 
       (.I0(ftw_H1_i[5]),
        .I1(ftw_slip_i[5]),
        .O(\ftw_H1_o[7]_INST_0_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[8]_INST_0 
       (.I0(ftw_H1_o00_in[8]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[8]),
        .I4(ftw_H1_i[8]),
        .O(ftw_H1_o[8]));
  LUT5 #(
    .INIT(32'hFB3BC808)) 
    \ftw_H1_o[9]_INST_0 
       (.I0(ftw_H1_o00_in[9]),
        .I1(slip_enable_i),
        .I2(slip_sign_i),
        .I3(ftw_H1_o0[9]),
        .I4(ftw_H1_i[9]),
        .O(ftw_H1_o[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_mux_soflLoad_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_mux_soflLoad_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_mux_soflLoad_0
   (A,
    B,
    C,
    sel);
  input [0:0]A;
  input [0:0]B;
  output [0:0]C;
  input sel;

  wire [0:0]A;
  wire [0:0]B;
  wire [0:0]C;
  wire sel;

  LUT3 #(
    .INIT(8'hB8)) 
    \C[0]_INST_0 
       (.I0(A),
        .I1(sel),
        .I2(B),
        .O(C));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_not_rst_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_not_rst_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=not,C_SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
module RFNCO_cmp_not_rst_0
   (Op1,
    Res);
  input [0:0]Op1;
  output [0:0]Res;

  wire [0:0]Op1;
  wire [0:0]Res;

  LUT1 #(
    .INIT(2'h1)) 
    \Res[0]_INST_0 
       (.I0(Op1),
        .O(Res));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_offset_FSK_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_offset_FSK_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_offset_FSK_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_offset_FSK_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_offset_FSK_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_offset_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_offset_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_offset_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_offset_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_offset_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_or_reset_FSK_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_or_reset_FSK_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
module RFNCO_cmp_or_master_reset_0
   (Op1,
    Op2,
    Res);
  input [0:0]Op1;
  input [0:0]Op2;
  output [0:0]Res;

  wire [0:0]Op1;
  wire [0:0]Op2;
  wire [0:0]Res;

  LUT2 #(
    .INIT(4'hE)) 
    \Res[0]_INST_0 
       (.I0(Op1),
        .I1(Op2),
        .O(Res));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_or_reset_FSK_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_or_reset_FSK_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
module RFNCO_cmp_or_reset_FSK_0
   (Op1,
    Op2,
    Res);
  input [0:0]Op1;
  input [0:0]Op2;
  output [0:0]Res;

  wire [0:0]Op1;
  wire [0:0]Op2;
  wire [0:0]Res;

  LUT2 #(
    .INIT(4'hE)) 
    \Res[0]_INST_0 
       (.I0(Op1),
        .I1(Op2),
        .O(Res));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_or_reset_FSK_0,util_vector_logic_v2_0_1_util_vector_logic,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_or_reset_FSK_0,util_vector_logic_v2_0_1_util_vector_logic,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=or,C_SIZE=1}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
module RFNCO_cmp_or_reset_slip_0
   (Op1,
    Op2,
    Res);
  input [0:0]Op1;
  input [0:0]Op2;
  output [0:0]Res;

  wire [0:0]Op1;
  wire [0:0]Op2;
  wire [0:0]Res;

  LUT2 #(
    .INIT(4'hE)) 
    \Res[0]_INST_0 
       (.I0(Op1),
        .I1(Op2),
        .O(Res));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_rate_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_rate_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=3}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_rate_mux_0
   (A,
    B,
    C,
    sel);
  input [2:0]A;
  input [2:0]B;
  output [2:0]C;
  input sel;

  wire [2:0]A;
  wire [2:0]B;
  wire [2:0]C;
  wire sel;

  RFNCO_cmp_rate_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_rate_mux_0_generic_mux
   (C,
    A,
    sel,
    B);
  output [2:0]C;
  input [2:0]A;
  input sel;
  input [2:0]B;

  wire [2:0]A;
  wire [2:0]B;
  wire [2:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(sel),
        .I2(B[0]),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(sel),
        .I2(B[1]),
        .O(C[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(sel),
        .I2(B[2]),
        .O(C[2]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_rfnco_regs_0,rfnco_regs,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_rfnco_regs_0,rfnco_regs,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=rfnco_regs,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "rfnco_regs,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_rfnco_regs_0
   (aclk,
    areset_n,
    awvalid,
    awready,
    awaddr,
    awprot,
    wvalid,
    wready,
    wdata,
    wstrb,
    bvalid,
    bready,
    bresp,
    arvalid,
    arready,
    araddr,
    arprot,
    rvalid,
    rready,
    rdata,
    rresp,
    ipInfo_ident_i,
    ipInfo_firmwareVersion_i,
    ipInfo_memMapVersion_i,
    ipInfo_echo_echo_o,
    control_reset_o,
    control_softLoad_o,
    control_selFtwLo0_o,
    control_selFtwLo1_o,
    control_selOffsetH1_o,
    control_selOffsetFskH1_o,
    control_selRate_o,
    control_selFtwH1_o,
    control_selFtwH1On_o,
    control_selWrFtwH1_o,
    control_selWrDftwH1slip_o,
    control_selDftwH1slip_o,
    control_selFtwH1prog_o,
    control_slipSign_o,
    control_enableFSK_o,
    control_resetFSK_o,
    control_enableSlip_o,
    control_resetSlip_o,
    control_signIF0_o,
    control_signIF1_o,
    control_extResetEnable_o,
    control_latchPhases_o,
    control_selLoad_o,
    control_enableFreqDoubling_o,
    control_forceAM_o,
    status_interlock_i,
    status_phaseH1Vld_i,
    status_amAutoOn_i,
    ftw_h1_reg_o,
    ftw_h1Prog_reg_o,
    ftw_on_reg_o,
    ftw_lo0_reg_o,
    ftw_lo1_reg_o,
    ftw_slip_o,
    inputs_offsetH1_reg_o,
    inputs_rate_o,
    inputs_h_o,
    inputs_offsetFSK_reg_o,
    inputs_offsetAM_reg_o,
    inputs_pulseLengthAM_reg_o,
    inputs_delayComp_o,
    phases_h1_reg_i,
    phases_h1Main_reg_i,
    phases_h1Slip_reg_i,
    phases_if0_reg_i,
    phases_if1_reg_i,
    presentLatch_frev_i,
    presentLatch_am_i,
    presentLatch_tw_i,
    presentLatch_coef_i,
    presentLatch_load_i,
    presentLatch_extReset_i,
    readback_coef_i,
    readback_tw_i,
    readback_phaseH1Comp_reg_i);
  (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 aclk CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME aclk, ASSOCIATED_BUSIF slave, FREQ_HZ 125000000, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i" *) input aclk;
  input areset_n;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave AWVALID" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME slave, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 125000000, ID_WIDTH 0, ADDR_WIDTH 12, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN RFNCO_clk_i, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input awvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave AWREADY" *) output awready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave AWADDR" *) input [11:0]awaddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave AWPROT" *) input [2:0]awprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave WVALID" *) input wvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave WREADY" *) output wready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave WDATA" *) input [31:0]wdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave WSTRB" *) input [3:0]wstrb;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave BVALID" *) output bvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave BREADY" *) input bready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave BRESP" *) output [1:0]bresp;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave ARVALID" *) input arvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave ARREADY" *) output arready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave ARADDR" *) input [11:0]araddr;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave ARPROT" *) input [2:0]arprot;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave RVALID" *) output rvalid;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave RREADY" *) input rready;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave RDATA" *) output [31:0]rdata;
  (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 slave RRESP" *) output [1:0]rresp;
  input [31:0]ipInfo_ident_i;
  input [31:0]ipInfo_firmwareVersion_i;
  input [31:0]ipInfo_memMapVersion_i;
  output [7:0]ipInfo_echo_echo_o;
  output control_reset_o;
  output control_softLoad_o;
  output control_selFtwLo0_o;
  output control_selFtwLo1_o;
  output control_selOffsetH1_o;
  output control_selOffsetFskH1_o;
  output control_selRate_o;
  output control_selFtwH1_o;
  output control_selFtwH1On_o;
  output control_selWrFtwH1_o;
  output control_selWrDftwH1slip_o;
  output control_selDftwH1slip_o;
  output control_selFtwH1prog_o;
  output control_slipSign_o;
  output control_enableFSK_o;
  output control_resetFSK_o;
  output control_enableSlip_o;
  output control_resetSlip_o;
  output control_signIF0_o;
  output control_signIF1_o;
  output control_extResetEnable_o;
  output control_latchPhases_o;
  output control_selLoad_o;
  output control_enableFreqDoubling_o;
  output control_forceAM_o;
  input status_interlock_i;
  input status_phaseH1Vld_i;
  input status_amAutoOn_i;
  output [47:0]ftw_h1_reg_o;
  output [47:0]ftw_h1Prog_reg_o;
  output [47:0]ftw_on_reg_o;
  output [47:0]ftw_lo0_reg_o;
  output [47:0]ftw_lo1_reg_o;
  output [31:0]ftw_slip_o;
  output [47:0]inputs_offsetH1_reg_o;
  output [31:0]inputs_rate_o;
  output [15:0]inputs_h_o;
  output [47:0]inputs_offsetFSK_reg_o;
  output [47:0]inputs_offsetAM_reg_o;
  output [47:0]inputs_pulseLengthAM_reg_o;
  output [31:0]inputs_delayComp_o;
  input [47:0]phases_h1_reg_i;
  input [47:0]phases_h1Main_reg_i;
  input [47:0]phases_h1Slip_reg_i;
  input [47:0]phases_if0_reg_i;
  input [47:0]phases_if1_reg_i;
  input presentLatch_frev_i;
  input presentLatch_am_i;
  input presentLatch_tw_i;
  input presentLatch_coef_i;
  input presentLatch_load_i;
  input presentLatch_extReset_i;
  input [31:0]readback_coef_i;
  input [31:0]readback_tw_i;
  input [47:0]readback_phaseH1Comp_reg_i;

  wire \<const0> ;
  wire aclk;
  wire [11:0]araddr;
  wire areset_n;
  wire arready;
  wire arvalid;
  wire [11:0]awaddr;
  wire awready;
  wire awvalid;
  wire bready;
  wire bvalid;
  wire control_enableFSK_o;
  wire control_enableFreqDoubling_o;
  wire control_enableSlip_o;
  wire control_extResetEnable_o;
  wire control_forceAM_o;
  wire control_latchPhases_o;
  wire control_resetFSK_o;
  wire control_resetSlip_o;
  wire control_reset_o;
  wire control_selDftwH1slip_o;
  wire control_selFtwH1On_o;
  wire control_selFtwH1_o;
  wire control_selFtwH1prog_o;
  wire control_selFtwLo0_o;
  wire control_selFtwLo1_o;
  wire control_selLoad_o;
  wire control_selOffsetFskH1_o;
  wire control_selOffsetH1_o;
  wire control_selRate_o;
  wire control_selWrDftwH1slip_o;
  wire control_selWrFtwH1_o;
  wire control_signIF0_o;
  wire control_signIF1_o;
  wire control_slipSign_o;
  wire control_softLoad_o;
  wire [47:0]ftw_h1Prog_reg_o;
  wire [47:0]ftw_h1_reg_o;
  wire [47:0]ftw_lo0_reg_o;
  wire [47:0]ftw_lo1_reg_o;
  wire [47:0]ftw_on_reg_o;
  wire [31:0]ftw_slip_o;
  wire [31:0]inputs_delayComp_o;
  wire [15:0]inputs_h_o;
  wire [47:0]inputs_offsetAM_reg_o;
  wire [47:0]inputs_offsetFSK_reg_o;
  wire [47:0]inputs_offsetH1_reg_o;
  wire [47:0]inputs_pulseLengthAM_reg_o;
  wire [31:0]inputs_rate_o;
  wire [7:0]ipInfo_echo_echo_o;
  wire [31:0]ipInfo_firmwareVersion_i;
  wire [31:0]ipInfo_ident_i;
  wire [31:0]ipInfo_memMapVersion_i;
  wire [47:0]phases_h1Main_reg_i;
  wire [47:0]phases_h1Slip_reg_i;
  wire [47:0]phases_h1_reg_i;
  wire [47:0]phases_if0_reg_i;
  wire [47:0]phases_if1_reg_i;
  wire presentLatch_am_i;
  wire presentLatch_coef_i;
  wire presentLatch_extReset_i;
  wire presentLatch_frev_i;
  wire presentLatch_load_i;
  wire presentLatch_tw_i;
  wire [31:0]rdata;
  wire [31:0]readback_coef_i;
  wire [47:0]readback_phaseH1Comp_reg_i;
  wire [31:0]readback_tw_i;
  wire rready;
  wire rvalid;
  wire status_amAutoOn_i;
  wire status_interlock_i;
  wire status_phaseH1Vld_i;
  wire [31:0]wdata;
  wire wready;
  wire wvalid;

  assign bresp[1] = \<const0> ;
  assign bresp[0] = \<const0> ;
  assign rresp[1] = \<const0> ;
  assign rresp[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  RFNCO_cmp_rfnco_regs_0_rfnco_regs U0
       (.aclk(aclk),
        .araddr(araddr[9:2]),
        .areset_n(areset_n),
        .arready(arready),
        .arvalid(arvalid),
        .awaddr(awaddr[11:2]),
        .awready(awready),
        .awvalid(awvalid),
        .bready(bready),
        .bvalid(bvalid),
        .control_enableFSK_o(control_enableFSK_o),
        .control_enableFreqDoubling_o(control_enableFreqDoubling_o),
        .control_enableSlip_o(control_enableSlip_o),
        .control_extResetEnable_o(control_extResetEnable_o),
        .control_forceAM_o(control_forceAM_o),
        .control_latchPhases_o(control_latchPhases_o),
        .control_resetFSK_o(control_resetFSK_o),
        .control_resetSlip_o(control_resetSlip_o),
        .control_reset_o(control_reset_o),
        .control_selDftwH1slip_o(control_selDftwH1slip_o),
        .control_selFtwH1On_o(control_selFtwH1On_o),
        .control_selFtwH1_o(control_selFtwH1_o),
        .control_selFtwH1prog_o(control_selFtwH1prog_o),
        .control_selFtwLo0_o(control_selFtwLo0_o),
        .control_selFtwLo1_o(control_selFtwLo1_o),
        .control_selLoad_o(control_selLoad_o),
        .control_selOffsetFskH1_o(control_selOffsetFskH1_o),
        .control_selOffsetH1_o(control_selOffsetH1_o),
        .control_selRate_o(control_selRate_o),
        .control_selWrDftwH1slip_o(control_selWrDftwH1slip_o),
        .control_selWrFtwH1_o(control_selWrFtwH1_o),
        .control_signIF0_o(control_signIF0_o),
        .control_signIF1_o(control_signIF1_o),
        .control_slipSign_o(control_slipSign_o),
        .control_softLoad_o(control_softLoad_o),
        .ftw_h1Prog_reg_o(ftw_h1Prog_reg_o),
        .ftw_h1_reg_o(ftw_h1_reg_o),
        .ftw_lo0_reg_o(ftw_lo0_reg_o),
        .ftw_lo1_reg_o(ftw_lo1_reg_o),
        .ftw_on_reg_o(ftw_on_reg_o),
        .ftw_slip_o(ftw_slip_o),
        .inputs_delayComp_o(inputs_delayComp_o),
        .inputs_h_o(inputs_h_o),
        .inputs_offsetAM_reg_o(inputs_offsetAM_reg_o),
        .inputs_offsetFSK_reg_o(inputs_offsetFSK_reg_o),
        .inputs_offsetH1_reg_o(inputs_offsetH1_reg_o),
        .inputs_pulseLengthAM_reg_o(inputs_pulseLengthAM_reg_o),
        .inputs_rate_o(inputs_rate_o),
        .ipInfo_echo_echo_o(ipInfo_echo_echo_o),
        .ipInfo_firmwareVersion_i(ipInfo_firmwareVersion_i[23:0]),
        .ipInfo_ident_i(ipInfo_ident_i),
        .ipInfo_memMapVersion_i(ipInfo_memMapVersion_i[23:0]),
        .phases_h1Main_reg_i(phases_h1Main_reg_i),
        .phases_h1Slip_reg_i(phases_h1Slip_reg_i),
        .phases_h1_reg_i(phases_h1_reg_i),
        .phases_if0_reg_i(phases_if0_reg_i),
        .phases_if1_reg_i(phases_if1_reg_i),
        .presentLatch_am_i(presentLatch_am_i),
        .presentLatch_coef_i(presentLatch_coef_i),
        .presentLatch_extReset_i(presentLatch_extReset_i),
        .presentLatch_frev_i(presentLatch_frev_i),
        .presentLatch_load_i(presentLatch_load_i),
        .presentLatch_tw_i(presentLatch_tw_i),
        .rdata(rdata),
        .readback_coef_i(readback_coef_i),
        .readback_phaseH1Comp_reg_i(readback_phaseH1Comp_reg_i),
        .readback_tw_i(readback_tw_i),
        .rready(rready),
        .rvalid(rvalid),
        .status_amAutoOn_i(status_amAutoOn_i),
        .status_interlock_i(status_interlock_i),
        .status_phaseH1Vld_i(status_phaseH1Vld_i),
        .wdata(wdata),
        .wready(wready),
        .wvalid(wvalid));
endmodule

(* ORIG_REF_NAME = "rfnco_regs" *) 
module RFNCO_cmp_rfnco_regs_0_rfnco_regs
   (ipInfo_echo_echo_o,
    control_reset_o,
    control_selFtwLo0_o,
    control_selFtwLo1_o,
    control_selOffsetH1_o,
    control_selOffsetFskH1_o,
    control_selRate_o,
    control_selFtwH1_o,
    control_selFtwH1On_o,
    control_selWrFtwH1_o,
    control_selWrDftwH1slip_o,
    control_selDftwH1slip_o,
    control_selFtwH1prog_o,
    control_slipSign_o,
    control_enableFSK_o,
    control_enableSlip_o,
    control_signIF0_o,
    control_signIF1_o,
    control_extResetEnable_o,
    control_selLoad_o,
    control_enableFreqDoubling_o,
    control_forceAM_o,
    ftw_h1_reg_o,
    ftw_h1Prog_reg_o,
    ftw_on_reg_o,
    ftw_lo0_reg_o,
    ftw_lo1_reg_o,
    ftw_slip_o,
    inputs_offsetH1_reg_o,
    inputs_h_o,
    inputs_rate_o,
    inputs_offsetFSK_reg_o,
    inputs_offsetAM_reg_o,
    inputs_pulseLengthAM_reg_o,
    inputs_delayComp_o,
    rdata,
    control_softLoad_o,
    control_resetFSK_o,
    control_resetSlip_o,
    control_latchPhases_o,
    rvalid,
    awready,
    wready,
    arready,
    bvalid,
    areset_n,
    ipInfo_ident_i,
    ipInfo_firmwareVersion_i,
    ipInfo_memMapVersion_i,
    phases_if1_reg_i,
    awaddr,
    aclk,
    wdata,
    araddr,
    wvalid,
    awvalid,
    arvalid,
    rready,
    presentLatch_frev_i,
    presentLatch_am_i,
    presentLatch_tw_i,
    presentLatch_coef_i,
    presentLatch_load_i,
    presentLatch_extReset_i,
    status_interlock_i,
    status_phaseH1Vld_i,
    status_amAutoOn_i,
    phases_h1Main_reg_i,
    phases_h1_reg_i,
    phases_if0_reg_i,
    phases_h1Slip_reg_i,
    readback_phaseH1Comp_reg_i,
    readback_tw_i,
    readback_coef_i,
    bready);
  output [7:0]ipInfo_echo_echo_o;
  output control_reset_o;
  output control_selFtwLo0_o;
  output control_selFtwLo1_o;
  output control_selOffsetH1_o;
  output control_selOffsetFskH1_o;
  output control_selRate_o;
  output control_selFtwH1_o;
  output control_selFtwH1On_o;
  output control_selWrFtwH1_o;
  output control_selWrDftwH1slip_o;
  output control_selDftwH1slip_o;
  output control_selFtwH1prog_o;
  output control_slipSign_o;
  output control_enableFSK_o;
  output control_enableSlip_o;
  output control_signIF0_o;
  output control_signIF1_o;
  output control_extResetEnable_o;
  output control_selLoad_o;
  output control_enableFreqDoubling_o;
  output control_forceAM_o;
  output [47:0]ftw_h1_reg_o;
  output [47:0]ftw_h1Prog_reg_o;
  output [47:0]ftw_on_reg_o;
  output [47:0]ftw_lo0_reg_o;
  output [47:0]ftw_lo1_reg_o;
  output [31:0]ftw_slip_o;
  output [47:0]inputs_offsetH1_reg_o;
  output [15:0]inputs_h_o;
  output [31:0]inputs_rate_o;
  output [47:0]inputs_offsetFSK_reg_o;
  output [47:0]inputs_offsetAM_reg_o;
  output [47:0]inputs_pulseLengthAM_reg_o;
  output [31:0]inputs_delayComp_o;
  output [31:0]rdata;
  output control_softLoad_o;
  output control_resetFSK_o;
  output control_resetSlip_o;
  output control_latchPhases_o;
  output rvalid;
  output awready;
  output wready;
  output arready;
  output bvalid;
  input areset_n;
  input [31:0]ipInfo_ident_i;
  input [23:0]ipInfo_firmwareVersion_i;
  input [23:0]ipInfo_memMapVersion_i;
  input [47:0]phases_if1_reg_i;
  input [9:0]awaddr;
  input aclk;
  input [31:0]wdata;
  input [7:0]araddr;
  input wvalid;
  input awvalid;
  input arvalid;
  input rready;
  input presentLatch_frev_i;
  input presentLatch_am_i;
  input presentLatch_tw_i;
  input presentLatch_coef_i;
  input presentLatch_load_i;
  input presentLatch_extReset_i;
  input status_interlock_i;
  input status_phaseH1Vld_i;
  input status_amAutoOn_i;
  input [47:0]phases_h1Main_reg_i;
  input [47:0]phases_h1_reg_i;
  input [47:0]phases_if0_reg_i;
  input [47:0]phases_h1Slip_reg_i;
  input [47:0]readback_phaseH1Comp_reg_i;
  input [31:0]readback_tw_i;
  input [31:0]readback_coef_i;
  input bready;

  wire \<const0> ;
  wire \<const1> ;
  wire aclk;
  wire [7:0]araddr;
  wire areset_n;
  wire arready;
  wire arvalid;
  wire [9:0]awaddr;
  wire awready;
  wire awvalid;
  wire axi_arset;
  wire axi_arset_i_1_n_0;
  wire axi_awset;
  wire axi_awset_i_1_n_0;
  wire axi_rdone_i_1_n_0;
  wire axi_wdone_i_10_n_0;
  wire axi_wdone_i_11_n_0;
  wire axi_wdone_i_12_n_0;
  wire axi_wdone_i_13_n_0;
  wire axi_wdone_i_14_n_0;
  wire axi_wdone_i_15_n_0;
  wire axi_wdone_i_16_n_0;
  wire axi_wdone_i_17_n_0;
  wire axi_wdone_i_18_n_0;
  wire axi_wdone_i_19_n_0;
  wire axi_wdone_i_1_n_0;
  wire axi_wdone_i_20_n_0;
  wire axi_wdone_i_21_n_0;
  wire axi_wdone_i_22_n_0;
  wire axi_wdone_i_23_n_0;
  wire axi_wdone_i_24_n_0;
  wire axi_wdone_i_2_n_0;
  wire axi_wdone_i_4_n_0;
  wire axi_wdone_i_5_n_0;
  wire axi_wdone_i_6_n_0;
  wire axi_wdone_i_7_n_0;
  wire axi_wdone_i_8_n_0;
  wire axi_wdone_i_9_n_0;
  wire axi_wset_i_1_n_0;
  wire axi_wset_reg_n_0;
  wire bready;
  wire bvalid;
  wire control_enableFSK_o;
  wire control_enableFreqDoubling_o;
  wire control_enableSlip_o;
  wire control_extResetEnable_o;
  wire control_forceAM_o;
  wire control_latchPhases_o;
  wire control_resetFSK_o;
  wire control_resetSlip_o;
  wire control_reset_o;
  wire control_reset_reg_i_1_n_0;
  wire control_reset_reg_i_2_n_0;
  wire control_reset_reg_i_3_n_0;
  wire control_reset_reg_i_4_n_0;
  wire control_selDftwH1slip_o;
  wire control_selFtwH1On_o;
  wire control_selFtwH1_o;
  wire control_selFtwH1prog_o;
  wire control_selFtwLo0_o;
  wire control_selFtwLo1_o;
  wire control_selLoad_o;
  wire control_selOffsetFskH1_o;
  wire control_selOffsetH1_o;
  wire control_selRate_o;
  wire control_selWrDftwH1slip_o;
  wire control_selWrFtwH1_o;
  wire control_signIF0_o;
  wire control_signIF1_o;
  wire control_slipSign_o;
  wire control_softLoad_o;
  wire control_softLoad_reg_i_1_n_0;
  wire control_wack;
  wire [31:16]data22;
  wire [47:0]ftw_h1Prog_reg_o;
  wire \ftw_h1Prog_reg_reg[31]_i_1_n_0 ;
  wire \ftw_h1Prog_reg_reg[31]_i_2_n_0 ;
  wire \ftw_h1Prog_reg_reg[47]_i_1_n_0 ;
  wire \ftw_h1Prog_reg_reg[47]_i_2_n_0 ;
  wire \ftw_h1Prog_reg_reg[47]_i_3_n_0 ;
  wire [1:0]ftw_h1Prog_wack;
  wire [47:0]ftw_h1_reg_o;
  wire \ftw_h1_reg_reg[31]_i_1_n_0 ;
  wire \ftw_h1_reg_reg[31]_i_2_n_0 ;
  wire \ftw_h1_reg_reg[47]_i_1_n_0 ;
  wire \ftw_h1_reg_reg[47]_i_2_n_0 ;
  wire \ftw_h1_reg_reg[47]_i_3_n_0 ;
  wire [1:0]ftw_h1_wack;
  wire [47:0]ftw_lo0_reg_o;
  wire \ftw_lo0_reg_reg[31]_i_1_n_0 ;
  wire \ftw_lo0_reg_reg[47]_i_1_n_0 ;
  wire \ftw_lo0_reg_reg[47]_i_2_n_0 ;
  wire \ftw_lo0_reg_reg[47]_i_3_n_0 ;
  wire [1:0]ftw_lo0_wack;
  wire [47:0]ftw_lo1_reg_o;
  wire \ftw_lo1_reg_reg[31]_i_1_n_0 ;
  wire \ftw_lo1_reg_reg[47]_i_1_n_0 ;
  wire [1:0]ftw_lo1_wack;
  wire [47:0]ftw_on_reg_o;
  wire \ftw_on_reg_reg[31]_i_1_n_0 ;
  wire \ftw_on_reg_reg[47]_i_1_n_0 ;
  wire \ftw_on_reg_reg[47]_i_2_n_0 ;
  wire [1:0]ftw_on_wack;
  wire [31:0]ftw_slip_o;
  wire \ftw_slip_reg[31]_i_1_n_0 ;
  wire \ftw_slip_reg[31]_i_2_n_0 ;
  wire \ftw_slip_reg[31]_i_3_n_0 ;
  wire ftw_slip_wack;
  wire [31:0]inputs_delayComp_o;
  wire \inputs_delayComp_reg[31]_i_1_n_0 ;
  wire \inputs_delayComp_reg[31]_i_2_n_0 ;
  wire inputs_delayComp_wack;
  wire [15:0]inputs_h_o;
  wire \inputs_h_reg[15]_i_1_n_0 ;
  wire inputs_h_wack;
  wire [47:0]inputs_offsetAM_reg_o;
  wire \inputs_offsetAM_reg_reg[31]_i_1_n_0 ;
  wire \inputs_offsetAM_reg_reg[47]_i_1_n_0 ;
  wire \inputs_offsetAM_reg_reg[47]_i_2_n_0 ;
  wire [1:0]inputs_offsetAM_wack;
  wire [47:0]inputs_offsetFSK_reg_o;
  wire \inputs_offsetFSK_reg_reg[31]_i_1_n_0 ;
  wire \inputs_offsetFSK_reg_reg[47]_i_1_n_0 ;
  wire \inputs_offsetFSK_reg_reg[47]_i_2_n_0 ;
  wire [1:0]inputs_offsetFSK_wack;
  wire [47:0]inputs_offsetH1_reg_o;
  wire \inputs_offsetH1_reg_reg[31]_i_1_n_0 ;
  wire \inputs_offsetH1_reg_reg[47]_i_1_n_0 ;
  wire \inputs_offsetH1_reg_reg[47]_i_2_n_0 ;
  wire [1:0]inputs_offsetH1_wack;
  wire [47:0]inputs_pulseLengthAM_reg_o;
  wire \inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ;
  wire \inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ;
  wire [1:0]inputs_pulseLengthAM_wack;
  wire [31:0]inputs_rate_o;
  wire \inputs_rate_reg[31]_i_1_n_0 ;
  wire \inputs_rate_reg[31]_i_2_n_0 ;
  wire inputs_rate_wack;
  wire [7:0]ipInfo_echo_echo_o;
  wire \ipInfo_echo_echo_reg[7]_i_1_n_0 ;
  wire \ipInfo_echo_echo_reg[7]_i_2_n_0 ;
  wire \ipInfo_echo_echo_reg[7]_i_3_n_0 ;
  wire ipInfo_echo_wack;
  wire [23:0]ipInfo_firmwareVersion_i;
  wire [31:0]ipInfo_ident_i;
  wire [23:0]ipInfo_memMapVersion_i;
  wire p_0_in;
  wire [5:0]p_1_in;
  wire p_2_in;
  wire [47:0]phases_h1Main_reg_i;
  wire [47:0]phases_h1Slip_reg_i;
  wire [47:0]phases_h1_reg_i;
  wire [47:0]phases_if0_reg_i;
  wire [47:0]phases_if1_reg_i;
  wire presentLatch_am_i;
  wire presentLatch_am_reg_i_1_n_0;
  wire presentLatch_coef_i;
  wire presentLatch_coef_reg_i_1_n_0;
  wire presentLatch_extReset_i;
  wire presentLatch_extReset_reg_i_1_n_0;
  wire presentLatch_frev_i;
  wire presentLatch_frev_reg_i_1_n_0;
  wire presentLatch_load_i;
  wire presentLatch_load_reg_i_1_n_0;
  wire presentLatch_tw_i;
  wire presentLatch_tw_reg_i_1_n_0;
  wire presentLatch_wack;
  wire presentLatch_wack_i_1_n_0;
  wire presentLatch_wack_i_2_n_0;
  wire rd_ack;
  wire rd_addr;
  wire \rd_addr_reg[2]_rep__0_n_0 ;
  wire \rd_addr_reg[2]_rep_n_0 ;
  wire \rd_addr_reg_n_0_[2] ;
  wire \rd_addr_reg_n_0_[3] ;
  wire \rd_addr_reg_n_0_[4] ;
  wire \rd_addr_reg_n_0_[5] ;
  wire \rd_addr_reg_n_0_[6] ;
  wire \rd_addr_reg_n_0_[7] ;
  wire \rd_addr_reg_n_0_[8] ;
  wire \rd_addr_reg_n_0_[9] ;
  wire [23:16]rd_dat_d0;
  wire [31:0]rd_data;
  wire \rd_data[0]_i_10_n_0 ;
  wire \rd_data[0]_i_11_n_0 ;
  wire \rd_data[0]_i_12_n_0 ;
  wire \rd_data[0]_i_13_n_0 ;
  wire \rd_data[0]_i_14_n_0 ;
  wire \rd_data[0]_i_15_n_0 ;
  wire \rd_data[0]_i_16_n_0 ;
  wire \rd_data[0]_i_1_n_0 ;
  wire \rd_data[0]_i_2_n_0 ;
  wire \rd_data[0]_i_3_n_0 ;
  wire \rd_data[0]_i_4_n_0 ;
  wire \rd_data[0]_i_5_n_0 ;
  wire \rd_data[0]_i_6_n_0 ;
  wire \rd_data[0]_i_7_n_0 ;
  wire \rd_data[0]_i_8_n_0 ;
  wire \rd_data[0]_i_9_n_0 ;
  wire \rd_data[10]_i_10_n_0 ;
  wire \rd_data[10]_i_11_n_0 ;
  wire \rd_data[10]_i_12_n_0 ;
  wire \rd_data[10]_i_13_n_0 ;
  wire \rd_data[10]_i_14_n_0 ;
  wire \rd_data[10]_i_15_n_0 ;
  wire \rd_data[10]_i_16_n_0 ;
  wire \rd_data[10]_i_1_n_0 ;
  wire \rd_data[10]_i_2_n_0 ;
  wire \rd_data[10]_i_3_n_0 ;
  wire \rd_data[10]_i_4_n_0 ;
  wire \rd_data[10]_i_5_n_0 ;
  wire \rd_data[10]_i_6_n_0 ;
  wire \rd_data[10]_i_7_n_0 ;
  wire \rd_data[10]_i_8_n_0 ;
  wire \rd_data[10]_i_9_n_0 ;
  wire \rd_data[11]_i_10_n_0 ;
  wire \rd_data[11]_i_11_n_0 ;
  wire \rd_data[11]_i_12_n_0 ;
  wire \rd_data[11]_i_13_n_0 ;
  wire \rd_data[11]_i_14_n_0 ;
  wire \rd_data[11]_i_15_n_0 ;
  wire \rd_data[11]_i_16_n_0 ;
  wire \rd_data[11]_i_1_n_0 ;
  wire \rd_data[11]_i_2_n_0 ;
  wire \rd_data[11]_i_3_n_0 ;
  wire \rd_data[11]_i_4_n_0 ;
  wire \rd_data[11]_i_5_n_0 ;
  wire \rd_data[11]_i_6_n_0 ;
  wire \rd_data[11]_i_7_n_0 ;
  wire \rd_data[11]_i_8_n_0 ;
  wire \rd_data[11]_i_9_n_0 ;
  wire \rd_data[12]_i_10_n_0 ;
  wire \rd_data[12]_i_11_n_0 ;
  wire \rd_data[12]_i_12_n_0 ;
  wire \rd_data[12]_i_13_n_0 ;
  wire \rd_data[12]_i_14_n_0 ;
  wire \rd_data[12]_i_15_n_0 ;
  wire \rd_data[12]_i_16_n_0 ;
  wire \rd_data[12]_i_1_n_0 ;
  wire \rd_data[12]_i_2_n_0 ;
  wire \rd_data[12]_i_3_n_0 ;
  wire \rd_data[12]_i_4_n_0 ;
  wire \rd_data[12]_i_5_n_0 ;
  wire \rd_data[12]_i_6_n_0 ;
  wire \rd_data[12]_i_7_n_0 ;
  wire \rd_data[12]_i_8_n_0 ;
  wire \rd_data[12]_i_9_n_0 ;
  wire \rd_data[13]_i_10_n_0 ;
  wire \rd_data[13]_i_11_n_0 ;
  wire \rd_data[13]_i_12_n_0 ;
  wire \rd_data[13]_i_13_n_0 ;
  wire \rd_data[13]_i_14_n_0 ;
  wire \rd_data[13]_i_15_n_0 ;
  wire \rd_data[13]_i_16_n_0 ;
  wire \rd_data[13]_i_1_n_0 ;
  wire \rd_data[13]_i_2_n_0 ;
  wire \rd_data[13]_i_3_n_0 ;
  wire \rd_data[13]_i_4_n_0 ;
  wire \rd_data[13]_i_5_n_0 ;
  wire \rd_data[13]_i_6_n_0 ;
  wire \rd_data[13]_i_7_n_0 ;
  wire \rd_data[13]_i_8_n_0 ;
  wire \rd_data[13]_i_9_n_0 ;
  wire \rd_data[14]_i_10_n_0 ;
  wire \rd_data[14]_i_11_n_0 ;
  wire \rd_data[14]_i_12_n_0 ;
  wire \rd_data[14]_i_13_n_0 ;
  wire \rd_data[14]_i_14_n_0 ;
  wire \rd_data[14]_i_15_n_0 ;
  wire \rd_data[14]_i_16_n_0 ;
  wire \rd_data[14]_i_1_n_0 ;
  wire \rd_data[14]_i_2_n_0 ;
  wire \rd_data[14]_i_3_n_0 ;
  wire \rd_data[14]_i_4_n_0 ;
  wire \rd_data[14]_i_5_n_0 ;
  wire \rd_data[14]_i_6_n_0 ;
  wire \rd_data[14]_i_7_n_0 ;
  wire \rd_data[14]_i_8_n_0 ;
  wire \rd_data[14]_i_9_n_0 ;
  wire \rd_data[15]_i_10_n_0 ;
  wire \rd_data[15]_i_11_n_0 ;
  wire \rd_data[15]_i_12_n_0 ;
  wire \rd_data[15]_i_13_n_0 ;
  wire \rd_data[15]_i_14_n_0 ;
  wire \rd_data[15]_i_15_n_0 ;
  wire \rd_data[15]_i_16_n_0 ;
  wire \rd_data[15]_i_1_n_0 ;
  wire \rd_data[15]_i_2_n_0 ;
  wire \rd_data[15]_i_3_n_0 ;
  wire \rd_data[15]_i_4_n_0 ;
  wire \rd_data[15]_i_5_n_0 ;
  wire \rd_data[15]_i_6_n_0 ;
  wire \rd_data[15]_i_7_n_0 ;
  wire \rd_data[15]_i_8_n_0 ;
  wire \rd_data[15]_i_9_n_0 ;
  wire \rd_data[16]_i_10_n_0 ;
  wire \rd_data[16]_i_11_n_0 ;
  wire \rd_data[16]_i_13_n_0 ;
  wire \rd_data[16]_i_14_n_0 ;
  wire \rd_data[16]_i_16_n_0 ;
  wire \rd_data[16]_i_1_n_0 ;
  wire \rd_data[16]_i_5_n_0 ;
  wire \rd_data[16]_i_6_n_0 ;
  wire \rd_data[16]_i_7_n_0 ;
  wire \rd_data[16]_i_8_n_0 ;
  wire \rd_data[16]_i_9_n_0 ;
  wire \rd_data[17]_i_10_n_0 ;
  wire \rd_data[17]_i_11_n_0 ;
  wire \rd_data[17]_i_13_n_0 ;
  wire \rd_data[17]_i_14_n_0 ;
  wire \rd_data[17]_i_15_n_0 ;
  wire \rd_data[17]_i_1_n_0 ;
  wire \rd_data[17]_i_5_n_0 ;
  wire \rd_data[17]_i_6_n_0 ;
  wire \rd_data[17]_i_7_n_0 ;
  wire \rd_data[17]_i_8_n_0 ;
  wire \rd_data[17]_i_9_n_0 ;
  wire \rd_data[18]_i_10_n_0 ;
  wire \rd_data[18]_i_11_n_0 ;
  wire \rd_data[18]_i_13_n_0 ;
  wire \rd_data[18]_i_14_n_0 ;
  wire \rd_data[18]_i_16_n_0 ;
  wire \rd_data[18]_i_1_n_0 ;
  wire \rd_data[18]_i_5_n_0 ;
  wire \rd_data[18]_i_6_n_0 ;
  wire \rd_data[18]_i_7_n_0 ;
  wire \rd_data[18]_i_8_n_0 ;
  wire \rd_data[18]_i_9_n_0 ;
  wire \rd_data[19]_i_10_n_0 ;
  wire \rd_data[19]_i_11_n_0 ;
  wire \rd_data[19]_i_13_n_0 ;
  wire \rd_data[19]_i_14_n_0 ;
  wire \rd_data[19]_i_16_n_0 ;
  wire \rd_data[19]_i_1_n_0 ;
  wire \rd_data[19]_i_5_n_0 ;
  wire \rd_data[19]_i_6_n_0 ;
  wire \rd_data[19]_i_7_n_0 ;
  wire \rd_data[19]_i_8_n_0 ;
  wire \rd_data[19]_i_9_n_0 ;
  wire \rd_data[1]_i_10_n_0 ;
  wire \rd_data[1]_i_11_n_0 ;
  wire \rd_data[1]_i_12_n_0 ;
  wire \rd_data[1]_i_13_n_0 ;
  wire \rd_data[1]_i_14_n_0 ;
  wire \rd_data[1]_i_15_n_0 ;
  wire \rd_data[1]_i_16_n_0 ;
  wire \rd_data[1]_i_1_n_0 ;
  wire \rd_data[1]_i_2_n_0 ;
  wire \rd_data[1]_i_3_n_0 ;
  wire \rd_data[1]_i_4_n_0 ;
  wire \rd_data[1]_i_5_n_0 ;
  wire \rd_data[1]_i_6_n_0 ;
  wire \rd_data[1]_i_7_n_0 ;
  wire \rd_data[1]_i_8_n_0 ;
  wire \rd_data[1]_i_9_n_0 ;
  wire \rd_data[20]_i_10_n_0 ;
  wire \rd_data[20]_i_11_n_0 ;
  wire \rd_data[20]_i_13_n_0 ;
  wire \rd_data[20]_i_14_n_0 ;
  wire \rd_data[20]_i_16_n_0 ;
  wire \rd_data[20]_i_1_n_0 ;
  wire \rd_data[20]_i_5_n_0 ;
  wire \rd_data[20]_i_6_n_0 ;
  wire \rd_data[20]_i_7_n_0 ;
  wire \rd_data[20]_i_8_n_0 ;
  wire \rd_data[20]_i_9_n_0 ;
  wire \rd_data[21]_i_10_n_0 ;
  wire \rd_data[21]_i_11_n_0 ;
  wire \rd_data[21]_i_13_n_0 ;
  wire \rd_data[21]_i_14_n_0 ;
  wire \rd_data[21]_i_15_n_0 ;
  wire \rd_data[21]_i_1_n_0 ;
  wire \rd_data[21]_i_5_n_0 ;
  wire \rd_data[21]_i_6_n_0 ;
  wire \rd_data[21]_i_7_n_0 ;
  wire \rd_data[21]_i_8_n_0 ;
  wire \rd_data[21]_i_9_n_0 ;
  wire \rd_data[22]_i_10_n_0 ;
  wire \rd_data[22]_i_11_n_0 ;
  wire \rd_data[22]_i_13_n_0 ;
  wire \rd_data[22]_i_14_n_0 ;
  wire \rd_data[22]_i_16_n_0 ;
  wire \rd_data[22]_i_1_n_0 ;
  wire \rd_data[22]_i_5_n_0 ;
  wire \rd_data[22]_i_6_n_0 ;
  wire \rd_data[22]_i_7_n_0 ;
  wire \rd_data[22]_i_8_n_0 ;
  wire \rd_data[22]_i_9_n_0 ;
  wire \rd_data[23]_i_10_n_0 ;
  wire \rd_data[23]_i_11_n_0 ;
  wire \rd_data[23]_i_13_n_0 ;
  wire \rd_data[23]_i_14_n_0 ;
  wire \rd_data[23]_i_16_n_0 ;
  wire \rd_data[23]_i_1_n_0 ;
  wire \rd_data[23]_i_5_n_0 ;
  wire \rd_data[23]_i_6_n_0 ;
  wire \rd_data[23]_i_7_n_0 ;
  wire \rd_data[23]_i_8_n_0 ;
  wire \rd_data[23]_i_9_n_0 ;
  wire \rd_data[24]_i_10_n_0 ;
  wire \rd_data[24]_i_11_n_0 ;
  wire \rd_data[24]_i_12_n_0 ;
  wire \rd_data[24]_i_14_n_0 ;
  wire \rd_data[24]_i_15_n_0 ;
  wire \rd_data[24]_i_16_n_0 ;
  wire \rd_data[24]_i_1_n_0 ;
  wire \rd_data[24]_i_5_n_0 ;
  wire \rd_data[24]_i_6_n_0 ;
  wire \rd_data[24]_i_7_n_0 ;
  wire \rd_data[24]_i_8_n_0 ;
  wire \rd_data[24]_i_9_n_0 ;
  wire \rd_data[25]_i_10_n_0 ;
  wire \rd_data[25]_i_11_n_0 ;
  wire \rd_data[25]_i_13_n_0 ;
  wire \rd_data[25]_i_14_n_0 ;
  wire \rd_data[25]_i_15_n_0 ;
  wire \rd_data[25]_i_1_n_0 ;
  wire \rd_data[25]_i_5_n_0 ;
  wire \rd_data[25]_i_6_n_0 ;
  wire \rd_data[25]_i_7_n_0 ;
  wire \rd_data[25]_i_8_n_0 ;
  wire \rd_data[25]_i_9_n_0 ;
  wire \rd_data[26]_i_10_n_0 ;
  wire \rd_data[26]_i_11_n_0 ;
  wire \rd_data[26]_i_13_n_0 ;
  wire \rd_data[26]_i_14_n_0 ;
  wire \rd_data[26]_i_15_n_0 ;
  wire \rd_data[26]_i_1_n_0 ;
  wire \rd_data[26]_i_5_n_0 ;
  wire \rd_data[26]_i_6_n_0 ;
  wire \rd_data[26]_i_7_n_0 ;
  wire \rd_data[26]_i_8_n_0 ;
  wire \rd_data[26]_i_9_n_0 ;
  wire \rd_data[27]_i_10_n_0 ;
  wire \rd_data[27]_i_11_n_0 ;
  wire \rd_data[27]_i_13_n_0 ;
  wire \rd_data[27]_i_14_n_0 ;
  wire \rd_data[27]_i_15_n_0 ;
  wire \rd_data[27]_i_1_n_0 ;
  wire \rd_data[27]_i_5_n_0 ;
  wire \rd_data[27]_i_6_n_0 ;
  wire \rd_data[27]_i_7_n_0 ;
  wire \rd_data[27]_i_8_n_0 ;
  wire \rd_data[27]_i_9_n_0 ;
  wire \rd_data[28]_i_10_n_0 ;
  wire \rd_data[28]_i_11_n_0 ;
  wire \rd_data[28]_i_13_n_0 ;
  wire \rd_data[28]_i_14_n_0 ;
  wire \rd_data[28]_i_15_n_0 ;
  wire \rd_data[28]_i_1_n_0 ;
  wire \rd_data[28]_i_5_n_0 ;
  wire \rd_data[28]_i_6_n_0 ;
  wire \rd_data[28]_i_7_n_0 ;
  wire \rd_data[28]_i_8_n_0 ;
  wire \rd_data[28]_i_9_n_0 ;
  wire \rd_data[29]_i_10_n_0 ;
  wire \rd_data[29]_i_11_n_0 ;
  wire \rd_data[29]_i_13_n_0 ;
  wire \rd_data[29]_i_14_n_0 ;
  wire \rd_data[29]_i_15_n_0 ;
  wire \rd_data[29]_i_1_n_0 ;
  wire \rd_data[29]_i_5_n_0 ;
  wire \rd_data[29]_i_6_n_0 ;
  wire \rd_data[29]_i_7_n_0 ;
  wire \rd_data[29]_i_8_n_0 ;
  wire \rd_data[29]_i_9_n_0 ;
  wire \rd_data[2]_i_10_n_0 ;
  wire \rd_data[2]_i_11_n_0 ;
  wire \rd_data[2]_i_12_n_0 ;
  wire \rd_data[2]_i_13_n_0 ;
  wire \rd_data[2]_i_14_n_0 ;
  wire \rd_data[2]_i_15_n_0 ;
  wire \rd_data[2]_i_16_n_0 ;
  wire \rd_data[2]_i_1_n_0 ;
  wire \rd_data[2]_i_2_n_0 ;
  wire \rd_data[2]_i_3_n_0 ;
  wire \rd_data[2]_i_4_n_0 ;
  wire \rd_data[2]_i_5_n_0 ;
  wire \rd_data[2]_i_6_n_0 ;
  wire \rd_data[2]_i_7_n_0 ;
  wire \rd_data[2]_i_8_n_0 ;
  wire \rd_data[2]_i_9_n_0 ;
  wire \rd_data[30]_i_10_n_0 ;
  wire \rd_data[30]_i_11_n_0 ;
  wire \rd_data[30]_i_13_n_0 ;
  wire \rd_data[30]_i_14_n_0 ;
  wire \rd_data[30]_i_15_n_0 ;
  wire \rd_data[30]_i_1_n_0 ;
  wire \rd_data[30]_i_5_n_0 ;
  wire \rd_data[30]_i_6_n_0 ;
  wire \rd_data[30]_i_7_n_0 ;
  wire \rd_data[30]_i_8_n_0 ;
  wire \rd_data[30]_i_9_n_0 ;
  wire \rd_data[31]_i_10_n_0 ;
  wire \rd_data[31]_i_11_n_0 ;
  wire \rd_data[31]_i_12_n_0 ;
  wire \rd_data[31]_i_13_n_0 ;
  wire \rd_data[31]_i_14_n_0 ;
  wire \rd_data[31]_i_15_n_0 ;
  wire \rd_data[31]_i_17_n_0 ;
  wire \rd_data[31]_i_18_n_0 ;
  wire \rd_data[31]_i_19_n_0 ;
  wire \rd_data[31]_i_1_n_0 ;
  wire \rd_data[31]_i_3_n_0 ;
  wire \rd_data[31]_i_5_n_0 ;
  wire \rd_data[31]_i_7_n_0 ;
  wire \rd_data[31]_i_8_n_0 ;
  wire \rd_data[31]_i_9_n_0 ;
  wire \rd_data[3]_i_10_n_0 ;
  wire \rd_data[3]_i_11_n_0 ;
  wire \rd_data[3]_i_12_n_0 ;
  wire \rd_data[3]_i_13_n_0 ;
  wire \rd_data[3]_i_14_n_0 ;
  wire \rd_data[3]_i_15_n_0 ;
  wire \rd_data[3]_i_16_n_0 ;
  wire \rd_data[3]_i_1_n_0 ;
  wire \rd_data[3]_i_2_n_0 ;
  wire \rd_data[3]_i_3_n_0 ;
  wire \rd_data[3]_i_4_n_0 ;
  wire \rd_data[3]_i_5_n_0 ;
  wire \rd_data[3]_i_6_n_0 ;
  wire \rd_data[3]_i_7_n_0 ;
  wire \rd_data[3]_i_8_n_0 ;
  wire \rd_data[3]_i_9_n_0 ;
  wire \rd_data[4]_i_10_n_0 ;
  wire \rd_data[4]_i_11_n_0 ;
  wire \rd_data[4]_i_12_n_0 ;
  wire \rd_data[4]_i_13_n_0 ;
  wire \rd_data[4]_i_14_n_0 ;
  wire \rd_data[4]_i_15_n_0 ;
  wire \rd_data[4]_i_16_n_0 ;
  wire \rd_data[4]_i_1_n_0 ;
  wire \rd_data[4]_i_2_n_0 ;
  wire \rd_data[4]_i_3_n_0 ;
  wire \rd_data[4]_i_4_n_0 ;
  wire \rd_data[4]_i_5_n_0 ;
  wire \rd_data[4]_i_6_n_0 ;
  wire \rd_data[4]_i_7_n_0 ;
  wire \rd_data[4]_i_8_n_0 ;
  wire \rd_data[4]_i_9_n_0 ;
  wire \rd_data[5]_i_10_n_0 ;
  wire \rd_data[5]_i_11_n_0 ;
  wire \rd_data[5]_i_12_n_0 ;
  wire \rd_data[5]_i_13_n_0 ;
  wire \rd_data[5]_i_14_n_0 ;
  wire \rd_data[5]_i_15_n_0 ;
  wire \rd_data[5]_i_16_n_0 ;
  wire \rd_data[5]_i_1_n_0 ;
  wire \rd_data[5]_i_2_n_0 ;
  wire \rd_data[5]_i_3_n_0 ;
  wire \rd_data[5]_i_4_n_0 ;
  wire \rd_data[5]_i_5_n_0 ;
  wire \rd_data[5]_i_6_n_0 ;
  wire \rd_data[5]_i_7_n_0 ;
  wire \rd_data[5]_i_8_n_0 ;
  wire \rd_data[5]_i_9_n_0 ;
  wire \rd_data[6]_i_10_n_0 ;
  wire \rd_data[6]_i_11_n_0 ;
  wire \rd_data[6]_i_12_n_0 ;
  wire \rd_data[6]_i_13_n_0 ;
  wire \rd_data[6]_i_14_n_0 ;
  wire \rd_data[6]_i_15_n_0 ;
  wire \rd_data[6]_i_16_n_0 ;
  wire \rd_data[6]_i_17_n_0 ;
  wire \rd_data[6]_i_1_n_0 ;
  wire \rd_data[6]_i_2_n_0 ;
  wire \rd_data[6]_i_3_n_0 ;
  wire \rd_data[6]_i_4_n_0 ;
  wire \rd_data[6]_i_5_n_0 ;
  wire \rd_data[6]_i_6_n_0 ;
  wire \rd_data[6]_i_7_n_0 ;
  wire \rd_data[6]_i_8_n_0 ;
  wire \rd_data[6]_i_9_n_0 ;
  wire \rd_data[7]_i_10_n_0 ;
  wire \rd_data[7]_i_11_n_0 ;
  wire \rd_data[7]_i_12_n_0 ;
  wire \rd_data[7]_i_13_n_0 ;
  wire \rd_data[7]_i_14_n_0 ;
  wire \rd_data[7]_i_15_n_0 ;
  wire \rd_data[7]_i_16_n_0 ;
  wire \rd_data[7]_i_1_n_0 ;
  wire \rd_data[7]_i_2_n_0 ;
  wire \rd_data[7]_i_3_n_0 ;
  wire \rd_data[7]_i_4_n_0 ;
  wire \rd_data[7]_i_5_n_0 ;
  wire \rd_data[7]_i_6_n_0 ;
  wire \rd_data[7]_i_7_n_0 ;
  wire \rd_data[7]_i_8_n_0 ;
  wire \rd_data[7]_i_9_n_0 ;
  wire \rd_data[8]_i_10_n_0 ;
  wire \rd_data[8]_i_11_n_0 ;
  wire \rd_data[8]_i_12_n_0 ;
  wire \rd_data[8]_i_13_n_0 ;
  wire \rd_data[8]_i_14_n_0 ;
  wire \rd_data[8]_i_15_n_0 ;
  wire \rd_data[8]_i_16_n_0 ;
  wire \rd_data[8]_i_1_n_0 ;
  wire \rd_data[8]_i_2_n_0 ;
  wire \rd_data[8]_i_3_n_0 ;
  wire \rd_data[8]_i_4_n_0 ;
  wire \rd_data[8]_i_5_n_0 ;
  wire \rd_data[8]_i_6_n_0 ;
  wire \rd_data[8]_i_7_n_0 ;
  wire \rd_data[8]_i_8_n_0 ;
  wire \rd_data[8]_i_9_n_0 ;
  wire \rd_data[9]_i_10_n_0 ;
  wire \rd_data[9]_i_11_n_0 ;
  wire \rd_data[9]_i_12_n_0 ;
  wire \rd_data[9]_i_13_n_0 ;
  wire \rd_data[9]_i_14_n_0 ;
  wire \rd_data[9]_i_15_n_0 ;
  wire \rd_data[9]_i_16_n_0 ;
  wire \rd_data[9]_i_1_n_0 ;
  wire \rd_data[9]_i_2_n_0 ;
  wire \rd_data[9]_i_3_n_0 ;
  wire \rd_data[9]_i_4_n_0 ;
  wire \rd_data[9]_i_5_n_0 ;
  wire \rd_data[9]_i_6_n_0 ;
  wire \rd_data[9]_i_7_n_0 ;
  wire \rd_data[9]_i_8_n_0 ;
  wire \rd_data[9]_i_9_n_0 ;
  wire \rd_data_reg[16]_i_2_n_0 ;
  wire \rd_data_reg[16]_i_3_n_0 ;
  wire \rd_data_reg[16]_i_4_n_0 ;
  wire \rd_data_reg[17]_i_2_n_0 ;
  wire \rd_data_reg[17]_i_3_n_0 ;
  wire \rd_data_reg[17]_i_4_n_0 ;
  wire \rd_data_reg[18]_i_2_n_0 ;
  wire \rd_data_reg[18]_i_3_n_0 ;
  wire \rd_data_reg[18]_i_4_n_0 ;
  wire \rd_data_reg[19]_i_2_n_0 ;
  wire \rd_data_reg[19]_i_3_n_0 ;
  wire \rd_data_reg[19]_i_4_n_0 ;
  wire \rd_data_reg[20]_i_2_n_0 ;
  wire \rd_data_reg[20]_i_3_n_0 ;
  wire \rd_data_reg[20]_i_4_n_0 ;
  wire \rd_data_reg[21]_i_2_n_0 ;
  wire \rd_data_reg[21]_i_3_n_0 ;
  wire \rd_data_reg[21]_i_4_n_0 ;
  wire \rd_data_reg[22]_i_2_n_0 ;
  wire \rd_data_reg[22]_i_3_n_0 ;
  wire \rd_data_reg[22]_i_4_n_0 ;
  wire \rd_data_reg[23]_i_2_n_0 ;
  wire \rd_data_reg[23]_i_3_n_0 ;
  wire \rd_data_reg[23]_i_4_n_0 ;
  wire \rd_data_reg[24]_i_2_n_0 ;
  wire \rd_data_reg[24]_i_3_n_0 ;
  wire \rd_data_reg[24]_i_4_n_0 ;
  wire \rd_data_reg[25]_i_2_n_0 ;
  wire \rd_data_reg[25]_i_3_n_0 ;
  wire \rd_data_reg[25]_i_4_n_0 ;
  wire \rd_data_reg[26]_i_2_n_0 ;
  wire \rd_data_reg[26]_i_3_n_0 ;
  wire \rd_data_reg[26]_i_4_n_0 ;
  wire \rd_data_reg[27]_i_2_n_0 ;
  wire \rd_data_reg[27]_i_3_n_0 ;
  wire \rd_data_reg[27]_i_4_n_0 ;
  wire \rd_data_reg[28]_i_2_n_0 ;
  wire \rd_data_reg[28]_i_3_n_0 ;
  wire \rd_data_reg[28]_i_4_n_0 ;
  wire \rd_data_reg[29]_i_2_n_0 ;
  wire \rd_data_reg[29]_i_3_n_0 ;
  wire \rd_data_reg[29]_i_4_n_0 ;
  wire \rd_data_reg[30]_i_2_n_0 ;
  wire \rd_data_reg[30]_i_3_n_0 ;
  wire \rd_data_reg[30]_i_4_n_0 ;
  wire \rd_data_reg[31]_i_2_n_0 ;
  wire \rd_data_reg[31]_i_4_n_0 ;
  wire \rd_data_reg[31]_i_6_n_0 ;
  wire rd_req;
  wire rd_req0;
  wire [31:0]rdata;
  wire [31:0]readback_coef_i;
  wire [47:0]readback_phaseH1Comp_reg_i;
  wire [31:0]readback_tw_i;
  wire rready;
  wire rvalid;
  wire [6:0]sel0;
  wire status_amAutoOn_i;
  wire status_interlock_i;
  wire status_phaseH1Vld_i;
  wire [31:0]wdata;
  wire wr_ack__15;
  wire [11:2]wr_addr;
  wire wr_addr_0;
  wire [2:2]wr_adr_d0;
  wire \wr_adr_d0_reg_n_0_[10] ;
  wire \wr_adr_d0_reg_n_0_[11] ;
  wire \wr_dat_d0_reg_n_0_[0] ;
  wire \wr_dat_d0_reg_n_0_[10] ;
  wire \wr_dat_d0_reg_n_0_[11] ;
  wire \wr_dat_d0_reg_n_0_[12] ;
  wire \wr_dat_d0_reg_n_0_[13] ;
  wire \wr_dat_d0_reg_n_0_[14] ;
  wire \wr_dat_d0_reg_n_0_[15] ;
  wire \wr_dat_d0_reg_n_0_[16] ;
  wire \wr_dat_d0_reg_n_0_[17] ;
  wire \wr_dat_d0_reg_n_0_[18] ;
  wire \wr_dat_d0_reg_n_0_[19] ;
  wire \wr_dat_d0_reg_n_0_[20] ;
  wire \wr_dat_d0_reg_n_0_[21] ;
  wire \wr_dat_d0_reg_n_0_[22] ;
  wire \wr_dat_d0_reg_n_0_[23] ;
  wire \wr_dat_d0_reg_n_0_[24] ;
  wire \wr_dat_d0_reg_n_0_[25] ;
  wire \wr_dat_d0_reg_n_0_[26] ;
  wire \wr_dat_d0_reg_n_0_[27] ;
  wire \wr_dat_d0_reg_n_0_[28] ;
  wire \wr_dat_d0_reg_n_0_[29] ;
  wire \wr_dat_d0_reg_n_0_[2] ;
  wire \wr_dat_d0_reg_n_0_[30] ;
  wire \wr_dat_d0_reg_n_0_[31] ;
  wire \wr_dat_d0_reg_n_0_[3] ;
  wire \wr_dat_d0_reg_n_0_[4] ;
  wire \wr_dat_d0_reg_n_0_[5] ;
  wire \wr_dat_d0_reg_n_0_[7] ;
  wire \wr_dat_d0_reg_n_0_[8] ;
  wire \wr_dat_d0_reg_n_0_[9] ;
  wire [31:0]wr_data;
  wire wr_data_1;
  wire wr_req;
  wire wr_req_d0;
  wire wr_req_i_1_n_0;
  wire wready;
  wire wvalid;

  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT1 #(
    .INIT(2'h1)) 
    arready_INST_0
       (.I0(axi_arset),
        .O(arready));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT1 #(
    .INIT(2'h1)) 
    awready_INST_0
       (.I0(axi_awset),
        .O(awready));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h00E0E0E0)) 
    axi_arset_i_1
       (.I0(axi_arset),
        .I1(arvalid),
        .I2(areset_n),
        .I3(rvalid),
        .I4(rready),
        .O(axi_arset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    axi_arset_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(axi_arset_i_1_n_0),
        .Q(axi_arset),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT5 #(
    .INIT(32'h00E0E0E0)) 
    axi_awset_i_1
       (.I0(axi_awset),
        .I1(awvalid),
        .I2(areset_n),
        .I3(bvalid),
        .I4(bready),
        .O(axi_awset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    axi_awset_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(axi_awset_i_1_n_0),
        .Q(axi_awset),
        .R(\<const0> ));
  LUT3 #(
    .INIT(8'hBA)) 
    axi_rdone_i_1
       (.I0(rd_ack),
        .I1(rready),
        .I2(rvalid),
        .O(axi_rdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RVALID" *) 
  FDRE #(
    .INIT(1'b0)) 
    axi_rdone_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(axi_rdone_i_1_n_0),
        .Q(rvalid),
        .R(axi_wdone_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    axi_wdone_i_1
       (.I0(areset_n),
        .O(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'hFF00ABABFF00A8A8)) 
    axi_wdone_i_10
       (.I0(control_wack),
        .I1(axi_wdone_i_17_n_0),
        .I2(axi_wdone_i_18_n_0),
        .I3(wr_req_d0),
        .I4(wr_adr_d0),
        .I5(ipInfo_echo_wack),
        .O(axi_wdone_i_10_n_0));
  LUT6 #(
    .INIT(64'h000000001111081A)) 
    axi_wdone_i_11
       (.I0(sel0[1]),
        .I1(sel0[4]),
        .I2(sel0[2]),
        .I3(sel0[0]),
        .I4(sel0[5]),
        .I5(\ftw_slip_reg[31]_i_3_n_0 ),
        .O(axi_wdone_i_11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT5 #(
    .INIT(32'hF0F1F0E0)) 
    axi_wdone_i_12
       (.I0(axi_wdone_i_17_n_0),
        .I1(axi_wdone_i_18_n_0),
        .I2(wr_req_d0),
        .I3(wr_adr_d0),
        .I4(presentLatch_wack),
        .O(axi_wdone_i_12_n_0));
  LUT6 #(
    .INIT(64'hB8B8B8FFB8B8B800)) 
    axi_wdone_i_13
       (.I0(wr_req_d0),
        .I1(wr_adr_d0),
        .I2(inputs_delayComp_wack),
        .I3(axi_wdone_i_17_n_0),
        .I4(axi_wdone_i_18_n_0),
        .I5(axi_wdone_i_21_n_0),
        .O(axi_wdone_i_13_n_0));
  LUT6 #(
    .INIT(64'hB8B8B8FFB8B8B800)) 
    axi_wdone_i_14
       (.I0(inputs_offsetAM_wack[1]),
        .I1(wr_adr_d0),
        .I2(inputs_offsetAM_wack[0]),
        .I3(axi_wdone_i_17_n_0),
        .I4(axi_wdone_i_18_n_0),
        .I5(axi_wdone_i_22_n_0),
        .O(axi_wdone_i_14_n_0));
  LUT6 #(
    .INIT(64'hB8B8B8FFB8B8B800)) 
    axi_wdone_i_15
       (.I0(inputs_h_wack),
        .I1(wr_adr_d0),
        .I2(inputs_rate_wack),
        .I3(axi_wdone_i_17_n_0),
        .I4(axi_wdone_i_18_n_0),
        .I5(axi_wdone_i_23_n_0),
        .O(axi_wdone_i_15_n_0));
  LUT6 #(
    .INIT(64'hB8B8B8FFB8B8B800)) 
    axi_wdone_i_16
       (.I0(wr_req_d0),
        .I1(wr_adr_d0),
        .I2(ftw_slip_wack),
        .I3(axi_wdone_i_17_n_0),
        .I4(axi_wdone_i_18_n_0),
        .I5(axi_wdone_i_24_n_0),
        .O(axi_wdone_i_16_n_0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'hAA02)) 
    axi_wdone_i_17
       (.I0(sel0[2]),
        .I1(sel0[4]),
        .I2(sel0[5]),
        .I3(sel0[1]),
        .O(axi_wdone_i_17_n_0));
  LUT6 #(
    .INIT(64'hFFFEFEFEFFFEFEEF)) 
    axi_wdone_i_18
       (.I0(sel0[3]),
        .I1(sel0[0]),
        .I2(sel0[6]),
        .I3(sel0[5]),
        .I4(sel0[4]),
        .I5(sel0[1]),
        .O(axi_wdone_i_18_n_0));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    axi_wdone_i_19
       (.I0(ftw_on_wack[1]),
        .I1(wr_adr_d0),
        .I2(ftw_on_wack[0]),
        .O(axi_wdone_i_19_n_0));
  LUT6 #(
    .INIT(64'hFE02FFFFFE02FE02)) 
    axi_wdone_i_2
       (.I0(wr_ack__15),
        .I1(\wr_adr_d0_reg_n_0_[10] ),
        .I2(\wr_adr_d0_reg_n_0_[11] ),
        .I3(wr_req_d0),
        .I4(bready),
        .I5(bvalid),
        .O(axi_wdone_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    axi_wdone_i_20
       (.I0(ftw_h1_wack[1]),
        .I1(wr_adr_d0),
        .I2(ftw_h1_wack[0]),
        .O(axi_wdone_i_20_n_0));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    axi_wdone_i_21
       (.I0(inputs_pulseLengthAM_wack[1]),
        .I1(wr_adr_d0),
        .I2(inputs_pulseLengthAM_wack[0]),
        .O(axi_wdone_i_21_n_0));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    axi_wdone_i_22
       (.I0(inputs_offsetFSK_wack[1]),
        .I1(wr_adr_d0),
        .I2(inputs_offsetFSK_wack[0]),
        .O(axi_wdone_i_22_n_0));
  LUT3 #(
    .INIT(8'hB8)) 
    axi_wdone_i_23
       (.I0(inputs_offsetH1_wack[1]),
        .I1(wr_adr_d0),
        .I2(inputs_offsetH1_wack[0]),
        .O(axi_wdone_i_23_n_0));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    axi_wdone_i_24
       (.I0(ftw_lo1_wack[1]),
        .I1(wr_adr_d0),
        .I2(ftw_lo1_wack[0]),
        .O(axi_wdone_i_24_n_0));
  LUT6 #(
    .INIT(64'h0000011001000100)) 
    axi_wdone_i_4
       (.I0(sel0[3]),
        .I1(sel0[6]),
        .I2(sel0[4]),
        .I3(sel0[5]),
        .I4(sel0[1]),
        .I5(sel0[2]),
        .O(axi_wdone_i_4_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    axi_wdone_i_5
       (.I0(axi_wdone_i_7_n_0),
        .I1(axi_wdone_i_8_n_0),
        .I2(axi_wdone_i_9_n_0),
        .I3(axi_wdone_i_10_n_0),
        .I4(axi_wdone_i_11_n_0),
        .I5(axi_wdone_i_12_n_0),
        .O(axi_wdone_i_5_n_0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    axi_wdone_i_6
       (.I0(axi_wdone_i_13_n_0),
        .I1(axi_wdone_i_14_n_0),
        .I2(axi_wdone_i_9_n_0),
        .I3(axi_wdone_i_15_n_0),
        .I4(axi_wdone_i_11_n_0),
        .I5(axi_wdone_i_16_n_0),
        .O(axi_wdone_i_6_n_0));
  LUT6 #(
    .INIT(64'hB8B8B8FFB8B8B800)) 
    axi_wdone_i_7
       (.I0(ftw_lo0_wack[1]),
        .I1(wr_adr_d0),
        .I2(ftw_lo0_wack[0]),
        .I3(axi_wdone_i_17_n_0),
        .I4(axi_wdone_i_18_n_0),
        .I5(axi_wdone_i_19_n_0),
        .O(axi_wdone_i_7_n_0));
  LUT6 #(
    .INIT(64'hB8B8B8FFB8B8B800)) 
    axi_wdone_i_8
       (.I0(ftw_h1Prog_wack[1]),
        .I1(wr_adr_d0),
        .I2(ftw_h1Prog_wack[0]),
        .I3(axi_wdone_i_17_n_0),
        .I4(axi_wdone_i_18_n_0),
        .I5(axi_wdone_i_20_n_0),
        .O(axi_wdone_i_8_n_0));
  LUT6 #(
    .INIT(64'h0000000000001218)) 
    axi_wdone_i_9
       (.I0(sel0[5]),
        .I1(sel0[2]),
        .I2(sel0[4]),
        .I3(sel0[1]),
        .I4(sel0[3]),
        .I5(sel0[6]),
        .O(axi_wdone_i_9_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave BVALID" *) 
  FDRE #(
    .INIT(1'b0)) 
    axi_wdone_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(axi_wdone_i_2_n_0),
        .Q(bvalid),
        .R(axi_wdone_i_1_n_0));
  MUXF7 axi_wdone_reg_i_3
       (.I0(axi_wdone_i_5_n_0),
        .I1(axi_wdone_i_6_n_0),
        .O(wr_ack__15),
        .S(axi_wdone_i_4_n_0));
  LUT5 #(
    .INIT(32'h00E0E0E0)) 
    axi_wset_i_1
       (.I0(axi_wset_reg_n_0),
        .I1(wvalid),
        .I2(areset_n),
        .I3(bvalid),
        .I4(bready),
        .O(axi_wset_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    axi_wset_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(axi_wset_i_1_n_0),
        .Q(axi_wset_reg_n_0),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    control_enableFSK_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(control_enableFSK_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_enableFreqDoubling_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(control_enableFreqDoubling_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_enableSlip_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(control_enableSlip_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_extResetEnable_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(control_extResetEnable_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_forceAM_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(control_forceAM_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_latchPhases_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(control_latchPhases_o),
        .R(control_softLoad_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_resetFSK_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(control_resetFSK_o),
        .R(control_softLoad_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_resetSlip_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(control_resetSlip_o),
        .R(control_softLoad_reg_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    control_reset_reg_i_1
       (.I0(sel0[0]),
        .I1(sel0[3]),
        .I2(control_reset_reg_i_2_n_0),
        .I3(control_reset_reg_i_3_n_0),
        .I4(control_reset_reg_i_4_n_0),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(control_reset_reg_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    control_reset_reg_i_2
       (.I0(wr_adr_d0),
        .I1(wr_req_d0),
        .I2(sel0[2]),
        .O(control_reset_reg_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'hE)) 
    control_reset_reg_i_3
       (.I0(sel0[6]),
        .I1(sel0[1]),
        .O(control_reset_reg_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h1)) 
    control_reset_reg_i_4
       (.I0(sel0[4]),
        .I1(sel0[5]),
        .O(control_reset_reg_i_4_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_reset_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(control_reset_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selDftwH1slip_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(control_selDftwH1slip_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selFtwH1On_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(control_selFtwH1On_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selFtwH1_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(control_selFtwH1_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selFtwH1prog_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(control_selFtwH1prog_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selFtwLo0_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(control_selFtwLo0_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selFtwLo1_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(control_selFtwLo1_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selLoad_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(control_selLoad_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selOffsetFskH1_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(control_selOffsetFskH1_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selOffsetH1_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(control_selOffsetH1_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selRate_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(p_2_in),
        .Q(control_selRate_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selWrDftwH1slip_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(control_selWrDftwH1slip_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_selWrFtwH1_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(control_selWrFtwH1_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_signIF0_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(control_signIF0_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_signIF1_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(control_signIF1_o),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_slipSign_reg_reg
       (.C(aclk),
        .CE(control_reset_reg_i_1_n_0),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(control_slipSign_o),
        .R(axi_wdone_i_1_n_0));
  LUT2 #(
    .INIT(4'h7)) 
    control_softLoad_reg_i_1
       (.I0(areset_n),
        .I1(control_reset_reg_i_1_n_0),
        .O(control_softLoad_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_softLoad_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(p_0_in),
        .Q(control_softLoad_o),
        .R(control_softLoad_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    control_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(control_reset_reg_i_1_n_0),
        .Q(control_wack),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \ftw_h1Prog_reg_reg[31]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ),
        .I1(sel0[0]),
        .I2(sel0[4]),
        .I3(\ftw_h1Prog_reg_reg[47]_i_3_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \ftw_h1Prog_reg_reg[31]_i_2 
       (.I0(sel0[3]),
        .I1(wr_adr_d0),
        .I2(wr_req_d0),
        .O(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \ftw_h1Prog_reg_reg[47]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[0]),
        .I2(sel0[4]),
        .I3(\ftw_h1Prog_reg_reg[47]_i_3_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \ftw_h1Prog_reg_reg[47]_i_2 
       (.I0(sel0[3]),
        .I1(wr_req_d0),
        .I2(wr_adr_d0),
        .O(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \ftw_h1Prog_reg_reg[47]_i_3 
       (.I0(sel0[2]),
        .I1(sel0[6]),
        .I2(sel0[1]),
        .I3(sel0[5]),
        .O(\ftw_h1Prog_reg_reg[47]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_h1Prog_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_h1Prog_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_h1Prog_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_h1Prog_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_h1Prog_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_h1Prog_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_h1Prog_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(ftw_h1Prog_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(ftw_h1Prog_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(ftw_h1Prog_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(ftw_h1Prog_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_h1Prog_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(ftw_h1Prog_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(ftw_h1Prog_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(ftw_h1Prog_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(ftw_h1Prog_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(ftw_h1Prog_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(ftw_h1Prog_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(ftw_h1Prog_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(ftw_h1Prog_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(ftw_h1Prog_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(ftw_h1Prog_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_h1Prog_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(ftw_h1Prog_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(ftw_h1Prog_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_h1Prog_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_h1Prog_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_h1Prog_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_h1Prog_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_h1Prog_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_h1Prog_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_h1Prog_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_h1Prog_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_h1Prog_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_h1Prog_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_h1Prog_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_h1Prog_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_h1Prog_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_h1Prog_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_h1Prog_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_h1Prog_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_h1Prog_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_h1Prog_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_h1Prog_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_h1Prog_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_h1Prog_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_h1Prog_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_h1Prog_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_h1Prog_reg_reg[31]_i_1_n_0 ),
        .Q(ftw_h1Prog_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1Prog_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_h1Prog_reg_reg[47]_i_1_n_0 ),
        .Q(ftw_h1Prog_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \ftw_h1_reg_reg[31]_i_1 
       (.I0(sel0[2]),
        .I1(sel0[3]),
        .I2(sel0[4]),
        .I3(\ftw_h1_reg_reg[31]_i_2_n_0 ),
        .I4(\ftw_h1_reg_reg[47]_i_3_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\ftw_h1_reg_reg[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \ftw_h1_reg_reg[31]_i_2 
       (.I0(wr_req_d0),
        .I1(wr_adr_d0),
        .O(\ftw_h1_reg_reg[31]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \ftw_h1_reg_reg[47]_i_1 
       (.I0(\ftw_h1_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[4]),
        .I2(wr_adr_d0),
        .I3(wr_req_d0),
        .I4(\ftw_h1_reg_reg[47]_i_3_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\ftw_h1_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ftw_h1_reg_reg[47]_i_2 
       (.I0(sel0[3]),
        .I1(sel0[2]),
        .O(\ftw_h1_reg_reg[47]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \ftw_h1_reg_reg[47]_i_3 
       (.I0(sel0[1]),
        .I1(sel0[6]),
        .I2(sel0[0]),
        .I3(sel0[5]),
        .O(\ftw_h1_reg_reg[47]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_h1_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_h1_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_h1_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_h1_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_h1_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_h1_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_h1_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(ftw_h1_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(ftw_h1_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(ftw_h1_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(ftw_h1_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_h1_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(ftw_h1_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(ftw_h1_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(ftw_h1_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(ftw_h1_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(ftw_h1_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(ftw_h1_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(ftw_h1_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(ftw_h1_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(ftw_h1_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(ftw_h1_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_h1_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(ftw_h1_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(ftw_h1_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_h1_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_h1_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_h1_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_h1_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_h1_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_h1_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_h1_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_h1_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_h1_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_h1_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_h1_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_h1_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_h1_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_h1_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_h1_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_h1_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_h1_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_h1_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_h1_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_h1_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_h1_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_h1_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_h1_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_h1_reg_reg[31]_i_1_n_0 ),
        .Q(ftw_h1_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_h1_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_h1_reg_reg[47]_i_1_n_0 ),
        .Q(ftw_h1_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \ftw_lo0_reg_reg[31]_i_1 
       (.I0(sel0[4]),
        .I1(\ftw_h1_reg_reg[31]_i_2_n_0 ),
        .I2(sel0[0]),
        .I3(sel0[1]),
        .I4(\ftw_lo0_reg_reg[47]_i_3_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\ftw_lo0_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \ftw_lo0_reg_reg[47]_i_1 
       (.I0(sel0[4]),
        .I1(wr_adr_d0),
        .I2(wr_req_d0),
        .I3(\ftw_lo0_reg_reg[47]_i_2_n_0 ),
        .I4(\ftw_lo0_reg_reg[47]_i_3_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\ftw_lo0_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \ftw_lo0_reg_reg[47]_i_2 
       (.I0(sel0[1]),
        .I1(sel0[0]),
        .O(\ftw_lo0_reg_reg[47]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \ftw_lo0_reg_reg[47]_i_3 
       (.I0(sel0[3]),
        .I1(sel0[6]),
        .I2(sel0[2]),
        .I3(sel0[5]),
        .O(\ftw_lo0_reg_reg[47]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_lo0_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_lo0_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_lo0_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_lo0_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_lo0_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_lo0_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_lo0_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(ftw_lo0_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(ftw_lo0_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(ftw_lo0_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(ftw_lo0_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_lo0_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(ftw_lo0_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(ftw_lo0_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(ftw_lo0_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(ftw_lo0_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(ftw_lo0_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(ftw_lo0_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(ftw_lo0_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(ftw_lo0_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(ftw_lo0_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(ftw_lo0_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_lo0_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(ftw_lo0_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(ftw_lo0_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_lo0_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_lo0_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_lo0_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_lo0_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_lo0_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_lo0_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_lo0_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_lo0_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_lo0_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_lo0_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_lo0_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_lo0_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_lo0_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_lo0_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_lo0_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_lo0_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_lo0_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_lo0_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_lo0_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_lo0_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_lo0_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_lo0_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_lo0_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_lo0_reg_reg[31]_i_1_n_0 ),
        .Q(ftw_lo0_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo0_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_lo0_reg_reg[47]_i_1_n_0 ),
        .Q(ftw_lo0_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \ftw_lo1_reg_reg[31]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ),
        .I1(sel0[4]),
        .I2(sel0[2]),
        .I3(\ftw_h1_reg_reg[47]_i_3_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\ftw_lo1_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \ftw_lo1_reg_reg[47]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[4]),
        .I2(sel0[2]),
        .I3(\ftw_h1_reg_reg[47]_i_3_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\ftw_lo1_reg_reg[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_lo1_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_lo1_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_lo1_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_lo1_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_lo1_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_lo1_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_lo1_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(ftw_lo1_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(ftw_lo1_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(ftw_lo1_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(ftw_lo1_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_lo1_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(ftw_lo1_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(ftw_lo1_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(ftw_lo1_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(ftw_lo1_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(ftw_lo1_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(ftw_lo1_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(ftw_lo1_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(ftw_lo1_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(ftw_lo1_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(ftw_lo1_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_lo1_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(ftw_lo1_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(ftw_lo1_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_lo1_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_lo1_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_lo1_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_lo1_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_lo1_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_lo1_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_lo1_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_lo1_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_lo1_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_lo1_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_lo1_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_lo1_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_lo1_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_lo1_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_lo1_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_lo1_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_lo1_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_lo1_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_lo1_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_lo1_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_lo1_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_lo1_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_lo1_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_lo1_reg_reg[31]_i_1_n_0 ),
        .Q(ftw_lo1_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_lo1_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_lo1_reg_reg[47]_i_1_n_0 ),
        .Q(ftw_lo1_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \ftw_on_reg_reg[31]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ),
        .I1(sel0[4]),
        .I2(sel0[1]),
        .I3(\ftw_on_reg_reg[47]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\ftw_on_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \ftw_on_reg_reg[47]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[4]),
        .I2(sel0[1]),
        .I3(\ftw_on_reg_reg[47]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\ftw_on_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \ftw_on_reg_reg[47]_i_2 
       (.I0(sel0[2]),
        .I1(sel0[6]),
        .I2(sel0[0]),
        .I3(sel0[5]),
        .O(\ftw_on_reg_reg[47]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_on_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_on_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_on_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_on_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_on_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_on_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_on_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(ftw_on_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(ftw_on_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(ftw_on_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(ftw_on_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_on_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(ftw_on_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(ftw_on_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(ftw_on_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(ftw_on_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(ftw_on_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(ftw_on_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(ftw_on_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(ftw_on_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(ftw_on_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(ftw_on_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_on_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(ftw_on_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(ftw_on_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_on_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_on_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_on_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_on_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_on_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_on_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_on_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_on_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_on_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_on_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_on_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_on_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_on_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_on_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_on_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_on_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_on_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_on_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_on_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_on_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_on_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_on_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_on_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_on_reg_reg[31]_i_1_n_0 ),
        .Q(ftw_on_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_on_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_on_reg_reg[47]_i_1_n_0 ),
        .Q(ftw_on_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ftw_slip_reg[31]_i_1 
       (.I0(control_reset_reg_i_2_n_0),
        .I1(\ftw_slip_reg[31]_i_2_n_0 ),
        .I2(\ftw_slip_reg[31]_i_3_n_0 ),
        .I3(sel0[1]),
        .I4(sel0[5]),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\ftw_slip_reg[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \ftw_slip_reg[31]_i_2 
       (.I0(sel0[4]),
        .I1(sel0[0]),
        .O(\ftw_slip_reg[31]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ftw_slip_reg[31]_i_3 
       (.I0(sel0[6]),
        .I1(sel0[3]),
        .O(\ftw_slip_reg[31]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[0] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ftw_slip_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[10] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(ftw_slip_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[11] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(ftw_slip_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[12] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(ftw_slip_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[13] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(ftw_slip_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[14] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(ftw_slip_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[15] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(ftw_slip_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[16] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(ftw_slip_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[17] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(ftw_slip_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[18] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(ftw_slip_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[19] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(ftw_slip_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[1] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ftw_slip_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[20] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(ftw_slip_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[21] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(ftw_slip_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[22] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(ftw_slip_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[23] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(ftw_slip_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[24] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(ftw_slip_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[25] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(ftw_slip_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[26] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(ftw_slip_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[27] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(ftw_slip_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[28] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(ftw_slip_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[29] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(ftw_slip_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[2] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ftw_slip_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[30] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(ftw_slip_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[31] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(ftw_slip_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[3] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ftw_slip_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[4] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ftw_slip_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[5] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ftw_slip_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[6] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ftw_slip_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[7] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ftw_slip_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[8] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(ftw_slip_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ftw_slip_reg_reg[9] 
       (.C(aclk),
        .CE(\ftw_slip_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(ftw_slip_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ftw_slip_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ftw_slip_reg[31]_i_1_n_0 ),
        .Q(ftw_slip_wack),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_delayComp_reg[31]_i_1 
       (.I0(control_reset_reg_i_2_n_0),
        .I1(sel0[0]),
        .I2(sel0[5]),
        .I3(\ftw_slip_reg[31]_i_3_n_0 ),
        .I4(\inputs_delayComp_reg[31]_i_2_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\inputs_delayComp_reg[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \inputs_delayComp_reg[31]_i_2 
       (.I0(sel0[1]),
        .I1(sel0[4]),
        .O(\inputs_delayComp_reg[31]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_delayComp_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_delayComp_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_delayComp_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_delayComp_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_delayComp_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_delayComp_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_delayComp_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[16] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(inputs_delayComp_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[17] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(inputs_delayComp_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[18] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(inputs_delayComp_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[19] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(inputs_delayComp_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_delayComp_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[20] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(inputs_delayComp_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[21] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(inputs_delayComp_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[22] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(inputs_delayComp_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[23] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(inputs_delayComp_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[24] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(inputs_delayComp_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[25] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(inputs_delayComp_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[26] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(inputs_delayComp_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[27] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(inputs_delayComp_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[28] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(inputs_delayComp_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[29] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(inputs_delayComp_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_delayComp_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[30] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(inputs_delayComp_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[31] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(inputs_delayComp_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_delayComp_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_delayComp_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_delayComp_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_delayComp_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_delayComp_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_delayComp_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_delayComp_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_delayComp_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_delayComp_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_delayComp_reg[31]_i_1_n_0 ),
        .Q(inputs_delayComp_wack),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_h_reg[15]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[0]),
        .I2(sel0[5]),
        .I3(\inputs_rate_reg[31]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\inputs_h_reg[15]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_h_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_h_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_h_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_h_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_h_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_h_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_h_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_h_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_h_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_h_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_h_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_h_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_h_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_h_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_h_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_h_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_h_reg[15]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_h_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_h_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_h_reg[15]_i_1_n_0 ),
        .Q(inputs_h_wack),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \inputs_offsetAM_reg_reg[31]_i_1 
       (.I0(sel0[5]),
        .I1(\ftw_h1_reg_reg[31]_i_2_n_0 ),
        .I2(sel0[0]),
        .I3(sel0[1]),
        .I4(\inputs_offsetAM_reg_reg[47]_i_2_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \inputs_offsetAM_reg_reg[47]_i_1 
       (.I0(sel0[5]),
        .I1(wr_adr_d0),
        .I2(wr_req_d0),
        .I3(\ftw_lo0_reg_reg[47]_i_2_n_0 ),
        .I4(\inputs_offsetAM_reg_reg[47]_i_2_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \inputs_offsetAM_reg_reg[47]_i_2 
       (.I0(sel0[3]),
        .I1(sel0[6]),
        .I2(sel0[4]),
        .I3(sel0[2]),
        .O(\inputs_offsetAM_reg_reg[47]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_offsetAM_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_offsetAM_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_offsetAM_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_offsetAM_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_offsetAM_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_offsetAM_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_offsetAM_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(inputs_offsetAM_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(inputs_offsetAM_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(inputs_offsetAM_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(inputs_offsetAM_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_offsetAM_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(inputs_offsetAM_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(inputs_offsetAM_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(inputs_offsetAM_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(inputs_offsetAM_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(inputs_offsetAM_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(inputs_offsetAM_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(inputs_offsetAM_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(inputs_offsetAM_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(inputs_offsetAM_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(inputs_offsetAM_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_offsetAM_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(inputs_offsetAM_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(inputs_offsetAM_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_offsetAM_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_offsetAM_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_offsetAM_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_offsetAM_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_offsetAM_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_offsetAM_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_offsetAM_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_offsetAM_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_offsetAM_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_offsetAM_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_offsetAM_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_offsetAM_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_offsetAM_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_offsetAM_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_offsetAM_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_offsetAM_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_offsetAM_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_offsetAM_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_offsetAM_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_offsetAM_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_offsetAM_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_offsetAM_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_offsetAM_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_offsetAM_reg_reg[31]_i_1_n_0 ),
        .Q(inputs_offsetAM_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetAM_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_offsetAM_reg_reg[47]_i_1_n_0 ),
        .Q(inputs_offsetAM_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_offsetFSK_reg_reg[31]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ),
        .I1(sel0[5]),
        .I2(sel0[1]),
        .I3(\inputs_offsetFSK_reg_reg[47]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_offsetFSK_reg_reg[47]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[5]),
        .I2(sel0[1]),
        .I3(\inputs_offsetFSK_reg_reg[47]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \inputs_offsetFSK_reg_reg[47]_i_2 
       (.I0(sel0[2]),
        .I1(sel0[6]),
        .I2(sel0[4]),
        .I3(sel0[0]),
        .O(\inputs_offsetFSK_reg_reg[47]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_offsetFSK_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_offsetFSK_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_offsetFSK_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_offsetFSK_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_offsetFSK_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_offsetFSK_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_offsetFSK_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(inputs_offsetFSK_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(inputs_offsetFSK_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(inputs_offsetFSK_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(inputs_offsetFSK_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_offsetFSK_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(inputs_offsetFSK_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(inputs_offsetFSK_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(inputs_offsetFSK_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(inputs_offsetFSK_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(inputs_offsetFSK_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(inputs_offsetFSK_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(inputs_offsetFSK_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(inputs_offsetFSK_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(inputs_offsetFSK_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(inputs_offsetFSK_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_offsetFSK_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(inputs_offsetFSK_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(inputs_offsetFSK_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_offsetFSK_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_offsetFSK_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_offsetFSK_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_offsetFSK_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_offsetFSK_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_offsetFSK_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_offsetFSK_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_offsetFSK_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_offsetFSK_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_offsetFSK_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_offsetFSK_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_offsetFSK_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_offsetFSK_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_offsetFSK_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_offsetFSK_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_offsetFSK_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_offsetFSK_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_offsetFSK_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_offsetFSK_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_offsetFSK_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_offsetFSK_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_offsetFSK_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_offsetFSK_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_offsetFSK_reg_reg[31]_i_1_n_0 ),
        .Q(inputs_offsetFSK_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetFSK_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_offsetFSK_reg_reg[47]_i_1_n_0 ),
        .Q(inputs_offsetFSK_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000001000)) 
    \inputs_offsetH1_reg_reg[31]_i_1 
       (.I0(sel0[2]),
        .I1(sel0[3]),
        .I2(sel0[5]),
        .I3(\ftw_h1_reg_reg[31]_i_2_n_0 ),
        .I4(\inputs_offsetH1_reg_reg[47]_i_2_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \inputs_offsetH1_reg_reg[47]_i_1 
       (.I0(\ftw_h1_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[5]),
        .I2(wr_adr_d0),
        .I3(wr_req_d0),
        .I4(\inputs_offsetH1_reg_reg[47]_i_2_n_0 ),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \inputs_offsetH1_reg_reg[47]_i_2 
       (.I0(sel0[1]),
        .I1(sel0[6]),
        .I2(sel0[4]),
        .I3(sel0[0]),
        .O(\inputs_offsetH1_reg_reg[47]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_offsetH1_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_offsetH1_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_offsetH1_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_offsetH1_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_offsetH1_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_offsetH1_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_offsetH1_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(inputs_offsetH1_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(inputs_offsetH1_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(inputs_offsetH1_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(inputs_offsetH1_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_offsetH1_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(inputs_offsetH1_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(inputs_offsetH1_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(inputs_offsetH1_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(inputs_offsetH1_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(inputs_offsetH1_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(inputs_offsetH1_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(inputs_offsetH1_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(inputs_offsetH1_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(inputs_offsetH1_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(inputs_offsetH1_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_offsetH1_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(inputs_offsetH1_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(inputs_offsetH1_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_offsetH1_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_offsetH1_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_offsetH1_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_offsetH1_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_offsetH1_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_offsetH1_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_offsetH1_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_offsetH1_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_offsetH1_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_offsetH1_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_offsetH1_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_offsetH1_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_offsetH1_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_offsetH1_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_offsetH1_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_offsetH1_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_offsetH1_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_offsetH1_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_offsetH1_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_offsetH1_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_offsetH1_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_offsetH1_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_offsetH1_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_offsetH1_reg_reg[31]_i_1_n_0 ),
        .Q(inputs_offsetH1_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_offsetH1_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_offsetH1_reg_reg[47]_i_1_n_0 ),
        .Q(inputs_offsetH1_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_pulseLengthAM_reg_reg[31]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ),
        .I1(sel0[2]),
        .I2(sel0[5]),
        .I3(\inputs_offsetH1_reg_reg[47]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_pulseLengthAM_reg_reg[47]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[47]_i_2_n_0 ),
        .I1(sel0[2]),
        .I2(sel0[5]),
        .I3(\inputs_offsetH1_reg_reg[47]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_pulseLengthAM_reg_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_pulseLengthAM_reg_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_pulseLengthAM_reg_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_pulseLengthAM_reg_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_pulseLengthAM_reg_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_pulseLengthAM_reg_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_pulseLengthAM_reg_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[16] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(inputs_pulseLengthAM_reg_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[17] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(inputs_pulseLengthAM_reg_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[18] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(inputs_pulseLengthAM_reg_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[19] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(inputs_pulseLengthAM_reg_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_pulseLengthAM_reg_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[20] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(inputs_pulseLengthAM_reg_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[21] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(inputs_pulseLengthAM_reg_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[22] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(inputs_pulseLengthAM_reg_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[23] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(inputs_pulseLengthAM_reg_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[24] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(inputs_pulseLengthAM_reg_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[25] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(inputs_pulseLengthAM_reg_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[26] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(inputs_pulseLengthAM_reg_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[27] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(inputs_pulseLengthAM_reg_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[28] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(inputs_pulseLengthAM_reg_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[29] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(inputs_pulseLengthAM_reg_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_pulseLengthAM_reg_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[30] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(inputs_pulseLengthAM_reg_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[31] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(inputs_pulseLengthAM_reg_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[32] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_pulseLengthAM_reg_o[32]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[33] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_pulseLengthAM_reg_o[33]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[34] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_pulseLengthAM_reg_o[34]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[35] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_pulseLengthAM_reg_o[35]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[36] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_pulseLengthAM_reg_o[36]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[37] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_pulseLengthAM_reg_o[37]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[38] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_pulseLengthAM_reg_o[38]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[39] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_pulseLengthAM_reg_o[39]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_pulseLengthAM_reg_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[40] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_pulseLengthAM_reg_o[40]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[41] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_pulseLengthAM_reg_o[41]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[42] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_pulseLengthAM_reg_o[42]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[43] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_pulseLengthAM_reg_o[43]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[44] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_pulseLengthAM_reg_o[44]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[45] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_pulseLengthAM_reg_o[45]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[46] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_pulseLengthAM_reg_o[46]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[47] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_pulseLengthAM_reg_o[47]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_pulseLengthAM_reg_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_pulseLengthAM_reg_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_pulseLengthAM_reg_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_pulseLengthAM_reg_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_pulseLengthAM_reg_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_reg_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_pulseLengthAM_reg_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_wack_reg[0] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_pulseLengthAM_reg_reg[31]_i_1_n_0 ),
        .Q(inputs_pulseLengthAM_wack[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_pulseLengthAM_wack_reg[1] 
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_pulseLengthAM_reg_reg[47]_i_1_n_0 ),
        .Q(inputs_pulseLengthAM_wack[1]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \inputs_rate_reg[31]_i_1 
       (.I0(\ftw_h1Prog_reg_reg[31]_i_2_n_0 ),
        .I1(sel0[0]),
        .I2(sel0[5]),
        .I3(\inputs_rate_reg[31]_i_2_n_0 ),
        .I4(\wr_adr_d0_reg_n_0_[10] ),
        .I5(\wr_adr_d0_reg_n_0_[11] ),
        .O(\inputs_rate_reg[31]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \inputs_rate_reg[31]_i_2 
       (.I0(sel0[2]),
        .I1(sel0[6]),
        .I2(sel0[4]),
        .I3(sel0[1]),
        .O(\inputs_rate_reg[31]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[0] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(inputs_rate_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[10] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[10] ),
        .Q(inputs_rate_o[10]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[11] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[11] ),
        .Q(inputs_rate_o[11]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[12] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[12] ),
        .Q(inputs_rate_o[12]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[13] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[13] ),
        .Q(inputs_rate_o[13]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[14] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[14] ),
        .Q(inputs_rate_o[14]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[15] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[15] ),
        .Q(inputs_rate_o[15]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[16] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[16] ),
        .Q(inputs_rate_o[16]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[17] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[17] ),
        .Q(inputs_rate_o[17]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[18] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[18] ),
        .Q(inputs_rate_o[18]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[19] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[19] ),
        .Q(inputs_rate_o[19]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[1] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(p_0_in),
        .Q(inputs_rate_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[20] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[20] ),
        .Q(inputs_rate_o[20]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[21] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[21] ),
        .Q(inputs_rate_o[21]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[22] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[22] ),
        .Q(inputs_rate_o[22]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[23] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[23] ),
        .Q(inputs_rate_o[23]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[24] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[24] ),
        .Q(inputs_rate_o[24]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[25] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[25] ),
        .Q(inputs_rate_o[25]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[26] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[26] ),
        .Q(inputs_rate_o[26]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[27] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[27] ),
        .Q(inputs_rate_o[27]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[28] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[28] ),
        .Q(inputs_rate_o[28]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[29] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[29] ),
        .Q(inputs_rate_o[29]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[2] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(inputs_rate_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[30] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[30] ),
        .Q(inputs_rate_o[30]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[31] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[31] ),
        .Q(inputs_rate_o[31]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[3] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(inputs_rate_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[4] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(inputs_rate_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[5] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(inputs_rate_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[6] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(p_2_in),
        .Q(inputs_rate_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[7] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(inputs_rate_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[8] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[8] ),
        .Q(inputs_rate_o[8]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \inputs_rate_reg_reg[9] 
       (.C(aclk),
        .CE(\inputs_rate_reg[31]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[9] ),
        .Q(inputs_rate_o[9]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    inputs_rate_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\inputs_rate_reg[31]_i_1_n_0 ),
        .Q(inputs_rate_wack),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \ipInfo_echo_echo_reg[7]_i_1 
       (.I0(\ipInfo_echo_echo_reg[7]_i_2_n_0 ),
        .I1(sel0[0]),
        .I2(sel0[6]),
        .I3(sel0[5]),
        .I4(sel0[4]),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(\ipInfo_echo_echo_reg[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'hFFFFEFFF)) 
    \ipInfo_echo_echo_reg[7]_i_2 
       (.I0(sel0[2]),
        .I1(sel0[3]),
        .I2(sel0[1]),
        .I3(wr_req_d0),
        .I4(wr_adr_d0),
        .O(\ipInfo_echo_echo_reg[7]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \ipInfo_echo_echo_reg[7]_i_3 
       (.I0(\wr_adr_d0_reg_n_0_[11] ),
        .I1(\wr_adr_d0_reg_n_0_[10] ),
        .O(\ipInfo_echo_echo_reg[7]_i_3_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[0] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[0] ),
        .Q(ipInfo_echo_echo_o[0]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[1] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(p_0_in),
        .Q(ipInfo_echo_echo_o[1]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[2] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[2] ),
        .Q(ipInfo_echo_echo_o[2]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[3] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[3] ),
        .Q(ipInfo_echo_echo_o[3]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[4] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[4] ),
        .Q(ipInfo_echo_echo_o[4]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[5] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[5] ),
        .Q(ipInfo_echo_echo_o[5]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[6] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(p_2_in),
        .Q(ipInfo_echo_echo_o[6]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    \ipInfo_echo_echo_reg_reg[7] 
       (.C(aclk),
        .CE(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .D(\wr_dat_d0_reg_n_0_[7] ),
        .Q(ipInfo_echo_echo_o[7]),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    ipInfo_echo_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(\ipInfo_echo_echo_reg[7]_i_1_n_0 ),
        .Q(ipInfo_echo_wack),
        .R(axi_wdone_i_1_n_0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    presentLatch_am_reg_i_1
       (.I0(p_0_in),
        .I1(presentLatch_wack_i_1_n_0),
        .I2(presentLatch_am_i),
        .I3(p_1_in[1]),
        .O(presentLatch_am_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_am_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_am_reg_i_1_n_0),
        .Q(p_1_in[1]),
        .R(axi_wdone_i_1_n_0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    presentLatch_coef_reg_i_1
       (.I0(\wr_dat_d0_reg_n_0_[3] ),
        .I1(presentLatch_wack_i_1_n_0),
        .I2(presentLatch_coef_i),
        .I3(p_1_in[3]),
        .O(presentLatch_coef_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_coef_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_coef_reg_i_1_n_0),
        .Q(p_1_in[3]),
        .R(axi_wdone_i_1_n_0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    presentLatch_extReset_reg_i_1
       (.I0(\wr_dat_d0_reg_n_0_[5] ),
        .I1(presentLatch_wack_i_1_n_0),
        .I2(presentLatch_extReset_i),
        .I3(p_1_in[5]),
        .O(presentLatch_extReset_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_extReset_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_extReset_reg_i_1_n_0),
        .Q(p_1_in[5]),
        .R(axi_wdone_i_1_n_0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    presentLatch_frev_reg_i_1
       (.I0(\wr_dat_d0_reg_n_0_[0] ),
        .I1(presentLatch_wack_i_1_n_0),
        .I2(presentLatch_frev_i),
        .I3(p_1_in[0]),
        .O(presentLatch_frev_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_frev_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_frev_reg_i_1_n_0),
        .Q(p_1_in[0]),
        .R(axi_wdone_i_1_n_0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    presentLatch_load_reg_i_1
       (.I0(\wr_dat_d0_reg_n_0_[4] ),
        .I1(presentLatch_wack_i_1_n_0),
        .I2(presentLatch_load_i),
        .I3(p_1_in[4]),
        .O(presentLatch_load_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_load_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_load_reg_i_1_n_0),
        .Q(p_1_in[4]),
        .R(axi_wdone_i_1_n_0));
  LUT4 #(
    .INIT(16'hF7F0)) 
    presentLatch_tw_reg_i_1
       (.I0(\wr_dat_d0_reg_n_0_[2] ),
        .I1(presentLatch_wack_i_1_n_0),
        .I2(presentLatch_tw_i),
        .I3(p_1_in[2]),
        .O(presentLatch_tw_reg_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_tw_reg_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_tw_reg_i_1_n_0),
        .Q(p_1_in[2]),
        .R(axi_wdone_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    presentLatch_wack_i_1
       (.I0(presentLatch_wack_i_2_n_0),
        .I1(sel0[0]),
        .I2(sel0[1]),
        .I3(sel0[5]),
        .I4(sel0[4]),
        .I5(\ipInfo_echo_echo_reg[7]_i_3_n_0 ),
        .O(presentLatch_wack_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    presentLatch_wack_i_2
       (.I0(sel0[2]),
        .I1(sel0[3]),
        .I2(wr_req_d0),
        .I3(wr_adr_d0),
        .I4(sel0[6]),
        .O(presentLatch_wack_i_2_n_0));
  FDRE #(
    .INIT(1'b0)) 
    presentLatch_wack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(presentLatch_wack_i_1_n_0),
        .Q(presentLatch_wack),
        .R(axi_wdone_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rd_ack_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(rd_req),
        .Q(rd_ack),
        .R(axi_wdone_i_1_n_0));
  LUT3 #(
    .INIT(8'h20)) 
    \rd_addr[9]_i_1 
       (.I0(areset_n),
        .I1(axi_arset),
        .I2(arvalid),
        .O(rd_addr));
  (* ORIG_CELL_NAME = "rd_addr_reg[2]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[2] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[0]),
        .Q(\rd_addr_reg_n_0_[2] ),
        .R(\<const0> ));
  (* ORIG_CELL_NAME = "rd_addr_reg[2]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[2]_rep 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[0]),
        .Q(\rd_addr_reg[2]_rep_n_0 ),
        .R(\<const0> ));
  (* ORIG_CELL_NAME = "rd_addr_reg[2]" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[2]_rep__0 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[0]),
        .Q(\rd_addr_reg[2]_rep__0_n_0 ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[3] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[1]),
        .Q(\rd_addr_reg_n_0_[3] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[4] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[2]),
        .Q(\rd_addr_reg_n_0_[4] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[5] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[3]),
        .Q(\rd_addr_reg_n_0_[5] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[6] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[4]),
        .Q(\rd_addr_reg_n_0_[6] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[7] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[5]),
        .Q(\rd_addr_reg_n_0_[7] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[8] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[6]),
        .Q(\rd_addr_reg_n_0_[8] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_addr_reg[9] 
       (.C(aclk),
        .CE(rd_addr),
        .D(araddr[7]),
        .Q(\rd_addr_reg_n_0_[9] ),
        .R(\<const0> ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[0]_i_1 
       (.I0(\rd_data[0]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[0]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[0]_i_4_n_0 ),
        .O(\rd_data[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_10 
       (.I0(inputs_offsetAM_reg_o[32]),
        .I1(inputs_offsetAM_reg_o[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[32]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[0]),
        .O(\rd_data[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_11 
       (.I0(inputs_h_o[0]),
        .I1(inputs_rate_o[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[32]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[0]),
        .O(\rd_data[0]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[0]_i_12 
       (.I0(ftw_slip_o[0]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[32]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[0]),
        .O(\rd_data[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_13 
       (.I0(ftw_lo0_reg_o[32]),
        .I1(ftw_lo0_reg_o[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[32]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[0]),
        .O(\rd_data[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_14 
       (.I0(ftw_h1Prog_reg_o[32]),
        .I1(ftw_h1Prog_reg_o[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[32]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[0]),
        .O(\rd_data[0]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \rd_data[0]_i_15 
       (.I0(status_interlock_i),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(control_reset_o),
        .I3(\rd_data[6]_i_17_n_0 ),
        .I4(ipInfo_echo_echo_o[0]),
        .O(\rd_data[0]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[0]_i_16 
       (.I0(ipInfo_memMapVersion_i[0]),
        .I1(ipInfo_firmwareVersion_i[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[0]),
        .O(\rd_data[0]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_2 
       (.I0(\rd_data[0]_i_5_n_0 ),
        .I1(\rd_data[0]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[0]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[0]_i_8_n_0 ),
        .O(\rd_data[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_3 
       (.I0(\rd_data[0]_i_9_n_0 ),
        .I1(\rd_data[0]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[0]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[0]_i_12_n_0 ),
        .O(\rd_data[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_4 
       (.I0(\rd_data[0]_i_13_n_0 ),
        .I1(\rd_data[0]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[0]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[0]_i_16_n_0 ),
        .O(\rd_data[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[0]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[32]),
        .I1(readback_phaseH1Comp_reg_i[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[0]),
        .I4(readback_coef_i[0]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[0]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[0]_i_6 
       (.I0(p_1_in[0]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(phases_if1_reg_i[32]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(phases_if1_reg_i[0]),
        .O(\rd_data[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_7 
       (.I0(phases_if0_reg_i[32]),
        .I1(phases_if0_reg_i[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[32]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[0]),
        .O(\rd_data[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[0]_i_8 
       (.I0(phases_h1Main_reg_i[32]),
        .I1(phases_h1Main_reg_i[0]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[32]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[0]),
        .O(\rd_data[0]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[0]_i_9 
       (.I0(inputs_delayComp_o[0]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[32]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[0]),
        .O(\rd_data[0]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[10]_i_1 
       (.I0(\rd_data[10]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[10]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[10]_i_4_n_0 ),
        .O(\rd_data[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_10 
       (.I0(inputs_offsetAM_reg_o[42]),
        .I1(inputs_offsetAM_reg_o[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[42]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[10]),
        .O(\rd_data[10]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_11 
       (.I0(inputs_h_o[10]),
        .I1(inputs_rate_o[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[42]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[10]),
        .O(\rd_data[10]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[10]_i_12 
       (.I0(ftw_slip_o[10]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[42]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[10]),
        .O(\rd_data[10]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_13 
       (.I0(ftw_lo0_reg_o[42]),
        .I1(ftw_lo0_reg_o[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[42]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[10]),
        .O(\rd_data[10]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_14 
       (.I0(ftw_h1Prog_reg_o[42]),
        .I1(ftw_h1Prog_reg_o[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[42]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[10]),
        .O(\rd_data[10]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[10]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(control_selWrDftwH1slip_o),
        .O(\rd_data[10]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[10]_i_16 
       (.I0(ipInfo_memMapVersion_i[10]),
        .I1(ipInfo_firmwareVersion_i[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[10]),
        .O(\rd_data[10]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_2 
       (.I0(\rd_data[10]_i_5_n_0 ),
        .I1(\rd_data[10]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[10]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[10]_i_8_n_0 ),
        .O(\rd_data[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_3 
       (.I0(\rd_data[10]_i_9_n_0 ),
        .I1(\rd_data[10]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[10]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[10]_i_12_n_0 ),
        .O(\rd_data[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_4 
       (.I0(\rd_data[10]_i_13_n_0 ),
        .I1(\rd_data[10]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[10]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[10]_i_16_n_0 ),
        .O(\rd_data[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[10]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[42]),
        .I1(readback_phaseH1Comp_reg_i[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[10]),
        .I4(readback_coef_i[10]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[10]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[10]_i_6 
       (.I0(phases_if1_reg_i[10]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[42]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[10]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_7 
       (.I0(phases_if0_reg_i[42]),
        .I1(phases_if0_reg_i[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[42]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[10]),
        .O(\rd_data[10]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[10]_i_8 
       (.I0(phases_h1Main_reg_i[42]),
        .I1(phases_h1Main_reg_i[10]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[42]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[10]),
        .O(\rd_data[10]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[10]_i_9 
       (.I0(inputs_delayComp_o[10]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[42]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[10]),
        .O(\rd_data[10]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[11]_i_1 
       (.I0(\rd_data[11]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[11]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[11]_i_4_n_0 ),
        .O(\rd_data[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_10 
       (.I0(inputs_offsetAM_reg_o[43]),
        .I1(inputs_offsetAM_reg_o[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[43]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[11]),
        .O(\rd_data[11]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_11 
       (.I0(inputs_h_o[11]),
        .I1(inputs_rate_o[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[43]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[11]),
        .O(\rd_data[11]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[11]_i_12 
       (.I0(ftw_slip_o[11]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[43]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[11]),
        .O(\rd_data[11]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_13 
       (.I0(ftw_lo0_reg_o[43]),
        .I1(ftw_lo0_reg_o[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[43]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[11]),
        .O(\rd_data[11]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_14 
       (.I0(ftw_h1Prog_reg_o[43]),
        .I1(ftw_h1Prog_reg_o[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[43]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[11]),
        .O(\rd_data[11]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[11]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(control_selDftwH1slip_o),
        .O(\rd_data[11]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[11]_i_16 
       (.I0(ipInfo_memMapVersion_i[11]),
        .I1(ipInfo_firmwareVersion_i[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[11]),
        .O(\rd_data[11]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_2 
       (.I0(\rd_data[11]_i_5_n_0 ),
        .I1(\rd_data[11]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[11]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[11]_i_8_n_0 ),
        .O(\rd_data[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_3 
       (.I0(\rd_data[11]_i_9_n_0 ),
        .I1(\rd_data[11]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[11]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[11]_i_12_n_0 ),
        .O(\rd_data[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_4 
       (.I0(\rd_data[11]_i_13_n_0 ),
        .I1(\rd_data[11]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[11]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[11]_i_16_n_0 ),
        .O(\rd_data[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[11]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[43]),
        .I1(readback_phaseH1Comp_reg_i[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[11]),
        .I4(readback_coef_i[11]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[11]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[11]_i_6 
       (.I0(phases_if1_reg_i[11]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[43]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[11]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_7 
       (.I0(phases_if0_reg_i[43]),
        .I1(phases_if0_reg_i[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[43]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[11]),
        .O(\rd_data[11]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[11]_i_8 
       (.I0(phases_h1Main_reg_i[43]),
        .I1(phases_h1Main_reg_i[11]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[43]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[11]),
        .O(\rd_data[11]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[11]_i_9 
       (.I0(inputs_delayComp_o[11]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[43]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[11]),
        .O(\rd_data[11]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[12]_i_1 
       (.I0(\rd_data[12]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[12]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[12]_i_4_n_0 ),
        .O(\rd_data[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_10 
       (.I0(inputs_offsetAM_reg_o[44]),
        .I1(inputs_offsetAM_reg_o[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[44]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[12]),
        .O(\rd_data[12]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_11 
       (.I0(inputs_h_o[12]),
        .I1(inputs_rate_o[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[44]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[12]),
        .O(\rd_data[12]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[12]_i_12 
       (.I0(ftw_slip_o[12]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[44]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[12]),
        .O(\rd_data[12]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_13 
       (.I0(ftw_lo0_reg_o[44]),
        .I1(ftw_lo0_reg_o[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[44]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[12]),
        .O(\rd_data[12]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_14 
       (.I0(ftw_h1Prog_reg_o[44]),
        .I1(ftw_h1Prog_reg_o[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[44]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[12]),
        .O(\rd_data[12]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[12]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(control_selFtwH1prog_o),
        .O(\rd_data[12]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[12]_i_16 
       (.I0(ipInfo_memMapVersion_i[12]),
        .I1(ipInfo_firmwareVersion_i[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[12]),
        .O(\rd_data[12]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_2 
       (.I0(\rd_data[12]_i_5_n_0 ),
        .I1(\rd_data[12]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[12]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[12]_i_8_n_0 ),
        .O(\rd_data[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_3 
       (.I0(\rd_data[12]_i_9_n_0 ),
        .I1(\rd_data[12]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[12]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[12]_i_12_n_0 ),
        .O(\rd_data[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_4 
       (.I0(\rd_data[12]_i_13_n_0 ),
        .I1(\rd_data[12]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[12]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[12]_i_16_n_0 ),
        .O(\rd_data[12]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[12]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[44]),
        .I1(readback_phaseH1Comp_reg_i[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[12]),
        .I4(readback_coef_i[12]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[12]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[12]_i_6 
       (.I0(phases_if1_reg_i[12]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[44]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[12]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_7 
       (.I0(phases_if0_reg_i[44]),
        .I1(phases_if0_reg_i[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[44]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[12]),
        .O(\rd_data[12]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[12]_i_8 
       (.I0(phases_h1Main_reg_i[44]),
        .I1(phases_h1Main_reg_i[12]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[44]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[12]),
        .O(\rd_data[12]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[12]_i_9 
       (.I0(inputs_delayComp_o[12]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[44]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[12]),
        .O(\rd_data[12]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[13]_i_1 
       (.I0(\rd_data[13]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[13]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[13]_i_4_n_0 ),
        .O(\rd_data[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_10 
       (.I0(inputs_offsetAM_reg_o[45]),
        .I1(inputs_offsetAM_reg_o[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[45]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[13]),
        .O(\rd_data[13]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_11 
       (.I0(inputs_h_o[13]),
        .I1(inputs_rate_o[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[45]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[13]),
        .O(\rd_data[13]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[13]_i_12 
       (.I0(ftw_slip_o[13]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[45]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[13]),
        .O(\rd_data[13]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_13 
       (.I0(ftw_lo0_reg_o[45]),
        .I1(ftw_lo0_reg_o[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[45]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[13]),
        .O(\rd_data[13]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_14 
       (.I0(ftw_h1Prog_reg_o[45]),
        .I1(ftw_h1Prog_reg_o[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[45]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[13]),
        .O(\rd_data[13]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[13]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(control_slipSign_o),
        .O(\rd_data[13]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[13]_i_16 
       (.I0(ipInfo_memMapVersion_i[13]),
        .I1(ipInfo_firmwareVersion_i[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[13]),
        .O(\rd_data[13]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_2 
       (.I0(\rd_data[13]_i_5_n_0 ),
        .I1(\rd_data[13]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[13]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[13]_i_8_n_0 ),
        .O(\rd_data[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_3 
       (.I0(\rd_data[13]_i_9_n_0 ),
        .I1(\rd_data[13]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[13]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[13]_i_12_n_0 ),
        .O(\rd_data[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_4 
       (.I0(\rd_data[13]_i_13_n_0 ),
        .I1(\rd_data[13]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[13]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[13]_i_16_n_0 ),
        .O(\rd_data[13]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[13]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[45]),
        .I1(readback_phaseH1Comp_reg_i[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[13]),
        .I4(readback_coef_i[13]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[13]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[13]_i_6 
       (.I0(phases_if1_reg_i[13]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[45]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[13]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_7 
       (.I0(phases_if0_reg_i[45]),
        .I1(phases_if0_reg_i[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[45]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[13]),
        .O(\rd_data[13]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[13]_i_8 
       (.I0(phases_h1Main_reg_i[45]),
        .I1(phases_h1Main_reg_i[13]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[45]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[13]),
        .O(\rd_data[13]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[13]_i_9 
       (.I0(inputs_delayComp_o[13]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[45]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[13]),
        .O(\rd_data[13]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[14]_i_1 
       (.I0(\rd_data[14]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[14]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[14]_i_4_n_0 ),
        .O(\rd_data[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_10 
       (.I0(inputs_offsetAM_reg_o[46]),
        .I1(inputs_offsetAM_reg_o[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[46]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[14]),
        .O(\rd_data[14]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_11 
       (.I0(inputs_h_o[14]),
        .I1(inputs_rate_o[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[46]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[14]),
        .O(\rd_data[14]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[14]_i_12 
       (.I0(ftw_slip_o[14]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[46]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[14]),
        .O(\rd_data[14]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_13 
       (.I0(ftw_lo0_reg_o[46]),
        .I1(ftw_lo0_reg_o[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[46]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[14]),
        .O(\rd_data[14]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_14 
       (.I0(ftw_h1Prog_reg_o[46]),
        .I1(ftw_h1Prog_reg_o[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[46]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[14]),
        .O(\rd_data[14]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[14]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(control_enableFSK_o),
        .O(\rd_data[14]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[14]_i_16 
       (.I0(ipInfo_memMapVersion_i[14]),
        .I1(ipInfo_firmwareVersion_i[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[14]),
        .O(\rd_data[14]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_2 
       (.I0(\rd_data[14]_i_5_n_0 ),
        .I1(\rd_data[14]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[14]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[14]_i_8_n_0 ),
        .O(\rd_data[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_3 
       (.I0(\rd_data[14]_i_9_n_0 ),
        .I1(\rd_data[14]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[14]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[14]_i_12_n_0 ),
        .O(\rd_data[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_4 
       (.I0(\rd_data[14]_i_13_n_0 ),
        .I1(\rd_data[14]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[14]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[14]_i_16_n_0 ),
        .O(\rd_data[14]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[14]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[46]),
        .I1(readback_phaseH1Comp_reg_i[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[14]),
        .I4(readback_coef_i[14]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[14]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[14]_i_6 
       (.I0(phases_if1_reg_i[14]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[46]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[14]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_7 
       (.I0(phases_if0_reg_i[46]),
        .I1(phases_if0_reg_i[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[46]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[14]),
        .O(\rd_data[14]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[14]_i_8 
       (.I0(phases_h1Main_reg_i[46]),
        .I1(phases_h1Main_reg_i[14]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[46]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[14]),
        .O(\rd_data[14]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[14]_i_9 
       (.I0(inputs_delayComp_o[14]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[46]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[14]),
        .O(\rd_data[14]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[15]_i_1 
       (.I0(\rd_data[15]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[15]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[15]_i_4_n_0 ),
        .O(\rd_data[15]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[15]_i_10 
       (.I0(inputs_delayComp_o[15]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[47]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[15]),
        .O(\rd_data[15]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_11 
       (.I0(inputs_offsetAM_reg_o[47]),
        .I1(inputs_offsetAM_reg_o[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[47]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[15]),
        .O(\rd_data[15]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_12 
       (.I0(inputs_h_o[15]),
        .I1(inputs_rate_o[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[47]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[15]),
        .O(\rd_data[15]_i_12_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[15]_i_13 
       (.I0(ftw_slip_o[15]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[47]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[15]),
        .O(\rd_data[15]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_14 
       (.I0(ftw_lo0_reg_o[47]),
        .I1(ftw_lo0_reg_o[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[47]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[15]),
        .O(\rd_data[15]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_15 
       (.I0(ftw_h1Prog_reg_o[47]),
        .I1(ftw_h1Prog_reg_o[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[47]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[15]),
        .O(\rd_data[15]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[15]_i_16 
       (.I0(ipInfo_memMapVersion_i[15]),
        .I1(ipInfo_firmwareVersion_i[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[15]),
        .O(\rd_data[15]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_2 
       (.I0(\rd_data[15]_i_5_n_0 ),
        .I1(\rd_data[15]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[15]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[15]_i_9_n_0 ),
        .O(\rd_data[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_3 
       (.I0(\rd_data[15]_i_10_n_0 ),
        .I1(\rd_data[15]_i_11_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[15]_i_12_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[15]_i_13_n_0 ),
        .O(\rd_data[15]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hA0A0CFC0)) 
    \rd_data[15]_i_4 
       (.I0(\rd_data[15]_i_14_n_0 ),
        .I1(\rd_data[15]_i_15_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[15]_i_16_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[15]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[15]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[47]),
        .I1(readback_phaseH1Comp_reg_i[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[15]),
        .I4(readback_coef_i[15]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[15]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[15]_i_6 
       (.I0(phases_if1_reg_i[15]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[47]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[15]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_7 
       (.I0(phases_if0_reg_i[47]),
        .I1(phases_if0_reg_i[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[47]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[15]),
        .O(\rd_data[15]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hFF0A0FFE)) 
    \rd_data[15]_i_8 
       (.I0(\rd_addr_reg_n_0_[6] ),
        .I1(\rd_addr_reg_n_0_[5] ),
        .I2(\rd_addr_reg_n_0_[8] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(\rd_addr_reg_n_0_[7] ),
        .O(\rd_data[15]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[15]_i_9 
       (.I0(phases_h1Main_reg_i[47]),
        .I1(phases_h1Main_reg_i[15]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[47]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[15]),
        .O(\rd_data[15]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[16]_i_1 
       (.I0(\rd_data_reg[16]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[16]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[16]_i_4_n_0 ),
        .O(\rd_data[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[16]_i_10 
       (.I0(ftw_lo0_reg_o[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[16]_i_16_n_0 ),
        .O(\rd_data[16]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[16]_i_11 
       (.I0(phases_h1Main_reg_i[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[16]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[16]_i_12 
       (.I0(readback_tw_i[16]),
        .I1(readback_coef_i[16]),
        .I2(\rd_addr_reg[2]_rep_n_0 ),
        .O(data22[16]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[16]_i_13 
       (.I0(ftw_slip_o[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[16]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[16]_i_14 
       (.I0(inputs_offsetAM_reg_o[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[16]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data[16]_i_15 
       (.I0(ipInfo_memMapVersion_i[16]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(ipInfo_firmwareVersion_i[16]),
        .O(rd_dat_d0[16]));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[16]_i_16 
       (.I0(ftw_h1Prog_reg_o[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[16]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[16]_i_5 
       (.I0(phases_if0_reg_i[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[16]_i_11_n_0 ),
        .O(\rd_data[16]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[16]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[16]),
        .I1(data22[16]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(phases_if1_reg_i[16]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[16]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[16]_i_7 
       (.I0(inputs_rate_o[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[16]_i_13_n_0 ),
        .O(\rd_data[16]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[16]_i_8 
       (.I0(inputs_delayComp_o[16]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[16]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[16]_i_14_n_0 ),
        .O(\rd_data[16]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h3033B8003000B800)) 
    \rd_data[16]_i_9 
       (.I0(control_enableSlip_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(rd_dat_d0[16]),
        .I3(\rd_data[31]_i_14_n_0 ),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ipInfo_ident_i[16]),
        .O(\rd_data[16]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[17]_i_1 
       (.I0(\rd_data_reg[17]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[17]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[17]_i_4_n_0 ),
        .O(\rd_data[17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[17]_i_10 
       (.I0(ftw_lo0_reg_o[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[17]_i_15_n_0 ),
        .O(\rd_data[17]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[17]_i_11 
       (.I0(phases_h1Main_reg_i[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[17]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[17]_i_12 
       (.I0(readback_tw_i[17]),
        .I1(readback_coef_i[17]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[17]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[17]_i_13 
       (.I0(ftw_slip_o[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[17]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[17]_i_14 
       (.I0(inputs_offsetAM_reg_o[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[17]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[17]_i_15 
       (.I0(ftw_h1Prog_reg_o[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[17]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[17]_i_5 
       (.I0(phases_if0_reg_i[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[17]_i_11_n_0 ),
        .O(\rd_data[17]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[17]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[17]),
        .I1(data22[17]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[17]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[17]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[17]_i_7 
       (.I0(inputs_rate_o[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[17]_i_13_n_0 ),
        .O(\rd_data[17]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[17]_i_8 
       (.I0(inputs_delayComp_o[17]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[17]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[17]_i_14_n_0 ),
        .O(\rd_data[17]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FDAD5D0D)) 
    \rd_data[17]_i_9 
       (.I0(\rd_addr_reg_n_0_[2] ),
        .I1(ipInfo_ident_i[17]),
        .I2(\rd_data[31]_i_14_n_0 ),
        .I3(ipInfo_firmwareVersion_i[17]),
        .I4(ipInfo_memMapVersion_i[17]),
        .I5(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[17]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[18]_i_1 
       (.I0(\rd_data_reg[18]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[18]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[18]_i_4_n_0 ),
        .O(\rd_data[18]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[18]_i_10 
       (.I0(ftw_lo0_reg_o[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[18]_i_16_n_0 ),
        .O(\rd_data[18]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[18]_i_11 
       (.I0(phases_h1Main_reg_i[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[18]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[18]_i_12 
       (.I0(readback_tw_i[18]),
        .I1(readback_coef_i[18]),
        .I2(\rd_addr_reg[2]_rep_n_0 ),
        .O(data22[18]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[18]_i_13 
       (.I0(ftw_slip_o[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[18]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[18]_i_14 
       (.I0(inputs_offsetAM_reg_o[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[18]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data[18]_i_15 
       (.I0(ipInfo_memMapVersion_i[18]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(ipInfo_firmwareVersion_i[18]),
        .O(rd_dat_d0[18]));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[18]_i_16 
       (.I0(ftw_h1Prog_reg_o[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[18]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[18]_i_5 
       (.I0(phases_if0_reg_i[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[18]_i_11_n_0 ),
        .O(\rd_data[18]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[18]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[18]),
        .I1(data22[18]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(phases_if1_reg_i[18]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[18]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[18]_i_7 
       (.I0(inputs_rate_o[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[18]_i_13_n_0 ),
        .O(\rd_data[18]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[18]_i_8 
       (.I0(inputs_delayComp_o[18]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[18]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[18]_i_14_n_0 ),
        .O(\rd_data[18]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h3033B8003000B800)) 
    \rd_data[18]_i_9 
       (.I0(control_signIF0_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(rd_dat_d0[18]),
        .I3(\rd_data[31]_i_14_n_0 ),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ipInfo_ident_i[18]),
        .O(\rd_data[18]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[19]_i_1 
       (.I0(\rd_data_reg[19]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[19]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[19]_i_4_n_0 ),
        .O(\rd_data[19]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[19]_i_10 
       (.I0(ftw_lo0_reg_o[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[19]_i_16_n_0 ),
        .O(\rd_data[19]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[19]_i_11 
       (.I0(phases_h1Main_reg_i[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[19]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[19]_i_12 
       (.I0(readback_tw_i[19]),
        .I1(readback_coef_i[19]),
        .I2(\rd_addr_reg[2]_rep_n_0 ),
        .O(data22[19]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[19]_i_13 
       (.I0(ftw_slip_o[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[19]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[19]_i_14 
       (.I0(inputs_offsetAM_reg_o[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[19]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data[19]_i_15 
       (.I0(ipInfo_memMapVersion_i[19]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(ipInfo_firmwareVersion_i[19]),
        .O(rd_dat_d0[19]));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[19]_i_16 
       (.I0(ftw_h1Prog_reg_o[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[19]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[19]_i_5 
       (.I0(phases_if0_reg_i[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[19]_i_11_n_0 ),
        .O(\rd_data[19]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[19]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[19]),
        .I1(data22[19]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(phases_if1_reg_i[19]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[19]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[19]_i_7 
       (.I0(inputs_rate_o[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[19]_i_13_n_0 ),
        .O(\rd_data[19]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[19]_i_8 
       (.I0(inputs_delayComp_o[19]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[19]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[19]_i_14_n_0 ),
        .O(\rd_data[19]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h3033B8003000B800)) 
    \rd_data[19]_i_9 
       (.I0(control_signIF1_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(rd_dat_d0[19]),
        .I3(\rd_data[31]_i_14_n_0 ),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ipInfo_ident_i[19]),
        .O(\rd_data[19]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[1]_i_1 
       (.I0(\rd_data[1]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[1]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[1]_i_4_n_0 ),
        .O(\rd_data[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_10 
       (.I0(inputs_offsetAM_reg_o[33]),
        .I1(inputs_offsetAM_reg_o[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[33]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[1]),
        .O(\rd_data[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_11 
       (.I0(inputs_h_o[1]),
        .I1(inputs_rate_o[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[33]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[1]),
        .O(\rd_data[1]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[1]_i_12 
       (.I0(ftw_slip_o[1]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[33]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[1]),
        .O(\rd_data[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_13 
       (.I0(ftw_lo0_reg_o[33]),
        .I1(ftw_lo0_reg_o[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[33]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[1]),
        .O(\rd_data[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_14 
       (.I0(ftw_h1Prog_reg_o[33]),
        .I1(ftw_h1Prog_reg_o[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[33]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[1]),
        .O(\rd_data[1]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rd_data[1]_i_15 
       (.I0(ipInfo_echo_echo_o[1]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .O(\rd_data[1]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[1]_i_16 
       (.I0(ipInfo_memMapVersion_i[1]),
        .I1(ipInfo_firmwareVersion_i[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[1]),
        .O(\rd_data[1]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_2 
       (.I0(\rd_data[1]_i_5_n_0 ),
        .I1(\rd_data[1]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[1]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[1]_i_8_n_0 ),
        .O(\rd_data[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_3 
       (.I0(\rd_data[1]_i_9_n_0 ),
        .I1(\rd_data[1]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[1]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[1]_i_12_n_0 ),
        .O(\rd_data[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_4 
       (.I0(\rd_data[1]_i_13_n_0 ),
        .I1(\rd_data[1]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[1]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[1]_i_16_n_0 ),
        .O(\rd_data[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[1]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[33]),
        .I1(readback_phaseH1Comp_reg_i[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[1]),
        .I4(readback_coef_i[1]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[1]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[1]_i_6 
       (.I0(p_1_in[1]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(phases_if1_reg_i[33]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(phases_if1_reg_i[1]),
        .O(\rd_data[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_7 
       (.I0(phases_if0_reg_i[33]),
        .I1(phases_if0_reg_i[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[33]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[1]),
        .O(\rd_data[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[1]_i_8 
       (.I0(phases_h1Main_reg_i[33]),
        .I1(phases_h1Main_reg_i[1]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[33]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[1]),
        .O(\rd_data[1]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[1]_i_9 
       (.I0(inputs_delayComp_o[1]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[33]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[1]),
        .O(\rd_data[1]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[20]_i_1 
       (.I0(\rd_data_reg[20]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[20]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[20]_i_4_n_0 ),
        .O(\rd_data[20]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[20]_i_10 
       (.I0(ftw_lo0_reg_o[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[20]_i_16_n_0 ),
        .O(\rd_data[20]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[20]_i_11 
       (.I0(phases_h1Main_reg_i[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[20]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[20]_i_12 
       (.I0(readback_tw_i[20]),
        .I1(readback_coef_i[20]),
        .I2(\rd_addr_reg[2]_rep_n_0 ),
        .O(data22[20]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[20]_i_13 
       (.I0(ftw_slip_o[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[20]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[20]_i_14 
       (.I0(inputs_offsetAM_reg_o[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[20]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data[20]_i_15 
       (.I0(ipInfo_memMapVersion_i[20]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(ipInfo_firmwareVersion_i[20]),
        .O(rd_dat_d0[20]));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[20]_i_16 
       (.I0(ftw_h1Prog_reg_o[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[20]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[20]_i_5 
       (.I0(phases_if0_reg_i[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[20]_i_11_n_0 ),
        .O(\rd_data[20]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[20]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[20]),
        .I1(data22[20]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(phases_if1_reg_i[20]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[20]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[20]_i_7 
       (.I0(inputs_rate_o[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[20]_i_13_n_0 ),
        .O(\rd_data[20]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[20]_i_8 
       (.I0(inputs_delayComp_o[20]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[20]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[20]_i_14_n_0 ),
        .O(\rd_data[20]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h3033B8003000B800)) 
    \rd_data[20]_i_9 
       (.I0(control_extResetEnable_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(rd_dat_d0[20]),
        .I3(\rd_data[31]_i_14_n_0 ),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ipInfo_ident_i[20]),
        .O(\rd_data[20]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[21]_i_1 
       (.I0(\rd_data_reg[21]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[21]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[21]_i_4_n_0 ),
        .O(\rd_data[21]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[21]_i_10 
       (.I0(ftw_lo0_reg_o[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[21]_i_15_n_0 ),
        .O(\rd_data[21]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[21]_i_11 
       (.I0(phases_h1Main_reg_i[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[21]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[21]_i_12 
       (.I0(readback_tw_i[21]),
        .I1(readback_coef_i[21]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[21]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[21]_i_13 
       (.I0(ftw_slip_o[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[21]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[21]_i_14 
       (.I0(inputs_offsetAM_reg_o[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[21]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[21]_i_15 
       (.I0(ftw_h1Prog_reg_o[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[21]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[21]_i_5 
       (.I0(phases_if0_reg_i[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[21]_i_11_n_0 ),
        .O(\rd_data[21]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[21]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[21]),
        .I1(data22[21]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[21]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[21]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[21]_i_7 
       (.I0(inputs_rate_o[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[21]_i_13_n_0 ),
        .O(\rd_data[21]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[21]_i_8 
       (.I0(inputs_delayComp_o[21]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[21]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[21]_i_14_n_0 ),
        .O(\rd_data[21]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F8C83808)) 
    \rd_data[21]_i_9 
       (.I0(ipInfo_ident_i[21]),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(\rd_data[31]_i_14_n_0 ),
        .I3(ipInfo_firmwareVersion_i[21]),
        .I4(ipInfo_memMapVersion_i[21]),
        .I5(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[21]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[22]_i_1 
       (.I0(\rd_data_reg[22]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[22]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[22]_i_4_n_0 ),
        .O(\rd_data[22]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[22]_i_10 
       (.I0(ftw_lo0_reg_o[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_on_reg_o[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[22]_i_16_n_0 ),
        .O(\rd_data[22]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[22]_i_11 
       (.I0(phases_h1Main_reg_i[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(phases_h1_reg_i[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[22]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[22]_i_12 
       (.I0(readback_tw_i[22]),
        .I1(readback_coef_i[22]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[22]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[22]_i_13 
       (.I0(ftw_slip_o[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[22]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[22]_i_14 
       (.I0(inputs_offsetAM_reg_o[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_offsetFSK_reg_o[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[22]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data[22]_i_15 
       (.I0(ipInfo_memMapVersion_i[22]),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_firmwareVersion_i[22]),
        .O(rd_dat_d0[22]));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[22]_i_16 
       (.I0(ftw_h1Prog_reg_o[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_h1_reg_o[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[22]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[22]_i_5 
       (.I0(phases_if0_reg_i[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(phases_h1Slip_reg_i[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[22]_i_11_n_0 ),
        .O(\rd_data[22]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[22]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[22]),
        .I1(data22[22]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[22]),
        .I5(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[22]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[22]_i_7 
       (.I0(inputs_rate_o[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_offsetH1_reg_o[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[22]_i_13_n_0 ),
        .O(\rd_data[22]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[22]_i_8 
       (.I0(inputs_delayComp_o[22]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[22]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[22]_i_14_n_0 ),
        .O(\rd_data[22]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h3033B8003000B800)) 
    \rd_data[22]_i_9 
       (.I0(control_selLoad_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(rd_dat_d0[22]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .I4(\rd_addr_reg_n_0_[2] ),
        .I5(ipInfo_ident_i[22]),
        .O(\rd_data[22]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[23]_i_1 
       (.I0(\rd_data_reg[23]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[23]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[23]_i_4_n_0 ),
        .O(\rd_data[23]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[23]_i_10 
       (.I0(ftw_lo0_reg_o[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_on_reg_o[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[23]_i_16_n_0 ),
        .O(\rd_data[23]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[23]_i_11 
       (.I0(phases_h1Main_reg_i[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(phases_h1_reg_i[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[23]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[23]_i_12 
       (.I0(readback_tw_i[23]),
        .I1(readback_coef_i[23]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[23]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[23]_i_13 
       (.I0(ftw_slip_o[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[23]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[23]_i_14 
       (.I0(inputs_offsetAM_reg_o[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_offsetFSK_reg_o[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[23]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \rd_data[23]_i_15 
       (.I0(ipInfo_memMapVersion_i[23]),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_firmwareVersion_i[23]),
        .O(rd_dat_d0[23]));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[23]_i_16 
       (.I0(ftw_h1Prog_reg_o[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_h1_reg_o[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[23]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[23]_i_5 
       (.I0(phases_if0_reg_i[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(phases_h1Slip_reg_i[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[23]_i_11_n_0 ),
        .O(\rd_data[23]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[23]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[23]),
        .I1(data22[23]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[23]),
        .I5(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[23]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[23]_i_7 
       (.I0(inputs_rate_o[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_offsetH1_reg_o[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[23]_i_13_n_0 ),
        .O(\rd_data[23]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[23]_i_8 
       (.I0(inputs_delayComp_o[23]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[23]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[23]_i_14_n_0 ),
        .O(\rd_data[23]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h3033B8003000B800)) 
    \rd_data[23]_i_9 
       (.I0(control_enableFreqDoubling_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(rd_dat_d0[23]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .I4(\rd_addr_reg_n_0_[2] ),
        .I5(ipInfo_ident_i[23]),
        .O(\rd_data[23]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[24]_i_1 
       (.I0(\rd_data_reg[24]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[24]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[24]_i_4_n_0 ),
        .O(\rd_data[24]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[24]_i_10 
       (.I0(ftw_lo0_reg_o[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_on_reg_o[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[24]_i_16_n_0 ),
        .O(\rd_data[24]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAAAEAAAEFFFFAAAE)) 
    \rd_data[24]_i_11 
       (.I0(\rd_addr_reg_n_0_[3] ),
        .I1(\rd_addr_reg_n_0_[5] ),
        .I2(\rd_addr_reg_n_0_[8] ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\rd_addr_reg_n_0_[9] ),
        .I5(\rd_addr_reg_n_0_[6] ),
        .O(\rd_data[24]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[24]_i_12 
       (.I0(phases_h1Main_reg_i[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(phases_h1_reg_i[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[24]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[24]_i_13 
       (.I0(readback_tw_i[24]),
        .I1(readback_coef_i[24]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[24]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[24]_i_14 
       (.I0(ftw_slip_o[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[24]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[24]_i_15 
       (.I0(inputs_offsetAM_reg_o[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_offsetFSK_reg_o[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[24]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[24]_i_16 
       (.I0(ftw_h1Prog_reg_o[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_h1_reg_o[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[24]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[24]_i_5 
       (.I0(phases_if0_reg_i[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(phases_h1Slip_reg_i[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[24]_i_12_n_0 ),
        .O(\rd_data[24]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[24]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[24]),
        .I1(data22[24]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[24]),
        .I5(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[24]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[24]_i_7 
       (.I0(inputs_rate_o[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_offsetH1_reg_o[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[24]_i_14_n_0 ),
        .O(\rd_data[24]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[24]_i_8 
       (.I0(inputs_delayComp_o[24]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[24]_i_15_n_0 ),
        .O(\rd_data[24]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h00883000)) 
    \rd_data[24]_i_9 
       (.I0(control_forceAM_o),
        .I1(\rd_data[15]_i_8_n_0 ),
        .I2(ipInfo_ident_i[24]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[24]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[25]_i_1 
       (.I0(\rd_data_reg[25]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[25]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[25]_i_4_n_0 ),
        .O(\rd_data[25]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[25]_i_10 
       (.I0(ftw_lo0_reg_o[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[25]_i_15_n_0 ),
        .O(\rd_data[25]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[25]_i_11 
       (.I0(phases_h1Main_reg_i[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[25]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[25]_i_12 
       (.I0(readback_tw_i[25]),
        .I1(readback_coef_i[25]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[25]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[25]_i_13 
       (.I0(ftw_slip_o[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[25]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[25]_i_14 
       (.I0(inputs_offsetAM_reg_o[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[25]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[25]_i_15 
       (.I0(ftw_h1Prog_reg_o[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[25]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[25]_i_5 
       (.I0(phases_if0_reg_i[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[25]_i_11_n_0 ),
        .O(\rd_data[25]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[25]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[25]),
        .I1(data22[25]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[25]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[25]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[25]_i_7 
       (.I0(inputs_rate_o[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[25]_i_13_n_0 ),
        .O(\rd_data[25]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[25]_i_8 
       (.I0(inputs_delayComp_o[25]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[25]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[25]_i_14_n_0 ),
        .O(\rd_data[25]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[25]_i_9 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[25]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[25]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[26]_i_1 
       (.I0(\rd_data_reg[26]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[26]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[26]_i_4_n_0 ),
        .O(\rd_data[26]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[26]_i_10 
       (.I0(ftw_lo0_reg_o[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[26]_i_15_n_0 ),
        .O(\rd_data[26]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[26]_i_11 
       (.I0(phases_h1Main_reg_i[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[26]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[26]_i_12 
       (.I0(readback_tw_i[26]),
        .I1(readback_coef_i[26]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[26]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[26]_i_13 
       (.I0(ftw_slip_o[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[26]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[26]_i_14 
       (.I0(inputs_offsetAM_reg_o[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[26]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[26]_i_15 
       (.I0(ftw_h1Prog_reg_o[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[26]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[26]_i_5 
       (.I0(phases_if0_reg_i[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[26]_i_11_n_0 ),
        .O(\rd_data[26]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[26]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[26]),
        .I1(data22[26]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[26]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[26]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[26]_i_7 
       (.I0(inputs_rate_o[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[26]_i_13_n_0 ),
        .O(\rd_data[26]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[26]_i_8 
       (.I0(inputs_delayComp_o[26]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[26]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[26]_i_14_n_0 ),
        .O(\rd_data[26]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[26]_i_9 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[26]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[26]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[27]_i_1 
       (.I0(\rd_data_reg[27]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[27]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[27]_i_4_n_0 ),
        .O(\rd_data[27]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[27]_i_10 
       (.I0(ftw_lo0_reg_o[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[27]_i_15_n_0 ),
        .O(\rd_data[27]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[27]_i_11 
       (.I0(phases_h1Main_reg_i[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[27]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[27]_i_12 
       (.I0(readback_tw_i[27]),
        .I1(readback_coef_i[27]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[27]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[27]_i_13 
       (.I0(ftw_slip_o[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[27]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[27]_i_14 
       (.I0(inputs_offsetAM_reg_o[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[27]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[27]_i_15 
       (.I0(ftw_h1Prog_reg_o[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[27]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[27]_i_5 
       (.I0(phases_if0_reg_i[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[27]_i_11_n_0 ),
        .O(\rd_data[27]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[27]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[27]),
        .I1(data22[27]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[27]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[27]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[27]_i_7 
       (.I0(inputs_rate_o[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[27]_i_13_n_0 ),
        .O(\rd_data[27]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[27]_i_8 
       (.I0(inputs_delayComp_o[27]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[27]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[27]_i_14_n_0 ),
        .O(\rd_data[27]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[27]_i_9 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[27]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[27]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[28]_i_1 
       (.I0(\rd_data_reg[28]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[28]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[28]_i_4_n_0 ),
        .O(\rd_data[28]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[28]_i_10 
       (.I0(ftw_lo0_reg_o[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[28]_i_15_n_0 ),
        .O(\rd_data[28]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[28]_i_11 
       (.I0(phases_h1Main_reg_i[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[28]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[28]_i_12 
       (.I0(readback_tw_i[28]),
        .I1(readback_coef_i[28]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[28]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[28]_i_13 
       (.I0(ftw_slip_o[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[28]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[28]_i_14 
       (.I0(inputs_offsetAM_reg_o[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[28]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[28]_i_15 
       (.I0(ftw_h1Prog_reg_o[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[28]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[28]_i_5 
       (.I0(phases_if0_reg_i[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[28]_i_11_n_0 ),
        .O(\rd_data[28]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[28]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[28]),
        .I1(data22[28]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[28]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[28]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[28]_i_7 
       (.I0(inputs_rate_o[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[28]_i_13_n_0 ),
        .O(\rd_data[28]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[28]_i_8 
       (.I0(inputs_delayComp_o[28]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[28]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[28]_i_14_n_0 ),
        .O(\rd_data[28]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[28]_i_9 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[28]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[28]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[29]_i_1 
       (.I0(\rd_data_reg[29]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[29]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[29]_i_4_n_0 ),
        .O(\rd_data[29]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[29]_i_10 
       (.I0(ftw_lo0_reg_o[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[29]_i_15_n_0 ),
        .O(\rd_data[29]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[29]_i_11 
       (.I0(phases_h1Main_reg_i[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[29]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[29]_i_12 
       (.I0(readback_tw_i[29]),
        .I1(readback_coef_i[29]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[29]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[29]_i_13 
       (.I0(ftw_slip_o[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[29]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[29]_i_14 
       (.I0(inputs_offsetAM_reg_o[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[29]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[29]_i_15 
       (.I0(ftw_h1Prog_reg_o[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[29]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[29]_i_5 
       (.I0(phases_if0_reg_i[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[29]_i_11_n_0 ),
        .O(\rd_data[29]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[29]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[29]),
        .I1(data22[29]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[29]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[29]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[29]_i_7 
       (.I0(inputs_rate_o[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[29]_i_13_n_0 ),
        .O(\rd_data[29]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[29]_i_8 
       (.I0(inputs_delayComp_o[29]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[29]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[29]_i_14_n_0 ),
        .O(\rd_data[29]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[29]_i_9 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[29]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[29]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[2]_i_1 
       (.I0(\rd_data[2]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[2]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[2]_i_4_n_0 ),
        .O(\rd_data[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_10 
       (.I0(inputs_offsetAM_reg_o[34]),
        .I1(inputs_offsetAM_reg_o[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[34]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[2]),
        .O(\rd_data[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_11 
       (.I0(inputs_h_o[2]),
        .I1(inputs_rate_o[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[34]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[2]),
        .O(\rd_data[2]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[2]_i_12 
       (.I0(ftw_slip_o[2]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[34]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[2]),
        .O(\rd_data[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_13 
       (.I0(ftw_lo0_reg_o[34]),
        .I1(ftw_lo0_reg_o[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[34]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[2]),
        .O(\rd_data[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_14 
       (.I0(ftw_h1Prog_reg_o[34]),
        .I1(ftw_h1Prog_reg_o[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[34]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[2]),
        .O(\rd_data[2]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \rd_data[2]_i_15 
       (.I0(control_selFtwLo0_o),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ipInfo_echo_echo_o[2]),
        .O(\rd_data[2]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[2]_i_16 
       (.I0(ipInfo_memMapVersion_i[2]),
        .I1(ipInfo_firmwareVersion_i[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[2]),
        .O(\rd_data[2]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_2 
       (.I0(\rd_data[2]_i_5_n_0 ),
        .I1(\rd_data[2]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[2]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[2]_i_8_n_0 ),
        .O(\rd_data[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_3 
       (.I0(\rd_data[2]_i_9_n_0 ),
        .I1(\rd_data[2]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[2]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[2]_i_12_n_0 ),
        .O(\rd_data[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_4 
       (.I0(\rd_data[2]_i_13_n_0 ),
        .I1(\rd_data[2]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[2]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[2]_i_16_n_0 ),
        .O(\rd_data[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[2]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[34]),
        .I1(readback_phaseH1Comp_reg_i[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[2]),
        .I4(readback_coef_i[2]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[2]_i_6 
       (.I0(p_1_in[2]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(phases_if1_reg_i[34]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(phases_if1_reg_i[2]),
        .O(\rd_data[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_7 
       (.I0(phases_if0_reg_i[34]),
        .I1(phases_if0_reg_i[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[34]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[2]),
        .O(\rd_data[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[2]_i_8 
       (.I0(phases_h1Main_reg_i[34]),
        .I1(phases_h1Main_reg_i[2]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[34]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[2]),
        .O(\rd_data[2]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[2]_i_9 
       (.I0(inputs_delayComp_o[2]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[34]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[2]),
        .O(\rd_data[2]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[30]_i_1 
       (.I0(\rd_data_reg[30]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[30]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[30]_i_4_n_0 ),
        .O(\rd_data[30]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[30]_i_10 
       (.I0(ftw_lo0_reg_o[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[30]_i_15_n_0 ),
        .O(\rd_data[30]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[30]_i_11 
       (.I0(phases_h1Main_reg_i[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[30]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[30]_i_12 
       (.I0(readback_tw_i[30]),
        .I1(readback_coef_i[30]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[30]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[30]_i_13 
       (.I0(ftw_slip_o[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[30]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[30]_i_14 
       (.I0(inputs_offsetAM_reg_o[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[30]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[30]_i_15 
       (.I0(ftw_h1Prog_reg_o[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[30]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[30]_i_5 
       (.I0(phases_if0_reg_i[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[30]_i_11_n_0 ),
        .O(\rd_data[30]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[30]_i_6 
       (.I0(readback_phaseH1Comp_reg_i[30]),
        .I1(data22[30]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[30]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[30]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[30]_i_7 
       (.I0(inputs_rate_o[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[30]_i_13_n_0 ),
        .O(\rd_data[30]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[30]_i_8 
       (.I0(inputs_delayComp_o[30]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[30]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[30]_i_14_n_0 ),
        .O(\rd_data[30]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[30]_i_9 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[30]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[30]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[31]_i_1 
       (.I0(\rd_data_reg[31]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data_reg[31]_i_4_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data_reg[31]_i_6_n_0 ),
        .O(\rd_data[31]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[31]_i_10 
       (.I0(inputs_rate_o[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetH1_reg_o[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[31]_i_17_n_0 ),
        .O(\rd_data[31]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    \rd_data[31]_i_11 
       (.I0(inputs_delayComp_o[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[31]_i_18_n_0 ),
        .O(\rd_data[31]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'h0040)) 
    \rd_data[31]_i_12 
       (.I0(\rd_data[31]_i_14_n_0 ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(ipInfo_ident_i[31]),
        .I3(\rd_data[15]_i_8_n_0 ),
        .O(\rd_data[31]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[31]_i_13 
       (.I0(ftw_lo0_reg_o[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_on_reg_o[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[31]_i_19_n_0 ),
        .O(\rd_data[31]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAAAEAAAEFFFFAAAE)) 
    \rd_data[31]_i_14 
       (.I0(\rd_addr_reg_n_0_[3] ),
        .I1(\rd_addr_reg_n_0_[5] ),
        .I2(\rd_addr_reg_n_0_[8] ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\rd_addr_reg_n_0_[9] ),
        .I5(\rd_addr_reg_n_0_[6] ),
        .O(\rd_data[31]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[31]_i_15 
       (.I0(phases_h1Main_reg_i[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1_reg_i[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[31]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \rd_data[31]_i_16 
       (.I0(readback_tw_i[31]),
        .I1(readback_coef_i[31]),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(data22[31]));
  LUT4 #(
    .INIT(16'h88B8)) 
    \rd_data[31]_i_17 
       (.I0(ftw_slip_o[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_lo1_reg_o[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[31]_i_17_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[31]_i_18 
       (.I0(inputs_offsetAM_reg_o[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(inputs_offsetFSK_reg_o[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[31]_i_18_n_0 ));
  LUT4 #(
    .INIT(16'h00B8)) 
    \rd_data[31]_i_19 
       (.I0(ftw_h1Prog_reg_o[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(ftw_h1_reg_o[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(\rd_data[31]_i_19_n_0 ));
  LUT3 #(
    .INIT(8'hEA)) 
    \rd_data[31]_i_3 
       (.I0(\rd_addr_reg_n_0_[9] ),
        .I1(\rd_addr_reg_n_0_[8] ),
        .I2(\rd_addr_reg_n_0_[7] ),
        .O(\rd_data[31]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'h38)) 
    \rd_data[31]_i_5 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[7] ),
        .I2(\rd_addr_reg_n_0_[8] ),
        .O(\rd_data[31]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFEFEEFEFEEFEE)) 
    \rd_data[31]_i_7 
       (.I0(\rd_addr_reg_n_0_[9] ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\rd_addr_reg_n_0_[5] ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\rd_addr_reg_n_0_[8] ),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\rd_data[31]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00B8FFFF00B80000)) 
    \rd_data[31]_i_8 
       (.I0(phases_if0_reg_i[31]),
        .I1(\rd_data[31]_i_14_n_0 ),
        .I2(phases_h1Slip_reg_i[31]),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[31]_i_15_n_0 ),
        .O(\rd_data[31]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00A000A0C0CFC0C0)) 
    \rd_data[31]_i_9 
       (.I0(readback_phaseH1Comp_reg_i[31]),
        .I1(data22[31]),
        .I2(\rd_data[15]_i_8_n_0 ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(phases_if1_reg_i[31]),
        .I5(\rd_data[31]_i_14_n_0 ),
        .O(\rd_data[31]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[3]_i_1 
       (.I0(\rd_data[3]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[3]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[3]_i_4_n_0 ),
        .O(\rd_data[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_10 
       (.I0(inputs_offsetAM_reg_o[35]),
        .I1(inputs_offsetAM_reg_o[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[35]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[3]),
        .O(\rd_data[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_11 
       (.I0(inputs_h_o[3]),
        .I1(inputs_rate_o[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[35]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[3]),
        .O(\rd_data[3]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[3]_i_12 
       (.I0(ftw_slip_o[3]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[35]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[3]),
        .O(\rd_data[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_13 
       (.I0(ftw_lo0_reg_o[35]),
        .I1(ftw_lo0_reg_o[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[35]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[3]),
        .O(\rd_data[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_14 
       (.I0(ftw_h1Prog_reg_o[35]),
        .I1(ftw_h1Prog_reg_o[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[35]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[3]),
        .O(\rd_data[3]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \rd_data[3]_i_15 
       (.I0(status_phaseH1Vld_i),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(control_selFtwLo1_o),
        .I3(\rd_data[6]_i_17_n_0 ),
        .I4(ipInfo_echo_echo_o[3]),
        .O(\rd_data[3]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[3]_i_16 
       (.I0(ipInfo_memMapVersion_i[3]),
        .I1(ipInfo_firmwareVersion_i[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[3]),
        .O(\rd_data[3]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_2 
       (.I0(\rd_data[3]_i_5_n_0 ),
        .I1(\rd_data[3]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[3]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[3]_i_8_n_0 ),
        .O(\rd_data[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_3 
       (.I0(\rd_data[3]_i_9_n_0 ),
        .I1(\rd_data[3]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[3]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[3]_i_12_n_0 ),
        .O(\rd_data[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_4 
       (.I0(\rd_data[3]_i_13_n_0 ),
        .I1(\rd_data[3]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[3]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[3]_i_16_n_0 ),
        .O(\rd_data[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[3]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[35]),
        .I1(readback_phaseH1Comp_reg_i[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[3]),
        .I4(readback_coef_i[3]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[3]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[3]_i_6 
       (.I0(p_1_in[3]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(phases_if1_reg_i[35]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(phases_if1_reg_i[3]),
        .O(\rd_data[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_7 
       (.I0(phases_if0_reg_i[35]),
        .I1(phases_if0_reg_i[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[35]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[3]),
        .O(\rd_data[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[3]_i_8 
       (.I0(phases_h1Main_reg_i[35]),
        .I1(phases_h1Main_reg_i[3]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[35]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[3]),
        .O(\rd_data[3]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[3]_i_9 
       (.I0(inputs_delayComp_o[3]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[35]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[3]),
        .O(\rd_data[3]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[4]_i_1 
       (.I0(\rd_data[4]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[4]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[4]_i_4_n_0 ),
        .O(\rd_data[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_10 
       (.I0(inputs_offsetAM_reg_o[36]),
        .I1(inputs_offsetAM_reg_o[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[36]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[4]),
        .O(\rd_data[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_11 
       (.I0(inputs_h_o[4]),
        .I1(inputs_rate_o[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[36]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[4]),
        .O(\rd_data[4]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[4]_i_12 
       (.I0(ftw_slip_o[4]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[36]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[4]),
        .O(\rd_data[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_13 
       (.I0(ftw_lo0_reg_o[36]),
        .I1(ftw_lo0_reg_o[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[36]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[4]),
        .O(\rd_data[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_14 
       (.I0(ftw_h1Prog_reg_o[36]),
        .I1(ftw_h1Prog_reg_o[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[36]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[4]),
        .O(\rd_data[4]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \rd_data[4]_i_15 
       (.I0(control_selOffsetH1_o),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ipInfo_echo_echo_o[4]),
        .O(\rd_data[4]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[4]_i_16 
       (.I0(ipInfo_memMapVersion_i[4]),
        .I1(ipInfo_firmwareVersion_i[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[4]),
        .O(\rd_data[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_2 
       (.I0(\rd_data[4]_i_5_n_0 ),
        .I1(\rd_data[4]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[4]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[4]_i_8_n_0 ),
        .O(\rd_data[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_3 
       (.I0(\rd_data[4]_i_9_n_0 ),
        .I1(\rd_data[4]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[4]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[4]_i_12_n_0 ),
        .O(\rd_data[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_4 
       (.I0(\rd_data[4]_i_13_n_0 ),
        .I1(\rd_data[4]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[4]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[4]_i_16_n_0 ),
        .O(\rd_data[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[4]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[36]),
        .I1(readback_phaseH1Comp_reg_i[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[4]),
        .I4(readback_coef_i[4]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[4]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[4]_i_6 
       (.I0(p_1_in[4]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(phases_if1_reg_i[36]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(phases_if1_reg_i[4]),
        .O(\rd_data[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_7 
       (.I0(phases_if0_reg_i[36]),
        .I1(phases_if0_reg_i[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[36]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[4]),
        .O(\rd_data[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[4]_i_8 
       (.I0(phases_h1Main_reg_i[36]),
        .I1(phases_h1Main_reg_i[4]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[36]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[4]),
        .O(\rd_data[4]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[4]_i_9 
       (.I0(inputs_delayComp_o[4]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[36]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[4]),
        .O(\rd_data[4]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[5]_i_1 
       (.I0(\rd_data[5]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[5]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[5]_i_4_n_0 ),
        .O(\rd_data[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_10 
       (.I0(inputs_offsetAM_reg_o[37]),
        .I1(inputs_offsetAM_reg_o[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[37]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[5]),
        .O(\rd_data[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_11 
       (.I0(inputs_h_o[5]),
        .I1(inputs_rate_o[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[37]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[5]),
        .O(\rd_data[5]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[5]_i_12 
       (.I0(ftw_slip_o[5]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[37]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[5]),
        .O(\rd_data[5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_13 
       (.I0(ftw_lo0_reg_o[37]),
        .I1(ftw_lo0_reg_o[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[37]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[5]),
        .O(\rd_data[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_14 
       (.I0(ftw_h1Prog_reg_o[37]),
        .I1(ftw_h1Prog_reg_o[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[37]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[5]),
        .O(\rd_data[5]_i_14_n_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    \rd_data[5]_i_15 
       (.I0(control_selOffsetFskH1_o),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ipInfo_echo_echo_o[5]),
        .O(\rd_data[5]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[5]_i_16 
       (.I0(ipInfo_memMapVersion_i[5]),
        .I1(ipInfo_firmwareVersion_i[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[5]),
        .O(\rd_data[5]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_2 
       (.I0(\rd_data[5]_i_5_n_0 ),
        .I1(\rd_data[5]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[5]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[5]_i_8_n_0 ),
        .O(\rd_data[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_3 
       (.I0(\rd_data[5]_i_9_n_0 ),
        .I1(\rd_data[5]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[5]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[5]_i_12_n_0 ),
        .O(\rd_data[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_4 
       (.I0(\rd_data[5]_i_13_n_0 ),
        .I1(\rd_data[5]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[5]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[5]_i_16_n_0 ),
        .O(\rd_data[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[5]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[37]),
        .I1(readback_phaseH1Comp_reg_i[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[5]),
        .I4(readback_coef_i[5]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[5]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[5]_i_6 
       (.I0(p_1_in[5]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(phases_if1_reg_i[37]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(phases_if1_reg_i[5]),
        .O(\rd_data[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_7 
       (.I0(phases_if0_reg_i[37]),
        .I1(phases_if0_reg_i[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[37]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[5]),
        .O(\rd_data[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[5]_i_8 
       (.I0(phases_h1Main_reg_i[37]),
        .I1(phases_h1Main_reg_i[5]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[37]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[5]),
        .O(\rd_data[5]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[5]_i_9 
       (.I0(inputs_delayComp_o[5]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[37]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[5]),
        .O(\rd_data[5]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[6]_i_1 
       (.I0(\rd_data[6]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[6]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[6]_i_4_n_0 ),
        .O(\rd_data[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_10 
       (.I0(inputs_offsetAM_reg_o[38]),
        .I1(inputs_offsetAM_reg_o[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetFSK_reg_o[38]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[6]),
        .O(\rd_data[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_11 
       (.I0(inputs_h_o[6]),
        .I1(inputs_rate_o[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(inputs_offsetH1_reg_o[38]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[6]),
        .O(\rd_data[6]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[6]_i_12 
       (.I0(ftw_slip_o[6]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(ftw_lo1_reg_o[38]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[6]),
        .O(\rd_data[6]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_13 
       (.I0(ftw_lo0_reg_o[38]),
        .I1(ftw_lo0_reg_o[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_on_reg_o[38]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[6]),
        .O(\rd_data[6]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_14 
       (.I0(ftw_h1Prog_reg_o[38]),
        .I1(ftw_h1Prog_reg_o[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(ftw_h1_reg_o[38]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[6]),
        .O(\rd_data[6]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \rd_data[6]_i_15 
       (.I0(status_amAutoOn_i),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(control_selRate_o),
        .I3(\rd_data[6]_i_17_n_0 ),
        .I4(ipInfo_echo_echo_o[6]),
        .O(\rd_data[6]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[6]_i_16 
       (.I0(ipInfo_memMapVersion_i[6]),
        .I1(ipInfo_firmwareVersion_i[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[6]),
        .O(\rd_data[6]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAAAEAAAEFFFFAAAE)) 
    \rd_data[6]_i_17 
       (.I0(\rd_addr_reg_n_0_[3] ),
        .I1(\rd_addr_reg_n_0_[5] ),
        .I2(\rd_addr_reg_n_0_[8] ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\rd_addr_reg_n_0_[9] ),
        .I5(\rd_addr_reg_n_0_[6] ),
        .O(\rd_data[6]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_2 
       (.I0(\rd_data[6]_i_5_n_0 ),
        .I1(\rd_data[6]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[6]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[6]_i_8_n_0 ),
        .O(\rd_data[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_3 
       (.I0(\rd_data[6]_i_9_n_0 ),
        .I1(\rd_data[6]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[6]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[6]_i_12_n_0 ),
        .O(\rd_data[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_4 
       (.I0(\rd_data[6]_i_13_n_0 ),
        .I1(\rd_data[6]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[6]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[6]_i_16_n_0 ),
        .O(\rd_data[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[6]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[38]),
        .I1(readback_phaseH1Comp_reg_i[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(readback_tw_i[6]),
        .I4(readback_coef_i[6]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[6]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[6]_i_6 
       (.I0(phases_if1_reg_i[6]),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(phases_if1_reg_i[38]),
        .I3(\rd_data[6]_i_17_n_0 ),
        .O(\rd_data[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_7 
       (.I0(phases_if0_reg_i[38]),
        .I1(phases_if0_reg_i[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1Slip_reg_i[38]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[6]),
        .O(\rd_data[6]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[6]_i_8 
       (.I0(phases_h1Main_reg_i[38]),
        .I1(phases_h1Main_reg_i[6]),
        .I2(\rd_data[6]_i_17_n_0 ),
        .I3(phases_h1_reg_i[38]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[6]),
        .O(\rd_data[6]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[6]_i_9 
       (.I0(inputs_delayComp_o[6]),
        .I1(\rd_data[6]_i_17_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[38]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[6]),
        .O(\rd_data[6]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[7]_i_1 
       (.I0(\rd_data[7]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[7]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[7]_i_4_n_0 ),
        .O(\rd_data[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_10 
       (.I0(inputs_offsetAM_reg_o[39]),
        .I1(inputs_offsetAM_reg_o[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[39]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[7]),
        .O(\rd_data[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_11 
       (.I0(inputs_h_o[7]),
        .I1(inputs_rate_o[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[39]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[7]),
        .O(\rd_data[7]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[7]_i_12 
       (.I0(ftw_slip_o[7]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[39]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[7]),
        .O(\rd_data[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_13 
       (.I0(ftw_lo0_reg_o[39]),
        .I1(ftw_lo0_reg_o[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[39]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[7]),
        .O(\rd_data[7]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_14 
       (.I0(ftw_h1Prog_reg_o[39]),
        .I1(ftw_h1Prog_reg_o[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[39]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[7]),
        .O(\rd_data[7]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    \rd_data[7]_i_15 
       (.I0(control_selFtwH1_o),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ipInfo_echo_echo_o[7]),
        .O(\rd_data[7]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[7]_i_16 
       (.I0(ipInfo_memMapVersion_i[7]),
        .I1(ipInfo_firmwareVersion_i[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[7]),
        .O(\rd_data[7]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_2 
       (.I0(\rd_data[7]_i_5_n_0 ),
        .I1(\rd_data[7]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[7]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[7]_i_8_n_0 ),
        .O(\rd_data[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_3 
       (.I0(\rd_data[7]_i_9_n_0 ),
        .I1(\rd_data[7]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[7]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[7]_i_12_n_0 ),
        .O(\rd_data[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_4 
       (.I0(\rd_data[7]_i_13_n_0 ),
        .I1(\rd_data[7]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[7]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[7]_i_16_n_0 ),
        .O(\rd_data[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[7]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[39]),
        .I1(readback_phaseH1Comp_reg_i[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[7]),
        .I4(readback_coef_i[7]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[7]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[7]_i_6 
       (.I0(phases_if1_reg_i[7]),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(phases_if1_reg_i[39]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_7 
       (.I0(phases_if0_reg_i[39]),
        .I1(phases_if0_reg_i[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[39]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[7]),
        .O(\rd_data[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[7]_i_8 
       (.I0(phases_h1Main_reg_i[39]),
        .I1(phases_h1Main_reg_i[7]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[39]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[7]),
        .O(\rd_data[7]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[7]_i_9 
       (.I0(inputs_delayComp_o[7]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[39]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[7]),
        .O(\rd_data[7]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[8]_i_1 
       (.I0(\rd_data[8]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[8]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[8]_i_4_n_0 ),
        .O(\rd_data[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_10 
       (.I0(inputs_offsetAM_reg_o[40]),
        .I1(inputs_offsetAM_reg_o[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[40]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetFSK_reg_o[8]),
        .O(\rd_data[8]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_11 
       (.I0(inputs_h_o[8]),
        .I1(inputs_rate_o[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[40]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(inputs_offsetH1_reg_o[8]),
        .O(\rd_data[8]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[8]_i_12 
       (.I0(ftw_slip_o[8]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[40]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ftw_lo1_reg_o[8]),
        .O(\rd_data[8]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_13 
       (.I0(ftw_lo0_reg_o[40]),
        .I1(ftw_lo0_reg_o[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[40]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_on_reg_o[8]),
        .O(\rd_data[8]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_14 
       (.I0(ftw_h1Prog_reg_o[40]),
        .I1(ftw_h1Prog_reg_o[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[40]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(ftw_h1_reg_o[8]),
        .O(\rd_data[8]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[8]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(control_selFtwH1On_o),
        .O(\rd_data[8]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[8]_i_16 
       (.I0(ipInfo_memMapVersion_i[8]),
        .I1(ipInfo_firmwareVersion_i[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(ipInfo_ident_i[8]),
        .O(\rd_data[8]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_2 
       (.I0(\rd_data[8]_i_5_n_0 ),
        .I1(\rd_data[8]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[8]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[8]_i_8_n_0 ),
        .O(\rd_data[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_3 
       (.I0(\rd_data[8]_i_9_n_0 ),
        .I1(\rd_data[8]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[8]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[8]_i_12_n_0 ),
        .O(\rd_data[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_4 
       (.I0(\rd_data[8]_i_13_n_0 ),
        .I1(\rd_data[8]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[8]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[8]_i_16_n_0 ),
        .O(\rd_data[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[8]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[40]),
        .I1(readback_phaseH1Comp_reg_i[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[8]),
        .I4(readback_coef_i[8]),
        .I5(\rd_addr_reg[2]_rep__0_n_0 ),
        .O(\rd_data[8]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[8]_i_6 
       (.I0(phases_if1_reg_i[8]),
        .I1(\rd_addr_reg[2]_rep__0_n_0 ),
        .I2(phases_if1_reg_i[40]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[8]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_7 
       (.I0(phases_if0_reg_i[40]),
        .I1(phases_if0_reg_i[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[40]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1Slip_reg_i[8]),
        .O(\rd_data[8]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[8]_i_8 
       (.I0(phases_h1Main_reg_i[40]),
        .I1(phases_h1Main_reg_i[8]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[40]),
        .I4(\rd_addr_reg[2]_rep__0_n_0 ),
        .I5(phases_h1_reg_i[8]),
        .O(\rd_data[8]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[8]_i_9 
       (.I0(inputs_delayComp_o[8]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[40]),
        .I3(\rd_addr_reg[2]_rep__0_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[8]),
        .O(\rd_data[8]_i_9_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[9]_i_1 
       (.I0(\rd_data[9]_i_2_n_0 ),
        .I1(\rd_data[31]_i_3_n_0 ),
        .I2(\rd_data[9]_i_3_n_0 ),
        .I3(\rd_data[31]_i_5_n_0 ),
        .I4(\rd_data[9]_i_4_n_0 ),
        .O(\rd_data[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_10 
       (.I0(inputs_offsetAM_reg_o[41]),
        .I1(inputs_offsetAM_reg_o[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetFSK_reg_o[41]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetFSK_reg_o[9]),
        .O(\rd_data[9]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_11 
       (.I0(inputs_h_o[9]),
        .I1(inputs_rate_o[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(inputs_offsetH1_reg_o[41]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(inputs_offsetH1_reg_o[9]),
        .O(\rd_data[9]_i_11_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[9]_i_12 
       (.I0(ftw_slip_o[9]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(ftw_lo1_reg_o[41]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ftw_lo1_reg_o[9]),
        .O(\rd_data[9]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_13 
       (.I0(ftw_lo0_reg_o[41]),
        .I1(ftw_lo0_reg_o[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_on_reg_o[41]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_on_reg_o[9]),
        .O(\rd_data[9]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_14 
       (.I0(ftw_h1Prog_reg_o[41]),
        .I1(ftw_h1Prog_reg_o[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(ftw_h1_reg_o[41]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(ftw_h1_reg_o[9]),
        .O(\rd_data[9]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'h20)) 
    \rd_data[9]_i_15 
       (.I0(\rd_data[24]_i_11_n_0 ),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(control_selWrFtwH1_o),
        .O(\rd_data[9]_i_15_n_0 ));
  LUT5 #(
    .INIT(32'hAFC0A0C0)) 
    \rd_data[9]_i_16 
       (.I0(ipInfo_memMapVersion_i[9]),
        .I1(ipInfo_firmwareVersion_i[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(ipInfo_ident_i[9]),
        .O(\rd_data[9]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_2 
       (.I0(\rd_data[9]_i_5_n_0 ),
        .I1(\rd_data[9]_i_6_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[9]_i_7_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[9]_i_8_n_0 ),
        .O(\rd_data[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_3 
       (.I0(\rd_data[9]_i_9_n_0 ),
        .I1(\rd_data[9]_i_10_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[9]_i_11_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[9]_i_12_n_0 ),
        .O(\rd_data[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_4 
       (.I0(\rd_data[9]_i_13_n_0 ),
        .I1(\rd_data[9]_i_14_n_0 ),
        .I2(\rd_data[31]_i_7_n_0 ),
        .I3(\rd_data[9]_i_15_n_0 ),
        .I4(\rd_data[15]_i_8_n_0 ),
        .I5(\rd_data[9]_i_16_n_0 ),
        .O(\rd_data[9]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0AFA0CFCFC0C0)) 
    \rd_data[9]_i_5 
       (.I0(readback_phaseH1Comp_reg_i[41]),
        .I1(readback_phaseH1Comp_reg_i[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(readback_tw_i[9]),
        .I4(readback_coef_i[9]),
        .I5(\rd_addr_reg[2]_rep_n_0 ),
        .O(\rd_data[9]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \rd_data[9]_i_6 
       (.I0(phases_if1_reg_i[9]),
        .I1(\rd_addr_reg[2]_rep_n_0 ),
        .I2(phases_if1_reg_i[41]),
        .I3(\rd_data[24]_i_11_n_0 ),
        .O(\rd_data[9]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_7 
       (.I0(phases_if0_reg_i[41]),
        .I1(phases_if0_reg_i[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1Slip_reg_i[41]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1Slip_reg_i[9]),
        .O(\rd_data[9]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data[9]_i_8 
       (.I0(phases_h1Main_reg_i[41]),
        .I1(phases_h1Main_reg_i[9]),
        .I2(\rd_data[24]_i_11_n_0 ),
        .I3(phases_h1_reg_i[41]),
        .I4(\rd_addr_reg[2]_rep_n_0 ),
        .I5(phases_h1_reg_i[9]),
        .O(\rd_data[9]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \rd_data[9]_i_9 
       (.I0(inputs_delayComp_o[9]),
        .I1(\rd_data[24]_i_11_n_0 ),
        .I2(inputs_pulseLengthAM_reg_o[41]),
        .I3(\rd_addr_reg[2]_rep_n_0 ),
        .I4(inputs_pulseLengthAM_reg_o[9]),
        .O(\rd_data[9]_i_9_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[0] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[0]_i_1_n_0 ),
        .Q(rd_data[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[10] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[10]_i_1_n_0 ),
        .Q(rd_data[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[11] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[11]_i_1_n_0 ),
        .Q(rd_data[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[12] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[12]_i_1_n_0 ),
        .Q(rd_data[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[13] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[13]_i_1_n_0 ),
        .Q(rd_data[13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[14] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[14]_i_1_n_0 ),
        .Q(rd_data[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[15] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[15]_i_1_n_0 ),
        .Q(rd_data[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[16] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[16]_i_1_n_0 ),
        .Q(rd_data[16]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[16]_i_2 
       (.I0(\rd_data[16]_i_5_n_0 ),
        .I1(\rd_data[16]_i_6_n_0 ),
        .O(\rd_data_reg[16]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[16]_i_3 
       (.I0(\rd_data[16]_i_7_n_0 ),
        .I1(\rd_data[16]_i_8_n_0 ),
        .O(\rd_data_reg[16]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[16]_i_4 
       (.I0(\rd_data[16]_i_9_n_0 ),
        .I1(\rd_data[16]_i_10_n_0 ),
        .O(\rd_data_reg[16]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[17] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[17]_i_1_n_0 ),
        .Q(rd_data[17]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[17]_i_2 
       (.I0(\rd_data[17]_i_5_n_0 ),
        .I1(\rd_data[17]_i_6_n_0 ),
        .O(\rd_data_reg[17]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[17]_i_3 
       (.I0(\rd_data[17]_i_7_n_0 ),
        .I1(\rd_data[17]_i_8_n_0 ),
        .O(\rd_data_reg[17]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[17]_i_4 
       (.I0(\rd_data[17]_i_9_n_0 ),
        .I1(\rd_data[17]_i_10_n_0 ),
        .O(\rd_data_reg[17]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[18] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[18]_i_1_n_0 ),
        .Q(rd_data[18]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[18]_i_2 
       (.I0(\rd_data[18]_i_5_n_0 ),
        .I1(\rd_data[18]_i_6_n_0 ),
        .O(\rd_data_reg[18]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[18]_i_3 
       (.I0(\rd_data[18]_i_7_n_0 ),
        .I1(\rd_data[18]_i_8_n_0 ),
        .O(\rd_data_reg[18]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[18]_i_4 
       (.I0(\rd_data[18]_i_9_n_0 ),
        .I1(\rd_data[18]_i_10_n_0 ),
        .O(\rd_data_reg[18]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[19] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[19]_i_1_n_0 ),
        .Q(rd_data[19]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[19]_i_2 
       (.I0(\rd_data[19]_i_5_n_0 ),
        .I1(\rd_data[19]_i_6_n_0 ),
        .O(\rd_data_reg[19]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[19]_i_3 
       (.I0(\rd_data[19]_i_7_n_0 ),
        .I1(\rd_data[19]_i_8_n_0 ),
        .O(\rd_data_reg[19]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[19]_i_4 
       (.I0(\rd_data[19]_i_9_n_0 ),
        .I1(\rd_data[19]_i_10_n_0 ),
        .O(\rd_data_reg[19]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[1] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[1]_i_1_n_0 ),
        .Q(rd_data[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[20] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[20]_i_1_n_0 ),
        .Q(rd_data[20]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[20]_i_2 
       (.I0(\rd_data[20]_i_5_n_0 ),
        .I1(\rd_data[20]_i_6_n_0 ),
        .O(\rd_data_reg[20]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[20]_i_3 
       (.I0(\rd_data[20]_i_7_n_0 ),
        .I1(\rd_data[20]_i_8_n_0 ),
        .O(\rd_data_reg[20]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[20]_i_4 
       (.I0(\rd_data[20]_i_9_n_0 ),
        .I1(\rd_data[20]_i_10_n_0 ),
        .O(\rd_data_reg[20]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[21] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[21]_i_1_n_0 ),
        .Q(rd_data[21]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[21]_i_2 
       (.I0(\rd_data[21]_i_5_n_0 ),
        .I1(\rd_data[21]_i_6_n_0 ),
        .O(\rd_data_reg[21]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[21]_i_3 
       (.I0(\rd_data[21]_i_7_n_0 ),
        .I1(\rd_data[21]_i_8_n_0 ),
        .O(\rd_data_reg[21]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[21]_i_4 
       (.I0(\rd_data[21]_i_9_n_0 ),
        .I1(\rd_data[21]_i_10_n_0 ),
        .O(\rd_data_reg[21]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[22] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[22]_i_1_n_0 ),
        .Q(rd_data[22]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[22]_i_2 
       (.I0(\rd_data[22]_i_5_n_0 ),
        .I1(\rd_data[22]_i_6_n_0 ),
        .O(\rd_data_reg[22]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[22]_i_3 
       (.I0(\rd_data[22]_i_7_n_0 ),
        .I1(\rd_data[22]_i_8_n_0 ),
        .O(\rd_data_reg[22]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[22]_i_4 
       (.I0(\rd_data[22]_i_9_n_0 ),
        .I1(\rd_data[22]_i_10_n_0 ),
        .O(\rd_data_reg[22]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[23] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[23]_i_1_n_0 ),
        .Q(rd_data[23]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[23]_i_2 
       (.I0(\rd_data[23]_i_5_n_0 ),
        .I1(\rd_data[23]_i_6_n_0 ),
        .O(\rd_data_reg[23]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[23]_i_3 
       (.I0(\rd_data[23]_i_7_n_0 ),
        .I1(\rd_data[23]_i_8_n_0 ),
        .O(\rd_data_reg[23]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[23]_i_4 
       (.I0(\rd_data[23]_i_9_n_0 ),
        .I1(\rd_data[23]_i_10_n_0 ),
        .O(\rd_data_reg[23]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[24] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[24]_i_1_n_0 ),
        .Q(rd_data[24]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[24]_i_2 
       (.I0(\rd_data[24]_i_5_n_0 ),
        .I1(\rd_data[24]_i_6_n_0 ),
        .O(\rd_data_reg[24]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[24]_i_3 
       (.I0(\rd_data[24]_i_7_n_0 ),
        .I1(\rd_data[24]_i_8_n_0 ),
        .O(\rd_data_reg[24]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[24]_i_4 
       (.I0(\rd_data[24]_i_9_n_0 ),
        .I1(\rd_data[24]_i_10_n_0 ),
        .O(\rd_data_reg[24]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[25] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[25]_i_1_n_0 ),
        .Q(rd_data[25]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[25]_i_2 
       (.I0(\rd_data[25]_i_5_n_0 ),
        .I1(\rd_data[25]_i_6_n_0 ),
        .O(\rd_data_reg[25]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[25]_i_3 
       (.I0(\rd_data[25]_i_7_n_0 ),
        .I1(\rd_data[25]_i_8_n_0 ),
        .O(\rd_data_reg[25]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[25]_i_4 
       (.I0(\rd_data[25]_i_9_n_0 ),
        .I1(\rd_data[25]_i_10_n_0 ),
        .O(\rd_data_reg[25]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[26] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[26]_i_1_n_0 ),
        .Q(rd_data[26]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[26]_i_2 
       (.I0(\rd_data[26]_i_5_n_0 ),
        .I1(\rd_data[26]_i_6_n_0 ),
        .O(\rd_data_reg[26]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[26]_i_3 
       (.I0(\rd_data[26]_i_7_n_0 ),
        .I1(\rd_data[26]_i_8_n_0 ),
        .O(\rd_data_reg[26]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[26]_i_4 
       (.I0(\rd_data[26]_i_9_n_0 ),
        .I1(\rd_data[26]_i_10_n_0 ),
        .O(\rd_data_reg[26]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[27] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[27]_i_1_n_0 ),
        .Q(rd_data[27]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[27]_i_2 
       (.I0(\rd_data[27]_i_5_n_0 ),
        .I1(\rd_data[27]_i_6_n_0 ),
        .O(\rd_data_reg[27]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[27]_i_3 
       (.I0(\rd_data[27]_i_7_n_0 ),
        .I1(\rd_data[27]_i_8_n_0 ),
        .O(\rd_data_reg[27]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[27]_i_4 
       (.I0(\rd_data[27]_i_9_n_0 ),
        .I1(\rd_data[27]_i_10_n_0 ),
        .O(\rd_data_reg[27]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[28] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[28]_i_1_n_0 ),
        .Q(rd_data[28]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[28]_i_2 
       (.I0(\rd_data[28]_i_5_n_0 ),
        .I1(\rd_data[28]_i_6_n_0 ),
        .O(\rd_data_reg[28]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[28]_i_3 
       (.I0(\rd_data[28]_i_7_n_0 ),
        .I1(\rd_data[28]_i_8_n_0 ),
        .O(\rd_data_reg[28]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[28]_i_4 
       (.I0(\rd_data[28]_i_9_n_0 ),
        .I1(\rd_data[28]_i_10_n_0 ),
        .O(\rd_data_reg[28]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[29] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[29]_i_1_n_0 ),
        .Q(rd_data[29]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[29]_i_2 
       (.I0(\rd_data[29]_i_5_n_0 ),
        .I1(\rd_data[29]_i_6_n_0 ),
        .O(\rd_data_reg[29]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[29]_i_3 
       (.I0(\rd_data[29]_i_7_n_0 ),
        .I1(\rd_data[29]_i_8_n_0 ),
        .O(\rd_data_reg[29]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[29]_i_4 
       (.I0(\rd_data[29]_i_9_n_0 ),
        .I1(\rd_data[29]_i_10_n_0 ),
        .O(\rd_data_reg[29]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[2] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[2]_i_1_n_0 ),
        .Q(rd_data[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[30] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[30]_i_1_n_0 ),
        .Q(rd_data[30]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[30]_i_2 
       (.I0(\rd_data[30]_i_5_n_0 ),
        .I1(\rd_data[30]_i_6_n_0 ),
        .O(\rd_data_reg[30]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[30]_i_3 
       (.I0(\rd_data[30]_i_7_n_0 ),
        .I1(\rd_data[30]_i_8_n_0 ),
        .O(\rd_data_reg[30]_i_3_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[30]_i_4 
       (.I0(\rd_data[30]_i_9_n_0 ),
        .I1(\rd_data[30]_i_10_n_0 ),
        .O(\rd_data_reg[30]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[31] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[31]_i_1_n_0 ),
        .Q(rd_data[31]),
        .R(\<const0> ));
  MUXF7 \rd_data_reg[31]_i_2 
       (.I0(\rd_data[31]_i_8_n_0 ),
        .I1(\rd_data[31]_i_9_n_0 ),
        .O(\rd_data_reg[31]_i_2_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[31]_i_4 
       (.I0(\rd_data[31]_i_10_n_0 ),
        .I1(\rd_data[31]_i_11_n_0 ),
        .O(\rd_data_reg[31]_i_4_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  MUXF7 \rd_data_reg[31]_i_6 
       (.I0(\rd_data[31]_i_12_n_0 ),
        .I1(\rd_data[31]_i_13_n_0 ),
        .O(\rd_data_reg[31]_i_6_n_0 ),
        .S(\rd_data[31]_i_7_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[3] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[3]_i_1_n_0 ),
        .Q(rd_data[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[4] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[4]_i_1_n_0 ),
        .Q(rd_data[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[5] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[5]_i_1_n_0 ),
        .Q(rd_data[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[6] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[6]_i_1_n_0 ),
        .Q(rd_data[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[7] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[7]_i_1_n_0 ),
        .Q(rd_data[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[8] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[8]_i_1_n_0 ),
        .Q(rd_data[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \rd_data_reg[9] 
       (.C(aclk),
        .CE(areset_n),
        .D(\rd_data[9]_i_1_n_0 ),
        .Q(rd_data[9]),
        .R(\<const0> ));
  LUT2 #(
    .INIT(4'h2)) 
    rd_req_i_1
       (.I0(arvalid),
        .I1(axi_arset),
        .O(rd_req0));
  FDRE #(
    .INIT(1'b0)) 
    rd_req_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(rd_req0),
        .Q(rd_req),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[0] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[0]),
        .Q(rdata[0]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[10] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[10]),
        .Q(rdata[10]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[11] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[11]),
        .Q(rdata[11]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[12] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[12]),
        .Q(rdata[12]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[13] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[13]),
        .Q(rdata[13]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[14] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[14]),
        .Q(rdata[14]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[15] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[15]),
        .Q(rdata[15]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[16] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[16]),
        .Q(rdata[16]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[17] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[17]),
        .Q(rdata[17]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[18] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[18]),
        .Q(rdata[18]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[19] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[19]),
        .Q(rdata[19]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[1] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[1]),
        .Q(rdata[1]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[20] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[20]),
        .Q(rdata[20]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[21] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[21]),
        .Q(rdata[21]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[22] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[22]),
        .Q(rdata[22]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[23] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[23]),
        .Q(rdata[23]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[24] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[24]),
        .Q(rdata[24]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[25] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[25]),
        .Q(rdata[25]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[26] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[26]),
        .Q(rdata[26]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[27] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[27]),
        .Q(rdata[27]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[28] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[28]),
        .Q(rdata[28]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[29] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[29]),
        .Q(rdata[29]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[2] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[2]),
        .Q(rdata[2]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[30] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[30]),
        .Q(rdata[30]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[31] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[31]),
        .Q(rdata[31]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[3] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[3]),
        .Q(rdata[3]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[4] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[4]),
        .Q(rdata[4]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[5] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[5]),
        .Q(rdata[5]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[6] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[6]),
        .Q(rdata[6]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[7] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[7]),
        .Q(rdata[7]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[8] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[8]),
        .Q(rdata[8]),
        .R(axi_wdone_i_1_n_0));
  (* x_interface_info = "xilinx.com:interface:aximm:1.0 slave RDATA" *) 
  FDRE #(
    .INIT(1'b0)) 
    \rdata_reg[9] 
       (.C(aclk),
        .CE(rd_ack),
        .D(rd_data[9]),
        .Q(rdata[9]),
        .R(axi_wdone_i_1_n_0));
  LUT3 #(
    .INIT(8'h20)) 
    \wr_addr[11]_i_1 
       (.I0(areset_n),
        .I1(axi_awset),
        .I2(awvalid),
        .O(wr_addr_0));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[10] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[8]),
        .Q(wr_addr[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[11] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[9]),
        .Q(wr_addr[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[2] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[0]),
        .Q(wr_addr[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[3] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[1]),
        .Q(wr_addr[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[4] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[2]),
        .Q(wr_addr[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[5] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[3]),
        .Q(wr_addr[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[6] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[4]),
        .Q(wr_addr[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[7] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[5]),
        .Q(wr_addr[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[8] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[6]),
        .Q(wr_addr[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_addr_reg[9] 
       (.C(aclk),
        .CE(wr_addr_0),
        .D(awaddr[7]),
        .Q(wr_addr[9]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[10] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[10]),
        .Q(\wr_adr_d0_reg_n_0_[10] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[11] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[11]),
        .Q(\wr_adr_d0_reg_n_0_[11] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[2] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[2]),
        .Q(wr_adr_d0),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[3] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[3]),
        .Q(sel0[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[4] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[4]),
        .Q(sel0[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[5] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[5]),
        .Q(sel0[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[6] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[6]),
        .Q(sel0[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[7] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[7]),
        .Q(sel0[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[8] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[8]),
        .Q(sel0[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_adr_d0_reg[9] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_addr[9]),
        .Q(sel0[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[0] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[0]),
        .Q(\wr_dat_d0_reg_n_0_[0] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[10] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[10]),
        .Q(\wr_dat_d0_reg_n_0_[10] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[11] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[11]),
        .Q(\wr_dat_d0_reg_n_0_[11] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[12] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[12]),
        .Q(\wr_dat_d0_reg_n_0_[12] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[13] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[13]),
        .Q(\wr_dat_d0_reg_n_0_[13] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[14] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[14]),
        .Q(\wr_dat_d0_reg_n_0_[14] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[15] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[15]),
        .Q(\wr_dat_d0_reg_n_0_[15] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[16] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[16]),
        .Q(\wr_dat_d0_reg_n_0_[16] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[17] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[17]),
        .Q(\wr_dat_d0_reg_n_0_[17] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[18] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[18]),
        .Q(\wr_dat_d0_reg_n_0_[18] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[19] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[19]),
        .Q(\wr_dat_d0_reg_n_0_[19] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[1] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[1]),
        .Q(p_0_in),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[20] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[20]),
        .Q(\wr_dat_d0_reg_n_0_[20] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[21] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[21]),
        .Q(\wr_dat_d0_reg_n_0_[21] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[22] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[22]),
        .Q(\wr_dat_d0_reg_n_0_[22] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[23] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[23]),
        .Q(\wr_dat_d0_reg_n_0_[23] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[24] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[24]),
        .Q(\wr_dat_d0_reg_n_0_[24] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[25] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[25]),
        .Q(\wr_dat_d0_reg_n_0_[25] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[26] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[26]),
        .Q(\wr_dat_d0_reg_n_0_[26] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[27] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[27]),
        .Q(\wr_dat_d0_reg_n_0_[27] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[28] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[28]),
        .Q(\wr_dat_d0_reg_n_0_[28] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[29] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[29]),
        .Q(\wr_dat_d0_reg_n_0_[29] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[2] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[2]),
        .Q(\wr_dat_d0_reg_n_0_[2] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[30] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[30]),
        .Q(\wr_dat_d0_reg_n_0_[30] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[31] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[31]),
        .Q(\wr_dat_d0_reg_n_0_[31] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[3] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[3]),
        .Q(\wr_dat_d0_reg_n_0_[3] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[4] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[4]),
        .Q(\wr_dat_d0_reg_n_0_[4] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[5] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[5]),
        .Q(\wr_dat_d0_reg_n_0_[5] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[6] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[6]),
        .Q(p_2_in),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[7] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[7]),
        .Q(\wr_dat_d0_reg_n_0_[7] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[8] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[8]),
        .Q(\wr_dat_d0_reg_n_0_[8] ),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_dat_d0_reg[9] 
       (.C(aclk),
        .CE(areset_n),
        .D(wr_data[9]),
        .Q(\wr_dat_d0_reg_n_0_[9] ),
        .R(\<const0> ));
  LUT3 #(
    .INIT(8'h20)) 
    \wr_data[31]_i_1 
       (.I0(areset_n),
        .I1(axi_wset_reg_n_0),
        .I2(wvalid),
        .O(wr_data_1));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[0] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[0]),
        .Q(wr_data[0]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[10] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[10]),
        .Q(wr_data[10]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[11] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[11]),
        .Q(wr_data[11]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[12] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[12]),
        .Q(wr_data[12]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[13] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[13]),
        .Q(wr_data[13]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[14] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[14]),
        .Q(wr_data[14]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[15] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[15]),
        .Q(wr_data[15]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[16] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[16]),
        .Q(wr_data[16]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[17] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[17]),
        .Q(wr_data[17]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[18] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[18]),
        .Q(wr_data[18]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[19] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[19]),
        .Q(wr_data[19]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[1] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[1]),
        .Q(wr_data[1]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[20] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[20]),
        .Q(wr_data[20]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[21] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[21]),
        .Q(wr_data[21]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[22] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[22]),
        .Q(wr_data[22]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[23] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[23]),
        .Q(wr_data[23]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[24] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[24]),
        .Q(wr_data[24]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[25] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[25]),
        .Q(wr_data[25]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[26] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[26]),
        .Q(wr_data[26]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[27] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[27]),
        .Q(wr_data[27]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[28] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[28]),
        .Q(wr_data[28]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[29] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[29]),
        .Q(wr_data[29]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[2] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[2]),
        .Q(wr_data[2]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[30] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[30]),
        .Q(wr_data[30]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[31] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[31]),
        .Q(wr_data[31]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[3] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[3]),
        .Q(wr_data[3]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[4] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[4]),
        .Q(wr_data[4]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[5] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[5]),
        .Q(wr_data[5]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[6] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[6]),
        .Q(wr_data[6]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[7] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[7]),
        .Q(wr_data[7]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[8] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[8]),
        .Q(wr_data[8]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    \wr_data_reg[9] 
       (.C(aclk),
        .CE(wr_data_1),
        .D(wdata[9]),
        .Q(wr_data[9]),
        .R(\<const0> ));
  FDRE #(
    .INIT(1'b0)) 
    wr_req_d0_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(wr_req),
        .Q(wr_req_d0),
        .R(axi_wdone_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT5 #(
    .INIT(32'h20A82000)) 
    wr_req_i_1
       (.I0(areset_n),
        .I1(axi_wset_reg_n_0),
        .I2(wvalid),
        .I3(axi_awset),
        .I4(awvalid),
        .O(wr_req_i_1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    wr_req_reg
       (.C(aclk),
        .CE(\<const1> ),
        .D(wr_req_i_1_n_0),
        .Q(wr_req),
        .R(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT1 #(
    .INIT(2'h1)) 
    wready_INST_0
       (.I0(axi_wset_reg_n_0),
        .O(wready));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_sign_invert0_0,sign_invert,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_sign_invert0_0,sign_invert,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sign_invert,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,width=25}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "sign_invert,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_sign_invert0_0
   (signed_i,
    invert_i,
    signed_o);
  input [24:0]signed_i;
  input invert_i;
  output [24:0]signed_o;

  wire invert_i;
  wire [24:0]signed_i;
  wire [24:1]\^signed_o ;

  assign signed_o[24:1] = \^signed_o [24:1];
  assign signed_o[0] = signed_i[0];
  RFNCO_cmp_sign_invert0_0_sign_invert U0
       (.invert_i(invert_i),
        .signed_i(signed_i),
        .signed_o(\^signed_o ));
endmodule

(* ORIG_REF_NAME = "sign_invert" *) 
module RFNCO_cmp_sign_invert0_0_sign_invert
   (signed_o,
    signed_i,
    invert_i);
  output [23:0]signed_o;
  input [24:0]signed_i;
  input invert_i;

  wire \<const0> ;
  wire invert_i;
  wire [24:0]p_0_in;
  wire [24:0]signed_i;
  wire [23:0]signed_o;
  wire [24:1]signed_o0;
  wire \signed_o[12]_INST_0_i_1_n_0 ;
  wire \signed_o[12]_INST_0_i_1_n_1 ;
  wire \signed_o[12]_INST_0_i_1_n_2 ;
  wire \signed_o[12]_INST_0_i_1_n_3 ;
  wire \signed_o[16]_INST_0_i_1_n_0 ;
  wire \signed_o[16]_INST_0_i_1_n_1 ;
  wire \signed_o[16]_INST_0_i_1_n_2 ;
  wire \signed_o[16]_INST_0_i_1_n_3 ;
  wire \signed_o[20]_INST_0_i_1_n_0 ;
  wire \signed_o[20]_INST_0_i_1_n_1 ;
  wire \signed_o[20]_INST_0_i_1_n_2 ;
  wire \signed_o[20]_INST_0_i_1_n_3 ;
  wire \signed_o[24]_INST_0_i_1_n_1 ;
  wire \signed_o[24]_INST_0_i_1_n_2 ;
  wire \signed_o[24]_INST_0_i_1_n_3 ;
  wire \signed_o[4]_INST_0_i_1_n_0 ;
  wire \signed_o[4]_INST_0_i_1_n_1 ;
  wire \signed_o[4]_INST_0_i_1_n_2 ;
  wire \signed_o[4]_INST_0_i_1_n_3 ;
  wire \signed_o[8]_INST_0_i_1_n_0 ;
  wire \signed_o[8]_INST_0_i_1_n_1 ;
  wire \signed_o[8]_INST_0_i_1_n_2 ;
  wire \signed_o[8]_INST_0_i_1_n_3 ;

  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[10]_INST_0 
       (.I0(signed_o0[10]),
        .I1(signed_i[10]),
        .I2(invert_i),
        .O(signed_o[9]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[11]_INST_0 
       (.I0(signed_o0[11]),
        .I1(signed_i[11]),
        .I2(invert_i),
        .O(signed_o[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[12]_INST_0 
       (.I0(signed_o0[12]),
        .I1(signed_i[12]),
        .I2(invert_i),
        .O(signed_o[11]));
  CARRY4 \signed_o[12]_INST_0_i_1 
       (.CI(\signed_o[8]_INST_0_i_1_n_0 ),
        .CO({\signed_o[12]_INST_0_i_1_n_0 ,\signed_o[12]_INST_0_i_1_n_1 ,\signed_o[12]_INST_0_i_1_n_2 ,\signed_o[12]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[12:9]),
        .S(p_0_in[12:9]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_2 
       (.I0(signed_i[12]),
        .O(p_0_in[12]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_3 
       (.I0(signed_i[11]),
        .O(p_0_in[11]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_4 
       (.I0(signed_i[10]),
        .O(p_0_in[10]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_5 
       (.I0(signed_i[9]),
        .O(p_0_in[9]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[13]_INST_0 
       (.I0(signed_o0[13]),
        .I1(signed_i[13]),
        .I2(invert_i),
        .O(signed_o[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[14]_INST_0 
       (.I0(signed_o0[14]),
        .I1(signed_i[14]),
        .I2(invert_i),
        .O(signed_o[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[15]_INST_0 
       (.I0(signed_o0[15]),
        .I1(signed_i[15]),
        .I2(invert_i),
        .O(signed_o[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[16]_INST_0 
       (.I0(signed_o0[16]),
        .I1(signed_i[16]),
        .I2(invert_i),
        .O(signed_o[15]));
  CARRY4 \signed_o[16]_INST_0_i_1 
       (.CI(\signed_o[12]_INST_0_i_1_n_0 ),
        .CO({\signed_o[16]_INST_0_i_1_n_0 ,\signed_o[16]_INST_0_i_1_n_1 ,\signed_o[16]_INST_0_i_1_n_2 ,\signed_o[16]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[16:13]),
        .S(p_0_in[16:13]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_2 
       (.I0(signed_i[16]),
        .O(p_0_in[16]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_3 
       (.I0(signed_i[15]),
        .O(p_0_in[15]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_4 
       (.I0(signed_i[14]),
        .O(p_0_in[14]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_5 
       (.I0(signed_i[13]),
        .O(p_0_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[17]_INST_0 
       (.I0(signed_o0[17]),
        .I1(signed_i[17]),
        .I2(invert_i),
        .O(signed_o[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[18]_INST_0 
       (.I0(signed_o0[18]),
        .I1(signed_i[18]),
        .I2(invert_i),
        .O(signed_o[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[19]_INST_0 
       (.I0(signed_o0[19]),
        .I1(signed_i[19]),
        .I2(invert_i),
        .O(signed_o[18]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[1]_INST_0 
       (.I0(signed_o0[1]),
        .I1(signed_i[1]),
        .I2(invert_i),
        .O(signed_o[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[20]_INST_0 
       (.I0(signed_o0[20]),
        .I1(signed_i[20]),
        .I2(invert_i),
        .O(signed_o[19]));
  CARRY4 \signed_o[20]_INST_0_i_1 
       (.CI(\signed_o[16]_INST_0_i_1_n_0 ),
        .CO({\signed_o[20]_INST_0_i_1_n_0 ,\signed_o[20]_INST_0_i_1_n_1 ,\signed_o[20]_INST_0_i_1_n_2 ,\signed_o[20]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[20:17]),
        .S(p_0_in[20:17]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_2 
       (.I0(signed_i[20]),
        .O(p_0_in[20]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_3 
       (.I0(signed_i[19]),
        .O(p_0_in[19]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_4 
       (.I0(signed_i[18]),
        .O(p_0_in[18]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_5 
       (.I0(signed_i[17]),
        .O(p_0_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[21]_INST_0 
       (.I0(signed_o0[21]),
        .I1(signed_i[21]),
        .I2(invert_i),
        .O(signed_o[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[22]_INST_0 
       (.I0(signed_o0[22]),
        .I1(signed_i[22]),
        .I2(invert_i),
        .O(signed_o[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[23]_INST_0 
       (.I0(signed_o0[23]),
        .I1(signed_i[23]),
        .I2(invert_i),
        .O(signed_o[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[24]_INST_0 
       (.I0(signed_o0[24]),
        .I1(signed_i[24]),
        .I2(invert_i),
        .O(signed_o[23]));
  CARRY4 \signed_o[24]_INST_0_i_1 
       (.CI(\signed_o[20]_INST_0_i_1_n_0 ),
        .CO({\signed_o[24]_INST_0_i_1_n_1 ,\signed_o[24]_INST_0_i_1_n_2 ,\signed_o[24]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[24:21]),
        .S(p_0_in[24:21]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_2 
       (.I0(signed_i[24]),
        .O(p_0_in[24]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_3 
       (.I0(signed_i[23]),
        .O(p_0_in[23]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_4 
       (.I0(signed_i[22]),
        .O(p_0_in[22]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_5 
       (.I0(signed_i[21]),
        .O(p_0_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[2]_INST_0 
       (.I0(signed_o0[2]),
        .I1(signed_i[2]),
        .I2(invert_i),
        .O(signed_o[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[3]_INST_0 
       (.I0(signed_o0[3]),
        .I1(signed_i[3]),
        .I2(invert_i),
        .O(signed_o[2]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[4]_INST_0 
       (.I0(signed_o0[4]),
        .I1(signed_i[4]),
        .I2(invert_i),
        .O(signed_o[3]));
  CARRY4 \signed_o[4]_INST_0_i_1 
       (.CI(\<const0> ),
        .CO({\signed_o[4]_INST_0_i_1_n_0 ,\signed_o[4]_INST_0_i_1_n_1 ,\signed_o[4]_INST_0_i_1_n_2 ,\signed_o[4]_INST_0_i_1_n_3 }),
        .CYINIT(p_0_in[0]),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[4:1]),
        .S(p_0_in[4:1]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_2 
       (.I0(signed_i[0]),
        .O(p_0_in[0]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_3 
       (.I0(signed_i[4]),
        .O(p_0_in[4]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_4 
       (.I0(signed_i[3]),
        .O(p_0_in[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_5 
       (.I0(signed_i[2]),
        .O(p_0_in[2]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_6 
       (.I0(signed_i[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[5]_INST_0 
       (.I0(signed_o0[5]),
        .I1(signed_i[5]),
        .I2(invert_i),
        .O(signed_o[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[6]_INST_0 
       (.I0(signed_o0[6]),
        .I1(signed_i[6]),
        .I2(invert_i),
        .O(signed_o[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[7]_INST_0 
       (.I0(signed_o0[7]),
        .I1(signed_i[7]),
        .I2(invert_i),
        .O(signed_o[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[8]_INST_0 
       (.I0(signed_o0[8]),
        .I1(signed_i[8]),
        .I2(invert_i),
        .O(signed_o[7]));
  CARRY4 \signed_o[8]_INST_0_i_1 
       (.CI(\signed_o[4]_INST_0_i_1_n_0 ),
        .CO({\signed_o[8]_INST_0_i_1_n_0 ,\signed_o[8]_INST_0_i_1_n_1 ,\signed_o[8]_INST_0_i_1_n_2 ,\signed_o[8]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[8:5]),
        .S(p_0_in[8:5]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_2 
       (.I0(signed_i[8]),
        .O(p_0_in[8]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_3 
       (.I0(signed_i[7]),
        .O(p_0_in[7]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_4 
       (.I0(signed_i[6]),
        .O(p_0_in[6]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_5 
       (.I0(signed_i[5]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[9]_INST_0 
       (.I0(signed_o0[9]),
        .I1(signed_i[9]),
        .I2(invert_i),
        .O(signed_o[8]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_sign_invert1_0,sign_invert,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_sign_invert1_0,sign_invert,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=sign_invert,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,width=25}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "sign_invert,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_sign_invert1_0
   (signed_i,
    invert_i,
    signed_o);
  input [24:0]signed_i;
  input invert_i;
  output [24:0]signed_o;

  wire invert_i;
  wire [24:0]signed_i;
  wire [24:1]\^signed_o ;

  assign signed_o[24:1] = \^signed_o [24:1];
  assign signed_o[0] = signed_i[0];
  RFNCO_cmp_sign_invert1_0_sign_invert U0
       (.invert_i(invert_i),
        .signed_i(signed_i),
        .signed_o(\^signed_o ));
endmodule

(* ORIG_REF_NAME = "sign_invert" *) 
module RFNCO_cmp_sign_invert1_0_sign_invert
   (signed_o,
    signed_i,
    invert_i);
  output [23:0]signed_o;
  input [24:0]signed_i;
  input invert_i;

  wire \<const0> ;
  wire invert_i;
  wire [24:0]p_0_in;
  wire [24:0]signed_i;
  wire [23:0]signed_o;
  wire [24:1]signed_o0;
  wire \signed_o[12]_INST_0_i_1_n_0 ;
  wire \signed_o[12]_INST_0_i_1_n_1 ;
  wire \signed_o[12]_INST_0_i_1_n_2 ;
  wire \signed_o[12]_INST_0_i_1_n_3 ;
  wire \signed_o[16]_INST_0_i_1_n_0 ;
  wire \signed_o[16]_INST_0_i_1_n_1 ;
  wire \signed_o[16]_INST_0_i_1_n_2 ;
  wire \signed_o[16]_INST_0_i_1_n_3 ;
  wire \signed_o[20]_INST_0_i_1_n_0 ;
  wire \signed_o[20]_INST_0_i_1_n_1 ;
  wire \signed_o[20]_INST_0_i_1_n_2 ;
  wire \signed_o[20]_INST_0_i_1_n_3 ;
  wire \signed_o[24]_INST_0_i_1_n_1 ;
  wire \signed_o[24]_INST_0_i_1_n_2 ;
  wire \signed_o[24]_INST_0_i_1_n_3 ;
  wire \signed_o[4]_INST_0_i_1_n_0 ;
  wire \signed_o[4]_INST_0_i_1_n_1 ;
  wire \signed_o[4]_INST_0_i_1_n_2 ;
  wire \signed_o[4]_INST_0_i_1_n_3 ;
  wire \signed_o[8]_INST_0_i_1_n_0 ;
  wire \signed_o[8]_INST_0_i_1_n_1 ;
  wire \signed_o[8]_INST_0_i_1_n_2 ;
  wire \signed_o[8]_INST_0_i_1_n_3 ;

  GND GND
       (.G(\<const0> ));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[10]_INST_0 
       (.I0(signed_o0[10]),
        .I1(signed_i[10]),
        .I2(invert_i),
        .O(signed_o[9]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[11]_INST_0 
       (.I0(signed_o0[11]),
        .I1(signed_i[11]),
        .I2(invert_i),
        .O(signed_o[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[12]_INST_0 
       (.I0(signed_o0[12]),
        .I1(signed_i[12]),
        .I2(invert_i),
        .O(signed_o[11]));
  CARRY4 \signed_o[12]_INST_0_i_1 
       (.CI(\signed_o[8]_INST_0_i_1_n_0 ),
        .CO({\signed_o[12]_INST_0_i_1_n_0 ,\signed_o[12]_INST_0_i_1_n_1 ,\signed_o[12]_INST_0_i_1_n_2 ,\signed_o[12]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[12:9]),
        .S(p_0_in[12:9]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_2 
       (.I0(signed_i[12]),
        .O(p_0_in[12]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_3 
       (.I0(signed_i[11]),
        .O(p_0_in[11]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_4 
       (.I0(signed_i[10]),
        .O(p_0_in[10]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[12]_INST_0_i_5 
       (.I0(signed_i[9]),
        .O(p_0_in[9]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[13]_INST_0 
       (.I0(signed_o0[13]),
        .I1(signed_i[13]),
        .I2(invert_i),
        .O(signed_o[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[14]_INST_0 
       (.I0(signed_o0[14]),
        .I1(signed_i[14]),
        .I2(invert_i),
        .O(signed_o[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[15]_INST_0 
       (.I0(signed_o0[15]),
        .I1(signed_i[15]),
        .I2(invert_i),
        .O(signed_o[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[16]_INST_0 
       (.I0(signed_o0[16]),
        .I1(signed_i[16]),
        .I2(invert_i),
        .O(signed_o[15]));
  CARRY4 \signed_o[16]_INST_0_i_1 
       (.CI(\signed_o[12]_INST_0_i_1_n_0 ),
        .CO({\signed_o[16]_INST_0_i_1_n_0 ,\signed_o[16]_INST_0_i_1_n_1 ,\signed_o[16]_INST_0_i_1_n_2 ,\signed_o[16]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[16:13]),
        .S(p_0_in[16:13]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_2 
       (.I0(signed_i[16]),
        .O(p_0_in[16]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_3 
       (.I0(signed_i[15]),
        .O(p_0_in[15]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_4 
       (.I0(signed_i[14]),
        .O(p_0_in[14]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[16]_INST_0_i_5 
       (.I0(signed_i[13]),
        .O(p_0_in[13]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[17]_INST_0 
       (.I0(signed_o0[17]),
        .I1(signed_i[17]),
        .I2(invert_i),
        .O(signed_o[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[18]_INST_0 
       (.I0(signed_o0[18]),
        .I1(signed_i[18]),
        .I2(invert_i),
        .O(signed_o[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[19]_INST_0 
       (.I0(signed_o0[19]),
        .I1(signed_i[19]),
        .I2(invert_i),
        .O(signed_o[18]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[1]_INST_0 
       (.I0(signed_o0[1]),
        .I1(signed_i[1]),
        .I2(invert_i),
        .O(signed_o[0]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[20]_INST_0 
       (.I0(signed_o0[20]),
        .I1(signed_i[20]),
        .I2(invert_i),
        .O(signed_o[19]));
  CARRY4 \signed_o[20]_INST_0_i_1 
       (.CI(\signed_o[16]_INST_0_i_1_n_0 ),
        .CO({\signed_o[20]_INST_0_i_1_n_0 ,\signed_o[20]_INST_0_i_1_n_1 ,\signed_o[20]_INST_0_i_1_n_2 ,\signed_o[20]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[20:17]),
        .S(p_0_in[20:17]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_2 
       (.I0(signed_i[20]),
        .O(p_0_in[20]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_3 
       (.I0(signed_i[19]),
        .O(p_0_in[19]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_4 
       (.I0(signed_i[18]),
        .O(p_0_in[18]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[20]_INST_0_i_5 
       (.I0(signed_i[17]),
        .O(p_0_in[17]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[21]_INST_0 
       (.I0(signed_o0[21]),
        .I1(signed_i[21]),
        .I2(invert_i),
        .O(signed_o[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[22]_INST_0 
       (.I0(signed_o0[22]),
        .I1(signed_i[22]),
        .I2(invert_i),
        .O(signed_o[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[23]_INST_0 
       (.I0(signed_o0[23]),
        .I1(signed_i[23]),
        .I2(invert_i),
        .O(signed_o[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[24]_INST_0 
       (.I0(signed_o0[24]),
        .I1(signed_i[24]),
        .I2(invert_i),
        .O(signed_o[23]));
  CARRY4 \signed_o[24]_INST_0_i_1 
       (.CI(\signed_o[20]_INST_0_i_1_n_0 ),
        .CO({\signed_o[24]_INST_0_i_1_n_1 ,\signed_o[24]_INST_0_i_1_n_2 ,\signed_o[24]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[24:21]),
        .S(p_0_in[24:21]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_2 
       (.I0(signed_i[24]),
        .O(p_0_in[24]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_3 
       (.I0(signed_i[23]),
        .O(p_0_in[23]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_4 
       (.I0(signed_i[22]),
        .O(p_0_in[22]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[24]_INST_0_i_5 
       (.I0(signed_i[21]),
        .O(p_0_in[21]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[2]_INST_0 
       (.I0(signed_o0[2]),
        .I1(signed_i[2]),
        .I2(invert_i),
        .O(signed_o[1]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[3]_INST_0 
       (.I0(signed_o0[3]),
        .I1(signed_i[3]),
        .I2(invert_i),
        .O(signed_o[2]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[4]_INST_0 
       (.I0(signed_o0[4]),
        .I1(signed_i[4]),
        .I2(invert_i),
        .O(signed_o[3]));
  CARRY4 \signed_o[4]_INST_0_i_1 
       (.CI(\<const0> ),
        .CO({\signed_o[4]_INST_0_i_1_n_0 ,\signed_o[4]_INST_0_i_1_n_1 ,\signed_o[4]_INST_0_i_1_n_2 ,\signed_o[4]_INST_0_i_1_n_3 }),
        .CYINIT(p_0_in[0]),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[4:1]),
        .S(p_0_in[4:1]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_2 
       (.I0(signed_i[0]),
        .O(p_0_in[0]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_3 
       (.I0(signed_i[4]),
        .O(p_0_in[4]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_4 
       (.I0(signed_i[3]),
        .O(p_0_in[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_5 
       (.I0(signed_i[2]),
        .O(p_0_in[2]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[4]_INST_0_i_6 
       (.I0(signed_i[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[5]_INST_0 
       (.I0(signed_o0[5]),
        .I1(signed_i[5]),
        .I2(invert_i),
        .O(signed_o[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[6]_INST_0 
       (.I0(signed_o0[6]),
        .I1(signed_i[6]),
        .I2(invert_i),
        .O(signed_o[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[7]_INST_0 
       (.I0(signed_o0[7]),
        .I1(signed_i[7]),
        .I2(invert_i),
        .O(signed_o[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[8]_INST_0 
       (.I0(signed_o0[8]),
        .I1(signed_i[8]),
        .I2(invert_i),
        .O(signed_o[7]));
  CARRY4 \signed_o[8]_INST_0_i_1 
       (.CI(\signed_o[4]_INST_0_i_1_n_0 ),
        .CO({\signed_o[8]_INST_0_i_1_n_0 ,\signed_o[8]_INST_0_i_1_n_1 ,\signed_o[8]_INST_0_i_1_n_2 ,\signed_o[8]_INST_0_i_1_n_3 }),
        .CYINIT(\<const0> ),
        .DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
        .O(signed_o0[8:5]),
        .S(p_0_in[8:5]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_2 
       (.I0(signed_i[8]),
        .O(p_0_in[8]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_3 
       (.I0(signed_i[7]),
        .O(p_0_in[7]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_4 
       (.I0(signed_i[6]),
        .O(p_0_in[6]));
  LUT1 #(
    .INIT(2'h1)) 
    \signed_o[8]_INST_0_i_5 
       (.I0(signed_i[5]),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \signed_o[9]_INST_0 
       (.I0(signed_o0[9]),
        .I1(signed_i[9]),
        .I2(invert_i),
        .O(signed_o[8]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_slice_cos_IF0_0,xlslice_v1_0_1_xlslice,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_slice_cos_IF0_0,xlslice_v1_0_1_xlslice,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=64,DIN_FROM=24,DIN_TO=0}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
module RFNCO_cmp_slice_cos_IF0_0
   (Din,
    Dout);
  input [63:0]Din;
  output [24:0]Dout;

  wire [63:0]Din;

  assign Dout[24:0] = Din[24:0];
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_slice_cos_IF0_0,xlslice_v1_0_1_xlslice,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_slice_cos_IF0_0,xlslice_v1_0_1_xlslice,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=64,DIN_FROM=24,DIN_TO=0}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
module RFNCO_cmp_slice_cos_IF1_0
   (Din,
    Dout);
  input [63:0]Din;
  output [24:0]Dout;

  wire [63:0]Din;

  assign Dout[24:0] = Din[24:0];
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_slice_phase_IF0_0,xlslice_v1_0_1_xlslice,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_slice_phase_IF0_0,xlslice_v1_0_1_xlslice,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=48,DIN_FROM=47,DIN_TO=23}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
module RFNCO_cmp_slice_phase_IF0_0
   (Din,
    Dout);
  input [47:0]Din;
  output [24:0]Dout;

  wire [47:0]Din;

  assign Dout[24:0] = Din[47:23];
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_slice_phase_IF0_0,xlslice_v1_0_1_xlslice,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_slice_phase_IF0_0,xlslice_v1_0_1_xlslice,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=48,DIN_FROM=47,DIN_TO=23}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
module RFNCO_cmp_slice_phase_IF1_0
   (Din,
    Dout);
  input [47:0]Din;
  output [24:0]Dout;

  wire [47:0]Din;

  assign Dout[24:0] = Din[47:23];
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_slice_sin_IF0_0,xlslice_v1_0_1_xlslice,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_slice_sin_IF0_0,xlslice_v1_0_1_xlslice,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=64,DIN_FROM=56,DIN_TO=32}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
module RFNCO_cmp_slice_sin_IF0_0
   (Din,
    Dout);
  input [63:0]Din;
  output [24:0]Dout;

  wire [63:0]Din;

  assign Dout[24:0] = Din[56:32];
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_slice_sin_IF0_0,xlslice_v1_0_1_xlslice,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_slice_sin_IF0_0,xlslice_v1_0_1_xlslice,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=64,DIN_FROM=56,DIN_TO=32}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
module RFNCO_cmp_slice_sin_IF1_0
   (Din,
    Dout);
  input [63:0]Din;
  output [24:0]Dout;

  wire [63:0]Din;

  assign Dout[24:0] = Din[56:32];
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_vector_to_std_AM_0,vector_to_std,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_vector_to_std_AM_0,vector_to_std,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=vector_to_std,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "vector_to_std,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_vector_to_std_AM_0
   (in_i,
    out_o);
  input [0:0]in_i;
  output out_o;

  wire [0:0]in_i;

  assign out_o = in_i;
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_vector_to_std_frev_0,vector_to_std,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_vector_to_std_frev_0,vector_to_std,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=vector_to_std,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "vector_to_std,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_vector_to_std_frev_0
   (in_i,
    out_o);
  input [0:0]in_i;
  output out_o;

  wire [0:0]in_i;

  assign out_o = in_i;
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_wr_dftw_slip_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_wr_dftw_slip_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=32}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_wr_dftw_slip_mux_0
   (A,
    B,
    C,
    sel);
  input [31:0]A;
  input [31:0]B;
  output [31:0]C;
  input sel;

  wire [31:0]A;
  wire [31:0]B;
  wire [31:0]C;
  wire sel;

  RFNCO_cmp_wr_dftw_slip_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_wr_dftw_slip_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [31:0]C;
  input [31:0]A;
  input [31:0]B;
  input sel;

  wire [31:0]A;
  wire [31:0]B;
  wire [31:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_wr_ftw_H1_mux_0,generic_mux,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_wr_ftw_H1_mux_0,generic_mux,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=generic_mux,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE=48}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "generic_mux,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_cmp_wr_ftw_H1_mux_0
   (A,
    B,
    C,
    sel);
  input [47:0]A;
  input [47:0]B;
  output [47:0]C;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  RFNCO_cmp_wr_ftw_H1_mux_0_generic_mux U0
       (.A(A),
        .B(B),
        .C(C),
        .sel(sel));
endmodule

(* ORIG_REF_NAME = "generic_mux" *) 
module RFNCO_cmp_wr_ftw_H1_mux_0_generic_mux
   (C,
    A,
    B,
    sel);
  output [47:0]C;
  input [47:0]A;
  input [47:0]B;
  input sel;

  wire [47:0]A;
  wire [47:0]B;
  wire [47:0]C;
  wire sel;

  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[0]_INST_0 
       (.I0(A[0]),
        .I1(B[0]),
        .I2(sel),
        .O(C[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[10]_INST_0 
       (.I0(A[10]),
        .I1(B[10]),
        .I2(sel),
        .O(C[10]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[11]_INST_0 
       (.I0(A[11]),
        .I1(B[11]),
        .I2(sel),
        .O(C[11]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[12]_INST_0 
       (.I0(A[12]),
        .I1(B[12]),
        .I2(sel),
        .O(C[12]));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[13]_INST_0 
       (.I0(A[13]),
        .I1(B[13]),
        .I2(sel),
        .O(C[13]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[14]_INST_0 
       (.I0(A[14]),
        .I1(B[14]),
        .I2(sel),
        .O(C[14]));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[15]_INST_0 
       (.I0(A[15]),
        .I1(B[15]),
        .I2(sel),
        .O(C[15]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[16]_INST_0 
       (.I0(A[16]),
        .I1(B[16]),
        .I2(sel),
        .O(C[16]));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[17]_INST_0 
       (.I0(A[17]),
        .I1(B[17]),
        .I2(sel),
        .O(C[17]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[18]_INST_0 
       (.I0(A[18]),
        .I1(B[18]),
        .I2(sel),
        .O(C[18]));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[19]_INST_0 
       (.I0(A[19]),
        .I1(B[19]),
        .I2(sel),
        .O(C[19]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[1]_INST_0 
       (.I0(A[1]),
        .I1(B[1]),
        .I2(sel),
        .O(C[1]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[20]_INST_0 
       (.I0(A[20]),
        .I1(B[20]),
        .I2(sel),
        .O(C[20]));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[21]_INST_0 
       (.I0(A[21]),
        .I1(B[21]),
        .I2(sel),
        .O(C[21]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[22]_INST_0 
       (.I0(A[22]),
        .I1(B[22]),
        .I2(sel),
        .O(C[22]));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[23]_INST_0 
       (.I0(A[23]),
        .I1(B[23]),
        .I2(sel),
        .O(C[23]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[24]_INST_0 
       (.I0(A[24]),
        .I1(B[24]),
        .I2(sel),
        .O(C[24]));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[25]_INST_0 
       (.I0(A[25]),
        .I1(B[25]),
        .I2(sel),
        .O(C[25]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[26]_INST_0 
       (.I0(A[26]),
        .I1(B[26]),
        .I2(sel),
        .O(C[26]));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[27]_INST_0 
       (.I0(A[27]),
        .I1(B[27]),
        .I2(sel),
        .O(C[27]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[28]_INST_0 
       (.I0(A[28]),
        .I1(B[28]),
        .I2(sel),
        .O(C[28]));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[29]_INST_0 
       (.I0(A[29]),
        .I1(B[29]),
        .I2(sel),
        .O(C[29]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[2]_INST_0 
       (.I0(A[2]),
        .I1(B[2]),
        .I2(sel),
        .O(C[2]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[30]_INST_0 
       (.I0(A[30]),
        .I1(B[30]),
        .I2(sel),
        .O(C[30]));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[31]_INST_0 
       (.I0(A[31]),
        .I1(B[31]),
        .I2(sel),
        .O(C[31]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[32]_INST_0 
       (.I0(A[32]),
        .I1(B[32]),
        .I2(sel),
        .O(C[32]));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[33]_INST_0 
       (.I0(A[33]),
        .I1(B[33]),
        .I2(sel),
        .O(C[33]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[34]_INST_0 
       (.I0(A[34]),
        .I1(B[34]),
        .I2(sel),
        .O(C[34]));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[35]_INST_0 
       (.I0(A[35]),
        .I1(B[35]),
        .I2(sel),
        .O(C[35]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[36]_INST_0 
       (.I0(A[36]),
        .I1(B[36]),
        .I2(sel),
        .O(C[36]));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[37]_INST_0 
       (.I0(A[37]),
        .I1(B[37]),
        .I2(sel),
        .O(C[37]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[38]_INST_0 
       (.I0(A[38]),
        .I1(B[38]),
        .I2(sel),
        .O(C[38]));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[39]_INST_0 
       (.I0(A[39]),
        .I1(B[39]),
        .I2(sel),
        .O(C[39]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[3]_INST_0 
       (.I0(A[3]),
        .I1(B[3]),
        .I2(sel),
        .O(C[3]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[40]_INST_0 
       (.I0(A[40]),
        .I1(B[40]),
        .I2(sel),
        .O(C[40]));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[41]_INST_0 
       (.I0(A[41]),
        .I1(B[41]),
        .I2(sel),
        .O(C[41]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[42]_INST_0 
       (.I0(A[42]),
        .I1(B[42]),
        .I2(sel),
        .O(C[42]));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[43]_INST_0 
       (.I0(A[43]),
        .I1(B[43]),
        .I2(sel),
        .O(C[43]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[44]_INST_0 
       (.I0(A[44]),
        .I1(B[44]),
        .I2(sel),
        .O(C[44]));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[45]_INST_0 
       (.I0(A[45]),
        .I1(B[45]),
        .I2(sel),
        .O(C[45]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[46]_INST_0 
       (.I0(A[46]),
        .I1(B[46]),
        .I2(sel),
        .O(C[46]));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[47]_INST_0 
       (.I0(A[47]),
        .I1(B[47]),
        .I2(sel),
        .O(C[47]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[4]_INST_0 
       (.I0(A[4]),
        .I1(B[4]),
        .I2(sel),
        .O(C[4]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[5]_INST_0 
       (.I0(A[5]),
        .I1(B[5]),
        .I2(sel),
        .O(C[5]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[6]_INST_0 
       (.I0(A[6]),
        .I1(B[6]),
        .I2(sel),
        .O(C[6]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[7]_INST_0 
       (.I0(A[7]),
        .I1(B[7]),
        .I2(sel),
        .O(C[7]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[8]_INST_0 
       (.I0(A[8]),
        .I1(B[8]),
        .I2(sel),
        .O(C[8]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \C[9]_INST_0 
       (.I0(A[9]),
        .I1(B[9]),
        .I2(sel),
        .O(C[9]));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_cmp_zero_7b_0,xlconstant_v1_1_5_xlconstant,{}" *) (* CORE_GENERATION_INFO = "RFNCO_cmp_zero_7b_0,xlconstant_v1_1_5_xlconstant,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconstant,x_ipVersion=1.1,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,CONST_WIDTH=7,CONST_VAL=0x00}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "xlconstant_v1_1_5_xlconstant,Vivado 2018.2" *) 
module RFNCO_cmp_zero_7b_0
   (dout);
  output [6:0]dout;

  wire \<const0> ;

  assign dout[6] = \<const0> ;
  assign dout[5] = \<const0> ;
  assign dout[4] = \<const0> ;
  assign dout[3] = \<const0> ;
  assign dout[2] = \<const0> ;
  assign dout[1] = \<const0> ;
  assign dout[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
endmodule

(* CHECK_LICENSE_TYPE = "RFNCO_rfnco_version_0,rfnco_version,{}" *) (* CORE_GENERATION_INFO = "RFNCO_rfnco_version_0,rfnco_version,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=rfnco_version,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* X_CORE_INFO = "rfnco_version,Vivado 2018.2" *) (* ip_definition_source = "module_ref" *) 
module RFNCO_rfnco_version_0
   (ident_o,
    firmwareVersion_o,
    memMapVersion_o);
  output [31:0]ident_o;
  output [31:0]firmwareVersion_o;
  output [31:0]memMapVersion_o;

  wire \<const0> ;
  wire \<const1> ;

  assign firmwareVersion_o[31] = \<const0> ;
  assign firmwareVersion_o[30] = \<const0> ;
  assign firmwareVersion_o[29] = \<const0> ;
  assign firmwareVersion_o[28] = \<const0> ;
  assign firmwareVersion_o[27] = \<const0> ;
  assign firmwareVersion_o[26] = \<const0> ;
  assign firmwareVersion_o[25] = \<const0> ;
  assign firmwareVersion_o[24] = \<const0> ;
  assign firmwareVersion_o[23] = \<const0> ;
  assign firmwareVersion_o[22] = \<const0> ;
  assign firmwareVersion_o[21] = \<const0> ;
  assign firmwareVersion_o[20] = \<const0> ;
  assign firmwareVersion_o[19] = \<const0> ;
  assign firmwareVersion_o[18] = \<const0> ;
  assign firmwareVersion_o[17] = \<const1> ;
  assign firmwareVersion_o[16] = \<const0> ;
  assign firmwareVersion_o[15] = \<const0> ;
  assign firmwareVersion_o[14] = \<const0> ;
  assign firmwareVersion_o[13] = \<const0> ;
  assign firmwareVersion_o[12] = \<const0> ;
  assign firmwareVersion_o[11] = \<const0> ;
  assign firmwareVersion_o[10] = \<const0> ;
  assign firmwareVersion_o[9] = \<const0> ;
  assign firmwareVersion_o[8] = \<const0> ;
  assign firmwareVersion_o[7] = \<const0> ;
  assign firmwareVersion_o[6] = \<const0> ;
  assign firmwareVersion_o[5] = \<const0> ;
  assign firmwareVersion_o[4] = \<const0> ;
  assign firmwareVersion_o[3] = \<const0> ;
  assign firmwareVersion_o[2] = \<const0> ;
  assign firmwareVersion_o[1] = \<const1> ;
  assign firmwareVersion_o[0] = \<const1> ;
  assign ident_o[31] = \<const0> ;
  assign ident_o[30] = \<const0> ;
  assign ident_o[29] = \<const0> ;
  assign ident_o[28] = \<const0> ;
  assign ident_o[27] = \<const0> ;
  assign ident_o[26] = \<const0> ;
  assign ident_o[25] = \<const0> ;
  assign ident_o[24] = \<const0> ;
  assign ident_o[23] = \<const0> ;
  assign ident_o[22] = \<const0> ;
  assign ident_o[21] = \<const0> ;
  assign ident_o[20] = \<const0> ;
  assign ident_o[19] = \<const0> ;
  assign ident_o[18] = \<const0> ;
  assign ident_o[17] = \<const0> ;
  assign ident_o[16] = \<const0> ;
  assign ident_o[15] = \<const0> ;
  assign ident_o[14] = \<const0> ;
  assign ident_o[13] = \<const0> ;
  assign ident_o[12] = \<const0> ;
  assign ident_o[11] = \<const0> ;
  assign ident_o[10] = \<const0> ;
  assign ident_o[9] = \<const0> ;
  assign ident_o[8] = \<const0> ;
  assign ident_o[7] = \<const0> ;
  assign ident_o[6] = \<const0> ;
  assign ident_o[5] = \<const0> ;
  assign ident_o[4] = \<const1> ;
  assign ident_o[3] = \<const0> ;
  assign ident_o[2] = \<const1> ;
  assign ident_o[1] = \<const0> ;
  assign ident_o[0] = \<const0> ;
  assign memMapVersion_o[31] = \<const0> ;
  assign memMapVersion_o[30] = \<const0> ;
  assign memMapVersion_o[29] = \<const0> ;
  assign memMapVersion_o[28] = \<const0> ;
  assign memMapVersion_o[27] = \<const0> ;
  assign memMapVersion_o[26] = \<const0> ;
  assign memMapVersion_o[25] = \<const0> ;
  assign memMapVersion_o[24] = \<const0> ;
  assign memMapVersion_o[23] = \<const0> ;
  assign memMapVersion_o[22] = \<const0> ;
  assign memMapVersion_o[21] = \<const0> ;
  assign memMapVersion_o[20] = \<const0> ;
  assign memMapVersion_o[19] = \<const0> ;
  assign memMapVersion_o[18] = \<const0> ;
  assign memMapVersion_o[17] = \<const1> ;
  assign memMapVersion_o[16] = \<const0> ;
  assign memMapVersion_o[15] = \<const0> ;
  assign memMapVersion_o[14] = \<const0> ;
  assign memMapVersion_o[13] = \<const0> ;
  assign memMapVersion_o[12] = \<const0> ;
  assign memMapVersion_o[11] = \<const0> ;
  assign memMapVersion_o[10] = \<const0> ;
  assign memMapVersion_o[9] = \<const0> ;
  assign memMapVersion_o[8] = \<const0> ;
  assign memMapVersion_o[7] = \<const0> ;
  assign memMapVersion_o[6] = \<const0> ;
  assign memMapVersion_o[5] = \<const0> ;
  assign memMapVersion_o[4] = \<const0> ;
  assign memMapVersion_o[3] = \<const0> ;
  assign memMapVersion_o[2] = \<const0> ;
  assign memMapVersion_o[1] = \<const0> ;
  assign memMapVersion_o[0] = \<const0> ;
  GND GND
       (.G(\<const0> ));
  VCC VCC
       (.P(\<const1> ));
endmodule

(* STRUCTURAL_NETLIST = "yes" *)
module RFNCO_wrapper_unused
   (AM_auto_on_o,
    AM_o,
    FTW_H1_on_muxed_o,
    FTW_H1_on_muxed_vld_o,
    aximm_i_araddr,
    aximm_i_arprot,
    aximm_i_arready,
    aximm_i_arvalid,
    aximm_i_awaddr,
    aximm_i_awprot,
    aximm_i_awready,
    aximm_i_awvalid,
    aximm_i_bready,
    aximm_i_bresp,
    aximm_i_bvalid,
    aximm_i_rdata,
    aximm_i_rready,
    aximm_i_rresp,
    aximm_i_rvalid,
    aximm_i_wdata,
    aximm_i_wready,
    aximm_i_wstrb,
    aximm_i_wvalid,
    clk_i,
    coef_o,
    coef_vld_o,
    cos_IF0_o,
    cos_IF1_o,
    ext_reset_enable_o,
    ext_reset_o,
    frev_main_o,
    frev_o,
    ftw_H1_o,
    ftw_H1_on_o,
    ftw_LO_0_i,
    ftw_LO_1_i,
    ftw_valid_o,
    interlock_o,
    offset_FSK_i_0,
    offset_i_0,
    phase_H1_comp_o,
    phase_H1_main_o,
    phase_H1_o,
    phase_H1_offset_o,
    phase_H1_prog_offset_o,
    phase_H1_slip_o,
    phase_IF0_o,
    phase_IF1_o,
    rst_i,
    sin_IF0_o,
    sin_IF1_o,
    sincos_vld_o,
    tw_H1_o,
    wr_rf_frame_bus_i_dftw_h1_slip0,
    wr_rf_frame_bus_i_dftw_h1_slip1,
    wr_rf_frame_bus_i_ftw_h1_main,
    wr_rf_frame_bus_i_ftw_h1_on,
    wr_rf_frame_bus_i_ftw_h1_prog,
    wr_rf_frame_bus_i_inputs_valid,
    wr_rf_frame_bus_i_rate,
    wr_rf_frame_bus_i_reset_fsk,
    wr_rf_frame_bus_i_reset_nco,
    wr_rf_frame_bus_i_reset_slip);
  output AM_auto_on_o;
  output AM_o;
  output [47:0]FTW_H1_on_muxed_o;
  output FTW_H1_on_muxed_vld_o;
  input [11:0]aximm_i_araddr;
  input [2:0]aximm_i_arprot;
  output aximm_i_arready;
  input aximm_i_arvalid;
  input [11:0]aximm_i_awaddr;
  input [2:0]aximm_i_awprot;
  output aximm_i_awready;
  input aximm_i_awvalid;
  input aximm_i_bready;
  output [1:0]aximm_i_bresp;
  output aximm_i_bvalid;
  output [31:0]aximm_i_rdata;
  input aximm_i_rready;
  output [1:0]aximm_i_rresp;
  output aximm_i_rvalid;
  input [31:0]aximm_i_wdata;
  output aximm_i_wready;
  input [3:0]aximm_i_wstrb;
  input aximm_i_wvalid;
  input clk_i;
  output [31:0]coef_o;
  output coef_vld_o;
  output [24:0]cos_IF0_o;
  output [24:0]cos_IF1_o;
  output ext_reset_enable_o;
  output [0:0]ext_reset_o;
  output frev_main_o;
  output frev_o;
  output [47:0]ftw_H1_o;
  output [47:0]ftw_H1_on_o;
  input [47:0]ftw_LO_0_i;
  input [47:0]ftw_LO_1_i;
  output [0:0]ftw_valid_o;
  output interlock_o;
  input [47:0]offset_FSK_i_0;
  input [47:0]offset_i_0;
  output [47:0]phase_H1_comp_o;
  output [47:0]phase_H1_main_o;
  output [47:0]phase_H1_o;
  output [47:0]phase_H1_offset_o;
  output [47:0]phase_H1_prog_offset_o;
  output [47:0]phase_H1_slip_o;
  output [47:0]phase_IF0_o;
  output [47:0]phase_IF1_o;
  input rst_i;
  output [24:0]sin_IF0_o;
  output [24:0]sin_IF1_o;
  output [0:0]sincos_vld_o;
  output [31:0]tw_H1_o;
  input [31:0]wr_rf_frame_bus_i_dftw_h1_slip0;
  input [31:0]wr_rf_frame_bus_i_dftw_h1_slip1;
  input [47:0]wr_rf_frame_bus_i_ftw_h1_main;
  input [47:0]wr_rf_frame_bus_i_ftw_h1_on;
  input [47:0]wr_rf_frame_bus_i_ftw_h1_prog;
  input wr_rf_frame_bus_i_inputs_valid;
  input [2:0]wr_rf_frame_bus_i_rate;
  input wr_rf_frame_bus_i_reset_fsk;
  input wr_rf_frame_bus_i_reset_nco;
  input wr_rf_frame_bus_i_reset_slip;

  wire AM_auto_on_o;
  wire AM_auto_on_o_OBUF;
  wire AM_o;
  wire AM_o_OBUF;
  wire [47:0]FTW_H1_on_muxed_o;
  wire [47:0]FTW_H1_on_muxed_o_OBUF;
  wire FTW_H1_on_muxed_vld_o;
  wire FTW_H1_on_muxed_vld_o_OBUF;
  wire [11:0]aximm_i_araddr;
  wire [11:0]aximm_i_araddr_IBUF;
  wire [2:0]aximm_i_arprot;
  wire [2:0]aximm_i_arprot_IBUF;
  wire aximm_i_arready;
  wire aximm_i_arready_OBUF;
  wire aximm_i_arvalid;
  wire aximm_i_arvalid_IBUF;
  wire [11:0]aximm_i_awaddr;
  wire [11:0]aximm_i_awaddr_IBUF;
  wire [2:0]aximm_i_awprot;
  wire [2:0]aximm_i_awprot_IBUF;
  wire aximm_i_awready;
  wire aximm_i_awready_OBUF;
  wire aximm_i_awvalid;
  wire aximm_i_awvalid_IBUF;
  wire aximm_i_bready;
  wire aximm_i_bready_IBUF;
  wire [1:0]aximm_i_bresp;
  wire [1:0]aximm_i_bresp_OBUF;
  wire aximm_i_bvalid;
  wire aximm_i_bvalid_OBUF;
  wire [31:0]aximm_i_rdata;
  wire [31:0]aximm_i_rdata_OBUF;
  wire aximm_i_rready;
  wire aximm_i_rready_IBUF;
  wire [1:0]aximm_i_rresp;
  wire [1:0]aximm_i_rresp_OBUF;
  wire aximm_i_rvalid;
  wire aximm_i_rvalid_OBUF;
  wire [31:0]aximm_i_wdata;
  wire [31:0]aximm_i_wdata_IBUF;
  wire aximm_i_wready;
  wire aximm_i_wready_OBUF;
  wire [3:0]aximm_i_wstrb;
  wire [3:0]aximm_i_wstrb_IBUF;
  wire aximm_i_wvalid;
  wire aximm_i_wvalid_IBUF;
  wire clk_i;
  wire clk_i_IBUF;
  wire [31:0]coef_o;
  wire [31:0]coef_o_OBUF;
  wire coef_vld_o;
  wire coef_vld_o_OBUF;
  wire [24:0]cos_IF0_o;
  wire [24:0]cos_IF0_o_OBUF;
  wire [24:0]cos_IF1_o;
  wire [24:0]cos_IF1_o_OBUF;
  wire ext_reset_enable_o;
  wire ext_reset_enable_o_OBUF;
  wire [0:0]ext_reset_o;
  wire [0:0]ext_reset_o_OBUF;
  wire frev_main_o;
  wire frev_main_o_OBUF;
  wire frev_o;
  wire frev_o_OBUF;
  wire [47:0]ftw_H1_o;
  wire [47:0]ftw_H1_o_OBUF;
  wire [47:0]ftw_H1_on_o;
  wire [47:0]ftw_H1_on_o_OBUF;
  wire [47:0]ftw_LO_0_i;
  wire [47:0]ftw_LO_0_i_IBUF;
  wire [47:0]ftw_LO_1_i;
  wire [47:0]ftw_LO_1_i_IBUF;
  wire [0:0]ftw_valid_o;
  wire [0:0]ftw_valid_o_OBUF;
  wire interlock_o;
  wire interlock_o_OBUF;
  wire [47:0]offset_FSK_i_0;
  wire [47:0]offset_FSK_i_0_IBUF;
  wire [47:0]offset_i_0;
  wire [47:0]offset_i_0_IBUF;
  wire [47:0]phase_H1_comp_o;
  wire [47:0]phase_H1_comp_o_OBUF;
  wire [47:0]phase_H1_main_o;
  wire [47:0]phase_H1_main_o_OBUF;
  wire [47:0]phase_H1_o;
  wire [47:0]phase_H1_o_OBUF;
  wire [47:0]phase_H1_offset_o;
  wire [47:0]phase_H1_offset_o_OBUF;
  wire [47:0]phase_H1_prog_offset_o;
  wire [47:0]phase_H1_prog_offset_o_OBUF;
  wire [47:0]phase_H1_slip_o;
  wire [47:0]phase_H1_slip_o_OBUF;
  wire [47:0]phase_IF0_o;
  wire [47:0]phase_IF0_o_OBUF;
  wire [47:0]phase_IF1_o;
  wire [47:0]phase_IF1_o_OBUF;
  wire rst_i;
  wire rst_i_IBUF;
  wire [24:0]sin_IF0_o;
  wire [24:0]sin_IF0_o_OBUF;
  wire [24:0]sin_IF1_o;
  wire [24:0]sin_IF1_o_OBUF;
  wire [0:0]sincos_vld_o;
  wire [0:0]sincos_vld_o_OBUF;
  wire [31:0]tw_H1_o;
  wire [31:0]tw_H1_o_OBUF;
  wire [31:0]wr_rf_frame_bus_i_dftw_h1_slip0;
  wire [31:0]wr_rf_frame_bus_i_dftw_h1_slip0_IBUF;
  wire [31:0]wr_rf_frame_bus_i_dftw_h1_slip1;
  wire [31:0]wr_rf_frame_bus_i_dftw_h1_slip1_IBUF;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_main;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_main_IBUF;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_on;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_on_IBUF;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_prog;
  wire [47:0]wr_rf_frame_bus_i_ftw_h1_prog_IBUF;
  wire wr_rf_frame_bus_i_inputs_valid;
  wire wr_rf_frame_bus_i_inputs_valid_IBUF;
  wire [2:0]wr_rf_frame_bus_i_rate;
  wire [2:0]wr_rf_frame_bus_i_rate_IBUF;
  wire wr_rf_frame_bus_i_reset_fsk;
  wire wr_rf_frame_bus_i_reset_fsk_IBUF;
  wire wr_rf_frame_bus_i_reset_nco;
  wire wr_rf_frame_bus_i_reset_nco_IBUF;
  wire wr_rf_frame_bus_i_reset_slip;
  wire wr_rf_frame_bus_i_reset_slip_IBUF;

  OBUF AM_auto_on_o_OBUF_inst
       (.I(AM_auto_on_o_OBUF),
        .O(AM_auto_on_o));
  OBUF AM_o_OBUF_inst
       (.I(AM_o_OBUF),
        .O(AM_o));
  OBUF \FTW_H1_on_muxed_o_OBUF[0]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[0]),
        .O(FTW_H1_on_muxed_o[0]));
  OBUF \FTW_H1_on_muxed_o_OBUF[10]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[10]),
        .O(FTW_H1_on_muxed_o[10]));
  OBUF \FTW_H1_on_muxed_o_OBUF[11]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[11]),
        .O(FTW_H1_on_muxed_o[11]));
  OBUF \FTW_H1_on_muxed_o_OBUF[12]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[12]),
        .O(FTW_H1_on_muxed_o[12]));
  OBUF \FTW_H1_on_muxed_o_OBUF[13]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[13]),
        .O(FTW_H1_on_muxed_o[13]));
  OBUF \FTW_H1_on_muxed_o_OBUF[14]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[14]),
        .O(FTW_H1_on_muxed_o[14]));
  OBUF \FTW_H1_on_muxed_o_OBUF[15]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[15]),
        .O(FTW_H1_on_muxed_o[15]));
  OBUF \FTW_H1_on_muxed_o_OBUF[16]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[16]),
        .O(FTW_H1_on_muxed_o[16]));
  OBUF \FTW_H1_on_muxed_o_OBUF[17]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[17]),
        .O(FTW_H1_on_muxed_o[17]));
  OBUF \FTW_H1_on_muxed_o_OBUF[18]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[18]),
        .O(FTW_H1_on_muxed_o[18]));
  OBUF \FTW_H1_on_muxed_o_OBUF[19]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[19]),
        .O(FTW_H1_on_muxed_o[19]));
  OBUF \FTW_H1_on_muxed_o_OBUF[1]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[1]),
        .O(FTW_H1_on_muxed_o[1]));
  OBUF \FTW_H1_on_muxed_o_OBUF[20]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[20]),
        .O(FTW_H1_on_muxed_o[20]));
  OBUF \FTW_H1_on_muxed_o_OBUF[21]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[21]),
        .O(FTW_H1_on_muxed_o[21]));
  OBUF \FTW_H1_on_muxed_o_OBUF[22]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[22]),
        .O(FTW_H1_on_muxed_o[22]));
  OBUF \FTW_H1_on_muxed_o_OBUF[23]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[23]),
        .O(FTW_H1_on_muxed_o[23]));
  OBUF \FTW_H1_on_muxed_o_OBUF[24]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[24]),
        .O(FTW_H1_on_muxed_o[24]));
  OBUF \FTW_H1_on_muxed_o_OBUF[25]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[25]),
        .O(FTW_H1_on_muxed_o[25]));
  OBUF \FTW_H1_on_muxed_o_OBUF[26]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[26]),
        .O(FTW_H1_on_muxed_o[26]));
  OBUF \FTW_H1_on_muxed_o_OBUF[27]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[27]),
        .O(FTW_H1_on_muxed_o[27]));
  OBUF \FTW_H1_on_muxed_o_OBUF[28]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[28]),
        .O(FTW_H1_on_muxed_o[28]));
  OBUF \FTW_H1_on_muxed_o_OBUF[29]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[29]),
        .O(FTW_H1_on_muxed_o[29]));
  OBUF \FTW_H1_on_muxed_o_OBUF[2]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[2]),
        .O(FTW_H1_on_muxed_o[2]));
  OBUF \FTW_H1_on_muxed_o_OBUF[30]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[30]),
        .O(FTW_H1_on_muxed_o[30]));
  OBUF \FTW_H1_on_muxed_o_OBUF[31]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[31]),
        .O(FTW_H1_on_muxed_o[31]));
  OBUF \FTW_H1_on_muxed_o_OBUF[32]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[32]),
        .O(FTW_H1_on_muxed_o[32]));
  OBUF \FTW_H1_on_muxed_o_OBUF[33]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[33]),
        .O(FTW_H1_on_muxed_o[33]));
  OBUF \FTW_H1_on_muxed_o_OBUF[34]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[34]),
        .O(FTW_H1_on_muxed_o[34]));
  OBUF \FTW_H1_on_muxed_o_OBUF[35]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[35]),
        .O(FTW_H1_on_muxed_o[35]));
  OBUF \FTW_H1_on_muxed_o_OBUF[36]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[36]),
        .O(FTW_H1_on_muxed_o[36]));
  OBUF \FTW_H1_on_muxed_o_OBUF[37]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[37]),
        .O(FTW_H1_on_muxed_o[37]));
  OBUF \FTW_H1_on_muxed_o_OBUF[38]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[38]),
        .O(FTW_H1_on_muxed_o[38]));
  OBUF \FTW_H1_on_muxed_o_OBUF[39]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[39]),
        .O(FTW_H1_on_muxed_o[39]));
  OBUF \FTW_H1_on_muxed_o_OBUF[3]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[3]),
        .O(FTW_H1_on_muxed_o[3]));
  OBUF \FTW_H1_on_muxed_o_OBUF[40]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[40]),
        .O(FTW_H1_on_muxed_o[40]));
  OBUF \FTW_H1_on_muxed_o_OBUF[41]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[41]),
        .O(FTW_H1_on_muxed_o[41]));
  OBUF \FTW_H1_on_muxed_o_OBUF[42]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[42]),
        .O(FTW_H1_on_muxed_o[42]));
  OBUF \FTW_H1_on_muxed_o_OBUF[43]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[43]),
        .O(FTW_H1_on_muxed_o[43]));
  OBUF \FTW_H1_on_muxed_o_OBUF[44]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[44]),
        .O(FTW_H1_on_muxed_o[44]));
  OBUF \FTW_H1_on_muxed_o_OBUF[45]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[45]),
        .O(FTW_H1_on_muxed_o[45]));
  OBUF \FTW_H1_on_muxed_o_OBUF[46]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[46]),
        .O(FTW_H1_on_muxed_o[46]));
  OBUF \FTW_H1_on_muxed_o_OBUF[47]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[47]),
        .O(FTW_H1_on_muxed_o[47]));
  OBUF \FTW_H1_on_muxed_o_OBUF[4]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[4]),
        .O(FTW_H1_on_muxed_o[4]));
  OBUF \FTW_H1_on_muxed_o_OBUF[5]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[5]),
        .O(FTW_H1_on_muxed_o[5]));
  OBUF \FTW_H1_on_muxed_o_OBUF[6]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[6]),
        .O(FTW_H1_on_muxed_o[6]));
  OBUF \FTW_H1_on_muxed_o_OBUF[7]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[7]),
        .O(FTW_H1_on_muxed_o[7]));
  OBUF \FTW_H1_on_muxed_o_OBUF[8]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[8]),
        .O(FTW_H1_on_muxed_o[8]));
  OBUF \FTW_H1_on_muxed_o_OBUF[9]_inst 
       (.I(FTW_H1_on_muxed_o_OBUF[9]),
        .O(FTW_H1_on_muxed_o[9]));
  OBUF FTW_H1_on_muxed_vld_o_OBUF_inst
       (.I(FTW_H1_on_muxed_vld_o_OBUF),
        .O(FTW_H1_on_muxed_vld_o));
  (* core_generation_info = "RFNCO,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=RFNCO,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=60,numReposBlks=56,numNonXlnxBlks=0,numHierBlks=4,maxHierDepth=1,numSysgenBlks=0,numHlsBlks=2,numHdlrefBlks=35,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) 
  (* hw_handoff = "RFNCO.hwdef" *) 
  RFNCO RFNCO_i
       (.AM_auto_on_o(AM_auto_on_o_OBUF),
        .AM_o(AM_o_OBUF),
        .FTW_H1_on_muxed_o(FTW_H1_on_muxed_o_OBUF),
        .FTW_H1_on_muxed_vld_o(FTW_H1_on_muxed_vld_o_OBUF),
        .aximm_i_araddr(aximm_i_araddr_IBUF),
        .aximm_i_arprot(aximm_i_arprot_IBUF),
        .aximm_i_arready(aximm_i_arready_OBUF),
        .aximm_i_arvalid(aximm_i_arvalid_IBUF),
        .aximm_i_awaddr(aximm_i_awaddr_IBUF),
        .aximm_i_awprot(aximm_i_awprot_IBUF),
        .aximm_i_awready(aximm_i_awready_OBUF),
        .aximm_i_awvalid(aximm_i_awvalid_IBUF),
        .aximm_i_bready(aximm_i_bready_IBUF),
        .aximm_i_bresp(aximm_i_bresp_OBUF),
        .aximm_i_bvalid(aximm_i_bvalid_OBUF),
        .aximm_i_rdata(aximm_i_rdata_OBUF),
        .aximm_i_rready(aximm_i_rready_IBUF),
        .aximm_i_rresp(aximm_i_rresp_OBUF),
        .aximm_i_rvalid(aximm_i_rvalid_OBUF),
        .aximm_i_wdata(aximm_i_wdata_IBUF),
        .aximm_i_wready(aximm_i_wready_OBUF),
        .aximm_i_wstrb(aximm_i_wstrb_IBUF),
        .aximm_i_wvalid(aximm_i_wvalid_IBUF),
        .clk_i(clk_i_IBUF),
        .coef_o(coef_o_OBUF),
        .coef_vld_o(coef_vld_o_OBUF),
        .cos_IF0_o(cos_IF0_o_OBUF),
        .cos_IF1_o(cos_IF1_o_OBUF),
        .ext_reset_enable_o(ext_reset_enable_o_OBUF),
        .ext_reset_o(ext_reset_o_OBUF),
        .frev_main_o(frev_main_o_OBUF),
        .frev_o(frev_o_OBUF),
        .ftw_H1_o(ftw_H1_o_OBUF),
        .ftw_H1_on_o(ftw_H1_on_o_OBUF),
        .ftw_LO_0_i(ftw_LO_0_i_IBUF),
        .ftw_LO_1_i(ftw_LO_1_i_IBUF),
        .ftw_valid_o(ftw_valid_o_OBUF),
        .interlock_o(interlock_o_OBUF),
        .offset_FSK_i_0(offset_FSK_i_0_IBUF),
        .offset_i_0(offset_i_0_IBUF),
        .phase_H1_comp_o(phase_H1_comp_o_OBUF),
        .phase_H1_main_o(phase_H1_main_o_OBUF),
        .phase_H1_o(phase_H1_o_OBUF),
        .phase_H1_offset_o(phase_H1_offset_o_OBUF),
        .phase_H1_prog_offset_o(phase_H1_prog_offset_o_OBUF),
        .phase_H1_slip_o(phase_H1_slip_o_OBUF),
        .phase_IF0_o(phase_IF0_o_OBUF),
        .phase_IF1_o(phase_IF1_o_OBUF),
        .rst_i(rst_i_IBUF),
        .sin_IF0_o(sin_IF0_o_OBUF),
        .sin_IF1_o(sin_IF1_o_OBUF),
        .sincos_vld_o(sincos_vld_o_OBUF),
        .tw_H1_o(tw_H1_o_OBUF),
        .wr_rf_frame_bus_i_dftw_h1_slip0(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF),
        .wr_rf_frame_bus_i_dftw_h1_slip1(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF),
        .wr_rf_frame_bus_i_ftw_h1_main(wr_rf_frame_bus_i_ftw_h1_main_IBUF),
        .wr_rf_frame_bus_i_ftw_h1_on(wr_rf_frame_bus_i_ftw_h1_on_IBUF),
        .wr_rf_frame_bus_i_ftw_h1_prog(wr_rf_frame_bus_i_ftw_h1_prog_IBUF),
        .wr_rf_frame_bus_i_inputs_valid(wr_rf_frame_bus_i_inputs_valid_IBUF),
        .wr_rf_frame_bus_i_rate(wr_rf_frame_bus_i_rate_IBUF),
        .wr_rf_frame_bus_i_reset_fsk(wr_rf_frame_bus_i_reset_fsk_IBUF),
        .wr_rf_frame_bus_i_reset_nco(wr_rf_frame_bus_i_reset_nco_IBUF),
        .wr_rf_frame_bus_i_reset_slip(wr_rf_frame_bus_i_reset_slip_IBUF));
  IBUF \aximm_i_araddr_IBUF[0]_inst 
       (.I(aximm_i_araddr[0]),
        .O(aximm_i_araddr_IBUF[0]));
  IBUF \aximm_i_araddr_IBUF[10]_inst 
       (.I(aximm_i_araddr[10]),
        .O(aximm_i_araddr_IBUF[10]));
  IBUF \aximm_i_araddr_IBUF[11]_inst 
       (.I(aximm_i_araddr[11]),
        .O(aximm_i_araddr_IBUF[11]));
  IBUF \aximm_i_araddr_IBUF[1]_inst 
       (.I(aximm_i_araddr[1]),
        .O(aximm_i_araddr_IBUF[1]));
  IBUF \aximm_i_araddr_IBUF[2]_inst 
       (.I(aximm_i_araddr[2]),
        .O(aximm_i_araddr_IBUF[2]));
  IBUF \aximm_i_araddr_IBUF[3]_inst 
       (.I(aximm_i_araddr[3]),
        .O(aximm_i_araddr_IBUF[3]));
  IBUF \aximm_i_araddr_IBUF[4]_inst 
       (.I(aximm_i_araddr[4]),
        .O(aximm_i_araddr_IBUF[4]));
  IBUF \aximm_i_araddr_IBUF[5]_inst 
       (.I(aximm_i_araddr[5]),
        .O(aximm_i_araddr_IBUF[5]));
  IBUF \aximm_i_araddr_IBUF[6]_inst 
       (.I(aximm_i_araddr[6]),
        .O(aximm_i_araddr_IBUF[6]));
  IBUF \aximm_i_araddr_IBUF[7]_inst 
       (.I(aximm_i_araddr[7]),
        .O(aximm_i_araddr_IBUF[7]));
  IBUF \aximm_i_araddr_IBUF[8]_inst 
       (.I(aximm_i_araddr[8]),
        .O(aximm_i_araddr_IBUF[8]));
  IBUF \aximm_i_araddr_IBUF[9]_inst 
       (.I(aximm_i_araddr[9]),
        .O(aximm_i_araddr_IBUF[9]));
  IBUF \aximm_i_arprot_IBUF[0]_inst 
       (.I(aximm_i_arprot[0]),
        .O(aximm_i_arprot_IBUF[0]));
  IBUF \aximm_i_arprot_IBUF[1]_inst 
       (.I(aximm_i_arprot[1]),
        .O(aximm_i_arprot_IBUF[1]));
  IBUF \aximm_i_arprot_IBUF[2]_inst 
       (.I(aximm_i_arprot[2]),
        .O(aximm_i_arprot_IBUF[2]));
  OBUF aximm_i_arready_OBUF_inst
       (.I(aximm_i_arready_OBUF),
        .O(aximm_i_arready));
  IBUF aximm_i_arvalid_IBUF_inst
       (.I(aximm_i_arvalid),
        .O(aximm_i_arvalid_IBUF));
  IBUF \aximm_i_awaddr_IBUF[0]_inst 
       (.I(aximm_i_awaddr[0]),
        .O(aximm_i_awaddr_IBUF[0]));
  IBUF \aximm_i_awaddr_IBUF[10]_inst 
       (.I(aximm_i_awaddr[10]),
        .O(aximm_i_awaddr_IBUF[10]));
  IBUF \aximm_i_awaddr_IBUF[11]_inst 
       (.I(aximm_i_awaddr[11]),
        .O(aximm_i_awaddr_IBUF[11]));
  IBUF \aximm_i_awaddr_IBUF[1]_inst 
       (.I(aximm_i_awaddr[1]),
        .O(aximm_i_awaddr_IBUF[1]));
  IBUF \aximm_i_awaddr_IBUF[2]_inst 
       (.I(aximm_i_awaddr[2]),
        .O(aximm_i_awaddr_IBUF[2]));
  IBUF \aximm_i_awaddr_IBUF[3]_inst 
       (.I(aximm_i_awaddr[3]),
        .O(aximm_i_awaddr_IBUF[3]));
  IBUF \aximm_i_awaddr_IBUF[4]_inst 
       (.I(aximm_i_awaddr[4]),
        .O(aximm_i_awaddr_IBUF[4]));
  IBUF \aximm_i_awaddr_IBUF[5]_inst 
       (.I(aximm_i_awaddr[5]),
        .O(aximm_i_awaddr_IBUF[5]));
  IBUF \aximm_i_awaddr_IBUF[6]_inst 
       (.I(aximm_i_awaddr[6]),
        .O(aximm_i_awaddr_IBUF[6]));
  IBUF \aximm_i_awaddr_IBUF[7]_inst 
       (.I(aximm_i_awaddr[7]),
        .O(aximm_i_awaddr_IBUF[7]));
  IBUF \aximm_i_awaddr_IBUF[8]_inst 
       (.I(aximm_i_awaddr[8]),
        .O(aximm_i_awaddr_IBUF[8]));
  IBUF \aximm_i_awaddr_IBUF[9]_inst 
       (.I(aximm_i_awaddr[9]),
        .O(aximm_i_awaddr_IBUF[9]));
  IBUF \aximm_i_awprot_IBUF[0]_inst 
       (.I(aximm_i_awprot[0]),
        .O(aximm_i_awprot_IBUF[0]));
  IBUF \aximm_i_awprot_IBUF[1]_inst 
       (.I(aximm_i_awprot[1]),
        .O(aximm_i_awprot_IBUF[1]));
  IBUF \aximm_i_awprot_IBUF[2]_inst 
       (.I(aximm_i_awprot[2]),
        .O(aximm_i_awprot_IBUF[2]));
  OBUF aximm_i_awready_OBUF_inst
       (.I(aximm_i_awready_OBUF),
        .O(aximm_i_awready));
  IBUF aximm_i_awvalid_IBUF_inst
       (.I(aximm_i_awvalid),
        .O(aximm_i_awvalid_IBUF));
  IBUF aximm_i_bready_IBUF_inst
       (.I(aximm_i_bready),
        .O(aximm_i_bready_IBUF));
  OBUF \aximm_i_bresp_OBUF[0]_inst 
       (.I(aximm_i_bresp_OBUF[0]),
        .O(aximm_i_bresp[0]));
  OBUF \aximm_i_bresp_OBUF[1]_inst 
       (.I(aximm_i_bresp_OBUF[1]),
        .O(aximm_i_bresp[1]));
  OBUF aximm_i_bvalid_OBUF_inst
       (.I(aximm_i_bvalid_OBUF),
        .O(aximm_i_bvalid));
  OBUF \aximm_i_rdata_OBUF[0]_inst 
       (.I(aximm_i_rdata_OBUF[0]),
        .O(aximm_i_rdata[0]));
  OBUF \aximm_i_rdata_OBUF[10]_inst 
       (.I(aximm_i_rdata_OBUF[10]),
        .O(aximm_i_rdata[10]));
  OBUF \aximm_i_rdata_OBUF[11]_inst 
       (.I(aximm_i_rdata_OBUF[11]),
        .O(aximm_i_rdata[11]));
  OBUF \aximm_i_rdata_OBUF[12]_inst 
       (.I(aximm_i_rdata_OBUF[12]),
        .O(aximm_i_rdata[12]));
  OBUF \aximm_i_rdata_OBUF[13]_inst 
       (.I(aximm_i_rdata_OBUF[13]),
        .O(aximm_i_rdata[13]));
  OBUF \aximm_i_rdata_OBUF[14]_inst 
       (.I(aximm_i_rdata_OBUF[14]),
        .O(aximm_i_rdata[14]));
  OBUF \aximm_i_rdata_OBUF[15]_inst 
       (.I(aximm_i_rdata_OBUF[15]),
        .O(aximm_i_rdata[15]));
  OBUF \aximm_i_rdata_OBUF[16]_inst 
       (.I(aximm_i_rdata_OBUF[16]),
        .O(aximm_i_rdata[16]));
  OBUF \aximm_i_rdata_OBUF[17]_inst 
       (.I(aximm_i_rdata_OBUF[17]),
        .O(aximm_i_rdata[17]));
  OBUF \aximm_i_rdata_OBUF[18]_inst 
       (.I(aximm_i_rdata_OBUF[18]),
        .O(aximm_i_rdata[18]));
  OBUF \aximm_i_rdata_OBUF[19]_inst 
       (.I(aximm_i_rdata_OBUF[19]),
        .O(aximm_i_rdata[19]));
  OBUF \aximm_i_rdata_OBUF[1]_inst 
       (.I(aximm_i_rdata_OBUF[1]),
        .O(aximm_i_rdata[1]));
  OBUF \aximm_i_rdata_OBUF[20]_inst 
       (.I(aximm_i_rdata_OBUF[20]),
        .O(aximm_i_rdata[20]));
  OBUF \aximm_i_rdata_OBUF[21]_inst 
       (.I(aximm_i_rdata_OBUF[21]),
        .O(aximm_i_rdata[21]));
  OBUF \aximm_i_rdata_OBUF[22]_inst 
       (.I(aximm_i_rdata_OBUF[22]),
        .O(aximm_i_rdata[22]));
  OBUF \aximm_i_rdata_OBUF[23]_inst 
       (.I(aximm_i_rdata_OBUF[23]),
        .O(aximm_i_rdata[23]));
  OBUF \aximm_i_rdata_OBUF[24]_inst 
       (.I(aximm_i_rdata_OBUF[24]),
        .O(aximm_i_rdata[24]));
  OBUF \aximm_i_rdata_OBUF[25]_inst 
       (.I(aximm_i_rdata_OBUF[25]),
        .O(aximm_i_rdata[25]));
  OBUF \aximm_i_rdata_OBUF[26]_inst 
       (.I(aximm_i_rdata_OBUF[26]),
        .O(aximm_i_rdata[26]));
  OBUF \aximm_i_rdata_OBUF[27]_inst 
       (.I(aximm_i_rdata_OBUF[27]),
        .O(aximm_i_rdata[27]));
  OBUF \aximm_i_rdata_OBUF[28]_inst 
       (.I(aximm_i_rdata_OBUF[28]),
        .O(aximm_i_rdata[28]));
  OBUF \aximm_i_rdata_OBUF[29]_inst 
       (.I(aximm_i_rdata_OBUF[29]),
        .O(aximm_i_rdata[29]));
  OBUF \aximm_i_rdata_OBUF[2]_inst 
       (.I(aximm_i_rdata_OBUF[2]),
        .O(aximm_i_rdata[2]));
  OBUF \aximm_i_rdata_OBUF[30]_inst 
       (.I(aximm_i_rdata_OBUF[30]),
        .O(aximm_i_rdata[30]));
  OBUF \aximm_i_rdata_OBUF[31]_inst 
       (.I(aximm_i_rdata_OBUF[31]),
        .O(aximm_i_rdata[31]));
  OBUF \aximm_i_rdata_OBUF[3]_inst 
       (.I(aximm_i_rdata_OBUF[3]),
        .O(aximm_i_rdata[3]));
  OBUF \aximm_i_rdata_OBUF[4]_inst 
       (.I(aximm_i_rdata_OBUF[4]),
        .O(aximm_i_rdata[4]));
  OBUF \aximm_i_rdata_OBUF[5]_inst 
       (.I(aximm_i_rdata_OBUF[5]),
        .O(aximm_i_rdata[5]));
  OBUF \aximm_i_rdata_OBUF[6]_inst 
       (.I(aximm_i_rdata_OBUF[6]),
        .O(aximm_i_rdata[6]));
  OBUF \aximm_i_rdata_OBUF[7]_inst 
       (.I(aximm_i_rdata_OBUF[7]),
        .O(aximm_i_rdata[7]));
  OBUF \aximm_i_rdata_OBUF[8]_inst 
       (.I(aximm_i_rdata_OBUF[8]),
        .O(aximm_i_rdata[8]));
  OBUF \aximm_i_rdata_OBUF[9]_inst 
       (.I(aximm_i_rdata_OBUF[9]),
        .O(aximm_i_rdata[9]));
  IBUF aximm_i_rready_IBUF_inst
       (.I(aximm_i_rready),
        .O(aximm_i_rready_IBUF));
  OBUF \aximm_i_rresp_OBUF[0]_inst 
       (.I(aximm_i_rresp_OBUF[0]),
        .O(aximm_i_rresp[0]));
  OBUF \aximm_i_rresp_OBUF[1]_inst 
       (.I(aximm_i_rresp_OBUF[1]),
        .O(aximm_i_rresp[1]));
  OBUF aximm_i_rvalid_OBUF_inst
       (.I(aximm_i_rvalid_OBUF),
        .O(aximm_i_rvalid));
  IBUF \aximm_i_wdata_IBUF[0]_inst 
       (.I(aximm_i_wdata[0]),
        .O(aximm_i_wdata_IBUF[0]));
  IBUF \aximm_i_wdata_IBUF[10]_inst 
       (.I(aximm_i_wdata[10]),
        .O(aximm_i_wdata_IBUF[10]));
  IBUF \aximm_i_wdata_IBUF[11]_inst 
       (.I(aximm_i_wdata[11]),
        .O(aximm_i_wdata_IBUF[11]));
  IBUF \aximm_i_wdata_IBUF[12]_inst 
       (.I(aximm_i_wdata[12]),
        .O(aximm_i_wdata_IBUF[12]));
  IBUF \aximm_i_wdata_IBUF[13]_inst 
       (.I(aximm_i_wdata[13]),
        .O(aximm_i_wdata_IBUF[13]));
  IBUF \aximm_i_wdata_IBUF[14]_inst 
       (.I(aximm_i_wdata[14]),
        .O(aximm_i_wdata_IBUF[14]));
  IBUF \aximm_i_wdata_IBUF[15]_inst 
       (.I(aximm_i_wdata[15]),
        .O(aximm_i_wdata_IBUF[15]));
  IBUF \aximm_i_wdata_IBUF[16]_inst 
       (.I(aximm_i_wdata[16]),
        .O(aximm_i_wdata_IBUF[16]));
  IBUF \aximm_i_wdata_IBUF[17]_inst 
       (.I(aximm_i_wdata[17]),
        .O(aximm_i_wdata_IBUF[17]));
  IBUF \aximm_i_wdata_IBUF[18]_inst 
       (.I(aximm_i_wdata[18]),
        .O(aximm_i_wdata_IBUF[18]));
  IBUF \aximm_i_wdata_IBUF[19]_inst 
       (.I(aximm_i_wdata[19]),
        .O(aximm_i_wdata_IBUF[19]));
  IBUF \aximm_i_wdata_IBUF[1]_inst 
       (.I(aximm_i_wdata[1]),
        .O(aximm_i_wdata_IBUF[1]));
  IBUF \aximm_i_wdata_IBUF[20]_inst 
       (.I(aximm_i_wdata[20]),
        .O(aximm_i_wdata_IBUF[20]));
  IBUF \aximm_i_wdata_IBUF[21]_inst 
       (.I(aximm_i_wdata[21]),
        .O(aximm_i_wdata_IBUF[21]));
  IBUF \aximm_i_wdata_IBUF[22]_inst 
       (.I(aximm_i_wdata[22]),
        .O(aximm_i_wdata_IBUF[22]));
  IBUF \aximm_i_wdata_IBUF[23]_inst 
       (.I(aximm_i_wdata[23]),
        .O(aximm_i_wdata_IBUF[23]));
  IBUF \aximm_i_wdata_IBUF[24]_inst 
       (.I(aximm_i_wdata[24]),
        .O(aximm_i_wdata_IBUF[24]));
  IBUF \aximm_i_wdata_IBUF[25]_inst 
       (.I(aximm_i_wdata[25]),
        .O(aximm_i_wdata_IBUF[25]));
  IBUF \aximm_i_wdata_IBUF[26]_inst 
       (.I(aximm_i_wdata[26]),
        .O(aximm_i_wdata_IBUF[26]));
  IBUF \aximm_i_wdata_IBUF[27]_inst 
       (.I(aximm_i_wdata[27]),
        .O(aximm_i_wdata_IBUF[27]));
  IBUF \aximm_i_wdata_IBUF[28]_inst 
       (.I(aximm_i_wdata[28]),
        .O(aximm_i_wdata_IBUF[28]));
  IBUF \aximm_i_wdata_IBUF[29]_inst 
       (.I(aximm_i_wdata[29]),
        .O(aximm_i_wdata_IBUF[29]));
  IBUF \aximm_i_wdata_IBUF[2]_inst 
       (.I(aximm_i_wdata[2]),
        .O(aximm_i_wdata_IBUF[2]));
  IBUF \aximm_i_wdata_IBUF[30]_inst 
       (.I(aximm_i_wdata[30]),
        .O(aximm_i_wdata_IBUF[30]));
  IBUF \aximm_i_wdata_IBUF[31]_inst 
       (.I(aximm_i_wdata[31]),
        .O(aximm_i_wdata_IBUF[31]));
  IBUF \aximm_i_wdata_IBUF[3]_inst 
       (.I(aximm_i_wdata[3]),
        .O(aximm_i_wdata_IBUF[3]));
  IBUF \aximm_i_wdata_IBUF[4]_inst 
       (.I(aximm_i_wdata[4]),
        .O(aximm_i_wdata_IBUF[4]));
  IBUF \aximm_i_wdata_IBUF[5]_inst 
       (.I(aximm_i_wdata[5]),
        .O(aximm_i_wdata_IBUF[5]));
  IBUF \aximm_i_wdata_IBUF[6]_inst 
       (.I(aximm_i_wdata[6]),
        .O(aximm_i_wdata_IBUF[6]));
  IBUF \aximm_i_wdata_IBUF[7]_inst 
       (.I(aximm_i_wdata[7]),
        .O(aximm_i_wdata_IBUF[7]));
  IBUF \aximm_i_wdata_IBUF[8]_inst 
       (.I(aximm_i_wdata[8]),
        .O(aximm_i_wdata_IBUF[8]));
  IBUF \aximm_i_wdata_IBUF[9]_inst 
       (.I(aximm_i_wdata[9]),
        .O(aximm_i_wdata_IBUF[9]));
  OBUF aximm_i_wready_OBUF_inst
       (.I(aximm_i_wready_OBUF),
        .O(aximm_i_wready));
  IBUF \aximm_i_wstrb_IBUF[0]_inst 
       (.I(aximm_i_wstrb[0]),
        .O(aximm_i_wstrb_IBUF[0]));
  IBUF \aximm_i_wstrb_IBUF[1]_inst 
       (.I(aximm_i_wstrb[1]),
        .O(aximm_i_wstrb_IBUF[1]));
  IBUF \aximm_i_wstrb_IBUF[2]_inst 
       (.I(aximm_i_wstrb[2]),
        .O(aximm_i_wstrb_IBUF[2]));
  IBUF \aximm_i_wstrb_IBUF[3]_inst 
       (.I(aximm_i_wstrb[3]),
        .O(aximm_i_wstrb_IBUF[3]));
  IBUF aximm_i_wvalid_IBUF_inst
       (.I(aximm_i_wvalid),
        .O(aximm_i_wvalid_IBUF));
  IBUF clk_i_IBUF_inst
       (.I(clk_i),
        .O(clk_i_IBUF));
  OBUF \coef_o_OBUF[0]_inst 
       (.I(coef_o_OBUF[0]),
        .O(coef_o[0]));
  OBUF \coef_o_OBUF[10]_inst 
       (.I(coef_o_OBUF[10]),
        .O(coef_o[10]));
  OBUF \coef_o_OBUF[11]_inst 
       (.I(coef_o_OBUF[11]),
        .O(coef_o[11]));
  OBUF \coef_o_OBUF[12]_inst 
       (.I(coef_o_OBUF[12]),
        .O(coef_o[12]));
  OBUF \coef_o_OBUF[13]_inst 
       (.I(coef_o_OBUF[13]),
        .O(coef_o[13]));
  OBUF \coef_o_OBUF[14]_inst 
       (.I(coef_o_OBUF[14]),
        .O(coef_o[14]));
  OBUF \coef_o_OBUF[15]_inst 
       (.I(coef_o_OBUF[15]),
        .O(coef_o[15]));
  OBUF \coef_o_OBUF[16]_inst 
       (.I(coef_o_OBUF[16]),
        .O(coef_o[16]));
  OBUF \coef_o_OBUF[17]_inst 
       (.I(coef_o_OBUF[17]),
        .O(coef_o[17]));
  OBUF \coef_o_OBUF[18]_inst 
       (.I(coef_o_OBUF[18]),
        .O(coef_o[18]));
  OBUF \coef_o_OBUF[19]_inst 
       (.I(coef_o_OBUF[19]),
        .O(coef_o[19]));
  OBUF \coef_o_OBUF[1]_inst 
       (.I(coef_o_OBUF[1]),
        .O(coef_o[1]));
  OBUF \coef_o_OBUF[20]_inst 
       (.I(coef_o_OBUF[20]),
        .O(coef_o[20]));
  OBUF \coef_o_OBUF[21]_inst 
       (.I(coef_o_OBUF[21]),
        .O(coef_o[21]));
  OBUF \coef_o_OBUF[22]_inst 
       (.I(coef_o_OBUF[22]),
        .O(coef_o[22]));
  OBUF \coef_o_OBUF[23]_inst 
       (.I(coef_o_OBUF[23]),
        .O(coef_o[23]));
  OBUF \coef_o_OBUF[24]_inst 
       (.I(coef_o_OBUF[24]),
        .O(coef_o[24]));
  OBUF \coef_o_OBUF[25]_inst 
       (.I(coef_o_OBUF[25]),
        .O(coef_o[25]));
  OBUF \coef_o_OBUF[26]_inst 
       (.I(coef_o_OBUF[26]),
        .O(coef_o[26]));
  OBUF \coef_o_OBUF[27]_inst 
       (.I(coef_o_OBUF[27]),
        .O(coef_o[27]));
  OBUF \coef_o_OBUF[28]_inst 
       (.I(coef_o_OBUF[28]),
        .O(coef_o[28]));
  OBUF \coef_o_OBUF[29]_inst 
       (.I(coef_o_OBUF[29]),
        .O(coef_o[29]));
  OBUF \coef_o_OBUF[2]_inst 
       (.I(coef_o_OBUF[2]),
        .O(coef_o[2]));
  OBUF \coef_o_OBUF[30]_inst 
       (.I(coef_o_OBUF[30]),
        .O(coef_o[30]));
  OBUF \coef_o_OBUF[31]_inst 
       (.I(coef_o_OBUF[31]),
        .O(coef_o[31]));
  OBUF \coef_o_OBUF[3]_inst 
       (.I(coef_o_OBUF[3]),
        .O(coef_o[3]));
  OBUF \coef_o_OBUF[4]_inst 
       (.I(coef_o_OBUF[4]),
        .O(coef_o[4]));
  OBUF \coef_o_OBUF[5]_inst 
       (.I(coef_o_OBUF[5]),
        .O(coef_o[5]));
  OBUF \coef_o_OBUF[6]_inst 
       (.I(coef_o_OBUF[6]),
        .O(coef_o[6]));
  OBUF \coef_o_OBUF[7]_inst 
       (.I(coef_o_OBUF[7]),
        .O(coef_o[7]));
  OBUF \coef_o_OBUF[8]_inst 
       (.I(coef_o_OBUF[8]),
        .O(coef_o[8]));
  OBUF \coef_o_OBUF[9]_inst 
       (.I(coef_o_OBUF[9]),
        .O(coef_o[9]));
  OBUF coef_vld_o_OBUF_inst
       (.I(coef_vld_o_OBUF),
        .O(coef_vld_o));
  OBUF \cos_IF0_o_OBUF[0]_inst 
       (.I(cos_IF0_o_OBUF[0]),
        .O(cos_IF0_o[0]));
  OBUF \cos_IF0_o_OBUF[10]_inst 
       (.I(cos_IF0_o_OBUF[10]),
        .O(cos_IF0_o[10]));
  OBUF \cos_IF0_o_OBUF[11]_inst 
       (.I(cos_IF0_o_OBUF[11]),
        .O(cos_IF0_o[11]));
  OBUF \cos_IF0_o_OBUF[12]_inst 
       (.I(cos_IF0_o_OBUF[12]),
        .O(cos_IF0_o[12]));
  OBUF \cos_IF0_o_OBUF[13]_inst 
       (.I(cos_IF0_o_OBUF[13]),
        .O(cos_IF0_o[13]));
  OBUF \cos_IF0_o_OBUF[14]_inst 
       (.I(cos_IF0_o_OBUF[14]),
        .O(cos_IF0_o[14]));
  OBUF \cos_IF0_o_OBUF[15]_inst 
       (.I(cos_IF0_o_OBUF[15]),
        .O(cos_IF0_o[15]));
  OBUF \cos_IF0_o_OBUF[16]_inst 
       (.I(cos_IF0_o_OBUF[16]),
        .O(cos_IF0_o[16]));
  OBUF \cos_IF0_o_OBUF[17]_inst 
       (.I(cos_IF0_o_OBUF[17]),
        .O(cos_IF0_o[17]));
  OBUF \cos_IF0_o_OBUF[18]_inst 
       (.I(cos_IF0_o_OBUF[18]),
        .O(cos_IF0_o[18]));
  OBUF \cos_IF0_o_OBUF[19]_inst 
       (.I(cos_IF0_o_OBUF[19]),
        .O(cos_IF0_o[19]));
  OBUF \cos_IF0_o_OBUF[1]_inst 
       (.I(cos_IF0_o_OBUF[1]),
        .O(cos_IF0_o[1]));
  OBUF \cos_IF0_o_OBUF[20]_inst 
       (.I(cos_IF0_o_OBUF[20]),
        .O(cos_IF0_o[20]));
  OBUF \cos_IF0_o_OBUF[21]_inst 
       (.I(cos_IF0_o_OBUF[21]),
        .O(cos_IF0_o[21]));
  OBUF \cos_IF0_o_OBUF[22]_inst 
       (.I(cos_IF0_o_OBUF[22]),
        .O(cos_IF0_o[22]));
  OBUF \cos_IF0_o_OBUF[23]_inst 
       (.I(cos_IF0_o_OBUF[23]),
        .O(cos_IF0_o[23]));
  OBUF \cos_IF0_o_OBUF[24]_inst 
       (.I(cos_IF0_o_OBUF[24]),
        .O(cos_IF0_o[24]));
  OBUF \cos_IF0_o_OBUF[2]_inst 
       (.I(cos_IF0_o_OBUF[2]),
        .O(cos_IF0_o[2]));
  OBUF \cos_IF0_o_OBUF[3]_inst 
       (.I(cos_IF0_o_OBUF[3]),
        .O(cos_IF0_o[3]));
  OBUF \cos_IF0_o_OBUF[4]_inst 
       (.I(cos_IF0_o_OBUF[4]),
        .O(cos_IF0_o[4]));
  OBUF \cos_IF0_o_OBUF[5]_inst 
       (.I(cos_IF0_o_OBUF[5]),
        .O(cos_IF0_o[5]));
  OBUF \cos_IF0_o_OBUF[6]_inst 
       (.I(cos_IF0_o_OBUF[6]),
        .O(cos_IF0_o[6]));
  OBUF \cos_IF0_o_OBUF[7]_inst 
       (.I(cos_IF0_o_OBUF[7]),
        .O(cos_IF0_o[7]));
  OBUF \cos_IF0_o_OBUF[8]_inst 
       (.I(cos_IF0_o_OBUF[8]),
        .O(cos_IF0_o[8]));
  OBUF \cos_IF0_o_OBUF[9]_inst 
       (.I(cos_IF0_o_OBUF[9]),
        .O(cos_IF0_o[9]));
  OBUF \cos_IF1_o_OBUF[0]_inst 
       (.I(cos_IF1_o_OBUF[0]),
        .O(cos_IF1_o[0]));
  OBUF \cos_IF1_o_OBUF[10]_inst 
       (.I(cos_IF1_o_OBUF[10]),
        .O(cos_IF1_o[10]));
  OBUF \cos_IF1_o_OBUF[11]_inst 
       (.I(cos_IF1_o_OBUF[11]),
        .O(cos_IF1_o[11]));
  OBUF \cos_IF1_o_OBUF[12]_inst 
       (.I(cos_IF1_o_OBUF[12]),
        .O(cos_IF1_o[12]));
  OBUF \cos_IF1_o_OBUF[13]_inst 
       (.I(cos_IF1_o_OBUF[13]),
        .O(cos_IF1_o[13]));
  OBUF \cos_IF1_o_OBUF[14]_inst 
       (.I(cos_IF1_o_OBUF[14]),
        .O(cos_IF1_o[14]));
  OBUF \cos_IF1_o_OBUF[15]_inst 
       (.I(cos_IF1_o_OBUF[15]),
        .O(cos_IF1_o[15]));
  OBUF \cos_IF1_o_OBUF[16]_inst 
       (.I(cos_IF1_o_OBUF[16]),
        .O(cos_IF1_o[16]));
  OBUF \cos_IF1_o_OBUF[17]_inst 
       (.I(cos_IF1_o_OBUF[17]),
        .O(cos_IF1_o[17]));
  OBUF \cos_IF1_o_OBUF[18]_inst 
       (.I(cos_IF1_o_OBUF[18]),
        .O(cos_IF1_o[18]));
  OBUF \cos_IF1_o_OBUF[19]_inst 
       (.I(cos_IF1_o_OBUF[19]),
        .O(cos_IF1_o[19]));
  OBUF \cos_IF1_o_OBUF[1]_inst 
       (.I(cos_IF1_o_OBUF[1]),
        .O(cos_IF1_o[1]));
  OBUF \cos_IF1_o_OBUF[20]_inst 
       (.I(cos_IF1_o_OBUF[20]),
        .O(cos_IF1_o[20]));
  OBUF \cos_IF1_o_OBUF[21]_inst 
       (.I(cos_IF1_o_OBUF[21]),
        .O(cos_IF1_o[21]));
  OBUF \cos_IF1_o_OBUF[22]_inst 
       (.I(cos_IF1_o_OBUF[22]),
        .O(cos_IF1_o[22]));
  OBUF \cos_IF1_o_OBUF[23]_inst 
       (.I(cos_IF1_o_OBUF[23]),
        .O(cos_IF1_o[23]));
  OBUF \cos_IF1_o_OBUF[24]_inst 
       (.I(cos_IF1_o_OBUF[24]),
        .O(cos_IF1_o[24]));
  OBUF \cos_IF1_o_OBUF[2]_inst 
       (.I(cos_IF1_o_OBUF[2]),
        .O(cos_IF1_o[2]));
  OBUF \cos_IF1_o_OBUF[3]_inst 
       (.I(cos_IF1_o_OBUF[3]),
        .O(cos_IF1_o[3]));
  OBUF \cos_IF1_o_OBUF[4]_inst 
       (.I(cos_IF1_o_OBUF[4]),
        .O(cos_IF1_o[4]));
  OBUF \cos_IF1_o_OBUF[5]_inst 
       (.I(cos_IF1_o_OBUF[5]),
        .O(cos_IF1_o[5]));
  OBUF \cos_IF1_o_OBUF[6]_inst 
       (.I(cos_IF1_o_OBUF[6]),
        .O(cos_IF1_o[6]));
  OBUF \cos_IF1_o_OBUF[7]_inst 
       (.I(cos_IF1_o_OBUF[7]),
        .O(cos_IF1_o[7]));
  OBUF \cos_IF1_o_OBUF[8]_inst 
       (.I(cos_IF1_o_OBUF[8]),
        .O(cos_IF1_o[8]));
  OBUF \cos_IF1_o_OBUF[9]_inst 
       (.I(cos_IF1_o_OBUF[9]),
        .O(cos_IF1_o[9]));
  OBUF ext_reset_enable_o_OBUF_inst
       (.I(ext_reset_enable_o_OBUF),
        .O(ext_reset_enable_o));
  OBUF \ext_reset_o_OBUF[0]_inst 
       (.I(ext_reset_o_OBUF),
        .O(ext_reset_o));
  OBUF frev_main_o_OBUF_inst
       (.I(frev_main_o_OBUF),
        .O(frev_main_o));
  OBUF frev_o_OBUF_inst
       (.I(frev_o_OBUF),
        .O(frev_o));
  OBUF \ftw_H1_o_OBUF[0]_inst 
       (.I(ftw_H1_o_OBUF[0]),
        .O(ftw_H1_o[0]));
  OBUF \ftw_H1_o_OBUF[10]_inst 
       (.I(ftw_H1_o_OBUF[10]),
        .O(ftw_H1_o[10]));
  OBUF \ftw_H1_o_OBUF[11]_inst 
       (.I(ftw_H1_o_OBUF[11]),
        .O(ftw_H1_o[11]));
  OBUF \ftw_H1_o_OBUF[12]_inst 
       (.I(ftw_H1_o_OBUF[12]),
        .O(ftw_H1_o[12]));
  OBUF \ftw_H1_o_OBUF[13]_inst 
       (.I(ftw_H1_o_OBUF[13]),
        .O(ftw_H1_o[13]));
  OBUF \ftw_H1_o_OBUF[14]_inst 
       (.I(ftw_H1_o_OBUF[14]),
        .O(ftw_H1_o[14]));
  OBUF \ftw_H1_o_OBUF[15]_inst 
       (.I(ftw_H1_o_OBUF[15]),
        .O(ftw_H1_o[15]));
  OBUF \ftw_H1_o_OBUF[16]_inst 
       (.I(ftw_H1_o_OBUF[16]),
        .O(ftw_H1_o[16]));
  OBUF \ftw_H1_o_OBUF[17]_inst 
       (.I(ftw_H1_o_OBUF[17]),
        .O(ftw_H1_o[17]));
  OBUF \ftw_H1_o_OBUF[18]_inst 
       (.I(ftw_H1_o_OBUF[18]),
        .O(ftw_H1_o[18]));
  OBUF \ftw_H1_o_OBUF[19]_inst 
       (.I(ftw_H1_o_OBUF[19]),
        .O(ftw_H1_o[19]));
  OBUF \ftw_H1_o_OBUF[1]_inst 
       (.I(ftw_H1_o_OBUF[1]),
        .O(ftw_H1_o[1]));
  OBUF \ftw_H1_o_OBUF[20]_inst 
       (.I(ftw_H1_o_OBUF[20]),
        .O(ftw_H1_o[20]));
  OBUF \ftw_H1_o_OBUF[21]_inst 
       (.I(ftw_H1_o_OBUF[21]),
        .O(ftw_H1_o[21]));
  OBUF \ftw_H1_o_OBUF[22]_inst 
       (.I(ftw_H1_o_OBUF[22]),
        .O(ftw_H1_o[22]));
  OBUF \ftw_H1_o_OBUF[23]_inst 
       (.I(ftw_H1_o_OBUF[23]),
        .O(ftw_H1_o[23]));
  OBUF \ftw_H1_o_OBUF[24]_inst 
       (.I(ftw_H1_o_OBUF[24]),
        .O(ftw_H1_o[24]));
  OBUF \ftw_H1_o_OBUF[25]_inst 
       (.I(ftw_H1_o_OBUF[25]),
        .O(ftw_H1_o[25]));
  OBUF \ftw_H1_o_OBUF[26]_inst 
       (.I(ftw_H1_o_OBUF[26]),
        .O(ftw_H1_o[26]));
  OBUF \ftw_H1_o_OBUF[27]_inst 
       (.I(ftw_H1_o_OBUF[27]),
        .O(ftw_H1_o[27]));
  OBUF \ftw_H1_o_OBUF[28]_inst 
       (.I(ftw_H1_o_OBUF[28]),
        .O(ftw_H1_o[28]));
  OBUF \ftw_H1_o_OBUF[29]_inst 
       (.I(ftw_H1_o_OBUF[29]),
        .O(ftw_H1_o[29]));
  OBUF \ftw_H1_o_OBUF[2]_inst 
       (.I(ftw_H1_o_OBUF[2]),
        .O(ftw_H1_o[2]));
  OBUF \ftw_H1_o_OBUF[30]_inst 
       (.I(ftw_H1_o_OBUF[30]),
        .O(ftw_H1_o[30]));
  OBUF \ftw_H1_o_OBUF[31]_inst 
       (.I(ftw_H1_o_OBUF[31]),
        .O(ftw_H1_o[31]));
  OBUF \ftw_H1_o_OBUF[32]_inst 
       (.I(ftw_H1_o_OBUF[32]),
        .O(ftw_H1_o[32]));
  OBUF \ftw_H1_o_OBUF[33]_inst 
       (.I(ftw_H1_o_OBUF[33]),
        .O(ftw_H1_o[33]));
  OBUF \ftw_H1_o_OBUF[34]_inst 
       (.I(ftw_H1_o_OBUF[34]),
        .O(ftw_H1_o[34]));
  OBUF \ftw_H1_o_OBUF[35]_inst 
       (.I(ftw_H1_o_OBUF[35]),
        .O(ftw_H1_o[35]));
  OBUF \ftw_H1_o_OBUF[36]_inst 
       (.I(ftw_H1_o_OBUF[36]),
        .O(ftw_H1_o[36]));
  OBUF \ftw_H1_o_OBUF[37]_inst 
       (.I(ftw_H1_o_OBUF[37]),
        .O(ftw_H1_o[37]));
  OBUF \ftw_H1_o_OBUF[38]_inst 
       (.I(ftw_H1_o_OBUF[38]),
        .O(ftw_H1_o[38]));
  OBUF \ftw_H1_o_OBUF[39]_inst 
       (.I(ftw_H1_o_OBUF[39]),
        .O(ftw_H1_o[39]));
  OBUF \ftw_H1_o_OBUF[3]_inst 
       (.I(ftw_H1_o_OBUF[3]),
        .O(ftw_H1_o[3]));
  OBUF \ftw_H1_o_OBUF[40]_inst 
       (.I(ftw_H1_o_OBUF[40]),
        .O(ftw_H1_o[40]));
  OBUF \ftw_H1_o_OBUF[41]_inst 
       (.I(ftw_H1_o_OBUF[41]),
        .O(ftw_H1_o[41]));
  OBUF \ftw_H1_o_OBUF[42]_inst 
       (.I(ftw_H1_o_OBUF[42]),
        .O(ftw_H1_o[42]));
  OBUF \ftw_H1_o_OBUF[43]_inst 
       (.I(ftw_H1_o_OBUF[43]),
        .O(ftw_H1_o[43]));
  OBUF \ftw_H1_o_OBUF[44]_inst 
       (.I(ftw_H1_o_OBUF[44]),
        .O(ftw_H1_o[44]));
  OBUF \ftw_H1_o_OBUF[45]_inst 
       (.I(ftw_H1_o_OBUF[45]),
        .O(ftw_H1_o[45]));
  OBUF \ftw_H1_o_OBUF[46]_inst 
       (.I(ftw_H1_o_OBUF[46]),
        .O(ftw_H1_o[46]));
  OBUF \ftw_H1_o_OBUF[47]_inst 
       (.I(ftw_H1_o_OBUF[47]),
        .O(ftw_H1_o[47]));
  OBUF \ftw_H1_o_OBUF[4]_inst 
       (.I(ftw_H1_o_OBUF[4]),
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  OBUF \phase_IF0_o_OBUF[2]_inst 
       (.I(phase_IF0_o_OBUF[2]),
        .O(phase_IF0_o[2]));
  OBUF \phase_IF0_o_OBUF[30]_inst 
       (.I(phase_IF0_o_OBUF[30]),
        .O(phase_IF0_o[30]));
  OBUF \phase_IF0_o_OBUF[31]_inst 
       (.I(phase_IF0_o_OBUF[31]),
        .O(phase_IF0_o[31]));
  OBUF \phase_IF0_o_OBUF[32]_inst 
       (.I(phase_IF0_o_OBUF[32]),
        .O(phase_IF0_o[32]));
  OBUF \phase_IF0_o_OBUF[33]_inst 
       (.I(phase_IF0_o_OBUF[33]),
        .O(phase_IF0_o[33]));
  OBUF \phase_IF0_o_OBUF[34]_inst 
       (.I(phase_IF0_o_OBUF[34]),
        .O(phase_IF0_o[34]));
  OBUF \phase_IF0_o_OBUF[35]_inst 
       (.I(phase_IF0_o_OBUF[35]),
        .O(phase_IF0_o[35]));
  OBUF \phase_IF0_o_OBUF[36]_inst 
       (.I(phase_IF0_o_OBUF[36]),
        .O(phase_IF0_o[36]));
  OBUF \phase_IF0_o_OBUF[37]_inst 
       (.I(phase_IF0_o_OBUF[37]),
        .O(phase_IF0_o[37]));
  OBUF \phase_IF0_o_OBUF[38]_inst 
       (.I(phase_IF0_o_OBUF[38]),
        .O(phase_IF0_o[38]));
  OBUF \phase_IF0_o_OBUF[39]_inst 
       (.I(phase_IF0_o_OBUF[39]),
        .O(phase_IF0_o[39]));
  OBUF \phase_IF0_o_OBUF[3]_inst 
       (.I(phase_IF0_o_OBUF[3]),
        .O(phase_IF0_o[3]));
  OBUF \phase_IF0_o_OBUF[40]_inst 
       (.I(phase_IF0_o_OBUF[40]),
        .O(phase_IF0_o[40]));
  OBUF \phase_IF0_o_OBUF[41]_inst 
       (.I(phase_IF0_o_OBUF[41]),
        .O(phase_IF0_o[41]));
  OBUF \phase_IF0_o_OBUF[42]_inst 
       (.I(phase_IF0_o_OBUF[42]),
        .O(phase_IF0_o[42]));
  OBUF \phase_IF0_o_OBUF[43]_inst 
       (.I(phase_IF0_o_OBUF[43]),
        .O(phase_IF0_o[43]));
  OBUF \phase_IF0_o_OBUF[44]_inst 
       (.I(phase_IF0_o_OBUF[44]),
        .O(phase_IF0_o[44]));
  OBUF \phase_IF0_o_OBUF[45]_inst 
       (.I(phase_IF0_o_OBUF[45]),
        .O(phase_IF0_o[45]));
  OBUF \phase_IF0_o_OBUF[46]_inst 
       (.I(phase_IF0_o_OBUF[46]),
        .O(phase_IF0_o[46]));
  OBUF \phase_IF0_o_OBUF[47]_inst 
       (.I(phase_IF0_o_OBUF[47]),
        .O(phase_IF0_o[47]));
  OBUF \phase_IF0_o_OBUF[4]_inst 
       (.I(phase_IF0_o_OBUF[4]),
        .O(phase_IF0_o[4]));
  OBUF \phase_IF0_o_OBUF[5]_inst 
       (.I(phase_IF0_o_OBUF[5]),
        .O(phase_IF0_o[5]));
  OBUF \phase_IF0_o_OBUF[6]_inst 
       (.I(phase_IF0_o_OBUF[6]),
        .O(phase_IF0_o[6]));
  OBUF \phase_IF0_o_OBUF[7]_inst 
       (.I(phase_IF0_o_OBUF[7]),
        .O(phase_IF0_o[7]));
  OBUF \phase_IF0_o_OBUF[8]_inst 
       (.I(phase_IF0_o_OBUF[8]),
        .O(phase_IF0_o[8]));
  OBUF \phase_IF0_o_OBUF[9]_inst 
       (.I(phase_IF0_o_OBUF[9]),
        .O(phase_IF0_o[9]));
  OBUF \phase_IF1_o_OBUF[0]_inst 
       (.I(phase_IF1_o_OBUF[0]),
        .O(phase_IF1_o[0]));
  OBUF \phase_IF1_o_OBUF[10]_inst 
       (.I(phase_IF1_o_OBUF[10]),
        .O(phase_IF1_o[10]));
  OBUF \phase_IF1_o_OBUF[11]_inst 
       (.I(phase_IF1_o_OBUF[11]),
        .O(phase_IF1_o[11]));
  OBUF \phase_IF1_o_OBUF[12]_inst 
       (.I(phase_IF1_o_OBUF[12]),
        .O(phase_IF1_o[12]));
  OBUF \phase_IF1_o_OBUF[13]_inst 
       (.I(phase_IF1_o_OBUF[13]),
        .O(phase_IF1_o[13]));
  OBUF \phase_IF1_o_OBUF[14]_inst 
       (.I(phase_IF1_o_OBUF[14]),
        .O(phase_IF1_o[14]));
  OBUF \phase_IF1_o_OBUF[15]_inst 
       (.I(phase_IF1_o_OBUF[15]),
        .O(phase_IF1_o[15]));
  OBUF \phase_IF1_o_OBUF[16]_inst 
       (.I(phase_IF1_o_OBUF[16]),
        .O(phase_IF1_o[16]));
  OBUF \phase_IF1_o_OBUF[17]_inst 
       (.I(phase_IF1_o_OBUF[17]),
        .O(phase_IF1_o[17]));
  OBUF \phase_IF1_o_OBUF[18]_inst 
       (.I(phase_IF1_o_OBUF[18]),
        .O(phase_IF1_o[18]));
  OBUF \phase_IF1_o_OBUF[19]_inst 
       (.I(phase_IF1_o_OBUF[19]),
        .O(phase_IF1_o[19]));
  OBUF \phase_IF1_o_OBUF[1]_inst 
       (.I(phase_IF1_o_OBUF[1]),
        .O(phase_IF1_o[1]));
  OBUF \phase_IF1_o_OBUF[20]_inst 
       (.I(phase_IF1_o_OBUF[20]),
        .O(phase_IF1_o[20]));
  OBUF \phase_IF1_o_OBUF[21]_inst 
       (.I(phase_IF1_o_OBUF[21]),
        .O(phase_IF1_o[21]));
  OBUF \phase_IF1_o_OBUF[22]_inst 
       (.I(phase_IF1_o_OBUF[22]),
        .O(phase_IF1_o[22]));
  OBUF \phase_IF1_o_OBUF[23]_inst 
       (.I(phase_IF1_o_OBUF[23]),
        .O(phase_IF1_o[23]));
  OBUF \phase_IF1_o_OBUF[24]_inst 
       (.I(phase_IF1_o_OBUF[24]),
        .O(phase_IF1_o[24]));
  OBUF \phase_IF1_o_OBUF[25]_inst 
       (.I(phase_IF1_o_OBUF[25]),
        .O(phase_IF1_o[25]));
  OBUF \phase_IF1_o_OBUF[26]_inst 
       (.I(phase_IF1_o_OBUF[26]),
        .O(phase_IF1_o[26]));
  OBUF \phase_IF1_o_OBUF[27]_inst 
       (.I(phase_IF1_o_OBUF[27]),
        .O(phase_IF1_o[27]));
  OBUF \phase_IF1_o_OBUF[28]_inst 
       (.I(phase_IF1_o_OBUF[28]),
        .O(phase_IF1_o[28]));
  OBUF \phase_IF1_o_OBUF[29]_inst 
       (.I(phase_IF1_o_OBUF[29]),
        .O(phase_IF1_o[29]));
  OBUF \phase_IF1_o_OBUF[2]_inst 
       (.I(phase_IF1_o_OBUF[2]),
        .O(phase_IF1_o[2]));
  OBUF \phase_IF1_o_OBUF[30]_inst 
       (.I(phase_IF1_o_OBUF[30]),
        .O(phase_IF1_o[30]));
  OBUF \phase_IF1_o_OBUF[31]_inst 
       (.I(phase_IF1_o_OBUF[31]),
        .O(phase_IF1_o[31]));
  OBUF \phase_IF1_o_OBUF[32]_inst 
       (.I(phase_IF1_o_OBUF[32]),
        .O(phase_IF1_o[32]));
  OBUF \phase_IF1_o_OBUF[33]_inst 
       (.I(phase_IF1_o_OBUF[33]),
        .O(phase_IF1_o[33]));
  OBUF \phase_IF1_o_OBUF[34]_inst 
       (.I(phase_IF1_o_OBUF[34]),
        .O(phase_IF1_o[34]));
  OBUF \phase_IF1_o_OBUF[35]_inst 
       (.I(phase_IF1_o_OBUF[35]),
        .O(phase_IF1_o[35]));
  OBUF \phase_IF1_o_OBUF[36]_inst 
       (.I(phase_IF1_o_OBUF[36]),
        .O(phase_IF1_o[36]));
  OBUF \phase_IF1_o_OBUF[37]_inst 
       (.I(phase_IF1_o_OBUF[37]),
        .O(phase_IF1_o[37]));
  OBUF \phase_IF1_o_OBUF[38]_inst 
       (.I(phase_IF1_o_OBUF[38]),
        .O(phase_IF1_o[38]));
  OBUF \phase_IF1_o_OBUF[39]_inst 
       (.I(phase_IF1_o_OBUF[39]),
        .O(phase_IF1_o[39]));
  OBUF \phase_IF1_o_OBUF[3]_inst 
       (.I(phase_IF1_o_OBUF[3]),
        .O(phase_IF1_o[3]));
  OBUF \phase_IF1_o_OBUF[40]_inst 
       (.I(phase_IF1_o_OBUF[40]),
        .O(phase_IF1_o[40]));
  OBUF \phase_IF1_o_OBUF[41]_inst 
       (.I(phase_IF1_o_OBUF[41]),
        .O(phase_IF1_o[41]));
  OBUF \phase_IF1_o_OBUF[42]_inst 
       (.I(phase_IF1_o_OBUF[42]),
        .O(phase_IF1_o[42]));
  OBUF \phase_IF1_o_OBUF[43]_inst 
       (.I(phase_IF1_o_OBUF[43]),
        .O(phase_IF1_o[43]));
  OBUF \phase_IF1_o_OBUF[44]_inst 
       (.I(phase_IF1_o_OBUF[44]),
        .O(phase_IF1_o[44]));
  OBUF \phase_IF1_o_OBUF[45]_inst 
       (.I(phase_IF1_o_OBUF[45]),
        .O(phase_IF1_o[45]));
  OBUF \phase_IF1_o_OBUF[46]_inst 
       (.I(phase_IF1_o_OBUF[46]),
        .O(phase_IF1_o[46]));
  OBUF \phase_IF1_o_OBUF[47]_inst 
       (.I(phase_IF1_o_OBUF[47]),
        .O(phase_IF1_o[47]));
  OBUF \phase_IF1_o_OBUF[4]_inst 
       (.I(phase_IF1_o_OBUF[4]),
        .O(phase_IF1_o[4]));
  OBUF \phase_IF1_o_OBUF[5]_inst 
       (.I(phase_IF1_o_OBUF[5]),
        .O(phase_IF1_o[5]));
  OBUF \phase_IF1_o_OBUF[6]_inst 
       (.I(phase_IF1_o_OBUF[6]),
        .O(phase_IF1_o[6]));
  OBUF \phase_IF1_o_OBUF[7]_inst 
       (.I(phase_IF1_o_OBUF[7]),
        .O(phase_IF1_o[7]));
  OBUF \phase_IF1_o_OBUF[8]_inst 
       (.I(phase_IF1_o_OBUF[8]),
        .O(phase_IF1_o[8]));
  OBUF \phase_IF1_o_OBUF[9]_inst 
       (.I(phase_IF1_o_OBUF[9]),
        .O(phase_IF1_o[9]));
  IBUF rst_i_IBUF_inst
       (.I(rst_i),
        .O(rst_i_IBUF));
  OBUF \sin_IF0_o_OBUF[0]_inst 
       (.I(sin_IF0_o_OBUF[0]),
        .O(sin_IF0_o[0]));
  OBUF \sin_IF0_o_OBUF[10]_inst 
       (.I(sin_IF0_o_OBUF[10]),
        .O(sin_IF0_o[10]));
  OBUF \sin_IF0_o_OBUF[11]_inst 
       (.I(sin_IF0_o_OBUF[11]),
        .O(sin_IF0_o[11]));
  OBUF \sin_IF0_o_OBUF[12]_inst 
       (.I(sin_IF0_o_OBUF[12]),
        .O(sin_IF0_o[12]));
  OBUF \sin_IF0_o_OBUF[13]_inst 
       (.I(sin_IF0_o_OBUF[13]),
        .O(sin_IF0_o[13]));
  OBUF \sin_IF0_o_OBUF[14]_inst 
       (.I(sin_IF0_o_OBUF[14]),
        .O(sin_IF0_o[14]));
  OBUF \sin_IF0_o_OBUF[15]_inst 
       (.I(sin_IF0_o_OBUF[15]),
        .O(sin_IF0_o[15]));
  OBUF \sin_IF0_o_OBUF[16]_inst 
       (.I(sin_IF0_o_OBUF[16]),
        .O(sin_IF0_o[16]));
  OBUF \sin_IF0_o_OBUF[17]_inst 
       (.I(sin_IF0_o_OBUF[17]),
        .O(sin_IF0_o[17]));
  OBUF \sin_IF0_o_OBUF[18]_inst 
       (.I(sin_IF0_o_OBUF[18]),
        .O(sin_IF0_o[18]));
  OBUF \sin_IF0_o_OBUF[19]_inst 
       (.I(sin_IF0_o_OBUF[19]),
        .O(sin_IF0_o[19]));
  OBUF \sin_IF0_o_OBUF[1]_inst 
       (.I(sin_IF0_o_OBUF[1]),
        .O(sin_IF0_o[1]));
  OBUF \sin_IF0_o_OBUF[20]_inst 
       (.I(sin_IF0_o_OBUF[20]),
        .O(sin_IF0_o[20]));
  OBUF \sin_IF0_o_OBUF[21]_inst 
       (.I(sin_IF0_o_OBUF[21]),
        .O(sin_IF0_o[21]));
  OBUF \sin_IF0_o_OBUF[22]_inst 
       (.I(sin_IF0_o_OBUF[22]),
        .O(sin_IF0_o[22]));
  OBUF \sin_IF0_o_OBUF[23]_inst 
       (.I(sin_IF0_o_OBUF[23]),
        .O(sin_IF0_o[23]));
  OBUF \sin_IF0_o_OBUF[24]_inst 
       (.I(sin_IF0_o_OBUF[24]),
        .O(sin_IF0_o[24]));
  OBUF \sin_IF0_o_OBUF[2]_inst 
       (.I(sin_IF0_o_OBUF[2]),
        .O(sin_IF0_o[2]));
  OBUF \sin_IF0_o_OBUF[3]_inst 
       (.I(sin_IF0_o_OBUF[3]),
        .O(sin_IF0_o[3]));
  OBUF \sin_IF0_o_OBUF[4]_inst 
       (.I(sin_IF0_o_OBUF[4]),
        .O(sin_IF0_o[4]));
  OBUF \sin_IF0_o_OBUF[5]_inst 
       (.I(sin_IF0_o_OBUF[5]),
        .O(sin_IF0_o[5]));
  OBUF \sin_IF0_o_OBUF[6]_inst 
       (.I(sin_IF0_o_OBUF[6]),
        .O(sin_IF0_o[6]));
  OBUF \sin_IF0_o_OBUF[7]_inst 
       (.I(sin_IF0_o_OBUF[7]),
        .O(sin_IF0_o[7]));
  OBUF \sin_IF0_o_OBUF[8]_inst 
       (.I(sin_IF0_o_OBUF[8]),
        .O(sin_IF0_o[8]));
  OBUF \sin_IF0_o_OBUF[9]_inst 
       (.I(sin_IF0_o_OBUF[9]),
        .O(sin_IF0_o[9]));
  OBUF \sin_IF1_o_OBUF[0]_inst 
       (.I(sin_IF1_o_OBUF[0]),
        .O(sin_IF1_o[0]));
  OBUF \sin_IF1_o_OBUF[10]_inst 
       (.I(sin_IF1_o_OBUF[10]),
        .O(sin_IF1_o[10]));
  OBUF \sin_IF1_o_OBUF[11]_inst 
       (.I(sin_IF1_o_OBUF[11]),
        .O(sin_IF1_o[11]));
  OBUF \sin_IF1_o_OBUF[12]_inst 
       (.I(sin_IF1_o_OBUF[12]),
        .O(sin_IF1_o[12]));
  OBUF \sin_IF1_o_OBUF[13]_inst 
       (.I(sin_IF1_o_OBUF[13]),
        .O(sin_IF1_o[13]));
  OBUF \sin_IF1_o_OBUF[14]_inst 
       (.I(sin_IF1_o_OBUF[14]),
        .O(sin_IF1_o[14]));
  OBUF \sin_IF1_o_OBUF[15]_inst 
       (.I(sin_IF1_o_OBUF[15]),
        .O(sin_IF1_o[15]));
  OBUF \sin_IF1_o_OBUF[16]_inst 
       (.I(sin_IF1_o_OBUF[16]),
        .O(sin_IF1_o[16]));
  OBUF \sin_IF1_o_OBUF[17]_inst 
       (.I(sin_IF1_o_OBUF[17]),
        .O(sin_IF1_o[17]));
  OBUF \sin_IF1_o_OBUF[18]_inst 
       (.I(sin_IF1_o_OBUF[18]),
        .O(sin_IF1_o[18]));
  OBUF \sin_IF1_o_OBUF[19]_inst 
       (.I(sin_IF1_o_OBUF[19]),
        .O(sin_IF1_o[19]));
  OBUF \sin_IF1_o_OBUF[1]_inst 
       (.I(sin_IF1_o_OBUF[1]),
        .O(sin_IF1_o[1]));
  OBUF \sin_IF1_o_OBUF[20]_inst 
       (.I(sin_IF1_o_OBUF[20]),
        .O(sin_IF1_o[20]));
  OBUF \sin_IF1_o_OBUF[21]_inst 
       (.I(sin_IF1_o_OBUF[21]),
        .O(sin_IF1_o[21]));
  OBUF \sin_IF1_o_OBUF[22]_inst 
       (.I(sin_IF1_o_OBUF[22]),
        .O(sin_IF1_o[22]));
  OBUF \sin_IF1_o_OBUF[23]_inst 
       (.I(sin_IF1_o_OBUF[23]),
        .O(sin_IF1_o[23]));
  OBUF \sin_IF1_o_OBUF[24]_inst 
       (.I(sin_IF1_o_OBUF[24]),
        .O(sin_IF1_o[24]));
  OBUF \sin_IF1_o_OBUF[2]_inst 
       (.I(sin_IF1_o_OBUF[2]),
        .O(sin_IF1_o[2]));
  OBUF \sin_IF1_o_OBUF[3]_inst 
       (.I(sin_IF1_o_OBUF[3]),
        .O(sin_IF1_o[3]));
  OBUF \sin_IF1_o_OBUF[4]_inst 
       (.I(sin_IF1_o_OBUF[4]),
        .O(sin_IF1_o[4]));
  OBUF \sin_IF1_o_OBUF[5]_inst 
       (.I(sin_IF1_o_OBUF[5]),
        .O(sin_IF1_o[5]));
  OBUF \sin_IF1_o_OBUF[6]_inst 
       (.I(sin_IF1_o_OBUF[6]),
        .O(sin_IF1_o[6]));
  OBUF \sin_IF1_o_OBUF[7]_inst 
       (.I(sin_IF1_o_OBUF[7]),
        .O(sin_IF1_o[7]));
  OBUF \sin_IF1_o_OBUF[8]_inst 
       (.I(sin_IF1_o_OBUF[8]),
        .O(sin_IF1_o[8]));
  OBUF \sin_IF1_o_OBUF[9]_inst 
       (.I(sin_IF1_o_OBUF[9]),
        .O(sin_IF1_o[9]));
  OBUF \sincos_vld_o_OBUF[0]_inst 
       (.I(sincos_vld_o_OBUF),
        .O(sincos_vld_o));
  OBUF \tw_H1_o_OBUF[0]_inst 
       (.I(tw_H1_o_OBUF[0]),
        .O(tw_H1_o[0]));
  OBUF \tw_H1_o_OBUF[10]_inst 
       (.I(tw_H1_o_OBUF[10]),
        .O(tw_H1_o[10]));
  OBUF \tw_H1_o_OBUF[11]_inst 
       (.I(tw_H1_o_OBUF[11]),
        .O(tw_H1_o[11]));
  OBUF \tw_H1_o_OBUF[12]_inst 
       (.I(tw_H1_o_OBUF[12]),
        .O(tw_H1_o[12]));
  OBUF \tw_H1_o_OBUF[13]_inst 
       (.I(tw_H1_o_OBUF[13]),
        .O(tw_H1_o[13]));
  OBUF \tw_H1_o_OBUF[14]_inst 
       (.I(tw_H1_o_OBUF[14]),
        .O(tw_H1_o[14]));
  OBUF \tw_H1_o_OBUF[15]_inst 
       (.I(tw_H1_o_OBUF[15]),
        .O(tw_H1_o[15]));
  OBUF \tw_H1_o_OBUF[16]_inst 
       (.I(tw_H1_o_OBUF[16]),
        .O(tw_H1_o[16]));
  OBUF \tw_H1_o_OBUF[17]_inst 
       (.I(tw_H1_o_OBUF[17]),
        .O(tw_H1_o[17]));
  OBUF \tw_H1_o_OBUF[18]_inst 
       (.I(tw_H1_o_OBUF[18]),
        .O(tw_H1_o[18]));
  OBUF \tw_H1_o_OBUF[19]_inst 
       (.I(tw_H1_o_OBUF[19]),
        .O(tw_H1_o[19]));
  OBUF \tw_H1_o_OBUF[1]_inst 
       (.I(tw_H1_o_OBUF[1]),
        .O(tw_H1_o[1]));
  OBUF \tw_H1_o_OBUF[20]_inst 
       (.I(tw_H1_o_OBUF[20]),
        .O(tw_H1_o[20]));
  OBUF \tw_H1_o_OBUF[21]_inst 
       (.I(tw_H1_o_OBUF[21]),
        .O(tw_H1_o[21]));
  OBUF \tw_H1_o_OBUF[22]_inst 
       (.I(tw_H1_o_OBUF[22]),
        .O(tw_H1_o[22]));
  OBUF \tw_H1_o_OBUF[23]_inst 
       (.I(tw_H1_o_OBUF[23]),
        .O(tw_H1_o[23]));
  OBUF \tw_H1_o_OBUF[24]_inst 
       (.I(tw_H1_o_OBUF[24]),
        .O(tw_H1_o[24]));
  OBUF \tw_H1_o_OBUF[25]_inst 
       (.I(tw_H1_o_OBUF[25]),
        .O(tw_H1_o[25]));
  OBUF \tw_H1_o_OBUF[26]_inst 
       (.I(tw_H1_o_OBUF[26]),
        .O(tw_H1_o[26]));
  OBUF \tw_H1_o_OBUF[27]_inst 
       (.I(tw_H1_o_OBUF[27]),
        .O(tw_H1_o[27]));
  OBUF \tw_H1_o_OBUF[28]_inst 
       (.I(tw_H1_o_OBUF[28]),
        .O(tw_H1_o[28]));
  OBUF \tw_H1_o_OBUF[29]_inst 
       (.I(tw_H1_o_OBUF[29]),
        .O(tw_H1_o[29]));
  OBUF \tw_H1_o_OBUF[2]_inst 
       (.I(tw_H1_o_OBUF[2]),
        .O(tw_H1_o[2]));
  OBUF \tw_H1_o_OBUF[30]_inst 
       (.I(tw_H1_o_OBUF[30]),
        .O(tw_H1_o[30]));
  OBUF \tw_H1_o_OBUF[31]_inst 
       (.I(tw_H1_o_OBUF[31]),
        .O(tw_H1_o[31]));
  OBUF \tw_H1_o_OBUF[3]_inst 
       (.I(tw_H1_o_OBUF[3]),
        .O(tw_H1_o[3]));
  OBUF \tw_H1_o_OBUF[4]_inst 
       (.I(tw_H1_o_OBUF[4]),
        .O(tw_H1_o[4]));
  OBUF \tw_H1_o_OBUF[5]_inst 
       (.I(tw_H1_o_OBUF[5]),
        .O(tw_H1_o[5]));
  OBUF \tw_H1_o_OBUF[6]_inst 
       (.I(tw_H1_o_OBUF[6]),
        .O(tw_H1_o[6]));
  OBUF \tw_H1_o_OBUF[7]_inst 
       (.I(tw_H1_o_OBUF[7]),
        .O(tw_H1_o[7]));
  OBUF \tw_H1_o_OBUF[8]_inst 
       (.I(tw_H1_o_OBUF[8]),
        .O(tw_H1_o[8]));
  OBUF \tw_H1_o_OBUF[9]_inst 
       (.I(tw_H1_o_OBUF[9]),
        .O(tw_H1_o[9]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[0]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[0]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[0]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[10]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[10]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[10]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[11]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[11]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[11]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[12]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[12]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[12]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[13]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[13]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[13]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[14]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[14]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[14]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[15]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[15]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[15]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[16]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[16]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[16]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[17]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[17]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[17]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[18]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[18]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[18]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[19]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[19]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[19]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[1]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[1]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[1]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[20]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[20]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[20]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[21]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[21]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[21]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[22]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[22]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[22]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[23]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[23]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[23]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[24]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[24]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[24]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[25]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[25]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[25]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[26]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[26]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[26]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[27]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[27]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[27]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[28]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[28]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[28]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[29]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[29]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[29]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[2]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[2]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[2]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[30]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[30]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[30]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[31]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[31]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[31]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[3]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[3]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[3]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[4]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[4]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[4]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[5]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[5]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[5]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[6]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[6]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[6]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[7]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[7]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[7]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[8]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[8]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[8]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[9]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip0[9]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip0_IBUF[9]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[0]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[0]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[0]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[10]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[10]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[10]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[11]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[11]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[11]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[12]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[12]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[12]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[13]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[13]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[13]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[14]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[14]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[14]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[15]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[15]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[15]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[16]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[16]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[16]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[17]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[17]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[17]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[18]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[18]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[18]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[19]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[19]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[19]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[1]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[1]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[1]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[20]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[20]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[20]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[21]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[21]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[21]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[22]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[22]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[22]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[23]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[23]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[23]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[24]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[24]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[24]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[25]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[25]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[25]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[26]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[26]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[26]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[27]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[27]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[27]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[28]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[28]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[28]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[29]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[29]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[29]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[2]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[2]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[2]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[30]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[30]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[30]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[31]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[31]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[31]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[3]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[3]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[3]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[4]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[4]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[4]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[5]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[5]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[5]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[6]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[6]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[6]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[7]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[7]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[7]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[8]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[8]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[8]));
  IBUF \wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[9]_inst 
       (.I(wr_rf_frame_bus_i_dftw_h1_slip1[9]),
        .O(wr_rf_frame_bus_i_dftw_h1_slip1_IBUF[9]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[0]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[0]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[0]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[10]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[10]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[10]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[11]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[11]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[11]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[12]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[12]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[12]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[13]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[13]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[13]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[14]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[14]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[14]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[15]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[15]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[15]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[16]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[16]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[16]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[17]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[17]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[17]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[18]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[18]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[18]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[19]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[19]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[19]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[1]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[1]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[1]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[20]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[20]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[20]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[21]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[21]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[21]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[22]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[22]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[22]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[23]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[23]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[23]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[24]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[24]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[24]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[25]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[25]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[25]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[26]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[26]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[26]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[27]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[27]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[27]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[28]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[28]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[28]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[29]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[29]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[29]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[2]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[2]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[2]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[30]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[30]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[30]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[31]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[31]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[31]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[32]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[32]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[32]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[33]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[33]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[33]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[34]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[34]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[34]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[35]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[35]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[35]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[36]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[36]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[36]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[37]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[37]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[37]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[38]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[38]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[38]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[39]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[39]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[39]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[3]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[3]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[3]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[40]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[40]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[40]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[41]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[41]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[41]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[42]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[42]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[42]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[43]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[43]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[43]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[44]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[44]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[44]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[45]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[45]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[45]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[46]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[46]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[46]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[47]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[47]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[47]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[4]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[4]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[4]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[5]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[5]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[5]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[6]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[6]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[6]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[7]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[7]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[7]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[8]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[8]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[8]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_main_IBUF[9]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_main[9]),
        .O(wr_rf_frame_bus_i_ftw_h1_main_IBUF[9]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[0]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[0]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[0]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[10]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[10]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[10]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[11]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[11]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[11]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[12]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[12]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[12]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[13]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[13]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[13]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[14]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[14]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[14]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[15]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[15]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[15]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[16]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[16]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[16]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[17]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[17]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[17]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[18]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[18]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[18]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[19]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[19]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[19]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[1]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[1]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[1]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[20]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[20]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[20]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[21]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[21]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[21]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[22]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[22]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[22]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[23]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[23]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[23]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[24]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[24]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[24]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[25]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[25]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[25]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[26]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[26]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[26]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[27]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[27]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[27]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[28]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[28]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[28]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[29]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[29]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[29]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[2]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[2]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[2]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[30]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[30]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[30]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[31]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[31]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[31]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[32]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[32]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[32]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[33]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[33]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[33]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[34]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[34]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[34]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[35]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[35]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[35]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[36]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[36]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[36]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[37]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[37]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[37]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[38]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[38]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[38]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[39]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[39]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[39]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[3]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[3]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[3]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[40]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[40]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[40]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[41]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[41]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[41]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[42]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[42]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[42]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[43]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[43]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[43]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[44]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[44]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[44]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[45]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[45]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[45]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[46]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[46]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[46]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[47]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[47]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[47]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[4]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[4]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[4]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[5]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[5]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[5]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[6]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[6]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[6]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[7]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[7]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[7]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[8]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[8]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[8]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_on_IBUF[9]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_on[9]),
        .O(wr_rf_frame_bus_i_ftw_h1_on_IBUF[9]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[0]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[0]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[0]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[10]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[10]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[10]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[11]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[11]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[11]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[12]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[12]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[12]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[13]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[13]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[13]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[14]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[14]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[14]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[15]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[15]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[15]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[16]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[16]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[16]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[17]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[17]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[17]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[18]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[18]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[18]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[19]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[19]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[19]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[1]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[1]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[1]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[20]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[20]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[20]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[21]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[21]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[21]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[22]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[22]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[22]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[23]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[23]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[23]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[24]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[24]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[24]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[25]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[25]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[25]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[26]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[26]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[26]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[27]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[27]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[27]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[28]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[28]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[28]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[29]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[29]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[29]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[2]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[2]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[2]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[30]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[30]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[30]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[31]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[31]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[31]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[32]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[32]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[32]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[33]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[33]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[33]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[34]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[34]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[34]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[35]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[35]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[35]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[36]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[36]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[36]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[37]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[37]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[37]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[38]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[38]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[38]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[39]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[39]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[39]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[3]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[3]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[3]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[40]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[40]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[40]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[41]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[41]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[41]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[42]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[42]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[42]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[43]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[43]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[43]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[44]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[44]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[44]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[45]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[45]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[45]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[46]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[46]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[46]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[47]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[47]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[47]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[4]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[4]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[4]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[5]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[5]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[5]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[6]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[6]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[6]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[7]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[7]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[7]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[8]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[8]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[8]));
  IBUF \wr_rf_frame_bus_i_ftw_h1_prog_IBUF[9]_inst 
       (.I(wr_rf_frame_bus_i_ftw_h1_prog[9]),
        .O(wr_rf_frame_bus_i_ftw_h1_prog_IBUF[9]));
  IBUF wr_rf_frame_bus_i_inputs_valid_IBUF_inst
       (.I(wr_rf_frame_bus_i_inputs_valid),
        .O(wr_rf_frame_bus_i_inputs_valid_IBUF));
  IBUF \wr_rf_frame_bus_i_rate_IBUF[0]_inst 
       (.I(wr_rf_frame_bus_i_rate[0]),
        .O(wr_rf_frame_bus_i_rate_IBUF[0]));
  IBUF \wr_rf_frame_bus_i_rate_IBUF[1]_inst 
       (.I(wr_rf_frame_bus_i_rate[1]),
        .O(wr_rf_frame_bus_i_rate_IBUF[1]));
  IBUF \wr_rf_frame_bus_i_rate_IBUF[2]_inst 
       (.I(wr_rf_frame_bus_i_rate[2]),
        .O(wr_rf_frame_bus_i_rate_IBUF[2]));
  IBUF wr_rf_frame_bus_i_reset_fsk_IBUF_inst
       (.I(wr_rf_frame_bus_i_reset_fsk),
        .O(wr_rf_frame_bus_i_reset_fsk_IBUF));
  IBUF wr_rf_frame_bus_i_reset_nco_IBUF_inst
       (.I(wr_rf_frame_bus_i_reset_nco),
        .O(wr_rf_frame_bus_i_reset_nco_IBUF));
  IBUF wr_rf_frame_bus_i_reset_slip_IBUF_inst
       (.I(wr_rf_frame_bus_i_reset_slip),
        .O(wr_rf_frame_bus_i_reset_slip_IBUF));
endmodule

module b_NCO_rst_imp_1APBVP
   (NCO_rst_o,
    ext_reset_o,
    master_reset_o,
    ext_reset_enable_o,
    NCO_rst_i,
    valid_i,
    rst_i,
    control_reset);
  output [0:0]NCO_rst_o;
  output [0:0]ext_reset_o;
  output [0:0]master_reset_o;
  input ext_reset_enable_o;
  input [0:0]NCO_rst_i;
  input [0:0]valid_i;
  input rst_i;
  input control_reset;

  wire [0:0]NCO_rst_i;
  wire [0:0]NCO_rst_o;
  wire control_reset;
  wire ext_reset_enable_o;
  wire [0:0]ext_reset_o;
  wire [0:0]master_reset_o;
  wire rst_i;
  wire [0:0]valid_i;

  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
  RFNCO_cmp_and_reset_enable_0 cmp_and_reset_enable
       (.Op1(ext_reset_enable_o),
        .Op2(NCO_rst_i),
        .Res(NCO_rst_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
  RFNCO_cmp_and_rstnco_valid_0 cmp_and_rstnco_valid
       (.Op1(NCO_rst_i),
        .Op2(valid_i),
        .Res(ext_reset_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
  RFNCO_cmp_or_master_reset_0 cmp_or_master_reset
       (.Op1(rst_i),
        .Op2(control_reset),
        .Res(master_reset_o));
endmodule

module b_memory_map_imp_QHGYDM
   (aximm_i_awready,
    aximm_i_wready,
    aximm_i_bvalid,
    aximm_i_bresp,
    aximm_i_arready,
    aximm_i_rvalid,
    aximm_i_rdata,
    aximm_i_rresp,
    control_reset,
    control_softLoad,
    control_selFtwLo0,
    control_selFtwLo1,
    control_selOffsetH1,
    control_selOffsetFskH1,
    control_selRate,
    control_selFtwH1,
    control_selFtwH1On,
    control_selWrFtwH1,
    control_selWrDftwH1slip,
    control_selDftwH1slip,
    control_selFtwH1prog_o,
    control_slipSign,
    control_enableFSK,
    control_resetFSK,
    control_enableSlip,
    control_resetSlip,
    control_signIF0,
    control_signIF1,
    ext_reset_enable_o,
    control_selLoad,
    control_enableFreqDoubling_o,
    control_forceAM_o,
    ftw_h1,
    ftw_h1Prog,
    ftw_on,
    ftw_lo0,
    ftw_lo1,
    ftw_slip,
    inputs_offsetH1,
    inputs_rate,
    inputs_h,
    inputs_offsetFSK,
    inputs_offsetAM_o,
    inputs_pulseLengthAM_o,
    delayComp,
    clk_i,
    phase_IF0_o,
    phase_IF1_o,
    phase_H1_o,
    phase_H1_main_o,
    phase_H1_slip_o,
    rst_i,
    aximm_i_awvalid,
    aximm_i_awaddr,
    aximm_i_awprot,
    aximm_i_wvalid,
    aximm_i_wdata,
    aximm_i_wstrb,
    aximm_i_bready,
    aximm_i_arvalid,
    aximm_i_araddr,
    aximm_i_arprot,
    aximm_i_rready,
    interlock_o,
    status_phaseH1Vld,
    AM_auto_on_o,
    presentLatch_frev,
    presentLatch_am,
    presentLatch_tw,
    status_coefVld,
    presentLatch_load,
    ext_reset_o,
    coef_o,
    tw_H1_o,
    phase_H1_comp_o);
  output aximm_i_awready;
  output aximm_i_wready;
  output aximm_i_bvalid;
  output [1:0]aximm_i_bresp;
  output aximm_i_arready;
  output aximm_i_rvalid;
  output [31:0]aximm_i_rdata;
  output [1:0]aximm_i_rresp;
  output control_reset;
  output control_softLoad;
  output control_selFtwLo0;
  output control_selFtwLo1;
  output control_selOffsetH1;
  output control_selOffsetFskH1;
  output control_selRate;
  output control_selFtwH1;
  output control_selFtwH1On;
  output control_selWrFtwH1;
  output control_selWrDftwH1slip;
  output control_selDftwH1slip;
  output control_selFtwH1prog_o;
  output control_slipSign;
  output control_enableFSK;
  output control_resetFSK;
  output control_enableSlip;
  output control_resetSlip;
  output control_signIF0;
  output control_signIF1;
  output ext_reset_enable_o;
  output control_selLoad;
  output control_enableFreqDoubling_o;
  output control_forceAM_o;
  output [47:0]ftw_h1;
  output [47:0]ftw_h1Prog;
  output [47:0]ftw_on;
  output [47:0]ftw_lo0;
  output [47:0]ftw_lo1;
  output [31:0]ftw_slip;
  output [47:0]inputs_offsetH1;
  output [2:0]inputs_rate;
  output [15:0]inputs_h;
  output [47:0]inputs_offsetFSK;
  output [47:0]inputs_offsetAM_o;
  output [47:0]inputs_pulseLengthAM_o;
  output [31:0]delayComp;
  input clk_i;
  input [47:0]phase_IF0_o;
  input [47:0]phase_IF1_o;
  input [47:0]phase_H1_o;
  input [47:0]phase_H1_main_o;
  input [47:0]phase_H1_slip_o;
  input rst_i;
  input aximm_i_awvalid;
  input [11:0]aximm_i_awaddr;
  input [2:0]aximm_i_awprot;
  input aximm_i_wvalid;
  input [31:0]aximm_i_wdata;
  input [3:0]aximm_i_wstrb;
  input aximm_i_bready;
  input aximm_i_arvalid;
  input [11:0]aximm_i_araddr;
  input [2:0]aximm_i_arprot;
  input aximm_i_rready;
  input interlock_o;
  input status_phaseH1Vld;
  input AM_auto_on_o;
  input presentLatch_frev;
  input presentLatch_am;
  input presentLatch_tw;
  input status_coefVld;
  input presentLatch_load;
  input [0:0]ext_reset_o;
  input [31:0]coef_o;
  input [31:0]tw_H1_o;
  input [47:0]phase_H1_comp_o;

  wire AM_auto_on_o;
  wire [31:3]RegCtrl_rfnco_0_ftw_rate;
  wire [11:0]aximm_i_araddr;
  wire [2:0]aximm_i_arprot;
  wire aximm_i_arready;
  wire aximm_i_arvalid;
  wire [11:0]aximm_i_awaddr;
  wire [2:0]aximm_i_awprot;
  wire aximm_i_awready;
  wire aximm_i_awvalid;
  wire aximm_i_bready;
  wire [1:0]aximm_i_bresp;
  wire aximm_i_bvalid;
  wire [31:0]aximm_i_rdata;
  wire aximm_i_rready;
  wire [1:0]aximm_i_rresp;
  wire aximm_i_rvalid;
  wire [31:0]aximm_i_wdata;
  wire aximm_i_wready;
  wire [3:0]aximm_i_wstrb;
  wire aximm_i_wvalid;
  wire c_zeros_16_dout;
  wire clk_i;
  wire [47:0]cmp_ff_phaseIf0_data_o;
  wire [47:0]cmp_ff_phaseIf1_data_o;
  wire [47:0]cmp_ff_phase_H1_data_o;
  wire [47:0]cmp_ff_phase_H1main_data_o;
  wire [47:0]cmp_ff_phase_H1slip_data_o;
  wire cmp_not_rst_Res;
  wire cmp_rfnco_regs_control_latchPhases_o;
  wire [31:0]coef_o;
  wire control_enableFSK;
  wire control_enableFreqDoubling_o;
  wire control_enableSlip;
  wire control_forceAM_o;
  wire control_reset;
  wire control_resetFSK;
  wire control_resetSlip;
  wire control_selDftwH1slip;
  wire control_selFtwH1;
  wire control_selFtwH1On;
  wire control_selFtwH1prog_o;
  wire control_selFtwLo0;
  wire control_selFtwLo1;
  wire control_selLoad;
  wire control_selOffsetFskH1;
  wire control_selOffsetH1;
  wire control_selRate;
  wire control_selWrDftwH1slip;
  wire control_selWrFtwH1;
  wire control_signIF0;
  wire control_signIF1;
  wire control_slipSign;
  wire control_softLoad;
  wire [31:0]delayComp;
  wire ext_reset_enable_o;
  wire [0:0]ext_reset_o;
  wire [47:0]ftw_h1;
  wire [47:0]ftw_h1Prog;
  wire [47:0]ftw_lo0;
  wire [47:0]ftw_lo1;
  wire [47:0]ftw_on;
  wire [31:0]ftw_slip;
  wire [15:0]inputs_h;
  wire [47:0]inputs_offsetAM_o;
  wire [47:0]inputs_offsetFSK;
  wire [47:0]inputs_offsetH1;
  wire [47:0]inputs_pulseLengthAM_o;
  wire [2:0]inputs_rate;
  wire interlock_o;
  wire [47:0]phase_H1_comp_o;
  wire [47:0]phase_H1_main_o;
  wire [47:0]phase_H1_o;
  wire [47:0]phase_H1_slip_o;
  wire [47:0]phase_IF0_o;
  wire [47:0]phase_IF1_o;
  wire presentLatch_am;
  wire presentLatch_frev;
  wire presentLatch_load;
  wire presentLatch_tw;
  wire [31:0]rfnco_version_firmwareVersion_o;
  wire [31:0]rfnco_version_ident_o;
  wire [31:0]rfnco_version_memMapVersion_o;
  wire rst_i;
  wire status_coefVld;
  wire status_phaseH1Vld;
  wire [31:0]tw_H1_o;

  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlconstant_v1_1_5_xlconstant,Vivado 2018.2" *) 
  RFNCO_c_zeros_1b_0 c_zeros_1b
       (.dout(c_zeros_16_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_phaseIf0_0 cmp_ff_phaseIf0
       (.clk_i(clk_i),
        .data_i(phase_IF0_o),
        .data_o(cmp_ff_phaseIf0_data_o),
        .enable_i(cmp_rfnco_regs_control_latchPhases_o),
        .rst_i(c_zeros_16_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_phaseIf1_0 cmp_ff_phaseIf1
       (.clk_i(clk_i),
        .data_i(phase_IF1_o),
        .data_o(cmp_ff_phaseIf1_data_o),
        .enable_i(cmp_rfnco_regs_control_latchPhases_o),
        .rst_i(c_zeros_16_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_phase_H1_0 cmp_ff_phase_H1
       (.clk_i(clk_i),
        .data_i(phase_H1_o),
        .data_o(cmp_ff_phase_H1_data_o),
        .enable_i(cmp_rfnco_regs_control_latchPhases_o),
        .rst_i(c_zeros_16_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_phase_H1main_0 cmp_ff_phase_H1main
       (.clk_i(clk_i),
        .data_i(phase_H1_main_o),
        .data_o(cmp_ff_phase_H1main_data_o),
        .enable_i(cmp_rfnco_regs_control_latchPhases_o),
        .rst_i(c_zeros_16_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "enable_ff,Vivado 2018.2" *) 
  RFNCO_cmp_ff_phase_H1slip_0 cmp_ff_phase_H1slip
       (.clk_i(clk_i),
        .data_i(phase_H1_slip_o),
        .data_o(cmp_ff_phase_H1slip_data_o),
        .enable_i(cmp_rfnco_regs_control_latchPhases_o),
        .rst_i(c_zeros_16_dout));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "util_vector_logic_v2_0_1_util_vector_logic,Vivado 2018.2" *) 
  RFNCO_cmp_not_rst_0 cmp_not_rst
       (.Op1(rst_i),
        .Res(cmp_not_rst_Res));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "rfnco_regs,Vivado 2018.2" *) 
  RFNCO_cmp_rfnco_regs_0 cmp_rfnco_regs
       (.aclk(clk_i),
        .araddr(aximm_i_araddr),
        .areset_n(cmp_not_rst_Res),
        .arprot(aximm_i_arprot),
        .arready(aximm_i_arready),
        .arvalid(aximm_i_arvalid),
        .awaddr(aximm_i_awaddr),
        .awprot(aximm_i_awprot),
        .awready(aximm_i_awready),
        .awvalid(aximm_i_awvalid),
        .bready(aximm_i_bready),
        .bresp(aximm_i_bresp),
        .bvalid(aximm_i_bvalid),
        .control_enableFSK_o(control_enableFSK),
        .control_enableFreqDoubling_o(control_enableFreqDoubling_o),
        .control_enableSlip_o(control_enableSlip),
        .control_extResetEnable_o(ext_reset_enable_o),
        .control_forceAM_o(control_forceAM_o),
        .control_latchPhases_o(cmp_rfnco_regs_control_latchPhases_o),
        .control_resetFSK_o(control_resetFSK),
        .control_resetSlip_o(control_resetSlip),
        .control_reset_o(control_reset),
        .control_selDftwH1slip_o(control_selDftwH1slip),
        .control_selFtwH1On_o(control_selFtwH1On),
        .control_selFtwH1_o(control_selFtwH1),
        .control_selFtwH1prog_o(control_selFtwH1prog_o),
        .control_selFtwLo0_o(control_selFtwLo0),
        .control_selFtwLo1_o(control_selFtwLo1),
        .control_selLoad_o(control_selLoad),
        .control_selOffsetFskH1_o(control_selOffsetFskH1),
        .control_selOffsetH1_o(control_selOffsetH1),
        .control_selRate_o(control_selRate),
        .control_selWrDftwH1slip_o(control_selWrDftwH1slip),
        .control_selWrFtwH1_o(control_selWrFtwH1),
        .control_signIF0_o(control_signIF0),
        .control_signIF1_o(control_signIF1),
        .control_slipSign_o(control_slipSign),
        .control_softLoad_o(control_softLoad),
        .ftw_h1Prog_reg_o(ftw_h1Prog),
        .ftw_h1_reg_o(ftw_h1),
        .ftw_lo0_reg_o(ftw_lo0),
        .ftw_lo1_reg_o(ftw_lo1),
        .ftw_on_reg_o(ftw_on),
        .ftw_slip_o(ftw_slip),
        .inputs_delayComp_o(delayComp),
        .inputs_h_o(inputs_h),
        .inputs_offsetAM_reg_o(inputs_offsetAM_o),
        .inputs_offsetFSK_reg_o(inputs_offsetFSK),
        .inputs_offsetH1_reg_o(inputs_offsetH1),
        .inputs_pulseLengthAM_reg_o(inputs_pulseLengthAM_o),
        .inputs_rate_o({RegCtrl_rfnco_0_ftw_rate,inputs_rate}),
        .ipInfo_firmwareVersion_i(rfnco_version_firmwareVersion_o),
        .ipInfo_ident_i(rfnco_version_ident_o),
        .ipInfo_memMapVersion_i(rfnco_version_memMapVersion_o),
        .phases_h1Main_reg_i(cmp_ff_phase_H1main_data_o),
        .phases_h1Slip_reg_i(cmp_ff_phase_H1slip_data_o),
        .phases_h1_reg_i(cmp_ff_phase_H1_data_o),
        .phases_if0_reg_i(cmp_ff_phaseIf0_data_o),
        .phases_if1_reg_i(cmp_ff_phaseIf1_data_o),
        .presentLatch_am_i(presentLatch_am),
        .presentLatch_coef_i(status_coefVld),
        .presentLatch_extReset_i(ext_reset_o),
        .presentLatch_frev_i(presentLatch_frev),
        .presentLatch_load_i(presentLatch_load),
        .presentLatch_tw_i(presentLatch_tw),
        .rdata(aximm_i_rdata),
        .readback_coef_i(coef_o),
        .readback_phaseH1Comp_reg_i(phase_H1_comp_o),
        .readback_tw_i(tw_H1_o),
        .rready(aximm_i_rready),
        .rresp(aximm_i_rresp),
        .rvalid(aximm_i_rvalid),
        .status_amAutoOn_i(AM_auto_on_o),
        .status_interlock_i(interlock_o),
        .status_phaseH1Vld_i(status_phaseH1Vld),
        .wdata(aximm_i_wdata),
        .wready(aximm_i_wready),
        .wstrb(aximm_i_wstrb),
        .wvalid(aximm_i_wvalid));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "rfnco_version,Vivado 2018.2" *) 
  RFNCO_rfnco_version_0 rfnco_version
       (.firmwareVersion_o(rfnco_version_firmwareVersion_o),
        .ident_o(rfnco_version_ident_o),
        .memMapVersion_o(rfnco_version_memMapVersion_o));
endmodule

module b_mux_imp_1CMX53U
   (H1_mux_o,
    H1_on_mux_o,
    H1_prog_mux_o,
    LO0_mux_o,
    LO1_mux_o,
    dftw_slip_mux_o,
    offset_FSK_mux_o,
    offset_mux_o,
    rate_mux_o,
    ftw_H1_mm_i,
    sel_H1_mux,
    ftw_H1_on_i,
    ftw_H1_on_mm_i,
    sel_H1_on_mux,
    ftw_H1_prog_i,
    ftw_H1_prog_mm_i,
    sel_H1_prog_mux,
    ftw_LO_0_i,
    ftw_LO_0_mm_i,
    sel_LO0_mux,
    ftw_LO_1_i,
    ftw_LO_1_mm_i,
    sel_LO1_mux,
    dftw_slip_mm,
    sel_dftw_slip_mux,
    offset_FSK_i_0,
    offset_FSK_mm_i,
    sel_offset_FSK_mux,
    offset_i_0,
    offset_mm_i,
    sel_offset_mux,
    rate_i,
    rate_mm_i,
    sel_rate_mux,
    dftw_H1_slip0_i,
    dftw_H1_slip1_i,
    sel_wr_dftw_slip_mux,
    ftw_H1_main_i,
    sel_wr_ftw_H1_mux);
  output [47:0]H1_mux_o;
  output [47:0]H1_on_mux_o;
  output [47:0]H1_prog_mux_o;
  output [47:0]LO0_mux_o;
  output [47:0]LO1_mux_o;
  output [31:0]dftw_slip_mux_o;
  output [47:0]offset_FSK_mux_o;
  output [47:0]offset_mux_o;
  output [2:0]rate_mux_o;
  input [47:0]ftw_H1_mm_i;
  input sel_H1_mux;
  input [47:0]ftw_H1_on_i;
  input [47:0]ftw_H1_on_mm_i;
  input sel_H1_on_mux;
  input [47:0]ftw_H1_prog_i;
  input [47:0]ftw_H1_prog_mm_i;
  input sel_H1_prog_mux;
  input [47:0]ftw_LO_0_i;
  input [47:0]ftw_LO_0_mm_i;
  input sel_LO0_mux;
  input [47:0]ftw_LO_1_i;
  input [47:0]ftw_LO_1_mm_i;
  input sel_LO1_mux;
  input [31:0]dftw_slip_mm;
  input sel_dftw_slip_mux;
  input [47:0]offset_FSK_i_0;
  input [47:0]offset_FSK_mm_i;
  input sel_offset_FSK_mux;
  input [47:0]offset_i_0;
  input [47:0]offset_mm_i;
  input sel_offset_mux;
  input [2:0]rate_i;
  input [2:0]rate_mm_i;
  input sel_rate_mux;
  input [31:0]dftw_H1_slip0_i;
  input [31:0]dftw_H1_slip1_i;
  input sel_wr_dftw_slip_mux;
  input [47:0]ftw_H1_main_i;
  input sel_wr_ftw_H1_mux;

  wire [47:0]H1_mux_o;
  wire [47:0]H1_on_mux_o;
  wire [47:0]H1_prog_mux_o;
  wire [47:0]LO0_mux_o;
  wire [47:0]LO1_mux_o;
  wire [31:0]cmp_wr_dftw_slip_mux_C;
  wire [47:0]cmp_wr_ftw_H1_mux_C;
  wire [31:0]dftw_H1_slip0_i;
  wire [31:0]dftw_H1_slip1_i;
  wire [31:0]dftw_slip_mm;
  wire [31:0]dftw_slip_mux_o;
  wire [47:0]ftw_H1_main_i;
  wire [47:0]ftw_H1_mm_i;
  wire [47:0]ftw_H1_on_i;
  wire [47:0]ftw_H1_on_mm_i;
  wire [47:0]ftw_H1_prog_i;
  wire [47:0]ftw_H1_prog_mm_i;
  wire [47:0]ftw_LO_0_i;
  wire [47:0]ftw_LO_0_mm_i;
  wire [47:0]ftw_LO_1_i;
  wire [47:0]ftw_LO_1_mm_i;
  wire [47:0]offset_FSK_i_0;
  wire [47:0]offset_FSK_mm_i;
  wire [47:0]offset_FSK_mux_o;
  wire [47:0]offset_i_0;
  wire [47:0]offset_mm_i;
  wire [47:0]offset_mux_o;
  wire [2:0]rate_i;
  wire [2:0]rate_mm_i;
  wire [2:0]rate_mux_o;
  wire sel_H1_mux;
  wire sel_H1_on_mux;
  wire sel_H1_prog_mux;
  wire sel_LO0_mux;
  wire sel_LO1_mux;
  wire sel_dftw_slip_mux;
  wire sel_offset_FSK_mux;
  wire sel_offset_mux;
  wire sel_rate_mux;
  wire sel_wr_dftw_slip_mux;
  wire sel_wr_ftw_H1_mux;

  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_H1_mux_0 cmp_H1_mux
       (.A(cmp_wr_ftw_H1_mux_C),
        .B(ftw_H1_mm_i),
        .C(H1_mux_o),
        .sel(sel_H1_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_H1_on_mux_0 cmp_H1_on_mux
       (.A(ftw_H1_on_i),
        .B(ftw_H1_on_mm_i),
        .C(H1_on_mux_o),
        .sel(sel_H1_on_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_H1_prog_mux_0 cmp_H1_prog_mux
       (.A(ftw_H1_prog_i),
        .B(ftw_H1_prog_mm_i),
        .C(H1_prog_mux_o),
        .sel(sel_H1_prog_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_LO0_mux_0 cmp_LO0_mux
       (.A(ftw_LO_0_i),
        .B(ftw_LO_0_mm_i),
        .C(LO0_mux_o),
        .sel(sel_LO0_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_LO1_mux_0 cmp_LO1_mux
       (.A(ftw_LO_1_i),
        .B(ftw_LO_1_mm_i),
        .C(LO1_mux_o),
        .sel(sel_LO1_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_dftw_slip_mux_0 cmp_dftw_slip_mux
       (.A(cmp_wr_dftw_slip_mux_C),
        .B(dftw_slip_mm),
        .C(dftw_slip_mux_o),
        .sel(sel_dftw_slip_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_offset_FSK_mux_0 cmp_offset_FSK_mux
       (.A(offset_FSK_i_0),
        .B(offset_FSK_mm_i),
        .C(offset_FSK_mux_o),
        .sel(sel_offset_FSK_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_offset_mux_0 cmp_offset_mux
       (.A(offset_i_0),
        .B(offset_mm_i),
        .C(offset_mux_o),
        .sel(sel_offset_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_rate_mux_0 cmp_rate_mux
       (.A(rate_i),
        .B(rate_mm_i),
        .C(rate_mux_o),
        .sel(sel_rate_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_wr_dftw_slip_mux_0 cmp_wr_dftw_slip_mux
       (.A(dftw_H1_slip0_i),
        .B(dftw_H1_slip1_i),
        .C(cmp_wr_dftw_slip_mux_C),
        .sel(sel_wr_dftw_slip_mux));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "generic_mux,Vivado 2018.2" *) 
  RFNCO_cmp_wr_ftw_H1_mux_0 cmp_wr_ftw_H1_mux
       (.A(ftw_H1_main_i),
        .B(ftw_H1_prog_i),
        .C(cmp_wr_ftw_H1_mux_C),
        .sel(sel_wr_ftw_H1_mux));
endmodule

module b_slices_imp_11H86KG
   (cos_IF0_o,
    cos_IF1_o,
    phase_IF0_o,
    phase_IF1_o,
    sin_IF0_o,
    sin_IF1_o,
    sincos_IF0_i,
    sincos_IF1_i,
    \bbstub_outputs_phase_IF_0_V[47] ,
    phase_IF1_i);
  output [24:0]cos_IF0_o;
  output [24:0]cos_IF1_o;
  output [24:0]phase_IF0_o;
  output [24:0]phase_IF1_o;
  output [24:0]sin_IF0_o;
  output [24:0]sin_IF1_o;
  input [63:0]sincos_IF0_i;
  input [63:0]sincos_IF1_i;
  input [47:0]\bbstub_outputs_phase_IF_0_V[47] ;
  input [47:0]phase_IF1_i;

  wire [47:0]\bbstub_outputs_phase_IF_0_V[47] ;
  wire [24:0]cos_IF0_o;
  wire [24:0]cos_IF1_o;
  wire [24:0]phase_IF0_o;
  wire [47:0]phase_IF1_i;
  wire [24:0]phase_IF1_o;
  wire [24:0]sin_IF0_o;
  wire [24:0]sin_IF1_o;
  wire [63:0]sincos_IF0_i;
  wire [63:0]sincos_IF1_i;

  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
  RFNCO_cmp_slice_cos_IF0_0 cmp_slice_cos_IF0
       (.Din(sincos_IF0_i),
        .Dout(cos_IF0_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
  RFNCO_cmp_slice_cos_IF1_0 cmp_slice_cos_IF1
       (.Din(sincos_IF1_i),
        .Dout(cos_IF1_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
  RFNCO_cmp_slice_phase_IF0_0 cmp_slice_phase_IF0
       (.Din(\bbstub_outputs_phase_IF_0_V[47] ),
        .Dout(phase_IF0_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
  RFNCO_cmp_slice_phase_IF1_0 cmp_slice_phase_IF1
       (.Din(phase_IF1_i),
        .Dout(phase_IF1_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
  RFNCO_cmp_slice_sin_IF0_0 cmp_slice_sin_IF0
       (.Din(sincos_IF0_i),
        .Dout(sin_IF0_o));
  (* syn_black_box = "TRUE" *) 
  (* x_core_info = "xlslice_v1_0_1_xlslice,Vivado 2018.2" *) 
  RFNCO_cmp_slice_sin_IF1_0 cmp_slice_sin_IF1
       (.Din(sincos_IF1_i),
        .Dout(sin_IF1_o));
endmodule

(* C_ACCUMULATOR_WIDTH = "25" *) (* C_AMPLITUDE = "0" *) (* C_CHANNELS = "1" *) 
(* C_CHAN_WIDTH = "1" *) (* C_DEBUG_INTERFACE = "0" *) (* C_HAS_ACLKEN = "0" *) 
(* C_HAS_ARESETN = "0" *) (* C_HAS_M_DATA = "1" *) (* C_HAS_M_PHASE = "0" *) 
(* C_HAS_PHASEGEN = "0" *) (* C_HAS_PHASE_OUT = "0" *) (* C_HAS_SINCOS = "1" *) 
(* C_HAS_S_CONFIG = "0" *) (* C_HAS_S_PHASE = "1" *) (* C_HAS_TLAST = "2" *) 
(* C_HAS_TREADY = "0" *) (* C_LATENCY = "9" *) (* C_MEM_TYPE = "1" *) 
(* C_MODE_OF_OPERATION = "0" *) (* C_MODULUS = "9" *) (* C_M_DATA_HAS_TUSER = "0" *) 
(* C_M_DATA_TDATA_WIDTH = "64" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_M_PHASE_HAS_TUSER = "0" *) 
(* C_M_PHASE_TDATA_WIDTH = "1" *) (* C_M_PHASE_TUSER_WIDTH = "1" *) (* C_NEGATIVE_COSINE = "0" *) 
(* C_NEGATIVE_SINE = "0" *) (* C_NOISE_SHAPING = "2" *) (* C_OPTIMISE_GOAL = "0" *) 
(* C_OUTPUTS_REQUIRED = "2" *) (* C_OUTPUT_FORM = "0" *) (* C_OUTPUT_WIDTH = "25" *) 
(* C_PHASE_ANGLE_WIDTH = "11" *) (* C_PHASE_INCREMENT = "2" *) (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
(* C_PHASE_OFFSET = "0" *) (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_POR_MODE = "0" *) 
(* C_RESYNC = "0" *) (* C_S_CONFIG_SYNC_MODE = "0" *) (* C_S_CONFIG_TDATA_WIDTH = "1" *) 
(* C_S_PHASE_HAS_TUSER = "0" *) (* C_S_PHASE_TDATA_WIDTH = "32" *) (* C_S_PHASE_TUSER_WIDTH = "1" *) 
(* C_USE_DSP48 = "0" *) (* C_XDEVICEFAMILY = "kintex7" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* ORIG_REF_NAME = "dds_compiler_v6_0_16" *) 
module RFNCO_cmp_dds_IF0_0_dds_compiler_v6_0_16
   (aclk,
    aclken,
    aresetn,
    s_axis_phase_tvalid,
    s_axis_phase_tready,
    s_axis_phase_tdata,
    s_axis_phase_tlast,
    s_axis_phase_tuser,
    s_axis_config_tvalid,
    s_axis_config_tready,
    s_axis_config_tdata,
    s_axis_config_tlast,
    m_axis_data_tvalid,
    m_axis_data_tready,
    m_axis_data_tdata,
    m_axis_data_tlast,
    m_axis_data_tuser,
    m_axis_phase_tvalid,
    m_axis_phase_tready,
    m_axis_phase_tdata,
    m_axis_phase_tlast,
    m_axis_phase_tuser,
    event_pinc_invalid,
    event_poff_invalid,
    event_phase_in_invalid,
    event_s_phase_tlast_missing,
    event_s_phase_tlast_unexpected,
    event_s_phase_chanid_incorrect,
    event_s_config_tlast_missing,
    event_s_config_tlast_unexpected,
    debug_axi_pinc_in,
    debug_axi_poff_in,
    debug_axi_resync_in,
    debug_axi_chan_in,
    debug_core_nd,
    debug_phase,
    debug_phase_nd);
  input aclk;
  input aclken;
  input aresetn;
  input s_axis_phase_tvalid;
  output s_axis_phase_tready;
  input [31:0]s_axis_phase_tdata;
  input s_axis_phase_tlast;
  input [0:0]s_axis_phase_tuser;
  input s_axis_config_tvalid;
  output s_axis_config_tready;
  input [0:0]s_axis_config_tdata;
  input s_axis_config_tlast;
  output m_axis_data_tvalid;
  input m_axis_data_tready;
  output [63:0]m_axis_data_tdata;
  output m_axis_data_tlast;
  output [0:0]m_axis_data_tuser;
  output m_axis_phase_tvalid;
  input m_axis_phase_tready;
  output [0:0]m_axis_phase_tdata;
  output m_axis_phase_tlast;
  output [0:0]m_axis_phase_tuser;
  output event_pinc_invalid;
  output event_poff_invalid;
  output event_phase_in_invalid;
  output event_s_phase_tlast_missing;
  output event_s_phase_tlast_unexpected;
  output event_s_phase_chanid_incorrect;
  output event_s_config_tlast_missing;
  output event_s_config_tlast_unexpected;
  output [24:0]debug_axi_pinc_in;
  output [24:0]debug_axi_poff_in;
  output debug_axi_resync_in;
  output [0:0]debug_axi_chan_in;
  output debug_core_nd;
  output [24:0]debug_phase;
  output debug_phase_nd;

  wire \<const0> ;
  wire aclk;
  wire event_s_phase_tlast_missing;
  wire [56:0]\^m_axis_data_tdata ;
  wire m_axis_data_tlast;
  wire m_axis_data_tvalid;
  wire [31:0]s_axis_phase_tdata;
  wire s_axis_phase_tlast;
  wire s_axis_phase_tvalid;
  wire [63:0]NLW_i_synth_m_axis_data_tdata_UNCONNECTED;

  assign debug_axi_chan_in[0] = \<const0> ;
  assign debug_axi_pinc_in[24] = \<const0> ;
  assign debug_axi_pinc_in[23] = \<const0> ;
  assign debug_axi_pinc_in[22] = \<const0> ;
  assign debug_axi_pinc_in[21] = \<const0> ;
  assign debug_axi_pinc_in[20] = \<const0> ;
  assign debug_axi_pinc_in[19] = \<const0> ;
  assign debug_axi_pinc_in[18] = \<const0> ;
  assign debug_axi_pinc_in[17] = \<const0> ;
  assign debug_axi_pinc_in[16] = \<const0> ;
  assign debug_axi_pinc_in[15] = \<const0> ;
  assign debug_axi_pinc_in[14] = \<const0> ;
  assign debug_axi_pinc_in[13] = \<const0> ;
  assign debug_axi_pinc_in[12] = \<const0> ;
  assign debug_axi_pinc_in[11] = \<const0> ;
  assign debug_axi_pinc_in[10] = \<const0> ;
  assign debug_axi_pinc_in[9] = \<const0> ;
  assign debug_axi_pinc_in[8] = \<const0> ;
  assign debug_axi_pinc_in[7] = \<const0> ;
  assign debug_axi_pinc_in[6] = \<const0> ;
  assign debug_axi_pinc_in[5] = \<const0> ;
  assign debug_axi_pinc_in[4] = \<const0> ;
  assign debug_axi_pinc_in[3] = \<const0> ;
  assign debug_axi_pinc_in[2] = \<const0> ;
  assign debug_axi_pinc_in[1] = \<const0> ;
  assign debug_axi_pinc_in[0] = \<const0> ;
  assign debug_axi_poff_in[24] = \<const0> ;
  assign debug_axi_poff_in[23] = \<const0> ;
  assign debug_axi_poff_in[22] = \<const0> ;
  assign debug_axi_poff_in[21] = \<const0> ;
  assign debug_axi_poff_in[20] = \<const0> ;
  assign debug_axi_poff_in[19] = \<const0> ;
  assign debug_axi_poff_in[18] = \<const0> ;
  assign debug_axi_poff_in[17] = \<const0> ;
  assign debug_axi_poff_in[16] = \<const0> ;
  assign debug_axi_poff_in[15] = \<const0> ;
  assign debug_axi_poff_in[14] = \<const0> ;
  assign debug_axi_poff_in[13] = \<const0> ;
  assign debug_axi_poff_in[12] = \<const0> ;
  assign debug_axi_poff_in[11] = \<const0> ;
  assign debug_axi_poff_in[10] = \<const0> ;
  assign debug_axi_poff_in[9] = \<const0> ;
  assign debug_axi_poff_in[8] = \<const0> ;
  assign debug_axi_poff_in[7] = \<const0> ;
  assign debug_axi_poff_in[6] = \<const0> ;
  assign debug_axi_poff_in[5] = \<const0> ;
  assign debug_axi_poff_in[4] = \<const0> ;
  assign debug_axi_poff_in[3] = \<const0> ;
  assign debug_axi_poff_in[2] = \<const0> ;
  assign debug_axi_poff_in[1] = \<const0> ;
  assign debug_axi_poff_in[0] = \<const0> ;
  assign debug_axi_resync_in = \<const0> ;
  assign debug_core_nd = \<const0> ;
  assign debug_phase[24] = \<const0> ;
  assign debug_phase[23] = \<const0> ;
  assign debug_phase[22] = \<const0> ;
  assign debug_phase[21] = \<const0> ;
  assign debug_phase[20] = \<const0> ;
  assign debug_phase[19] = \<const0> ;
  assign debug_phase[18] = \<const0> ;
  assign debug_phase[17] = \<const0> ;
  assign debug_phase[16] = \<const0> ;
  assign debug_phase[15] = \<const0> ;
  assign debug_phase[14] = \<const0> ;
  assign debug_phase[13] = \<const0> ;
  assign debug_phase[12] = \<const0> ;
  assign debug_phase[11] = \<const0> ;
  assign debug_phase[10] = \<const0> ;
  assign debug_phase[9] = \<const0> ;
  assign debug_phase[8] = \<const0> ;
  assign debug_phase[7] = \<const0> ;
  assign debug_phase[6] = \<const0> ;
  assign debug_phase[5] = \<const0> ;
  assign debug_phase[4] = \<const0> ;
  assign debug_phase[3] = \<const0> ;
  assign debug_phase[2] = \<const0> ;
  assign debug_phase[1] = \<const0> ;
  assign debug_phase[0] = \<const0> ;
  assign debug_phase_nd = \<const0> ;
  assign event_phase_in_invalid = \<const0> ;
  assign event_pinc_invalid = \<const0> ;
  assign event_poff_invalid = \<const0> ;
  assign event_s_config_tlast_missing = \<const0> ;
  assign event_s_config_tlast_unexpected = \<const0> ;
  assign event_s_phase_chanid_incorrect = \<const0> ;
  assign event_s_phase_tlast_unexpected = \<const0> ;
  assign m_axis_data_tdata[63] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[62] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[61] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[60] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[59] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[58] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[57] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[56:32] = \^m_axis_data_tdata [56:32];
  assign m_axis_data_tdata[31] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[30] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[29] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[28] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[27] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[26] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[25] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[24:0] = \^m_axis_data_tdata [24:0];
  assign m_axis_data_tuser[0] = \<const0> ;
  assign m_axis_phase_tdata[0] = \<const0> ;
  assign m_axis_phase_tlast = \<const0> ;
  assign m_axis_phase_tuser[0] = \<const0> ;
  assign m_axis_phase_tvalid = \<const0> ;
  assign s_axis_config_tready = \<const0> ;
  assign s_axis_phase_tready = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ACCUMULATOR_WIDTH = "25" *) 
  (* C_AMPLITUDE = "0" *) 
  (* C_CHANNELS = "1" *) 
  (* C_CHAN_WIDTH = "1" *) 
  (* C_DEBUG_INTERFACE = "0" *) 
  (* C_HAS_ACLKEN = "0" *) 
  (* C_HAS_ARESETN = "0" *) 
  (* C_HAS_M_DATA = "1" *) 
  (* C_HAS_M_PHASE = "0" *) 
  (* C_HAS_PHASEGEN = "0" *) 
  (* C_HAS_PHASE_OUT = "0" *) 
  (* C_HAS_SINCOS = "1" *) 
  (* C_HAS_S_CONFIG = "0" *) 
  (* C_HAS_S_PHASE = "1" *) 
  (* C_HAS_TLAST = "2" *) 
  (* C_HAS_TREADY = "0" *) 
  (* C_LATENCY = "9" *) 
  (* C_MEM_TYPE = "1" *) 
  (* C_MODE_OF_OPERATION = "0" *) 
  (* C_MODULUS = "9" *) 
  (* C_M_DATA_HAS_TUSER = "0" *) 
  (* C_M_DATA_TDATA_WIDTH = "64" *) 
  (* C_M_DATA_TUSER_WIDTH = "1" *) 
  (* C_M_PHASE_HAS_TUSER = "0" *) 
  (* C_M_PHASE_TDATA_WIDTH = "1" *) 
  (* C_M_PHASE_TUSER_WIDTH = "1" *) 
  (* C_NEGATIVE_COSINE = "0" *) 
  (* C_NEGATIVE_SINE = "0" *) 
  (* C_NOISE_SHAPING = "2" *) 
  (* C_OPTIMISE_GOAL = "0" *) 
  (* C_OUTPUTS_REQUIRED = "2" *) 
  (* C_OUTPUT_FORM = "0" *) 
  (* C_OUTPUT_WIDTH = "25" *) 
  (* C_PHASE_ANGLE_WIDTH = "11" *) 
  (* C_PHASE_INCREMENT = "2" *) 
  (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_PHASE_OFFSET = "0" *) 
  (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_POR_MODE = "0" *) 
  (* C_RESYNC = "0" *) 
  (* C_S_CONFIG_SYNC_MODE = "0" *) 
  (* C_S_CONFIG_TDATA_WIDTH = "1" *) 
  (* C_S_PHASE_HAS_TUSER = "0" *) 
  (* C_S_PHASE_TDATA_WIDTH = "32" *) 
  (* C_S_PHASE_TUSER_WIDTH = "1" *) 
  (* C_USE_DSP48 = "0" *) 
  (* C_XDEVICEFAMILY = "kintex7" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  RFNCO_cmp_dds_IF0_0_dds_compiler_v6_0_16_viv i_synth
       (.aclk(aclk),
        .aclken(\<const0> ),
        .aresetn(\<const0> ),
        .event_s_phase_tlast_missing(event_s_phase_tlast_missing),
        .m_axis_data_tdata({\^m_axis_data_tdata [56],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[62:56],\^m_axis_data_tdata [55:32],\^m_axis_data_tdata [24],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[30:24],\^m_axis_data_tdata [23:0]}),
        .m_axis_data_tlast(m_axis_data_tlast),
        .m_axis_data_tready(\<const0> ),
        .m_axis_data_tvalid(m_axis_data_tvalid),
        .m_axis_phase_tready(\<const0> ),
        .s_axis_config_tdata(\<const0> ),
        .s_axis_config_tlast(\<const0> ),
        .s_axis_config_tvalid(\<const0> ),
        .s_axis_phase_tdata({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,s_axis_phase_tdata[24:0]}),
        .s_axis_phase_tlast(s_axis_phase_tlast),
        .s_axis_phase_tuser(\<const0> ),
        .s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule

(* C_ACCUMULATOR_WIDTH = "25" *) (* C_AMPLITUDE = "0" *) (* C_CHANNELS = "1" *) 
(* C_CHAN_WIDTH = "1" *) (* C_DEBUG_INTERFACE = "0" *) (* C_HAS_ACLKEN = "0" *) 
(* C_HAS_ARESETN = "0" *) (* C_HAS_M_DATA = "1" *) (* C_HAS_M_PHASE = "0" *) 
(* C_HAS_PHASEGEN = "0" *) (* C_HAS_PHASE_OUT = "0" *) (* C_HAS_SINCOS = "1" *) 
(* C_HAS_S_CONFIG = "0" *) (* C_HAS_S_PHASE = "1" *) (* C_HAS_TLAST = "0" *) 
(* C_HAS_TREADY = "0" *) (* C_LATENCY = "9" *) (* C_MEM_TYPE = "1" *) 
(* C_MODE_OF_OPERATION = "0" *) (* C_MODULUS = "9" *) (* C_M_DATA_HAS_TUSER = "0" *) 
(* C_M_DATA_TDATA_WIDTH = "64" *) (* C_M_DATA_TUSER_WIDTH = "1" *) (* C_M_PHASE_HAS_TUSER = "0" *) 
(* C_M_PHASE_TDATA_WIDTH = "1" *) (* C_M_PHASE_TUSER_WIDTH = "1" *) (* C_NEGATIVE_COSINE = "0" *) 
(* C_NEGATIVE_SINE = "0" *) (* C_NOISE_SHAPING = "2" *) (* C_OPTIMISE_GOAL = "0" *) 
(* C_OUTPUTS_REQUIRED = "2" *) (* C_OUTPUT_FORM = "0" *) (* C_OUTPUT_WIDTH = "25" *) 
(* C_PHASE_ANGLE_WIDTH = "11" *) (* C_PHASE_INCREMENT = "2" *) (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
(* C_PHASE_OFFSET = "0" *) (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_POR_MODE = "0" *) 
(* C_RESYNC = "0" *) (* C_S_CONFIG_SYNC_MODE = "0" *) (* C_S_CONFIG_TDATA_WIDTH = "1" *) 
(* C_S_PHASE_HAS_TUSER = "0" *) (* C_S_PHASE_TDATA_WIDTH = "32" *) (* C_S_PHASE_TUSER_WIDTH = "1" *) 
(* C_USE_DSP48 = "0" *) (* C_XDEVICEFAMILY = "kintex7" *) (* DowngradeIPIdentifiedWarnings = "yes" *) 
(* ORIG_REF_NAME = "dds_compiler_v6_0_16" *) 
module RFNCO_cmp_dds_IF1_0_dds_compiler_v6_0_16
   (aclk,
    aclken,
    aresetn,
    s_axis_phase_tvalid,
    s_axis_phase_tready,
    s_axis_phase_tdata,
    s_axis_phase_tlast,
    s_axis_phase_tuser,
    s_axis_config_tvalid,
    s_axis_config_tready,
    s_axis_config_tdata,
    s_axis_config_tlast,
    m_axis_data_tvalid,
    m_axis_data_tready,
    m_axis_data_tdata,
    m_axis_data_tlast,
    m_axis_data_tuser,
    m_axis_phase_tvalid,
    m_axis_phase_tready,
    m_axis_phase_tdata,
    m_axis_phase_tlast,
    m_axis_phase_tuser,
    event_pinc_invalid,
    event_poff_invalid,
    event_phase_in_invalid,
    event_s_phase_tlast_missing,
    event_s_phase_tlast_unexpected,
    event_s_phase_chanid_incorrect,
    event_s_config_tlast_missing,
    event_s_config_tlast_unexpected,
    debug_axi_pinc_in,
    debug_axi_poff_in,
    debug_axi_resync_in,
    debug_axi_chan_in,
    debug_core_nd,
    debug_phase,
    debug_phase_nd);
  input aclk;
  input aclken;
  input aresetn;
  input s_axis_phase_tvalid;
  output s_axis_phase_tready;
  input [31:0]s_axis_phase_tdata;
  input s_axis_phase_tlast;
  input [0:0]s_axis_phase_tuser;
  input s_axis_config_tvalid;
  output s_axis_config_tready;
  input [0:0]s_axis_config_tdata;
  input s_axis_config_tlast;
  output m_axis_data_tvalid;
  input m_axis_data_tready;
  output [63:0]m_axis_data_tdata;
  output m_axis_data_tlast;
  output [0:0]m_axis_data_tuser;
  output m_axis_phase_tvalid;
  input m_axis_phase_tready;
  output [0:0]m_axis_phase_tdata;
  output m_axis_phase_tlast;
  output [0:0]m_axis_phase_tuser;
  output event_pinc_invalid;
  output event_poff_invalid;
  output event_phase_in_invalid;
  output event_s_phase_tlast_missing;
  output event_s_phase_tlast_unexpected;
  output event_s_phase_chanid_incorrect;
  output event_s_config_tlast_missing;
  output event_s_config_tlast_unexpected;
  output [24:0]debug_axi_pinc_in;
  output [24:0]debug_axi_poff_in;
  output debug_axi_resync_in;
  output [0:0]debug_axi_chan_in;
  output debug_core_nd;
  output [24:0]debug_phase;
  output debug_phase_nd;

  wire \<const0> ;
  wire aclk;
  wire event_s_phase_tlast_missing;
  wire [56:0]\^m_axis_data_tdata ;
  wire m_axis_data_tvalid;
  wire [31:0]s_axis_phase_tdata;
  wire s_axis_phase_tvalid;
  wire [63:0]NLW_i_synth_m_axis_data_tdata_UNCONNECTED;

  assign debug_axi_chan_in[0] = \<const0> ;
  assign debug_axi_pinc_in[24] = \<const0> ;
  assign debug_axi_pinc_in[23] = \<const0> ;
  assign debug_axi_pinc_in[22] = \<const0> ;
  assign debug_axi_pinc_in[21] = \<const0> ;
  assign debug_axi_pinc_in[20] = \<const0> ;
  assign debug_axi_pinc_in[19] = \<const0> ;
  assign debug_axi_pinc_in[18] = \<const0> ;
  assign debug_axi_pinc_in[17] = \<const0> ;
  assign debug_axi_pinc_in[16] = \<const0> ;
  assign debug_axi_pinc_in[15] = \<const0> ;
  assign debug_axi_pinc_in[14] = \<const0> ;
  assign debug_axi_pinc_in[13] = \<const0> ;
  assign debug_axi_pinc_in[12] = \<const0> ;
  assign debug_axi_pinc_in[11] = \<const0> ;
  assign debug_axi_pinc_in[10] = \<const0> ;
  assign debug_axi_pinc_in[9] = \<const0> ;
  assign debug_axi_pinc_in[8] = \<const0> ;
  assign debug_axi_pinc_in[7] = \<const0> ;
  assign debug_axi_pinc_in[6] = \<const0> ;
  assign debug_axi_pinc_in[5] = \<const0> ;
  assign debug_axi_pinc_in[4] = \<const0> ;
  assign debug_axi_pinc_in[3] = \<const0> ;
  assign debug_axi_pinc_in[2] = \<const0> ;
  assign debug_axi_pinc_in[1] = \<const0> ;
  assign debug_axi_pinc_in[0] = \<const0> ;
  assign debug_axi_poff_in[24] = \<const0> ;
  assign debug_axi_poff_in[23] = \<const0> ;
  assign debug_axi_poff_in[22] = \<const0> ;
  assign debug_axi_poff_in[21] = \<const0> ;
  assign debug_axi_poff_in[20] = \<const0> ;
  assign debug_axi_poff_in[19] = \<const0> ;
  assign debug_axi_poff_in[18] = \<const0> ;
  assign debug_axi_poff_in[17] = \<const0> ;
  assign debug_axi_poff_in[16] = \<const0> ;
  assign debug_axi_poff_in[15] = \<const0> ;
  assign debug_axi_poff_in[14] = \<const0> ;
  assign debug_axi_poff_in[13] = \<const0> ;
  assign debug_axi_poff_in[12] = \<const0> ;
  assign debug_axi_poff_in[11] = \<const0> ;
  assign debug_axi_poff_in[10] = \<const0> ;
  assign debug_axi_poff_in[9] = \<const0> ;
  assign debug_axi_poff_in[8] = \<const0> ;
  assign debug_axi_poff_in[7] = \<const0> ;
  assign debug_axi_poff_in[6] = \<const0> ;
  assign debug_axi_poff_in[5] = \<const0> ;
  assign debug_axi_poff_in[4] = \<const0> ;
  assign debug_axi_poff_in[3] = \<const0> ;
  assign debug_axi_poff_in[2] = \<const0> ;
  assign debug_axi_poff_in[1] = \<const0> ;
  assign debug_axi_poff_in[0] = \<const0> ;
  assign debug_axi_resync_in = \<const0> ;
  assign debug_core_nd = \<const0> ;
  assign debug_phase[24] = \<const0> ;
  assign debug_phase[23] = \<const0> ;
  assign debug_phase[22] = \<const0> ;
  assign debug_phase[21] = \<const0> ;
  assign debug_phase[20] = \<const0> ;
  assign debug_phase[19] = \<const0> ;
  assign debug_phase[18] = \<const0> ;
  assign debug_phase[17] = \<const0> ;
  assign debug_phase[16] = \<const0> ;
  assign debug_phase[15] = \<const0> ;
  assign debug_phase[14] = \<const0> ;
  assign debug_phase[13] = \<const0> ;
  assign debug_phase[12] = \<const0> ;
  assign debug_phase[11] = \<const0> ;
  assign debug_phase[10] = \<const0> ;
  assign debug_phase[9] = \<const0> ;
  assign debug_phase[8] = \<const0> ;
  assign debug_phase[7] = \<const0> ;
  assign debug_phase[6] = \<const0> ;
  assign debug_phase[5] = \<const0> ;
  assign debug_phase[4] = \<const0> ;
  assign debug_phase[3] = \<const0> ;
  assign debug_phase[2] = \<const0> ;
  assign debug_phase[1] = \<const0> ;
  assign debug_phase[0] = \<const0> ;
  assign debug_phase_nd = \<const0> ;
  assign event_phase_in_invalid = \<const0> ;
  assign event_pinc_invalid = \<const0> ;
  assign event_poff_invalid = \<const0> ;
  assign event_s_config_tlast_missing = \<const0> ;
  assign event_s_config_tlast_unexpected = \<const0> ;
  assign event_s_phase_chanid_incorrect = \<const0> ;
  assign event_s_phase_tlast_unexpected = \<const0> ;
  assign m_axis_data_tdata[63] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[62] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[61] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[60] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[59] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[58] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[57] = \^m_axis_data_tdata [56];
  assign m_axis_data_tdata[56:32] = \^m_axis_data_tdata [56:32];
  assign m_axis_data_tdata[31] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[30] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[29] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[28] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[27] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[26] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[25] = \^m_axis_data_tdata [24];
  assign m_axis_data_tdata[24:0] = \^m_axis_data_tdata [24:0];
  assign m_axis_data_tlast = \<const0> ;
  assign m_axis_data_tuser[0] = \<const0> ;
  assign m_axis_phase_tdata[0] = \<const0> ;
  assign m_axis_phase_tlast = \<const0> ;
  assign m_axis_phase_tuser[0] = \<const0> ;
  assign m_axis_phase_tvalid = \<const0> ;
  assign s_axis_config_tready = \<const0> ;
  assign s_axis_phase_tready = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_ACCUMULATOR_WIDTH = "25" *) 
  (* C_AMPLITUDE = "0" *) 
  (* C_CHANNELS = "1" *) 
  (* C_CHAN_WIDTH = "1" *) 
  (* C_DEBUG_INTERFACE = "0" *) 
  (* C_HAS_ACLKEN = "0" *) 
  (* C_HAS_ARESETN = "0" *) 
  (* C_HAS_M_DATA = "1" *) 
  (* C_HAS_M_PHASE = "0" *) 
  (* C_HAS_PHASEGEN = "0" *) 
  (* C_HAS_PHASE_OUT = "0" *) 
  (* C_HAS_SINCOS = "1" *) 
  (* C_HAS_S_CONFIG = "0" *) 
  (* C_HAS_S_PHASE = "1" *) 
  (* C_HAS_TLAST = "0" *) 
  (* C_HAS_TREADY = "0" *) 
  (* C_LATENCY = "9" *) 
  (* C_MEM_TYPE = "1" *) 
  (* C_MODE_OF_OPERATION = "0" *) 
  (* C_MODULUS = "9" *) 
  (* C_M_DATA_HAS_TUSER = "0" *) 
  (* C_M_DATA_TDATA_WIDTH = "64" *) 
  (* C_M_DATA_TUSER_WIDTH = "1" *) 
  (* C_M_PHASE_HAS_TUSER = "0" *) 
  (* C_M_PHASE_TDATA_WIDTH = "1" *) 
  (* C_M_PHASE_TUSER_WIDTH = "1" *) 
  (* C_NEGATIVE_COSINE = "0" *) 
  (* C_NEGATIVE_SINE = "0" *) 
  (* C_NOISE_SHAPING = "2" *) 
  (* C_OPTIMISE_GOAL = "0" *) 
  (* C_OUTPUTS_REQUIRED = "2" *) 
  (* C_OUTPUT_FORM = "0" *) 
  (* C_OUTPUT_WIDTH = "25" *) 
  (* C_PHASE_ANGLE_WIDTH = "11" *) 
  (* C_PHASE_INCREMENT = "2" *) 
  (* C_PHASE_INCREMENT_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_PHASE_OFFSET = "0" *) 
  (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) 
  (* C_POR_MODE = "0" *) 
  (* C_RESYNC = "0" *) 
  (* C_S_CONFIG_SYNC_MODE = "0" *) 
  (* C_S_CONFIG_TDATA_WIDTH = "1" *) 
  (* C_S_PHASE_HAS_TUSER = "0" *) 
  (* C_S_PHASE_TDATA_WIDTH = "32" *) 
  (* C_S_PHASE_TUSER_WIDTH = "1" *) 
  (* C_USE_DSP48 = "0" *) 
  (* C_XDEVICEFAMILY = "kintex7" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  RFNCO_cmp_dds_IF1_0_dds_compiler_v6_0_16_viv i_synth
       (.aclk(aclk),
        .aclken(\<const0> ),
        .aresetn(\<const0> ),
        .event_s_phase_tlast_missing(event_s_phase_tlast_missing),
        .m_axis_data_tdata({\^m_axis_data_tdata [56],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[62:56],\^m_axis_data_tdata [55:32],\^m_axis_data_tdata [24],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[30:24],\^m_axis_data_tdata [23:0]}),
        .m_axis_data_tready(\<const0> ),
        .m_axis_data_tvalid(m_axis_data_tvalid),
        .m_axis_phase_tready(\<const0> ),
        .s_axis_config_tdata(\<const0> ),
        .s_axis_config_tlast(\<const0> ),
        .s_axis_config_tvalid(\<const0> ),
        .s_axis_phase_tdata({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,s_axis_phase_tdata[24:0]}),
        .s_axis_phase_tlast(\<const0> ),
        .s_axis_phase_tuser(\<const0> ),
        .s_axis_phase_tvalid(s_axis_phase_tvalid));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`pragma protect key_keyowner="Cadence Design Systems.", key_keyname="cds_rsa_key", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=64)
`pragma protect key_block
ihvl9qvl6mtGSCn2QmTq24p+4WK+wehYw2BbTxVxOCa6AomXDDHWk3N+fCT7Ec6ymOwaE84zl0AE
FfZ+2lebag==

`pragma protect key_keyowner="Synopsys", key_keyname="SNPS-VCS-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
AHSEaMSHfcPE7ySf3fWQlVVbNBrSBwx7+2AARSD3OQbYwQqttf2jqz1AS0VS/c8hbcCH5/xEo6wc
0YCLC0TLjuP2NG+0xTTkINJp9RP36eLtRQ2gjEU9+Pygg4ojLhxKahp/JEhqwbC1zJ0m6z6tXz28
bTJx42bN7mGmsF/5Vgo=

`pragma protect key_keyowner="Aldec", key_keyname="ALDEC15_001", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
eUgf8tzJSzGYR4YGwogvvkQDrltsQcVA9ax6H/7FMeGxBK2ExpkrnTayKuSWcrEPmKPLWojzX4Rp
jrntLR03FJ33vvdw2iwqsMr+YZSn0FiWqFMgiPpkhPbKlP4d15bbtMD1Gko6ThnUYsNe1Uokkn4j
XnzAaz7aLS/P1FfaZrZVJLZBmqw+M4M3WTQh3kHKZi1NfWDWFanvoTIJ8umhWll7zTiRIxxlj2sf
1AcaTjGRqpbPx1fswKwB7zjTxMYAB6XDrFCMn5GWHrXicRi1BSZ1dc9X0RaAEy2+fbCe/QSMIv19
MDudZjBjTBvKNBHTvAxVaCQR/r6TjwYyPHNUow==

`pragma protect key_keyowner="ATRENTA", key_keyname="ATR-SG-2015-RSA-3", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
fCE0iqQqQmMaiqxfu+lTOtYiRgejwUsC7ex66qrLPjZOeOOR6VFQe0j18JJeWW1cqE1CqiDHXXhL
6qtSICA9OSpeVggF9+AotqgyKE2nkxSN+OH8BinQb+BCes2TzJdC0Q8T8bvLRGMoliywPlIhdI6M
pVGSFhdws+piimMdaiPwhMLA0wE+YYK+4mN+QesiOMEQp3/Cv4ACToB5iiqSUx8R1uBNs+IBsaLd
CAPHniHtsT0elqUJOwqg9qiDbSvuE6UgMnvSrPAsFvL62QdWpPybBWyfKrhItzQnrneRgsJNsmbD
TdnUyZ73dN5jp+L64ScrCI3oJTqLgQ/GAoegqQ==

`pragma protect key_keyowner="Xilinx", key_keyname="xilinxt_2017_05", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
KP8tDEaMtNiHb7fLSQNSmIn6f3quyU2/8znjyIPJk9gEjSsUmr7PpaLzh7KITyetyAykLNDy0+If
oi9FlchUdYS1S8pIc+xKb4AysqoPNQ+I+BYMgLboZ2BRi67NmSNSZYIhupYI3kmhhdoBdG0KzW7A
Aa4Qz9i9rgI0nLPReO8LZ1al6lYDHDry02cDN+z+OiGpkpvQiPH1p/hGXvKiTMWnkZNiRGteD3q8
NidKjK7vDwMwTVfAhWlaTHlCguRO0FMdED3Flrh0oUCH2MyAsCHNAsNEF/4qI+Lk3OL1BLUoHCO/
hHnZPWSiBfVLKyuWqMN3Hqm/+H7K+iaKo2cU/A==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VELOCE-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=128)
`pragma protect key_block
VYINJP/X0xCgvLZxQq9WoLczB1D4IDZ/fiNpsohtGnTSTTQAZTTkHNgUYHINe8Hnm+sHY/z+79mf
SZmevlmaMyfQ/bruVpg7xkGk0kbsRE0657dK7+oA8vBZP50PGrnmyAUz9JthH6ARIL//Z+jFQIOm
3AEyJSkfolORpd6jmrA=

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-VERIF-SIM-RSA-2", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
BCuflP0+YszOWk6oPUbw/aQvnws00cRjSsHJnmgdFgTaszbu6AWa6hxrBP5OsH4RBPYxnsCAzzmv
F5qT51GZNkOOZdTFTAcngBKxoMJSIxiAaRhxchN7P0V+S0FF7xLP/fGcJOqyFT6KpjP/RTwm3vUe
xD8zDgnEwlNjVHzIqTKpFHYOSL3LJUDoF1rbjBDNfrVak1lMu0CVMwqb+wnGLhRZ1UjS/sXTSCp+
vZNSonNgI1muW5JsxMZapVVzl8zcz4B4MQirD3E8dZylgZJrpaW5nyfCS6axpHQXarqv+DjNU4u9
nolZ1lTfG/mT8DJpdiBfhnV1wNBkgF9/OFqaIw==

`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
DHPhB7Bv1SOwEAyEtlpQ/KKws25yRf7YXHDsfFYO7nzyjMdk9l4FupgTy9Zi9kwV+jfEcPA1e05o
KRdbcleypB8nV75zkmrErMFM3AZhsNO4iPMZrSvdqu1+bZQuDbkLANmQXN5ndw8wq0XGW8Vyn1Ge
H0o4QGfgTg2nyCq919HSIpKnC1tFXByX+K1zxW14I4Zz74LIhN3Ilr8LkcJdMwMcgNAB2hNpvHZH
qNrDWOacVl4rDwZ+Jw1J5OLTJaXLacWn50CrAJEipHA7029wTZwOWdqg5DC+K6sR/jNiPhczGtXD
6LRCsfjnG5qe2R9vLf016ekJRaLVg7M08Qj40Q==

`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
NFKUVmmHj1Z2emQ9jshdlArufectNzRAJsIy35EHt7JRkjj4iIv9X9Skz8zvcLjc/dv9DLrzBQKb
EG6ZlPq5JJv2AZAN/RRtnh3r7PIWOW1hQRuMTfINgg1iGA7dkLxLcdJiIQO2DSI3yggTLkpeE+X7
IUx98F23FyZVdTQehtAJZoTVYfkZmWYBrqlAeBQvX1nW8dAc0f/K+Ou5ksPRY1+EVc4sXMuOppYp
d+rUXvP9pLy7vT67d0fOR7AHGlyMUUtsUMpyZao0hRPWJVHfcNq5M4FiFmML2R2DG+SkKsEPx84u
IwWs7bdEpBZz1xR6EYQFsQfvtnM1GiV1VSwOZg==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 382640)
`pragma protect data_block
NaGI49uuE8PeGrPwqnXih80mZX3YgfUqq7E9PuT5FRF9UXazjaVzyBnGXOGQ8Fc+2+izuMalTQRN
BQ9cQU4zQd8WVtStgxds6uMcRjHOR9Ua1gsUWcGXUrN9whK3YiBlQ8BUR1r/8LlfLpF0t3oMF/0Q
G4EwhTSctAfYhqmCA70q4ggZujYcpao0gsWIcL0F58PWYBXR5645geysD51xBWLLonELo7DpHR9j
GoxTMa28aAZaGcoMezAx5TPG7LrAMWX6g9fqB3PafDE/NdC+IP2YwUflEboPXg7TgnEVuXM6cTcI
3Pm6R8jR7hRxbDX+ZGyAI4ScVsRm0+hJhuP1pMA6SBW2tFyz71dIQ2TSJ4b1KgEO6mebrODHD6yt
OMpnVWDg5zCwfyZPOIMxjn7P0jTTgFDdmuZyhLl94g8hGJeqPYf/RtD/7UoP3kaGQvsThzfp83wL
gBG3Q/YMckDKjevpEswucLwJG8cfIM6Oh9fdSIF2JbYb3Xpzo9FwI1pQUiWo33bvI9Q4pQchwvlx
fST7iMCDfu79F3QW1QQr/9OhHnmip6G/NeVD2ztq34JHX6GWoENLrczdXxeuknf/0Xnbw88+TneQ
DQmgOjLIzq1HI+jMXmCRQE6+GbDSE4UHCdcCZ5t51I+S/aLlxo/8VpzxCqPOjgIzqg/UivxoFLbt
NczjOO/VJxx3UQkwlGYXwBVAwl7/MYdcPD1ZOQlXuURetIcIb8tCyNwiUbyv7bSMxRgUVX8vsnSX
3P/Sc/Jdre2S10HFvlm2S8JZOlH1Ns8pXIafkUIjCIFVLHd45LcgiUvAy+Ii5oB2NbkBI9/FSmG6
cLTbaBhNUsrJhfmIHl/kFkmGqo60Lw4b5FKEaXXXnAQltS+7Kt37GV6AgsfOdqfT/74X3/mz4Exe
1x5GlqxU56Iiawcjmid+vuFATJU1eWEgA1byPMEv6NDfC4AIJTfiXlsAoxNgkyM3Iw5AtSCzo1x8
dQXojbflwYcyBNF5thPOmi04KKOBieZdS2s1OTovTe5Y2zJ8kLbWs3NeGNPcm+lc3nn6bVx/gjw1
1I1KloRDxuWke42EkZ7/EvhU9XzyVn2ZFkP44lI6aP8zD8iF8HZLOZCKEArbH0Sv0kv63SLB5tP5
VzOB2WKiRrbKZBPyz8mbAN+Yom2ikU4QSn7k2GMPhrhStdPuJnPJGLAnmqHJ+mUcudlP09VUXql7
m5k1TduX/8htBhjvtrTBl6apWwFUzziwTg0d6QRPwtDXq5MRQ9QkSbaord5WjC4qaSopgxg913Er
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AHHVfdKAMRMXpRy5b5rKWrRDBWmaK/ZdTKUPIbTs6WRyiuVKiBzGXNHM/ErWDkQYr3aZtDL09GJI
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`pragma protect end_protected
