-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i RFNCO.cheby --gen-hdl
-- Generated on Wed May 10 11:16:39 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rfnco_regs is
  port (
    aclk                 : in    std_logic;
    areset_n             : in    std_logic;
    awvalid              : in    std_logic;
    awready              : out   std_logic;
    awaddr               : in    std_logic_vector(11 downto 0);
    awprot               : in    std_logic_vector(2 downto 0);
    wvalid               : in    std_logic;
    wready               : out   std_logic;
    wdata                : in    std_logic_vector(31 downto 0);
    wstrb                : in    std_logic_vector(3 downto 0);
    bvalid               : out   std_logic;
    bready               : in    std_logic;
    bresp                : out   std_logic_vector(1 downto 0);
    arvalid              : in    std_logic;
    arready              : out   std_logic;
    araddr               : in    std_logic_vector(11 downto 0);
    arprot               : in    std_logic_vector(2 downto 0);
    rvalid               : out   std_logic;
    rready               : in    std_logic;
    rdata                : out   std_logic_vector(31 downto 0);
    rresp                : out   std_logic_vector(1 downto 0);

    -- IP Ident code
    ipInfo_ident_i       : in    std_logic_vector(31 downto 0);

    -- Firmware Version
    ipInfo_firmwareVersion_i : in    std_logic_vector(31 downto 0);

    -- Memory Map Version
    ipInfo_memMapVersion_i : in    std_logic_vector(31 downto 0);

    -- Register used solely by software. No interaction with the firmware foreseen.
    -- The idea is to use this register as "flag" in the hardware to remember your actions from the software side.

    -- Reading 0xFF often happens when the board is not even reachable (i.e. bus problems on VME)

    -- On the other hand if the board is reachable the usual state of flipflops are 0x00. Thus this would indicate that no initialization has been attempted yet.

    -- At start of your software (FESA class) you should set the value 0x40 indicating that initialization is in progress. 
    -- This is important for you to later one check if you can read this value back before finally setting it to 0x80 (the value previously used with Cheburashka).

    -- If your initialization failed but you want to continue anyway you should set the register to 0xC0 to indicate this error 

    -- This register is in particular useful if you have several entities interacting with the hardware. In this case several bits could be assigned to this entities (bits 5..0) to signalize that they have done there part successful and a main entity checks all the expected bits.
    -- This version of the standard foresees only 8bits linked to real memory
    ipInfo_echo_echo_o   : out   std_logic_vector(7 downto 0);

    -- control register
    -- global reset
    control_reset_o      : out   std_logic;
    -- loads the ftw and settings to the NCO
    control_softLoad_o   : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selFtwLo0_o  : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selFtwLo1_o  : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selOffsetH1_o : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selOffsetFskH1_o : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selRate_o    : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selFtwH1_o   : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selFtwH1On_o : out   std_logic;
    -- When true, FTW_H1_main from external input selected, else FTW_H1_prog
    control_selWrFtwH1_o : out   std_logic;
    -- When true, dFTW_Slip dFTW_slip0 of external input, else dFTW_slip1
    control_selWrDftwH1slip_o : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selDftwH1slip_o : out   std_logic;
    -- When true, data comes from external input, else from the memory map
    control_selFtwH1prog_o : out   std_logic;
    -- When true changes the polarity of slip offset to negative
    control_slipSign_o   : out   std_logic;
    -- FSK enabled when true.
    control_enableFSK_o  : out   std_logic;
    -- resets the FSK accumulator.
    control_resetFSK_o   : out   std_logic;
    -- enables slip stacking, the slip accumulator is still running.
    control_enableSlip_o : out   std_logic;
    -- resets the slip accumulator.
    control_resetSlip_o  : out   std_logic;
    -- When true inverts the sign of IF0 sin
    control_signIF0_o    : out   std_logic;
    -- When true inverts the sign of IF1 sin
    control_signIF1_o    : out   std_logic;
    -- enable external reset
    control_extResetEnable_o : out   std_logic;
    -- latch phase registers for synchronous readout
    control_latchPhases_o : out   std_logic;
    -- When true, load comes from external input, else from the memory map
    control_selLoad_o    : out   std_logic;
    -- enable frequency doubling on IF1 channel
    control_enableFreqDoubling_o : out   std_logic;
    -- force amplitude modulation
    control_forceAM_o    : out   std_logic;

    -- status register
    -- true when not configured for operation
    status_interlock_i   : in    std_logic;
    -- phase output valid
    status_phaseH1Vld_i  : in    std_logic;
    -- The NCO has detected frequency modulation is necessary
    status_amAutoOn_i    : in    std_logic;

    -- Harmonic 1 FTW
    ftw_h1_reg_o         : out   std_logic_vector(47 downto 0);

    -- Harmonic 1 program FTW
    ftw_h1Prog_reg_o     : out   std_logic_vector(47 downto 0);

    -- Cavity on H1 FTW
    ftw_on_reg_o         : out   std_logic_vector(47 downto 0);

    -- LO 0 FTW
    ftw_lo0_reg_o        : out   std_logic_vector(47 downto 0);

    -- LO 1 FTW
    ftw_lo1_reg_o        : out   std_logic_vector(47 downto 0);

    -- slip H1 FTW
    ftw_slip_o           : out   std_logic_vector(31 downto 0);

    -- H1 phase offset (Azimuth)
    inputs_offsetH1_reg_o : out   std_logic_vector(47 downto 0);

    -- FSK rate
    inputs_rate_o        : out   std_logic_vector(31 downto 0);

    -- Harmonic number
    inputs_h_o           : out   std_logic_vector(15 downto 0);

    -- offset from Frev for FSK
    inputs_offsetFSK_reg_o : out   std_logic_vector(47 downto 0);

    -- offset from FSK to AM (Amplitude Modulation)
    inputs_offsetAM_reg_o : out   std_logic_vector(47 downto 0);

    -- pulse length of AM (Amplitude Modulation)
    inputs_pulseLengthAM_reg_o : out   std_logic_vector(47 downto 0);

    -- fixed delay for phase compensation in sec.
    inputs_delayComp_o   : out   std_logic_vector(31 downto 0);

    -- H1 phase with compensation
    phases_h1_reg_i      : in    std_logic_vector(47 downto 0);

    -- H1 phase direct
    phases_h1Main_reg_i  : in    std_logic_vector(47 downto 0);

    -- H1 slippage phase
    phases_h1Slip_reg_i  : in    std_logic_vector(47 downto 0);

    -- IF0 phase
    phases_if0_reg_i     : in    std_logic_vector(47 downto 0);

    -- IF1 phase
    phases_if1_reg_i     : in    std_logic_vector(47 downto 0);

    -- latches the presence of pulses
    -- Frev pulse detected since last reset
    presentLatch_frev_i  : in    std_logic;
    -- Amplitude modulation detected since last reset
    presentLatch_am_i    : in    std_logic;
    -- time word valid output detected since last reset
    presentLatch_tw_i    : in    std_logic;
    -- coefficients output valid detected since last reset
    presentLatch_coef_i  : in    std_logic;
    -- input load detected (hw or sw) since last reset
    presentLatch_load_i  : in    std_logic;
    -- external NCO reset detected
    presentLatch_extReset_i : in    std_logic;

    -- FSK coefficent raw readback
    readback_coef_i      : in    std_logic_vector(31 downto 0);

    -- Time word readback
    readback_tw_i        : in    std_logic_vector(31 downto 0);

    -- Cable delay compensation phase raw readback
    readback_phaseH1Comp_reg_i : in    std_logic_vector(47 downto 0)
  );
end rfnco_regs;

architecture syn of rfnco_regs is
  signal wr_req                         : std_logic;
  signal wr_ack                         : std_logic;
  signal wr_addr                        : std_logic_vector(11 downto 2);
  signal wr_data                        : std_logic_vector(31 downto 0);
  signal axi_awset                      : std_logic;
  signal axi_wset                       : std_logic;
  signal axi_wdone                      : std_logic;
  signal rd_req                         : std_logic;
  signal rd_ack                         : std_logic;
  signal rd_addr                        : std_logic_vector(11 downto 2);
  signal rd_data                        : std_logic_vector(31 downto 0);
  signal axi_arset                      : std_logic;
  signal axi_rdone                      : std_logic;
  signal ipInfo_echo_echo_reg           : std_logic_vector(7 downto 0);
  signal ipInfo_echo_wreq               : std_logic;
  signal ipInfo_echo_wack               : std_logic;
  signal control_reset_reg              : std_logic;
  signal control_softLoad_reg           : std_logic;
  signal control_selFtwLo0_reg          : std_logic;
  signal control_selFtwLo1_reg          : std_logic;
  signal control_selOffsetH1_reg        : std_logic;
  signal control_selOffsetFskH1_reg     : std_logic;
  signal control_selRate_reg            : std_logic;
  signal control_selFtwH1_reg           : std_logic;
  signal control_selFtwH1On_reg         : std_logic;
  signal control_selWrFtwH1_reg         : std_logic;
  signal control_selWrDftwH1slip_reg    : std_logic;
  signal control_selDftwH1slip_reg      : std_logic;
  signal control_selFtwH1prog_reg       : std_logic;
  signal control_slipSign_reg           : std_logic;
  signal control_enableFSK_reg          : std_logic;
  signal control_resetFSK_reg           : std_logic;
  signal control_enableSlip_reg         : std_logic;
  signal control_resetSlip_reg          : std_logic;
  signal control_signIF0_reg            : std_logic;
  signal control_signIF1_reg            : std_logic;
  signal control_extResetEnable_reg     : std_logic;
  signal control_latchPhases_reg        : std_logic;
  signal control_selLoad_reg            : std_logic;
  signal control_enableFreqDoubling_reg : std_logic;
  signal control_forceAM_reg            : std_logic;
  signal control_wreq                   : std_logic;
  signal control_wack                   : std_logic;
  signal ftw_h1_reg_reg                 : std_logic_vector(47 downto 0);
  signal ftw_h1_wreq                    : std_logic_vector(1 downto 0);
  signal ftw_h1_wack                    : std_logic_vector(1 downto 0);
  signal ftw_h1Prog_reg_reg             : std_logic_vector(47 downto 0);
  signal ftw_h1Prog_wreq                : std_logic_vector(1 downto 0);
  signal ftw_h1Prog_wack                : std_logic_vector(1 downto 0);
  signal ftw_on_reg_reg                 : std_logic_vector(47 downto 0);
  signal ftw_on_wreq                    : std_logic_vector(1 downto 0);
  signal ftw_on_wack                    : std_logic_vector(1 downto 0);
  signal ftw_lo0_reg_reg                : std_logic_vector(47 downto 0);
  signal ftw_lo0_wreq                   : std_logic_vector(1 downto 0);
  signal ftw_lo0_wack                   : std_logic_vector(1 downto 0);
  signal ftw_lo1_reg_reg                : std_logic_vector(47 downto 0);
  signal ftw_lo1_wreq                   : std_logic_vector(1 downto 0);
  signal ftw_lo1_wack                   : std_logic_vector(1 downto 0);
  signal ftw_slip_reg                   : std_logic_vector(31 downto 0);
  signal ftw_slip_wreq                  : std_logic;
  signal ftw_slip_wack                  : std_logic;
  signal inputs_offsetH1_reg_reg        : std_logic_vector(47 downto 0);
  signal inputs_offsetH1_wreq           : std_logic_vector(1 downto 0);
  signal inputs_offsetH1_wack           : std_logic_vector(1 downto 0);
  signal inputs_rate_reg                : std_logic_vector(31 downto 0);
  signal inputs_rate_wreq               : std_logic;
  signal inputs_rate_wack               : std_logic;
  signal inputs_h_reg                   : std_logic_vector(15 downto 0);
  signal inputs_h_wreq                  : std_logic;
  signal inputs_h_wack                  : std_logic;
  signal inputs_offsetFSK_reg_reg       : std_logic_vector(47 downto 0);
  signal inputs_offsetFSK_wreq          : std_logic_vector(1 downto 0);
  signal inputs_offsetFSK_wack          : std_logic_vector(1 downto 0);
  signal inputs_offsetAM_reg_reg        : std_logic_vector(47 downto 0);
  signal inputs_offsetAM_wreq           : std_logic_vector(1 downto 0);
  signal inputs_offsetAM_wack           : std_logic_vector(1 downto 0);
  signal inputs_pulseLengthAM_reg_reg   : std_logic_vector(47 downto 0);
  signal inputs_pulseLengthAM_wreq      : std_logic_vector(1 downto 0);
  signal inputs_pulseLengthAM_wack      : std_logic_vector(1 downto 0);
  signal inputs_delayComp_reg           : std_logic_vector(31 downto 0);
  signal inputs_delayComp_wreq          : std_logic;
  signal inputs_delayComp_wack          : std_logic;
  signal presentLatch_frev_reg          : std_logic;
  signal presentLatch_am_reg            : std_logic;
  signal presentLatch_tw_reg            : std_logic;
  signal presentLatch_coef_reg          : std_logic;
  signal presentLatch_load_reg          : std_logic;
  signal presentLatch_extReset_reg      : std_logic;
  signal presentLatch_wreq              : std_logic;
  signal presentLatch_wack              : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(31 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(11 downto 2);
  signal wr_dat_d0                      : std_logic_vector(31 downto 0);
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of awvalid : signal is
    "xilinx.com:interface:aximm:1.0 slave AWVALID";
  attribute X_INTERFACE_INFO of awready : signal is
    "xilinx.com:interface:aximm:1.0 slave AWREADY";
  attribute X_INTERFACE_INFO of awaddr : signal is
    "xilinx.com:interface:aximm:1.0 slave AWADDR";
  attribute X_INTERFACE_INFO of awprot : signal is
    "xilinx.com:interface:aximm:1.0 slave AWPROT";
  attribute X_INTERFACE_INFO of wvalid : signal is
    "xilinx.com:interface:aximm:1.0 slave WVALID";
  attribute X_INTERFACE_INFO of wready : signal is
    "xilinx.com:interface:aximm:1.0 slave WREADY";
  attribute X_INTERFACE_INFO of wdata : signal is
    "xilinx.com:interface:aximm:1.0 slave WDATA";
  attribute X_INTERFACE_INFO of wstrb : signal is
    "xilinx.com:interface:aximm:1.0 slave WSTRB";
  attribute X_INTERFACE_INFO of bvalid : signal is
    "xilinx.com:interface:aximm:1.0 slave BVALID";
  attribute X_INTERFACE_INFO of bready : signal is
    "xilinx.com:interface:aximm:1.0 slave BREADY";
  attribute X_INTERFACE_INFO of bresp : signal is
    "xilinx.com:interface:aximm:1.0 slave BRESP";
  attribute X_INTERFACE_INFO of arvalid : signal is
    "xilinx.com:interface:aximm:1.0 slave ARVALID";
  attribute X_INTERFACE_INFO of arready : signal is
    "xilinx.com:interface:aximm:1.0 slave ARREADY";
  attribute X_INTERFACE_INFO of araddr : signal is
    "xilinx.com:interface:aximm:1.0 slave ARADDR";
  attribute X_INTERFACE_INFO of arprot : signal is
    "xilinx.com:interface:aximm:1.0 slave ARPROT";
  attribute X_INTERFACE_INFO of rvalid : signal is
    "xilinx.com:interface:aximm:1.0 slave RVALID";
  attribute X_INTERFACE_INFO of rready : signal is
    "xilinx.com:interface:aximm:1.0 slave RREADY";
  attribute X_INTERFACE_INFO of rdata : signal is
    "xilinx.com:interface:aximm:1.0 slave RDATA";
  attribute X_INTERFACE_INFO of rresp : signal is
    "xilinx.com:interface:aximm:1.0 slave RRESP";
begin

  -- AW, W and B channels
  awready <= not axi_awset;
  wready <= not axi_wset;
  bvalid <= axi_wdone;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        wr_req <= '0';
        axi_awset <= '0';
        axi_wset <= '0';
        axi_wdone <= '0';
      else
        wr_req <= '0';
        if awvalid = '1' and axi_awset = '0' then
          wr_addr <= awaddr(11 downto 2);
          axi_awset <= '1';
          wr_req <= axi_wset;
        end if;
        if wvalid = '1' and axi_wset = '0' then
          wr_data <= wdata;
          axi_wset <= '1';
          wr_req <= axi_awset or awvalid;
        end if;
        if (axi_wdone and bready) = '1' then
          axi_wset <= '0';
          axi_awset <= '0';
          axi_wdone <= '0';
        end if;
        if wr_ack = '1' then
          axi_wdone <= '1';
        end if;
      end if;
    end if;
  end process;
  bresp <= "00";

  -- AR and R channels
  arready <= not axi_arset;
  rvalid <= axi_rdone;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        rd_req <= '0';
        axi_arset <= '0';
        axi_rdone <= '0';
        rdata <= (others => '0');
      else
        rd_req <= '0';
        if arvalid = '1' and axi_arset = '0' then
          rd_addr <= araddr(11 downto 2);
          axi_arset <= '1';
          rd_req <= '1';
        end if;
        if (axi_rdone and rready) = '1' then
          axi_arset <= '0';
          axi_rdone <= '0';
        end if;
        if rd_ack = '1' then
          axi_rdone <= '1';
          rdata <= rd_data;
        end if;
      end if;
    end if;
  end process;
  rresp <= "00";

  -- pipelining for wr-in+rd-out
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        rd_ack <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack <= rd_ack_d0;
        rd_data <= rd_dat_d0;
        wr_req_d0 <= wr_req;
        wr_adr_d0 <= wr_addr;
        wr_dat_d0 <= wr_data;
      end if;
    end if;
  end process;

  -- Register ipInfo_stdVersion

  -- Register ipInfo_ident

  -- Register ipInfo_firmwareVersion

  -- Register ipInfo_memMapVersion

  -- Register ipInfo_echo
  ipInfo_echo_echo_o <= ipInfo_echo_echo_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ipInfo_echo_echo_reg <= "00000000";
        ipInfo_echo_wack <= '0';
      else
        if ipInfo_echo_wreq = '1' then
          ipInfo_echo_echo_reg <= wr_dat_d0(7 downto 0);
        end if;
        ipInfo_echo_wack <= ipInfo_echo_wreq;
      end if;
    end if;
  end process;

  -- Register control
  control_reset_o <= control_reset_reg;
  control_softLoad_o <= control_softLoad_reg;
  control_selFtwLo0_o <= control_selFtwLo0_reg;
  control_selFtwLo1_o <= control_selFtwLo1_reg;
  control_selOffsetH1_o <= control_selOffsetH1_reg;
  control_selOffsetFskH1_o <= control_selOffsetFskH1_reg;
  control_selRate_o <= control_selRate_reg;
  control_selFtwH1_o <= control_selFtwH1_reg;
  control_selFtwH1On_o <= control_selFtwH1On_reg;
  control_selWrFtwH1_o <= control_selWrFtwH1_reg;
  control_selWrDftwH1slip_o <= control_selWrDftwH1slip_reg;
  control_selDftwH1slip_o <= control_selDftwH1slip_reg;
  control_selFtwH1prog_o <= control_selFtwH1prog_reg;
  control_slipSign_o <= control_slipSign_reg;
  control_enableFSK_o <= control_enableFSK_reg;
  control_resetFSK_o <= control_resetFSK_reg;
  control_enableSlip_o <= control_enableSlip_reg;
  control_resetSlip_o <= control_resetSlip_reg;
  control_signIF0_o <= control_signIF0_reg;
  control_signIF1_o <= control_signIF1_reg;
  control_extResetEnable_o <= control_extResetEnable_reg;
  control_latchPhases_o <= control_latchPhases_reg;
  control_selLoad_o <= control_selLoad_reg;
  control_enableFreqDoubling_o <= control_enableFreqDoubling_reg;
  control_forceAM_o <= control_forceAM_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        control_reset_reg <= '0';
        control_softLoad_reg <= '0';
        control_selFtwLo0_reg <= '0';
        control_selFtwLo1_reg <= '0';
        control_selOffsetH1_reg <= '0';
        control_selOffsetFskH1_reg <= '0';
        control_selRate_reg <= '0';
        control_selFtwH1_reg <= '0';
        control_selFtwH1On_reg <= '0';
        control_selWrFtwH1_reg <= '0';
        control_selWrDftwH1slip_reg <= '0';
        control_selDftwH1slip_reg <= '0';
        control_selFtwH1prog_reg <= '0';
        control_slipSign_reg <= '0';
        control_enableFSK_reg <= '0';
        control_resetFSK_reg <= '0';
        control_enableSlip_reg <= '0';
        control_resetSlip_reg <= '0';
        control_signIF0_reg <= '0';
        control_signIF1_reg <= '0';
        control_extResetEnable_reg <= '0';
        control_latchPhases_reg <= '0';
        control_selLoad_reg <= '0';
        control_enableFreqDoubling_reg <= '0';
        control_forceAM_reg <= '0';
        control_wack <= '0';
      else
        if control_wreq = '1' then
          control_reset_reg <= wr_dat_d0(0);
          control_softLoad_reg <= wr_dat_d0(1);
          control_selFtwLo0_reg <= wr_dat_d0(2);
          control_selFtwLo1_reg <= wr_dat_d0(3);
          control_selOffsetH1_reg <= wr_dat_d0(4);
          control_selOffsetFskH1_reg <= wr_dat_d0(5);
          control_selRate_reg <= wr_dat_d0(6);
          control_selFtwH1_reg <= wr_dat_d0(7);
          control_selFtwH1On_reg <= wr_dat_d0(8);
          control_selWrFtwH1_reg <= wr_dat_d0(9);
          control_selWrDftwH1slip_reg <= wr_dat_d0(10);
          control_selDftwH1slip_reg <= wr_dat_d0(11);
          control_selFtwH1prog_reg <= wr_dat_d0(12);
          control_slipSign_reg <= wr_dat_d0(13);
          control_enableFSK_reg <= wr_dat_d0(14);
          control_resetFSK_reg <= wr_dat_d0(15);
          control_enableSlip_reg <= wr_dat_d0(16);
          control_resetSlip_reg <= wr_dat_d0(17);
          control_signIF0_reg <= wr_dat_d0(18);
          control_signIF1_reg <= wr_dat_d0(19);
          control_extResetEnable_reg <= wr_dat_d0(20);
          control_latchPhases_reg <= wr_dat_d0(21);
          control_selLoad_reg <= wr_dat_d0(22);
          control_enableFreqDoubling_reg <= wr_dat_d0(23);
          control_forceAM_reg <= wr_dat_d0(24);
        else
          control_softLoad_reg <= '0';
          control_resetFSK_reg <= '0';
          control_resetSlip_reg <= '0';
          control_latchPhases_reg <= '0';
        end if;
        control_wack <= control_wreq;
      end if;
    end if;
  end process;

  -- Register status

  -- Register ftw_h1
  ftw_h1_reg_o <= ftw_h1_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ftw_h1_reg_reg <= "000000000000000000000000000000000000000000000000";
        ftw_h1_wack <= (others => '0');
      else
        if ftw_h1_wreq(0) = '1' then
          ftw_h1_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if ftw_h1_wreq(1) = '1' then
          ftw_h1_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        ftw_h1_wack <= ftw_h1_wreq;
      end if;
    end if;
  end process;

  -- Register ftw_h1Prog
  ftw_h1Prog_reg_o <= ftw_h1Prog_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ftw_h1Prog_reg_reg <= "000000000000000000000000000000000000000000000000";
        ftw_h1Prog_wack <= (others => '0');
      else
        if ftw_h1Prog_wreq(0) = '1' then
          ftw_h1Prog_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if ftw_h1Prog_wreq(1) = '1' then
          ftw_h1Prog_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        ftw_h1Prog_wack <= ftw_h1Prog_wreq;
      end if;
    end if;
  end process;

  -- Register ftw_on
  ftw_on_reg_o <= ftw_on_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ftw_on_reg_reg <= "000000000000000000000000000000000000000000000000";
        ftw_on_wack <= (others => '0');
      else
        if ftw_on_wreq(0) = '1' then
          ftw_on_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if ftw_on_wreq(1) = '1' then
          ftw_on_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        ftw_on_wack <= ftw_on_wreq;
      end if;
    end if;
  end process;

  -- Register ftw_lo0
  ftw_lo0_reg_o <= ftw_lo0_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ftw_lo0_reg_reg <= "000000000000000000000000000000000000000000000000";
        ftw_lo0_wack <= (others => '0');
      else
        if ftw_lo0_wreq(0) = '1' then
          ftw_lo0_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if ftw_lo0_wreq(1) = '1' then
          ftw_lo0_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        ftw_lo0_wack <= ftw_lo0_wreq;
      end if;
    end if;
  end process;

  -- Register ftw_lo1
  ftw_lo1_reg_o <= ftw_lo1_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ftw_lo1_reg_reg <= "000000000000000000000000000000000000000000000000";
        ftw_lo1_wack <= (others => '0');
      else
        if ftw_lo1_wreq(0) = '1' then
          ftw_lo1_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if ftw_lo1_wreq(1) = '1' then
          ftw_lo1_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        ftw_lo1_wack <= ftw_lo1_wreq;
      end if;
    end if;
  end process;

  -- Register ftw_slip
  ftw_slip_o <= ftw_slip_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        ftw_slip_reg <= "00000000000000000000000000000000";
        ftw_slip_wack <= '0';
      else
        if ftw_slip_wreq = '1' then
          ftw_slip_reg <= wr_dat_d0;
        end if;
        ftw_slip_wack <= ftw_slip_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_offsetH1
  inputs_offsetH1_reg_o <= inputs_offsetH1_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_offsetH1_reg_reg <= "000000000000000000000000000000000000000000000000";
        inputs_offsetH1_wack <= (others => '0');
      else
        if inputs_offsetH1_wreq(0) = '1' then
          inputs_offsetH1_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if inputs_offsetH1_wreq(1) = '1' then
          inputs_offsetH1_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        inputs_offsetH1_wack <= inputs_offsetH1_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_rate
  inputs_rate_o <= inputs_rate_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_rate_reg <= "00000000000000000000000000000000";
        inputs_rate_wack <= '0';
      else
        if inputs_rate_wreq = '1' then
          inputs_rate_reg <= wr_dat_d0;
        end if;
        inputs_rate_wack <= inputs_rate_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_h
  inputs_h_o <= inputs_h_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_h_reg <= "0000000000000000";
        inputs_h_wack <= '0';
      else
        if inputs_h_wreq = '1' then
          inputs_h_reg <= wr_dat_d0(15 downto 0);
        end if;
        inputs_h_wack <= inputs_h_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_offsetFSK
  inputs_offsetFSK_reg_o <= inputs_offsetFSK_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_offsetFSK_reg_reg <= "000000000000000000000000000000000000000000000000";
        inputs_offsetFSK_wack <= (others => '0');
      else
        if inputs_offsetFSK_wreq(0) = '1' then
          inputs_offsetFSK_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if inputs_offsetFSK_wreq(1) = '1' then
          inputs_offsetFSK_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        inputs_offsetFSK_wack <= inputs_offsetFSK_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_offsetAM
  inputs_offsetAM_reg_o <= inputs_offsetAM_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_offsetAM_reg_reg <= "000000000000000000000000000000000000000000000000";
        inputs_offsetAM_wack <= (others => '0');
      else
        if inputs_offsetAM_wreq(0) = '1' then
          inputs_offsetAM_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if inputs_offsetAM_wreq(1) = '1' then
          inputs_offsetAM_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        inputs_offsetAM_wack <= inputs_offsetAM_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_pulseLengthAM
  inputs_pulseLengthAM_reg_o <= inputs_pulseLengthAM_reg_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_pulseLengthAM_reg_reg <= "000000000000000000000000000000000000000000000000";
        inputs_pulseLengthAM_wack <= (others => '0');
      else
        if inputs_pulseLengthAM_wreq(0) = '1' then
          inputs_pulseLengthAM_reg_reg(31 downto 0) <= wr_dat_d0;
        end if;
        if inputs_pulseLengthAM_wreq(1) = '1' then
          inputs_pulseLengthAM_reg_reg(47 downto 32) <= wr_dat_d0(15 downto 0);
        end if;
        inputs_pulseLengthAM_wack <= inputs_pulseLengthAM_wreq;
      end if;
    end if;
  end process;

  -- Register inputs_delayComp
  inputs_delayComp_o <= inputs_delayComp_reg;
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        inputs_delayComp_reg <= "00000000000000000000000000000000";
        inputs_delayComp_wack <= '0';
      else
        if inputs_delayComp_wreq = '1' then
          inputs_delayComp_reg <= wr_dat_d0;
        end if;
        inputs_delayComp_wack <= inputs_delayComp_wreq;
      end if;
    end if;
  end process;

  -- Register phases_h1

  -- Register phases_h1Main

  -- Register phases_h1Slip

  -- Register phases_if0

  -- Register phases_if1

  -- Register presentLatch
  process (aclk) begin
    if rising_edge(aclk) then
      if areset_n = '0' then
        presentLatch_frev_reg <= '0';
        presentLatch_am_reg <= '0';
        presentLatch_tw_reg <= '0';
        presentLatch_coef_reg <= '0';
        presentLatch_load_reg <= '0';
        presentLatch_extReset_reg <= '0';
        presentLatch_wack <= '0';
      else
        if presentLatch_wreq = '1' then
          presentLatch_frev_reg <= presentLatch_frev_i or (presentLatch_frev_reg and not wr_dat_d0(0));
          presentLatch_am_reg <= presentLatch_am_i or (presentLatch_am_reg and not wr_dat_d0(1));
          presentLatch_tw_reg <= presentLatch_tw_i or (presentLatch_tw_reg and not wr_dat_d0(2));
          presentLatch_coef_reg <= presentLatch_coef_i or (presentLatch_coef_reg and not wr_dat_d0(3));
          presentLatch_load_reg <= presentLatch_load_i or (presentLatch_load_reg and not wr_dat_d0(4));
          presentLatch_extReset_reg <= presentLatch_extReset_i or (presentLatch_extReset_reg and not wr_dat_d0(5));
        else
          presentLatch_frev_reg <= presentLatch_frev_i or presentLatch_frev_reg;
          presentLatch_am_reg <= presentLatch_am_i or presentLatch_am_reg;
          presentLatch_tw_reg <= presentLatch_tw_i or presentLatch_tw_reg;
          presentLatch_coef_reg <= presentLatch_coef_i or presentLatch_coef_reg;
          presentLatch_load_reg <= presentLatch_load_i or presentLatch_load_reg;
          presentLatch_extReset_reg <= presentLatch_extReset_i or presentLatch_extReset_reg;
        end if;
        presentLatch_wack <= presentLatch_wreq;
      end if;
    end if;
  end process;

  -- Register readback_coef

  -- Register readback_tw

  -- Register readback_phaseH1Comp

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, ipInfo_echo_wack, control_wack, ftw_h1_wack,
           ftw_h1Prog_wack, ftw_on_wack, ftw_lo0_wack, ftw_lo1_wack, ftw_slip_wack,
           inputs_offsetH1_wack, inputs_rate_wack, inputs_h_wack,
           inputs_offsetFSK_wack, inputs_offsetAM_wack,
           inputs_pulseLengthAM_wack, inputs_delayComp_wack, presentLatch_wack) begin
    ipInfo_echo_wreq <= '0';
    control_wreq <= '0';
    ftw_h1_wreq <= (others => '0');
    ftw_h1Prog_wreq <= (others => '0');
    ftw_on_wreq <= (others => '0');
    ftw_lo0_wreq <= (others => '0');
    ftw_lo1_wreq <= (others => '0');
    ftw_slip_wreq <= '0';
    inputs_offsetH1_wreq <= (others => '0');
    inputs_rate_wreq <= '0';
    inputs_h_wreq <= '0';
    inputs_offsetFSK_wreq <= (others => '0');
    inputs_offsetAM_wreq <= (others => '0');
    inputs_pulseLengthAM_wreq <= (others => '0');
    inputs_delayComp_wreq <= '0';
    presentLatch_wreq <= '0';
    case wr_adr_d0(11 downto 3) is
    when "000000000" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ipInfo_stdVersion
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg ipInfo_ident
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000000001" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ipInfo_firmwareVersion
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg ipInfo_memMapVersion
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000000010" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ipInfo_echo
        ipInfo_echo_wreq <= wr_req_d0;
        wr_ack <= ipInfo_echo_wack;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000000100" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg control
        control_wreq <= wr_req_d0;
        wr_ack <= control_wack;
      when "1" =>
        -- Reg status
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000010000" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ftw_h1
        ftw_h1_wreq(0) <= wr_req_d0;
        wr_ack <= ftw_h1_wack(0);
      when "1" =>
        -- Reg ftw_h1
        ftw_h1_wreq(1) <= wr_req_d0;
        wr_ack <= ftw_h1_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000010001" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ftw_h1Prog
        ftw_h1Prog_wreq(0) <= wr_req_d0;
        wr_ack <= ftw_h1Prog_wack(0);
      when "1" =>
        -- Reg ftw_h1Prog
        ftw_h1Prog_wreq(1) <= wr_req_d0;
        wr_ack <= ftw_h1Prog_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000010010" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ftw_on
        ftw_on_wreq(0) <= wr_req_d0;
        wr_ack <= ftw_on_wack(0);
      when "1" =>
        -- Reg ftw_on
        ftw_on_wreq(1) <= wr_req_d0;
        wr_ack <= ftw_on_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000010011" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ftw_lo0
        ftw_lo0_wreq(0) <= wr_req_d0;
        wr_ack <= ftw_lo0_wack(0);
      when "1" =>
        -- Reg ftw_lo0
        ftw_lo0_wreq(1) <= wr_req_d0;
        wr_ack <= ftw_lo0_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000010100" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ftw_lo1
        ftw_lo1_wreq(0) <= wr_req_d0;
        wr_ack <= ftw_lo1_wack(0);
      when "1" =>
        -- Reg ftw_lo1
        ftw_lo1_wreq(1) <= wr_req_d0;
        wr_ack <= ftw_lo1_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000010101" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg ftw_slip
        ftw_slip_wreq <= wr_req_d0;
        wr_ack <= ftw_slip_wack;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000100000" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg inputs_offsetH1
        inputs_offsetH1_wreq(0) <= wr_req_d0;
        wr_ack <= inputs_offsetH1_wack(0);
      when "1" =>
        -- Reg inputs_offsetH1
        inputs_offsetH1_wreq(1) <= wr_req_d0;
        wr_ack <= inputs_offsetH1_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000100001" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg inputs_rate
        inputs_rate_wreq <= wr_req_d0;
        wr_ack <= inputs_rate_wack;
      when "1" =>
        -- Reg inputs_h
        inputs_h_wreq <= wr_req_d0;
        wr_ack <= inputs_h_wack;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000100010" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg inputs_offsetFSK
        inputs_offsetFSK_wreq(0) <= wr_req_d0;
        wr_ack <= inputs_offsetFSK_wack(0);
      when "1" =>
        -- Reg inputs_offsetFSK
        inputs_offsetFSK_wreq(1) <= wr_req_d0;
        wr_ack <= inputs_offsetFSK_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000100011" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg inputs_offsetAM
        inputs_offsetAM_wreq(0) <= wr_req_d0;
        wr_ack <= inputs_offsetAM_wack(0);
      when "1" =>
        -- Reg inputs_offsetAM
        inputs_offsetAM_wreq(1) <= wr_req_d0;
        wr_ack <= inputs_offsetAM_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000100100" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg inputs_pulseLengthAM
        inputs_pulseLengthAM_wreq(0) <= wr_req_d0;
        wr_ack <= inputs_pulseLengthAM_wack(0);
      when "1" =>
        -- Reg inputs_pulseLengthAM
        inputs_pulseLengthAM_wreq(1) <= wr_req_d0;
        wr_ack <= inputs_pulseLengthAM_wack(1);
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000100101" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg inputs_delayComp
        inputs_delayComp_wreq <= wr_req_d0;
        wr_ack <= inputs_delayComp_wack;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000110000" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg phases_h1
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg phases_h1
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000110001" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg phases_h1Main
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg phases_h1Main
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000110010" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg phases_h1Slip
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg phases_h1Slip
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000110011" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg phases_if0
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg phases_if0
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "000110100" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg phases_if1
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg phases_if1
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "001000000" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg presentLatch
        presentLatch_wreq <= wr_req_d0;
        wr_ack <= presentLatch_wack;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "001001000" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg readback_coef
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg readback_tw
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when "001001001" =>
      case wr_adr_d0(2 downto 2) is
      when "0" =>
        -- Reg readback_phaseH1Comp
        wr_ack <= wr_req_d0;
      when "1" =>
        -- Reg readback_phaseH1Comp
        wr_ack <= wr_req_d0;
      when others =>
        wr_ack <= wr_req_d0;
      end case;
    when others =>
      wr_ack <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (rd_addr, rd_req, ipInfo_ident_i, ipInfo_firmwareVersion_i,
           ipInfo_memMapVersion_i, ipInfo_echo_echo_reg, control_reset_reg,
           control_selFtwLo0_reg, control_selFtwLo1_reg,
           control_selOffsetH1_reg, control_selOffsetFskH1_reg,
           control_selRate_reg, control_selFtwH1_reg, control_selFtwH1On_reg,
           control_selWrFtwH1_reg, control_selWrDftwH1slip_reg,
           control_selDftwH1slip_reg, control_selFtwH1prog_reg,
           control_slipSign_reg, control_enableFSK_reg, control_enableSlip_reg,
           control_signIF0_reg, control_signIF1_reg,
           control_extResetEnable_reg, control_selLoad_reg,
           control_enableFreqDoubling_reg, control_forceAM_reg,
           status_interlock_i, status_phaseH1Vld_i, status_amAutoOn_i,
           ftw_h1_reg_reg, ftw_h1Prog_reg_reg, ftw_on_reg_reg, ftw_lo0_reg_reg,
           ftw_lo1_reg_reg, ftw_slip_reg, inputs_offsetH1_reg_reg,
           inputs_rate_reg, inputs_h_reg, inputs_offsetFSK_reg_reg,
           inputs_offsetAM_reg_reg, inputs_pulseLengthAM_reg_reg,
           inputs_delayComp_reg, phases_h1_reg_i, phases_h1Main_reg_i,
           phases_h1Slip_reg_i, phases_if0_reg_i, phases_if1_reg_i,
           presentLatch_frev_reg, presentLatch_am_reg, presentLatch_tw_reg,
           presentLatch_coef_reg, presentLatch_load_reg,
           presentLatch_extReset_reg, readback_coef_i, readback_tw_i,
           readback_phaseH1Comp_reg_i) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case rd_addr(11 downto 3) is
    when "000000000" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ipInfo_stdVersion
        rd_ack_d0 <= rd_req;
        rd_dat_d0(7 downto 0) <= "00000000";
        rd_dat_d0(15 downto 8) <= "00000000";
        rd_dat_d0(23 downto 16) <= "00000010";
        rd_dat_d0(31 downto 24) <= (others => '0');
      when "1" =>
        -- Reg ipInfo_ident
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ipInfo_ident_i;
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000000001" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ipInfo_firmwareVersion
        rd_ack_d0 <= rd_req;
        rd_dat_d0(7 downto 0) <= ipInfo_firmwareVersion_i(7 downto 0);
        rd_dat_d0(15 downto 8) <= ipInfo_firmwareVersion_i(15 downto 8);
        rd_dat_d0(23 downto 16) <= ipInfo_firmwareVersion_i(23 downto 16);
        rd_dat_d0(31 downto 24) <= (others => '0');
      when "1" =>
        -- Reg ipInfo_memMapVersion
        rd_ack_d0 <= rd_req;
        rd_dat_d0(7 downto 0) <= ipInfo_memMapVersion_i(7 downto 0);
        rd_dat_d0(15 downto 8) <= ipInfo_memMapVersion_i(15 downto 8);
        rd_dat_d0(23 downto 16) <= ipInfo_memMapVersion_i(23 downto 16);
        rd_dat_d0(31 downto 24) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000000010" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ipInfo_echo
        rd_ack_d0 <= rd_req;
        rd_dat_d0(7 downto 0) <= ipInfo_echo_echo_reg;
        rd_dat_d0(31 downto 8) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000000100" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg control
        rd_ack_d0 <= rd_req;
        rd_dat_d0(0) <= control_reset_reg;
        rd_dat_d0(1) <= '0';
        rd_dat_d0(2) <= control_selFtwLo0_reg;
        rd_dat_d0(3) <= control_selFtwLo1_reg;
        rd_dat_d0(4) <= control_selOffsetH1_reg;
        rd_dat_d0(5) <= control_selOffsetFskH1_reg;
        rd_dat_d0(6) <= control_selRate_reg;
        rd_dat_d0(7) <= control_selFtwH1_reg;
        rd_dat_d0(8) <= control_selFtwH1On_reg;
        rd_dat_d0(9) <= control_selWrFtwH1_reg;
        rd_dat_d0(10) <= control_selWrDftwH1slip_reg;
        rd_dat_d0(11) <= control_selDftwH1slip_reg;
        rd_dat_d0(12) <= control_selFtwH1prog_reg;
        rd_dat_d0(13) <= control_slipSign_reg;
        rd_dat_d0(14) <= control_enableFSK_reg;
        rd_dat_d0(15) <= '0';
        rd_dat_d0(16) <= control_enableSlip_reg;
        rd_dat_d0(17) <= '0';
        rd_dat_d0(18) <= control_signIF0_reg;
        rd_dat_d0(19) <= control_signIF1_reg;
        rd_dat_d0(20) <= control_extResetEnable_reg;
        rd_dat_d0(21) <= '0';
        rd_dat_d0(22) <= control_selLoad_reg;
        rd_dat_d0(23) <= control_enableFreqDoubling_reg;
        rd_dat_d0(24) <= control_forceAM_reg;
        rd_dat_d0(31 downto 25) <= (others => '0');
      when "1" =>
        -- Reg status
        rd_ack_d0 <= rd_req;
        rd_dat_d0(0) <= status_interlock_i;
        rd_dat_d0(2 downto 1) <= (others => '0');
        rd_dat_d0(3) <= status_phaseH1Vld_i;
        rd_dat_d0(5 downto 4) <= (others => '0');
        rd_dat_d0(6) <= status_amAutoOn_i;
        rd_dat_d0(31 downto 7) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000010000" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ftw_h1
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ftw_h1_reg_reg(31 downto 0);
      when "1" =>
        -- Reg ftw_h1
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= ftw_h1_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000010001" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ftw_h1Prog
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ftw_h1Prog_reg_reg(31 downto 0);
      when "1" =>
        -- Reg ftw_h1Prog
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= ftw_h1Prog_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000010010" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ftw_on
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ftw_on_reg_reg(31 downto 0);
      when "1" =>
        -- Reg ftw_on
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= ftw_on_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000010011" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ftw_lo0
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ftw_lo0_reg_reg(31 downto 0);
      when "1" =>
        -- Reg ftw_lo0
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= ftw_lo0_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000010100" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ftw_lo1
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ftw_lo1_reg_reg(31 downto 0);
      when "1" =>
        -- Reg ftw_lo1
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= ftw_lo1_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000010101" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg ftw_slip
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= ftw_slip_reg;
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000100000" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg inputs_offsetH1
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= inputs_offsetH1_reg_reg(31 downto 0);
      when "1" =>
        -- Reg inputs_offsetH1
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= inputs_offsetH1_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000100001" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg inputs_rate
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= inputs_rate_reg;
      when "1" =>
        -- Reg inputs_h
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= inputs_h_reg;
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000100010" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg inputs_offsetFSK
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= inputs_offsetFSK_reg_reg(31 downto 0);
      when "1" =>
        -- Reg inputs_offsetFSK
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= inputs_offsetFSK_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000100011" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg inputs_offsetAM
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= inputs_offsetAM_reg_reg(31 downto 0);
      when "1" =>
        -- Reg inputs_offsetAM
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= inputs_offsetAM_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000100100" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg inputs_pulseLengthAM
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= inputs_pulseLengthAM_reg_reg(31 downto 0);
      when "1" =>
        -- Reg inputs_pulseLengthAM
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= inputs_pulseLengthAM_reg_reg(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000100101" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg inputs_delayComp
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= inputs_delayComp_reg;
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000110000" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg phases_h1
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= phases_h1_reg_i(31 downto 0);
      when "1" =>
        -- Reg phases_h1
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= phases_h1_reg_i(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000110001" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg phases_h1Main
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= phases_h1Main_reg_i(31 downto 0);
      when "1" =>
        -- Reg phases_h1Main
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= phases_h1Main_reg_i(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000110010" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg phases_h1Slip
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= phases_h1Slip_reg_i(31 downto 0);
      when "1" =>
        -- Reg phases_h1Slip
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= phases_h1Slip_reg_i(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000110011" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg phases_if0
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= phases_if0_reg_i(31 downto 0);
      when "1" =>
        -- Reg phases_if0
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= phases_if0_reg_i(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "000110100" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg phases_if1
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= phases_if1_reg_i(31 downto 0);
      when "1" =>
        -- Reg phases_if1
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= phases_if1_reg_i(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "001000000" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg presentLatch
        rd_ack_d0 <= rd_req;
        rd_dat_d0(0) <= presentLatch_frev_reg;
        rd_dat_d0(1) <= presentLatch_am_reg;
        rd_dat_d0(2) <= presentLatch_tw_reg;
        rd_dat_d0(3) <= presentLatch_coef_reg;
        rd_dat_d0(4) <= presentLatch_load_reg;
        rd_dat_d0(5) <= presentLatch_extReset_reg;
        rd_dat_d0(31 downto 6) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "001001000" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg readback_coef
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= readback_coef_i;
      when "1" =>
        -- Reg readback_tw
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= readback_tw_i;
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when "001001001" =>
      case rd_addr(2 downto 2) is
      when "0" =>
        -- Reg readback_phaseH1Comp
        rd_ack_d0 <= rd_req;
        rd_dat_d0 <= readback_phaseH1Comp_reg_i(31 downto 0);
      when "1" =>
        -- Reg readback_phaseH1Comp
        rd_ack_d0 <= rd_req;
        rd_dat_d0(15 downto 0) <= readback_phaseH1Comp_reg_i(47 downto 32);
        rd_dat_d0(31 downto 16) <= (others => '0');
      when others =>
        rd_ack_d0 <= rd_req;
      end case;
    when others =>
      rd_ack_d0 <= rd_req;
    end case;
  end process;
end syn;
