set argv [list --device xc7k160tfbg676-2]
set argc [llength $argv]
source Options/build.tcl

launch_runs synth_1 -jobs 24
wait_on_run synth_1
update_compile_order -fileset sources_1
open_run synth_1 -name synth_1

write_verilog RFNCO.v

set_property target_language VHDL [current_project]
make_wrapper -files [get_files Work/RFNCO.srcs/sources_1/bd/RFNCO/RFNCO.bd] -top

exit
