-- file: rf_oserdes_8to1.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;

library unisim;
use unisim.vcomponents.all;

entity rf_oserdes_8to1 is
generic
 (-- width of the data for the system
  sys_w       : integer := 1;
  -- width of the data for the device
  dev_w       : integer := 8);
port
 (
  -- From the device out to the system
  DATA_OUT_FROM_DEVICE_i    : in    std_logic_vector(dev_w-1 downto 0);
  DATA_OUT_TO_PINS_o        : out   std_logic_vector(sys_w-1 downto 0);

-- Clock and reset signals
  CLK_IN_i                  : in    std_logic;                    -- Single ended Fast clock from IOB
  CLK_DIV_i                 : in    std_logic;                    -- Slow clock output
  serdesstrobe_i            : in    std_logic;
  IO_RESET_i                : in    std_logic);                   -- Reset signal for IO circuit
end rf_oserdes_8to1;

architecture xilinx of rf_oserdes_8to1 is
  attribute CORE_GENERATION_INFO            : string;
  attribute CORE_GENERATION_INFO of xilinx  : architecture is "rf_oserdes_8to1,selectio_wiz_v4_1,{component_name=rf_oserdes_8to1,bus_dir=OUTPUTS,bus_sig_type=SINGLE,bus_io_std=LVCMOS18,use_serialization=true,use_phase_detector=false,serialization_factor=8,enable_bitslip=false,enable_train=false,system_data_width=1,bus_in_delay=NONE,bus_out_delay=NONE,clk_sig_type=SINGLE,clk_io_std=LVCMOS18,clk_buf=BUFIO2,active_edge=RISING,clk_delay=NONE,v6_bus_in_delay=NONE,v6_bus_out_delay=NONE,v6_clk_buf=BUFIO,v6_active_edge=NOT_APP,v6_ddr_alignment=SAME_EDGE_PIPELINED,v6_oddr_alignment=SAME_EDGE,ddr_alignment=C0,v6_interface_type=NETWORKING,interface_type=NETWORKING,v6_bus_in_tap=0,v6_bus_out_tap=0,v6_clk_io_std=LVCMOS18,v6_clk_sig_type=SINGLE}";
  constant clock_enable            : std_logic := '1';
  signal unused : std_logic;
  signal clk_in_int                : std_logic;
  signal clk_div                   : std_logic;
  signal clk_div_int               : std_logic;
  signal clk_in_int_buf            : std_logic;


  -- Before the buffer
  signal data_out_to_pins_int      : std_logic_vector(sys_w-1 downto 0);
  -- Between the delay and serdes
  signal data_out_to_pins_predelay : std_logic_vector(sys_w-1 downto 0);
  constant num_serial_bits         : integer := dev_w/sys_w;
  type serdarr is array (0 to 7) of std_logic_vector(sys_w-1 downto 0);
  -- Array to use intermediately from the serdes to the internal
  --  devices. bus "0" is the leftmost bus
   --  * fills in from higher order
  signal oserdes_d                 : serdarr := (( others => (others => '0')));
  signal serdesstrobe             : std_logic;
  signal ocascade_ms_d            : std_logic_vector(sys_w-1 downto 0);
  signal ocascade_ms_t            : std_logic_vector(sys_w-1 downto 0);
  signal ocascade_sm_d            : std_logic_vector(sys_w-1 downto 0);
  signal ocascade_sm_t            : std_logic_vector(sys_w-1 downto 0);



begin




  -- Create the clock logic
--  ibufg_clk_inst : IBUFG
--    generic map (
--      IOSTANDARD => "LVCMOS18")
--    port map (
--      I          => CLK_IN,
--      O          => clk_in_int);

  -- Set up the clock for use in the serdes
--  bufio2_inst : BUFIO2
--    generic map (
--      DIVIDE_BYPASS => FALSE,
--      I_INVERT      => FALSE,
--      USE_DOUBLER   => FALSE,
--      DIVIDE        => 8)
--    port map (
--      DIVCLK       => clk_div,
--      IOCLK        => clk_in_int_buf,
--      SERDESSTROBE => serdesstrobe,
--      I            => clk_in_int);

   -- Buffer up the divided clock
--   clkdiv_buf_inst : BUFG
--     port map (
--       O => clk_div_int,
--       I => clk_div);

--   CLK_DIV_OUT <= clk_div_int;

   serdesstrobe <= serdesstrobe_i;
  
  -- We have multiple bits- step over every bit, instantiating the required elements
  pins: for pin_count in 0 to sys_w-1 generate 
  begin
    -- Instantiate the buffers
    ----------------------------------
    -- Instantiate a buffer for every bit of the data bus
--     obuf_inst : OBUF
--       generic map (
--         IOSTANDARD => "LVCMOS18")
--       port map (
--         O          => DATA_OUT_TO_PINS    (pin_count),
--         I          => data_out_to_pins_int(pin_count));

     DATA_OUT_TO_PINS_o(pin_count) <= data_out_to_pins_int(pin_count);
    -- Pass through the delay
    -----------------------------------
   data_out_to_pins_int(pin_count)    <= data_out_to_pins_predelay(pin_count);

     -- Instantiate the serdes primitive
     ----------------------------------
     -- declare the oserdes
     oserdes2_master : OSERDES2
       generic map (
         DATA_RATE_OQ   => "SDR",
         DATA_RATE_OT   => "SDR",
         TRAIN_PATTERN  => 0,
         DATA_WIDTH     => 8,
         SERDES_MODE    => "MASTER",
         OUTPUT_MODE    => "SINGLE_ENDED")
       port map (
        D1         => oserdes_d(3)(pin_count),
        D2         => oserdes_d(2)(pin_count),
        D3         => oserdes_d(1)(pin_count),
        D4         => oserdes_d(0)(pin_count),
        T1         => '0',
        T2         => '0',
        T3         => '0',
        T4         => '0',
        SHIFTIN1   => '1',
        SHIFTIN2   => '1',
        SHIFTIN3   => ocascade_sm_d(pin_count),
        SHIFTIN4   => ocascade_sm_t(pin_count),
        SHIFTOUT1  => ocascade_ms_d(pin_count),
        SHIFTOUT2  => ocascade_ms_t(pin_count),
        SHIFTOUT3  => open,
        SHIFTOUT4  => open,
        TRAIN      => '0',
        OCE        => clock_enable,
        CLK0       => clk_in_i,
        CLK1       => '0',
        CLKDIV     => clk_div_i,
        OQ         => data_out_to_pins_predelay(pin_count),
        TQ         => open,
        IOCE       => serdesstrobe,
        TCE        => clock_enable,
        RST        => IO_RESET_i);


     oserdes2_slave : OSERDES2
       generic map (
         DATA_RATE_OQ   => "SDR",
         DATA_RATE_OT   => "SDR",
         DATA_WIDTH     => 8,
         SERDES_MODE    => "SLAVE",
         TRAIN_PATTERN  => 0,
         OUTPUT_MODE    => "SINGLE_ENDED")
       port map (
        D1         => oserdes_d(7)(pin_count),
        D2         => oserdes_d(6)(pin_count),
        D3         => oserdes_d(5)(pin_count),
        D4         => oserdes_d(4)(pin_count),
        T1         => '0',
        T2         => '0',
        T3         => '0',
        T4         => '0',
        SHIFTIN1   => ocascade_ms_d(pin_count),
        SHIFTIN2   => ocascade_ms_t(pin_count),
        SHIFTIN3   => '1',
        SHIFTIN4   => '1',
        SHIFTOUT1  => open,
        SHIFTOUT2  => open,
        SHIFTOUT3  => ocascade_sm_d(pin_count),
        SHIFTOUT4  => ocascade_sm_t(pin_count),
        TRAIN      => '0',
        OCE        => clock_enable,
        CLK0       => clk_in_i,
        CLK1       => '0',
        CLKDIV     => clk_div_i,
        OQ         => open,
        TQ         => open,
        IOCE       => serdesstrobe,
        TCE        => clock_enable,
        RST        => IO_RESET_i);


     -- Concatenate the serdes outputs together. Keep the timesliced
     --   bits together, and placing the earliest bits on the right
     --   ie, if data comes in 0, 1, 2, 3, 4, 5, 6, 7, ...
     --       the output will be 3210, 7654, ...
     -------------------------------------------------------------


    out_slices: for slice_count in 0 to num_serial_bits-1 generate begin
        -- This places the first data in time on the right
        oserdes_d(8-slice_count-1)(0) <=
           DATA_OUT_FROM_DEVICE_i(slice_count);
        -- To place the first data in time on the left, use the
        --   following code, instead
        -- oserdes_d(slice_count) <=
        --    DATA_OUT_FROM_DEVICE(slice_count);
     end generate out_slices;

  end generate pins;





end xilinx;



