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--$Date: 2011/07/18 06:12:03 $
--$RCSfile: example_design_vhd.ejava,v $
--$Revision: 1.3 $
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--   ____  ____ 
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version : 1.05
--  \   \         Application : ILA V1.05a
--  /   /         Filename : example_chipscope_ila.vhd
-- /___/   /\     
-- \   \  /  \ 
--  \___\/\___\
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
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-- Library Declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.vcomponents.all;

--The example module here illustrates how ila core can be instantiated in
--a user design. This helps the user on how various ports selected for the core can be used.

-- Entity Declaration
entity example_chipscope_ila is
  port (
    clk_i : in std_logic
    );
end example_chipscope_ila;

-- Architecture Declaration
architecture ila_arch of example_chipscope_ila is

  ---------------------------------------------------------------------
  --
  --  ICON component declaration
  --
  ---------------------------------------------------------------------

  component chipscope_icon
    port (
      CONTROL0	: inout std_logic_vector(35 downto 0)
      );
  end component;


  ---------------------------------------------------------------------
  -- 
  --  ILA component declaration
  --
  ---------------------------------------------------------------------

  component chipscope_ila
    port (
      CONTROL	: inout std_logic_vector(35 downto 0);
      CLK	:  in  std_logic;
      TRIG0	:  in std_logic_vector(127 downto 0)
      );
  end component;


  ---------------------------------------------------------------------
  --
  --  Shift Reg component declaration
  --
  ---------------------------------------------------------------------
  component shift_reg
    generic (
      WIDTH    : integer := 8
    );
    port (
      clk_in       : in std_logic;
      en_in        : in std_logic;
      en_out       : out std_logic;
      shiftout     : out std_logic_vector(WIDTH-1 downto 0)
      );
  end component;

  -----------------------------------------------------------------------
  --  Constant Declaration
  -----------------------------------------------------------------------
  constant C_NUM_OF_TRIGPORTS   : integer       := 1;
  constant C_TRIG0_SIZE         : integer	:= 128;


  -----------------------------------------------------------------------
  --  Local Signals
  -----------------------------------------------------------------------
  signal clk_o                 : std_logic;
  signal control_0             : std_logic_vector (35 downto 0);
  signal trig_0	: std_logic_vector(C_TRIG0_SIZE-1 downto 0);
  signal en_out_int	: std_logic_vector(C_NUM_OF_TRIGPORTS downto 0) ;


begin
   
  bufg_inst : BUFG
    port map(
      O          => clk_o,
      I          => clk_i
      );
  -------------------------------------------------------------------
  --  For TRIG0
  -------------------------------------------------------------------
  -- This shift register takes enable_in and registers enable_out. Size of 
  -- shift register is given as TRIG0 width. Output of shift register 
  -- is mapped to TRIG0.en_out of this shift_reg instance can be used as
  -- en_in for next shift_reg instance. 

  -- Enabling First shift register
  en_out_int(0) <= '1';

  SHIFT_REG_I_0 : shift_reg
    generic map (
      WIDTH => C_TRIG0_SIZE
      )
    port map (
      clk_in	=> clk_o,
      en_in	=> en_out_int(0),
      en_out	=> en_out_int(1),
      shiftout	=> trig_0
      );



  -------------------------------------------------------------------
  --
  --  If Trigout port is selected
  --
  -------------------------------------------------------------------


  -------------------------------------------------------------------
  --
  --  If Data not same as trigger
  --
  -------------------------------------------------------------------

  -------------------------------------------------------------------
  --
  --  ICON Pro core instance
  --
  -------------------------------------------------------------------
  -- Icon core is instantiated to connect to ILA core.
  ICON_inst : chipscope_icon  
    port map(
      CONTROL0 => control_0 -- INOUT BUS [35:0]
      );


  
  -------------------------------------------------------------------
  --
  --  ILA Pro core instance
  --
  -------------------------------------------------------------------
  -- When this design is run on analyzer, shift operation is observed on each trigger port.
  -- The pulse width is different for any two trigger ports. If Data port is selected, 
  -- Johnson Counter operation can be observed on Data port. If Trig_out port is selected,
  -- shift operation can be viewed on VIO core. 


  ILA_inst : chipscope_ila
    port map (
      CONTROL	=> control_0,	-- INOUT BUS (35:0)
      CLK	=> clk_o,	-- IN
      TRIG0	=> trig_0	-- IN BUS (127:0) 
      );


end ila_arch;

-- Library Declaration
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library UNISIM;
use UNISIM.vcomponents.all;
-- -------------------------------------------------------------------
--   Shift Register module
-- -------------------------------------------------------------------
-- Shift register module is a ring counter logic along with en_in and en_out. 
-- This logic generates walking one pattern of given width when en_in is '1'. 
-- en_out is MSB of the shiftout. Width of shift register is parameterized 
-- and default width is specified as '8'. If the width is '1', toggle pattern is generated.

entity shift_reg is
  generic (
    WIDTH : integer := 8
    );
  port (
    clk_in          : in std_logic;
    en_in        : in std_logic;
    en_out       : out std_logic;
    shiftout     : out std_logic_vector(WIDTH-1 downto 0)
    );
end shift_reg;

architecture bhv of shift_reg is

  signal val        : std_logic_vector(WIDTH-1 downto 0) := (0=>'1', OTHERS=>'0');
  signal en_out_reg : std_logic;
 
  begin 

  shiftout <= val;
  
  -- One shot enable
  en_out <= (val(WIDTH-1) and (not(en_out_reg)));

  -- Ring Counter logic
  RING_CNT_GEN :  if (WIDTH > 1) generate
    begin
      process (clk_in)
      begin
        if (clk_in'event and clk_in='1') then
          if(en_in = '1') then
            val <= (val(WIDTH-2 downto 0) & val(WIDTH-1));
          end if;
        end if;
      end process;
    end generate RING_CNT_GEN;

  -- Toggle logic
  TOGGLE_GEN :  if (WIDTH = 1) generate
    begin
      process (clk_in)
      begin
        if (clk_in'event and clk_in='1') then
          if(en_in = '1') then
            val <= not val;
          end if;
        end if;
      end process;
    end generate TOGGLE_GEN;

 
  -- Registering enable out
  process (clk_in)
  begin
    if (clk_in'event and clk_in='1') then
        en_out_reg <= val(WIDTH-1);
    end if;
  end process;
end bhv;
