#ifndef __CHEBY__RFNCO__H__
#define __CHEBY__RFNCO__H__

#include "ipInfo.h"
#define RFNCO_SIZE 4096 /* 0x1000 = 4KB */
#define RFNCO_MEMMAP_VERSION 0x20000UL
#define RFNCO_IDENT 0x14UL

/* None */
#define RFNCO_IPINFO 0x0UL
#define ADDR_MASK_RFNCO_IPINFO 0xfe0UL
#define RFNCO_IPINFO_SIZE 32 /* 0x20 */

/* control register */
#define RFNCO_CONTROL 0x20UL
#define RFNCO_CONTROL_RESET 0x1UL
#define RFNCO_CONTROL_SOFTLOAD 0x2UL
#define RFNCO_CONTROL_SELFTWLO0 0x4UL
#define RFNCO_CONTROL_SELFTWLO1 0x8UL
#define RFNCO_CONTROL_SELOFFSETH1 0x10UL
#define RFNCO_CONTROL_SELOFFSETFSKH1 0x20UL
#define RFNCO_CONTROL_SELRATE 0x40UL
#define RFNCO_CONTROL_SELFTWH1 0x80UL
#define RFNCO_CONTROL_SELFTWH1ON 0x100UL
#define RFNCO_CONTROL_SELWRFTWH1 0x200UL
#define RFNCO_CONTROL_SELWRDFTWH1SLIP 0x400UL
#define RFNCO_CONTROL_SELDFTWH1SLIP 0x800UL
#define RFNCO_CONTROL_SELFTWH1PROG 0x1000UL
#define RFNCO_CONTROL_SLIPSIGN 0x2000UL
#define RFNCO_CONTROL_ENABLEFSK 0x4000UL
#define RFNCO_CONTROL_RESETFSK 0x8000UL
#define RFNCO_CONTROL_ENABLESLIP 0x10000UL
#define RFNCO_CONTROL_RESETSLIP 0x20000UL
#define RFNCO_CONTROL_SIGNIF0 0x40000UL
#define RFNCO_CONTROL_SIGNIF1 0x80000UL
#define RFNCO_CONTROL_EXTRESETENABLE 0x100000UL
#define RFNCO_CONTROL_LATCHPHASES 0x200000UL
#define RFNCO_CONTROL_SELLOAD 0x400000UL
#define RFNCO_CONTROL_ENABLEFREQDOUBLING 0x800000UL
#define RFNCO_CONTROL_FORCEAM 0x1000000UL

/* status register */
#define RFNCO_STATUS 0x24UL
#define RFNCO_STATUS_INTERLOCK 0x1UL
#define RFNCO_STATUS_PHASEH1VLD 0x8UL
#define RFNCO_STATUS_AMAUTOON 0x40UL

/* Frequency Tuning Words and values loaded at softLoad or hw inputs valid */
#define RFNCO_FTW 0x80UL
#define RFNCO_FTW_SIZE 128 /* 0x80 */

/* Harmonic 1 FTW */
#define RFNCO_FTW_H1 0x80UL
#define RFNCO_FTW_H1_REG_MASK 0xffffffffffffULL
#define RFNCO_FTW_H1_REG_SHIFT 0

/* Harmonic 1 program FTW */
#define RFNCO_FTW_H1PROG 0x88UL
#define RFNCO_FTW_H1PROG_REG_MASK 0xffffffffffffULL
#define RFNCO_FTW_H1PROG_REG_SHIFT 0

/* Cavity on H1 FTW */
#define RFNCO_FTW_ON 0x90UL
#define RFNCO_FTW_ON_REG_MASK 0xffffffffffffULL
#define RFNCO_FTW_ON_REG_SHIFT 0

/* LO 0 FTW */
#define RFNCO_FTW_LO0 0x98UL
#define RFNCO_FTW_LO0_REG_MASK 0xffffffffffffULL
#define RFNCO_FTW_LO0_REG_SHIFT 0

/* LO 1 FTW */
#define RFNCO_FTW_LO1 0xa0UL
#define RFNCO_FTW_LO1_REG_MASK 0xffffffffffffULL
#define RFNCO_FTW_LO1_REG_SHIFT 0

/* slip H1 FTW */
#define RFNCO_FTW_SLIP 0xa8UL

/* None */
#define RFNCO_INPUTS 0x100UL
#define RFNCO_INPUTS_SIZE 64 /* 0x40 */

/* H1 phase offset (Azimuth) */
#define RFNCO_INPUTS_OFFSETH1 0x100UL
#define RFNCO_INPUTS_OFFSETH1_REG_MASK 0xffffffffffffULL
#define RFNCO_INPUTS_OFFSETH1_REG_SHIFT 0

/* FSK rate */
#define RFNCO_INPUTS_RATE 0x108UL

/* Harmonic number */
#define RFNCO_INPUTS_H 0x10cUL

/* offset from Frev for FSK */
#define RFNCO_INPUTS_OFFSETFSK 0x110UL
#define RFNCO_INPUTS_OFFSETFSK_REG_MASK 0xffffffffffffULL
#define RFNCO_INPUTS_OFFSETFSK_REG_SHIFT 0

/* offset from FSK to AM (Amplitude Modulation) */
#define RFNCO_INPUTS_OFFSETAM 0x118UL
#define RFNCO_INPUTS_OFFSETAM_REG_MASK 0xffffffffffffULL
#define RFNCO_INPUTS_OFFSETAM_REG_SHIFT 0

/* pulse length of AM (Amplitude Modulation) */
#define RFNCO_INPUTS_PULSELENGTHAM 0x120UL
#define RFNCO_INPUTS_PULSELENGTHAM_REG_MASK 0xffffffffffffULL
#define RFNCO_INPUTS_PULSELENGTHAM_REG_SHIFT 0

/* fixed delay for phase compensation in sec. */
#define RFNCO_INPUTS_DELAYCOMP 0x128UL

/* Output phases readout */
#define RFNCO_PHASES 0x180UL
#define RFNCO_PHASES_SIZE 128 /* 0x80 */

/* H1 phase with compensation */
#define RFNCO_PHASES_H1 0x180UL
#define RFNCO_PHASES_H1_REG_MASK 0xffffffffffffULL
#define RFNCO_PHASES_H1_REG_SHIFT 0

/* H1 phase direct */
#define RFNCO_PHASES_H1MAIN 0x188UL
#define RFNCO_PHASES_H1MAIN_REG_MASK 0xffffffffffffULL
#define RFNCO_PHASES_H1MAIN_REG_SHIFT 0

/* H1 slippage phase */
#define RFNCO_PHASES_H1SLIP 0x190UL
#define RFNCO_PHASES_H1SLIP_REG_MASK 0xffffffffffffULL
#define RFNCO_PHASES_H1SLIP_REG_SHIFT 0

/* IF0 phase */
#define RFNCO_PHASES_IF0 0x198UL
#define RFNCO_PHASES_IF0_REG_MASK 0xffffffffffffULL
#define RFNCO_PHASES_IF0_REG_SHIFT 0

/* IF1 phase */
#define RFNCO_PHASES_IF1 0x1a0UL
#define RFNCO_PHASES_IF1_REG_MASK 0xffffffffffffULL
#define RFNCO_PHASES_IF1_REG_SHIFT 0

/* latches the presence of pulses */
#define RFNCO_PRESENTLATCH 0x200UL
#define RFNCO_PRESENTLATCH_FREV 0x1UL
#define RFNCO_PRESENTLATCH_AM 0x2UL
#define RFNCO_PRESENTLATCH_TW 0x4UL
#define RFNCO_PRESENTLATCH_COEF 0x8UL
#define RFNCO_PRESENTLATCH_LOAD 0x10UL
#define RFNCO_PRESENTLATCH_EXTRESET 0x20UL

/* readouts from NCO divider */
#define RFNCO_READBACK 0x240UL
#define RFNCO_READBACK_SIZE 64 /* 0x40 */

/* None */
#define RFNCO_READBACK_COEF 0x240UL

/* None */
#define RFNCO_READBACK_TW 0x244UL

/* None */
#define RFNCO_READBACK_PHASEH1COMP 0x248UL
#define RFNCO_READBACK_PHASEH1COMP_REG_MASK 0xffffffffffffULL
#define RFNCO_READBACK_PHASEH1COMP_REG_SHIFT 0

#ifndef __ASSEMBLER__
struct rfnco {
  /* [0x0]: SUBMAP (no description) */
  struct ipInfo ipInfo;

  /* padding to: 8 words */
  uint32_t __padding_0[3];

  /* [0x20]: REG (rw) control register */
  uint32_t control;

  /* [0x24]: REG (ro) status register */
  uint32_t status;

  /* padding to: 32 words */
  uint32_t __padding_1[22];

  /* [0x80]: BLOCK Frequency Tuning Words and values loaded at softLoad or hw inputs valid */
  struct ftw {
    /* [0x0]: REG (rw) Harmonic 1 FTW */
    uint64_t h1;

    /* [0x8]: REG (rw) Harmonic 1 program FTW */
    uint64_t h1Prog;

    /* [0x10]: REG (rw) Cavity on H1 FTW */
    uint64_t on;

    /* [0x18]: REG (rw) LO 0 FTW */
    uint64_t lo0;

    /* [0x20]: REG (rw) LO 1 FTW */
    uint64_t lo1;

    /* [0x28]: REG (rw) slip H1 FTW */
    uint32_t slip;

    /* padding to: 10 words */
    uint32_t __padding_0[21];
  } ftw;

  /* [0x100]: BLOCK (no description) */
  struct inputs {
    /* [0x0]: REG (rw) H1 phase offset (Azimuth) */
    uint64_t offsetH1;

    /* [0x8]: REG (rw) FSK rate */
    uint32_t rate;

    /* [0xc]: REG (rw) Harmonic number */
    uint16_t h;

    /* padding to: 16 words */
    uint8_t __padding_0[2];

    /* [0x10]: REG (rw) offset from Frev for FSK */
    uint64_t offsetFSK;

    /* [0x18]: REG (rw) offset from FSK to AM (Amplitude Modulation) */
    uint64_t offsetAM;

    /* [0x20]: REG (rw) pulse length of AM (Amplitude Modulation) */
    uint64_t pulseLengthAM;

    /* [0x28]: REG (rw) fixed delay for phase compensation in sec. */
    uint32_t delayComp;

    /* padding to: 10 words */
    uint32_t __padding_1[5];
  } inputs;

  /* padding to: 96 words */
  uint32_t __padding_2[16];

  /* [0x180]: BLOCK Output phases readout */
  struct phases {
    /* [0x0]: REG (ro) H1 phase with compensation */
    uint64_t h1;

    /* [0x8]: REG (ro) H1 phase direct */
    uint64_t h1Main;

    /* [0x10]: REG (ro) H1 slippage phase */
    uint64_t h1Slip;

    /* [0x18]: REG (ro) IF0 phase */
    uint64_t if0;

    /* [0x20]: REG (ro) IF1 phase */
    uint64_t if1;

    /* padding to: 8 words */
    uint32_t __padding_0[22];
  } phases;

  /* [0x200]: REG (rw) latches the presence of pulses */
  uint32_t presentLatch;

  /* padding to: 144 words */
  uint32_t __padding_3[15];

  /* [0x240]: BLOCK readouts from NCO divider */
  struct readback {
    /* [0x0]: REG (ro) (no description) */
    uint32_t coef;

    /* [0x4]: REG (ro) (no description) */
    uint32_t tw;

    /* [0x8]: REG (ro) (no description) */
    uint64_t phaseH1Comp;

    /* padding to: 2 words */
    uint32_t __padding_0[12];
  } readback;

  /* padding to: 144 words */
  uint32_t __padding_4[864];
};
#endif /* !__ASSEMBLER__*/

#endif /* __CHEBY__RFNCO__H__ */
