--Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
--Date        : Thu May 11 08:57:38 2023
--Host        : cispace running 64-bit Ubuntu 22.04.2 LTS
--Command     : generate_target RFNCO_wrapper.bd
--Design      : RFNCO_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity RFNCO_wrapper is
  port (
    AM_auto_on_o : out STD_LOGIC;
    AM_o : out STD_LOGIC;
    FTW_H1_on_muxed_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    FTW_H1_on_muxed_vld_o : out STD_LOGIC;
    aximm_i_araddr : in STD_LOGIC_VECTOR ( 11 downto 0 );
    aximm_i_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    aximm_i_arready : out STD_LOGIC;
    aximm_i_arvalid : in STD_LOGIC;
    aximm_i_awaddr : in STD_LOGIC_VECTOR ( 11 downto 0 );
    aximm_i_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    aximm_i_awready : out STD_LOGIC;
    aximm_i_awvalid : in STD_LOGIC;
    aximm_i_bready : in STD_LOGIC;
    aximm_i_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aximm_i_bvalid : out STD_LOGIC;
    aximm_i_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    aximm_i_rready : in STD_LOGIC;
    aximm_i_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aximm_i_rvalid : out STD_LOGIC;
    aximm_i_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    aximm_i_wready : out STD_LOGIC;
    aximm_i_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    aximm_i_wvalid : in STD_LOGIC;
    clk_i : in STD_LOGIC;
    coef_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    coef_vld_o : out STD_LOGIC;
    cos_IF0_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    cos_IF1_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    ext_reset_enable_o : out STD_LOGIC;
    ext_reset_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    frev_main_o : out STD_LOGIC;
    frev_o : out STD_LOGIC;
    ftw_H1_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_H1_on_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_LO_0_i : in STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_LO_1_i : in STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_valid_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    interlock_o : out STD_LOGIC;
    offset_FSK_i_0 : in STD_LOGIC_VECTOR ( 47 downto 0 );
    offset_i_0 : in STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_comp_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_main_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_offset_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_prog_offset_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_slip_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_IF0_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_IF1_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    rst_i : in STD_LOGIC;
    sin_IF0_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sin_IF1_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sincos_vld_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    tw_H1_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    wr_rf_frame_bus_i_dftw_h1_slip0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    wr_rf_frame_bus_i_dftw_h1_slip1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    wr_rf_frame_bus_i_ftw_h1_main : in STD_LOGIC_VECTOR ( 47 downto 0 );
    wr_rf_frame_bus_i_ftw_h1_on : in STD_LOGIC_VECTOR ( 47 downto 0 );
    wr_rf_frame_bus_i_ftw_h1_prog : in STD_LOGIC_VECTOR ( 47 downto 0 );
    wr_rf_frame_bus_i_inputs_valid : in STD_LOGIC;
    wr_rf_frame_bus_i_rate : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wr_rf_frame_bus_i_reset_fsk : in STD_LOGIC;
    wr_rf_frame_bus_i_reset_nco : in STD_LOGIC;
    wr_rf_frame_bus_i_reset_slip : in STD_LOGIC
  );
end RFNCO_wrapper;

architecture STRUCTURE of RFNCO_wrapper is
  component RFNCO is
  port (
    AM_auto_on_o : out STD_LOGIC;
    AM_o : out STD_LOGIC;
    FTW_H1_on_muxed_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    FTW_H1_on_muxed_vld_o : out STD_LOGIC;
    clk_i : in STD_LOGIC;
    coef_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    coef_vld_o : out STD_LOGIC;
    cos_IF0_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    cos_IF1_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    ext_reset_enable_o : out STD_LOGIC;
    ext_reset_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    frev_main_o : out STD_LOGIC;
    frev_o : out STD_LOGIC;
    ftw_H1_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_H1_on_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_LO_0_i : in STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_LO_1_i : in STD_LOGIC_VECTOR ( 47 downto 0 );
    ftw_valid_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    interlock_o : out STD_LOGIC;
    offset_FSK_i_0 : in STD_LOGIC_VECTOR ( 47 downto 0 );
    offset_i_0 : in STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_comp_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_main_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_offset_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_prog_offset_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_H1_slip_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_IF0_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    phase_IF1_o : out STD_LOGIC_VECTOR ( 47 downto 0 );
    rst_i : in STD_LOGIC;
    sin_IF0_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sin_IF1_o : out STD_LOGIC_VECTOR ( 24 downto 0 );
    sincos_vld_o : out STD_LOGIC_VECTOR ( 0 to 0 );
    tw_H1_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    aximm_i_awaddr : in STD_LOGIC_VECTOR ( 11 downto 0 );
    aximm_i_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    aximm_i_awvalid : in STD_LOGIC;
    aximm_i_awready : out STD_LOGIC;
    aximm_i_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
    aximm_i_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
    aximm_i_wvalid : in STD_LOGIC;
    aximm_i_wready : out STD_LOGIC;
    aximm_i_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aximm_i_bvalid : out STD_LOGIC;
    aximm_i_bready : in STD_LOGIC;
    aximm_i_araddr : in STD_LOGIC_VECTOR ( 11 downto 0 );
    aximm_i_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
    aximm_i_arvalid : in STD_LOGIC;
    aximm_i_arready : out STD_LOGIC;
    aximm_i_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
    aximm_i_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    aximm_i_rvalid : out STD_LOGIC;
    aximm_i_rready : in STD_LOGIC;
    wr_rf_frame_bus_i_ftw_h1_main : in STD_LOGIC_VECTOR ( 47 downto 0 );
    wr_rf_frame_bus_i_ftw_h1_prog : in STD_LOGIC_VECTOR ( 47 downto 0 );
    wr_rf_frame_bus_i_ftw_h1_on : in STD_LOGIC_VECTOR ( 47 downto 0 );
    wr_rf_frame_bus_i_rate : in STD_LOGIC_VECTOR ( 2 downto 0 );
    wr_rf_frame_bus_i_dftw_h1_slip0 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    wr_rf_frame_bus_i_dftw_h1_slip1 : in STD_LOGIC_VECTOR ( 31 downto 0 );
    wr_rf_frame_bus_i_inputs_valid : in STD_LOGIC;
    wr_rf_frame_bus_i_reset_nco : in STD_LOGIC;
    wr_rf_frame_bus_i_reset_slip : in STD_LOGIC;
    wr_rf_frame_bus_i_reset_fsk : in STD_LOGIC
  );
  end component RFNCO;
begin
RFNCO_i: component RFNCO
     port map (
      AM_auto_on_o => AM_auto_on_o,
      AM_o => AM_o,
      FTW_H1_on_muxed_o(47 downto 0) => FTW_H1_on_muxed_o(47 downto 0),
      FTW_H1_on_muxed_vld_o => FTW_H1_on_muxed_vld_o,
      aximm_i_araddr(11 downto 0) => aximm_i_araddr(11 downto 0),
      aximm_i_arprot(2 downto 0) => aximm_i_arprot(2 downto 0),
      aximm_i_arready => aximm_i_arready,
      aximm_i_arvalid => aximm_i_arvalid,
      aximm_i_awaddr(11 downto 0) => aximm_i_awaddr(11 downto 0),
      aximm_i_awprot(2 downto 0) => aximm_i_awprot(2 downto 0),
      aximm_i_awready => aximm_i_awready,
      aximm_i_awvalid => aximm_i_awvalid,
      aximm_i_bready => aximm_i_bready,
      aximm_i_bresp(1 downto 0) => aximm_i_bresp(1 downto 0),
      aximm_i_bvalid => aximm_i_bvalid,
      aximm_i_rdata(31 downto 0) => aximm_i_rdata(31 downto 0),
      aximm_i_rready => aximm_i_rready,
      aximm_i_rresp(1 downto 0) => aximm_i_rresp(1 downto 0),
      aximm_i_rvalid => aximm_i_rvalid,
      aximm_i_wdata(31 downto 0) => aximm_i_wdata(31 downto 0),
      aximm_i_wready => aximm_i_wready,
      aximm_i_wstrb(3 downto 0) => aximm_i_wstrb(3 downto 0),
      aximm_i_wvalid => aximm_i_wvalid,
      clk_i => clk_i,
      coef_o(31 downto 0) => coef_o(31 downto 0),
      coef_vld_o => coef_vld_o,
      cos_IF0_o(24 downto 0) => cos_IF0_o(24 downto 0),
      cos_IF1_o(24 downto 0) => cos_IF1_o(24 downto 0),
      ext_reset_enable_o => ext_reset_enable_o,
      ext_reset_o(0) => ext_reset_o(0),
      frev_main_o => frev_main_o,
      frev_o => frev_o,
      ftw_H1_o(47 downto 0) => ftw_H1_o(47 downto 0),
      ftw_H1_on_o(47 downto 0) => ftw_H1_on_o(47 downto 0),
      ftw_LO_0_i(47 downto 0) => ftw_LO_0_i(47 downto 0),
      ftw_LO_1_i(47 downto 0) => ftw_LO_1_i(47 downto 0),
      ftw_valid_o(0) => ftw_valid_o(0),
      interlock_o => interlock_o,
      offset_FSK_i_0(47 downto 0) => offset_FSK_i_0(47 downto 0),
      offset_i_0(47 downto 0) => offset_i_0(47 downto 0),
      phase_H1_comp_o(47 downto 0) => phase_H1_comp_o(47 downto 0),
      phase_H1_main_o(47 downto 0) => phase_H1_main_o(47 downto 0),
      phase_H1_o(47 downto 0) => phase_H1_o(47 downto 0),
      phase_H1_offset_o(47 downto 0) => phase_H1_offset_o(47 downto 0),
      phase_H1_prog_offset_o(47 downto 0) => phase_H1_prog_offset_o(47 downto 0),
      phase_H1_slip_o(47 downto 0) => phase_H1_slip_o(47 downto 0),
      phase_IF0_o(47 downto 0) => phase_IF0_o(47 downto 0),
      phase_IF1_o(47 downto 0) => phase_IF1_o(47 downto 0),
      rst_i => rst_i,
      sin_IF0_o(24 downto 0) => sin_IF0_o(24 downto 0),
      sin_IF1_o(24 downto 0) => sin_IF1_o(24 downto 0),
      sincos_vld_o(0) => sincos_vld_o(0),
      tw_H1_o(31 downto 0) => tw_H1_o(31 downto 0),
      wr_rf_frame_bus_i_dftw_h1_slip0(31 downto 0) => wr_rf_frame_bus_i_dftw_h1_slip0(31 downto 0),
      wr_rf_frame_bus_i_dftw_h1_slip1(31 downto 0) => wr_rf_frame_bus_i_dftw_h1_slip1(31 downto 0),
      wr_rf_frame_bus_i_ftw_h1_main(47 downto 0) => wr_rf_frame_bus_i_ftw_h1_main(47 downto 0),
      wr_rf_frame_bus_i_ftw_h1_on(47 downto 0) => wr_rf_frame_bus_i_ftw_h1_on(47 downto 0),
      wr_rf_frame_bus_i_ftw_h1_prog(47 downto 0) => wr_rf_frame_bus_i_ftw_h1_prog(47 downto 0),
      wr_rf_frame_bus_i_inputs_valid => wr_rf_frame_bus_i_inputs_valid,
      wr_rf_frame_bus_i_rate(2 downto 0) => wr_rf_frame_bus_i_rate(2 downto 0),
      wr_rf_frame_bus_i_reset_fsk => wr_rf_frame_bus_i_reset_fsk,
      wr_rf_frame_bus_i_reset_nco => wr_rf_frame_bus_i_reset_nco,
      wr_rf_frame_bus_i_reset_slip => wr_rf_frame_bus_i_reset_slip
    );
end STRUCTURE;
