files = ['wr2rf_vme.vhd',
         ('debug/chipscope_icon.ngc','chipscope_icon'),
         ('debug/chipscope_ila.ngc','chipscope_ila'),
         ('debug/dds_compiler_v5_0.ngc','wrapped_dds_compiler_v5_0'),
         'debug/dds_compiler_v5_0.vhd' ]
fetchto = "../../../dependencies"
modules = {'local': [ '../../rtl', 
                      '../../rtl/registers', 
                      '../../rtl/rfnco', 
                      '../../rtl/noniqmodinterp2fir' ],
           'system': ['xilinx'],
           'git': [ "git://ohwr.org/project/general-cores.git",
                    "git://ohwr.org/project/vme64x-core.git",
                    "git://ohwr.org/project/wr-cores.git",
                    "git://ohwr.org/project/urv-core.git",
                    "https://gitlab.cern.ch/BE-RF-PLDesign/Libraries/xilinx/RFFrameTransceiver.git"] }
