-- Do not edit.  Generated by cheby 1.6.dev0 using these options:
--  -i wr2rf_init_rf_regs.cheby --gen-hdl wr2rf_init_rf_regs.vhd
-- Generated on Wed May 10 11:16:39 2023 by tgingold


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;

entity wr2rf_init_rf_regs is
  port (
    rst_n_i              : in    std_logic;
    clk_i                : in    std_logic;
    wb_i                 : in    t_wishbone_slave_in;
    wb_o                 : out   t_wishbone_slave_out;

    -- Sets the rf trigger unit delay value
    rf_trigger_ff_delay_o : out   std_logic_vector(15 downto 0);

    -- Control register for both channels
    rf1_common_mixer_en_o : out   std_logic;
    rf1_common_mux_sel_o : out   std_logic_vector(1 downto 0);
    rf1_common_iqdac_reset_o : out   std_logic;
    -- Enable internal loopback (e.g. frev) into rf_start signals for the trigger unit
    rf1_common_start_lpbk_o : out   std_logic;

    -- Determines for how many sys-cycles (16 ns) cdelay, and slipped by fdelay (1 ns) the nco_reset will be delayed before reaching the primary trigger unit.
    rf1_t1_sync_progdelay_cdelay_o : out   std_logic_vector(6 downto 0);
    rf1_t1_sync_progdelay_fdelay_o : out   std_logic_vector(3 downto 0);
    rf1_t1_sync_progdelay_odelay_o : out   std_logic_vector(4 downto 0);

    -- How many sys-cycles is the rst applied less than cdelay
    rf1_rst_cdelay_offset_o : out   std_logic_vector(6 downto 0);

    -- REG csr
    rf1_ch_0_csr_delay_oen_o : out   std_logic;
    -- Select between the delayed output (=0) or the delayed and shaped output (=1)
    rf1_ch_0_csr_mux_sel_o : out   std_logic;
    rf1_ch_0_csr_trig_rst_o : out   std_logic;
    -- A 0->1 transition latches the rf_trigger_delay value
    rf1_ch_0_csr_delay_latch_o : out   std_logic;

    -- REG csr
    rf1_ch_1_csr_delay_oen_o : out   std_logic;
    -- Select between the delayed output (=0) or the delayed and shaped output (=1)
    rf1_ch_1_csr_mux_sel_o : out   std_logic;
    rf1_ch_1_csr_trig_rst_o : out   std_logic;
    -- A 0->1 transition latches the rf_trigger_delay value
    rf1_ch_1_csr_delay_latch_o : out   std_logic;

    -- Control register for both channels
    rf2_common_mixer_en_o : out   std_logic;
    rf2_common_mux_sel_o : out   std_logic_vector(1 downto 0);
    rf2_common_iqdac_reset_o : out   std_logic;
    -- Enable internal loopback (e.g. frev) into rf_start signals for the trigger unit
    rf2_common_start_lpbk_o : out   std_logic;

    -- Determines for how many sys-cycles (16 ns) cdelay, and slipped by fdelay (1 ns) the nco_reset will be delayed before reaching the primary trigger unit.
    rf2_t1_sync_progdelay_cdelay_o : out   std_logic_vector(6 downto 0);
    rf2_t1_sync_progdelay_fdelay_o : out   std_logic_vector(3 downto 0);
    rf2_t1_sync_progdelay_odelay_o : out   std_logic_vector(4 downto 0);

    -- How many sys-cycles is the rst applied less than cdelay
    rf2_rst_cdelay_offset_o : out   std_logic_vector(6 downto 0);

    -- REG csr
    rf2_ch_0_csr_delay_oen_o : out   std_logic;
    -- Select between the delayed output (=0) or the delayed and shaped output (=1)
    rf2_ch_0_csr_mux_sel_o : out   std_logic;
    rf2_ch_0_csr_trig_rst_o : out   std_logic;
    -- A 0->1 transition latches the rf_trigger_delay value
    rf2_ch_0_csr_delay_latch_o : out   std_logic;

    -- REG csr
    rf2_ch_1_csr_delay_oen_o : out   std_logic;
    -- Select between the delayed output (=0) or the delayed and shaped output (=1)
    rf2_ch_1_csr_mux_sel_o : out   std_logic;
    rf2_ch_1_csr_trig_rst_o : out   std_logic;
    -- A 0->1 transition latches the rf_trigger_delay value
    rf2_ch_1_csr_delay_latch_o : out   std_logic
  );
end wr2rf_init_rf_regs;

architecture syn of wr2rf_init_rf_regs is
  signal adr_int                        : std_logic_vector(5 downto 1);
  signal rd_req_int                     : std_logic;
  signal wr_req_int                     : std_logic;
  signal rd_ack_int                     : std_logic;
  signal wr_ack_int                     : std_logic;
  signal wb_en                          : std_logic;
  signal ack_int                        : std_logic;
  signal wb_rip                         : std_logic;
  signal wb_wip                         : std_logic;
  signal rf_trigger_ff_delay_reg        : std_logic_vector(15 downto 0);
  signal rf_trigger_ff_delay_wreq       : std_logic;
  signal rf_trigger_ff_delay_wack       : std_logic;
  signal rf1_common_mixer_en_reg        : std_logic;
  signal rf1_common_mux_sel_reg         : std_logic_vector(1 downto 0);
  signal rf1_common_iqdac_reset_reg     : std_logic;
  signal rf1_common_start_lpbk_reg      : std_logic;
  signal rf1_common_wreq                : std_logic;
  signal rf1_common_wack                : std_logic;
  signal rf1_t1_sync_progdelay_cdelay_reg : std_logic_vector(6 downto 0);
  signal rf1_t1_sync_progdelay_fdelay_reg : std_logic_vector(3 downto 0);
  signal rf1_t1_sync_progdelay_odelay_reg : std_logic_vector(4 downto 0);
  signal rf1_t1_sync_progdelay_wreq     : std_logic;
  signal rf1_t1_sync_progdelay_wack     : std_logic;
  signal rf1_rst_cdelay_offset_reg      : std_logic_vector(6 downto 0);
  signal rf1_rst_cdelay_wreq            : std_logic;
  signal rf1_rst_cdelay_wack            : std_logic;
  signal rf1_ch_0_csr_delay_oen_reg     : std_logic;
  signal rf1_ch_0_csr_mux_sel_reg       : std_logic;
  signal rf1_ch_0_csr_trig_rst_reg      : std_logic;
  signal rf1_ch_0_csr_delay_latch_reg   : std_logic;
  signal rf1_ch_0_csr_wreq              : std_logic;
  signal rf1_ch_0_csr_wack              : std_logic;
  signal rf1_ch_1_csr_delay_oen_reg     : std_logic;
  signal rf1_ch_1_csr_mux_sel_reg       : std_logic;
  signal rf1_ch_1_csr_trig_rst_reg      : std_logic;
  signal rf1_ch_1_csr_delay_latch_reg   : std_logic;
  signal rf1_ch_1_csr_wreq              : std_logic;
  signal rf1_ch_1_csr_wack              : std_logic;
  signal rf2_common_mixer_en_reg        : std_logic;
  signal rf2_common_mux_sel_reg         : std_logic_vector(1 downto 0);
  signal rf2_common_iqdac_reset_reg     : std_logic;
  signal rf2_common_start_lpbk_reg      : std_logic;
  signal rf2_common_wreq                : std_logic;
  signal rf2_common_wack                : std_logic;
  signal rf2_t1_sync_progdelay_cdelay_reg : std_logic_vector(6 downto 0);
  signal rf2_t1_sync_progdelay_fdelay_reg : std_logic_vector(3 downto 0);
  signal rf2_t1_sync_progdelay_odelay_reg : std_logic_vector(4 downto 0);
  signal rf2_t1_sync_progdelay_wreq     : std_logic;
  signal rf2_t1_sync_progdelay_wack     : std_logic;
  signal rf2_rst_cdelay_offset_reg      : std_logic_vector(6 downto 0);
  signal rf2_rst_cdelay_wreq            : std_logic;
  signal rf2_rst_cdelay_wack            : std_logic;
  signal rf2_ch_0_csr_delay_oen_reg     : std_logic;
  signal rf2_ch_0_csr_mux_sel_reg       : std_logic;
  signal rf2_ch_0_csr_trig_rst_reg      : std_logic;
  signal rf2_ch_0_csr_delay_latch_reg   : std_logic;
  signal rf2_ch_0_csr_wreq              : std_logic;
  signal rf2_ch_0_csr_wack              : std_logic;
  signal rf2_ch_1_csr_delay_oen_reg     : std_logic;
  signal rf2_ch_1_csr_mux_sel_reg       : std_logic;
  signal rf2_ch_1_csr_trig_rst_reg      : std_logic;
  signal rf2_ch_1_csr_delay_latch_reg   : std_logic;
  signal rf2_ch_1_csr_wreq              : std_logic;
  signal rf2_ch_1_csr_wack              : std_logic;
  signal rd_ack_d0                      : std_logic;
  signal rd_dat_d0                      : std_logic_vector(15 downto 0);
  signal wr_req_d0                      : std_logic;
  signal wr_adr_d0                      : std_logic_vector(5 downto 1);
  signal wr_dat_d0                      : std_logic_vector(15 downto 0);
begin

  -- WB decode signals
  adr_int <= wb_i.adr(5 downto 1);
  wb_en <= wb_i.cyc and wb_i.stb;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_rip <= '0';
      else
        wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
      end if;
    end if;
  end process;
  rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;

  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        wb_wip <= '0';
      else
        wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
      end if;
    end if;
  end process;
  wr_req_int <= (wb_en and wb_i.we) and not wb_wip;

  ack_int <= rd_ack_int or wr_ack_int;
  wb_o.ack <= ack_int;
  wb_o.stall <= not ack_int and wb_en;
  wb_o.rty <= '0';
  wb_o.err <= '0';

  -- pipelining for wr-in+rd-out
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rd_ack_int <= '0';
        wr_req_d0 <= '0';
      else
        rd_ack_int <= rd_ack_d0;
        wb_o.dat(15 downto 0) <= rd_dat_d0;
        wr_req_d0 <= wr_req_int;
        wr_adr_d0 <= adr_int;
        wr_dat_d0 <= wb_i.dat(15 downto 0);
      end if;
    end if;
  end process;

  -- Register rf_trigger_ff_delay
  rf_trigger_ff_delay_o <= rf_trigger_ff_delay_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf_trigger_ff_delay_reg <= "0000000000000000";
        rf_trigger_ff_delay_wack <= '0';
      else
        if rf_trigger_ff_delay_wreq = '1' then
          rf_trigger_ff_delay_reg <= wr_dat_d0;
        end if;
        rf_trigger_ff_delay_wack <= rf_trigger_ff_delay_wreq;
      end if;
    end if;
  end process;

  -- Register rf1_common
  rf1_common_mixer_en_o <= rf1_common_mixer_en_reg;
  rf1_common_mux_sel_o <= rf1_common_mux_sel_reg;
  rf1_common_iqdac_reset_o <= rf1_common_iqdac_reset_reg;
  rf1_common_start_lpbk_o <= rf1_common_start_lpbk_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf1_common_mixer_en_reg <= '0';
        rf1_common_mux_sel_reg <= "00";
        rf1_common_iqdac_reset_reg <= '0';
        rf1_common_start_lpbk_reg <= '0';
        rf1_common_wack <= '0';
      else
        if rf1_common_wreq = '1' then
          rf1_common_mixer_en_reg <= wr_dat_d0(0);
          rf1_common_mux_sel_reg <= wr_dat_d0(2 downto 1);
          rf1_common_iqdac_reset_reg <= wr_dat_d0(3);
          rf1_common_start_lpbk_reg <= wr_dat_d0(4);
        end if;
        rf1_common_wack <= rf1_common_wreq;
      end if;
    end if;
  end process;

  -- Register rf1_t1_sync_progdelay
  rf1_t1_sync_progdelay_cdelay_o <= rf1_t1_sync_progdelay_cdelay_reg;
  rf1_t1_sync_progdelay_fdelay_o <= rf1_t1_sync_progdelay_fdelay_reg;
  rf1_t1_sync_progdelay_odelay_o <= rf1_t1_sync_progdelay_odelay_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf1_t1_sync_progdelay_cdelay_reg <= "1001011";
        rf1_t1_sync_progdelay_fdelay_reg <= "0000";
        rf1_t1_sync_progdelay_odelay_reg <= "00000";
        rf1_t1_sync_progdelay_wack <= '0';
      else
        if rf1_t1_sync_progdelay_wreq = '1' then
          rf1_t1_sync_progdelay_cdelay_reg <= wr_dat_d0(6 downto 0);
          rf1_t1_sync_progdelay_fdelay_reg <= wr_dat_d0(10 downto 7);
          rf1_t1_sync_progdelay_odelay_reg <= wr_dat_d0(15 downto 11);
        end if;
        rf1_t1_sync_progdelay_wack <= rf1_t1_sync_progdelay_wreq;
      end if;
    end if;
  end process;

  -- Register rf1_rst_cdelay
  rf1_rst_cdelay_offset_o <= rf1_rst_cdelay_offset_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf1_rst_cdelay_offset_reg <= "0001000";
        rf1_rst_cdelay_wack <= '0';
      else
        if rf1_rst_cdelay_wreq = '1' then
          rf1_rst_cdelay_offset_reg <= wr_dat_d0(6 downto 0);
        end if;
        rf1_rst_cdelay_wack <= rf1_rst_cdelay_wreq;
      end if;
    end if;
  end process;

  -- Register rf1_ch_0_csr
  rf1_ch_0_csr_delay_oen_o <= rf1_ch_0_csr_delay_oen_reg;
  rf1_ch_0_csr_mux_sel_o <= rf1_ch_0_csr_mux_sel_reg;
  rf1_ch_0_csr_trig_rst_o <= rf1_ch_0_csr_trig_rst_reg;
  rf1_ch_0_csr_delay_latch_o <= rf1_ch_0_csr_delay_latch_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf1_ch_0_csr_delay_oen_reg <= '0';
        rf1_ch_0_csr_mux_sel_reg <= '0';
        rf1_ch_0_csr_trig_rst_reg <= '1';
        rf1_ch_0_csr_delay_latch_reg <= '1';
        rf1_ch_0_csr_wack <= '0';
      else
        if rf1_ch_0_csr_wreq = '1' then
          rf1_ch_0_csr_delay_oen_reg <= wr_dat_d0(0);
          rf1_ch_0_csr_mux_sel_reg <= wr_dat_d0(1);
          rf1_ch_0_csr_trig_rst_reg <= wr_dat_d0(2);
          rf1_ch_0_csr_delay_latch_reg <= wr_dat_d0(3);
        end if;
        rf1_ch_0_csr_wack <= rf1_ch_0_csr_wreq;
      end if;
    end if;
  end process;

  -- Register rf1_ch_1_csr
  rf1_ch_1_csr_delay_oen_o <= rf1_ch_1_csr_delay_oen_reg;
  rf1_ch_1_csr_mux_sel_o <= rf1_ch_1_csr_mux_sel_reg;
  rf1_ch_1_csr_trig_rst_o <= rf1_ch_1_csr_trig_rst_reg;
  rf1_ch_1_csr_delay_latch_o <= rf1_ch_1_csr_delay_latch_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf1_ch_1_csr_delay_oen_reg <= '0';
        rf1_ch_1_csr_mux_sel_reg <= '0';
        rf1_ch_1_csr_trig_rst_reg <= '1';
        rf1_ch_1_csr_delay_latch_reg <= '1';
        rf1_ch_1_csr_wack <= '0';
      else
        if rf1_ch_1_csr_wreq = '1' then
          rf1_ch_1_csr_delay_oen_reg <= wr_dat_d0(0);
          rf1_ch_1_csr_mux_sel_reg <= wr_dat_d0(1);
          rf1_ch_1_csr_trig_rst_reg <= wr_dat_d0(2);
          rf1_ch_1_csr_delay_latch_reg <= wr_dat_d0(3);
        end if;
        rf1_ch_1_csr_wack <= rf1_ch_1_csr_wreq;
      end if;
    end if;
  end process;

  -- Register rf2_common
  rf2_common_mixer_en_o <= rf2_common_mixer_en_reg;
  rf2_common_mux_sel_o <= rf2_common_mux_sel_reg;
  rf2_common_iqdac_reset_o <= rf2_common_iqdac_reset_reg;
  rf2_common_start_lpbk_o <= rf2_common_start_lpbk_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf2_common_mixer_en_reg <= '0';
        rf2_common_mux_sel_reg <= "00";
        rf2_common_iqdac_reset_reg <= '0';
        rf2_common_start_lpbk_reg <= '0';
        rf2_common_wack <= '0';
      else
        if rf2_common_wreq = '1' then
          rf2_common_mixer_en_reg <= wr_dat_d0(0);
          rf2_common_mux_sel_reg <= wr_dat_d0(2 downto 1);
          rf2_common_iqdac_reset_reg <= wr_dat_d0(3);
          rf2_common_start_lpbk_reg <= wr_dat_d0(4);
        end if;
        rf2_common_wack <= rf2_common_wreq;
      end if;
    end if;
  end process;

  -- Register rf2_t1_sync_progdelay
  rf2_t1_sync_progdelay_cdelay_o <= rf2_t1_sync_progdelay_cdelay_reg;
  rf2_t1_sync_progdelay_fdelay_o <= rf2_t1_sync_progdelay_fdelay_reg;
  rf2_t1_sync_progdelay_odelay_o <= rf2_t1_sync_progdelay_odelay_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf2_t1_sync_progdelay_cdelay_reg <= "1001011";
        rf2_t1_sync_progdelay_fdelay_reg <= "0000";
        rf2_t1_sync_progdelay_odelay_reg <= "00000";
        rf2_t1_sync_progdelay_wack <= '0';
      else
        if rf2_t1_sync_progdelay_wreq = '1' then
          rf2_t1_sync_progdelay_cdelay_reg <= wr_dat_d0(6 downto 0);
          rf2_t1_sync_progdelay_fdelay_reg <= wr_dat_d0(10 downto 7);
          rf2_t1_sync_progdelay_odelay_reg <= wr_dat_d0(15 downto 11);
        end if;
        rf2_t1_sync_progdelay_wack <= rf2_t1_sync_progdelay_wreq;
      end if;
    end if;
  end process;

  -- Register rf2_rst_cdelay
  rf2_rst_cdelay_offset_o <= rf2_rst_cdelay_offset_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf2_rst_cdelay_offset_reg <= "0001000";
        rf2_rst_cdelay_wack <= '0';
      else
        if rf2_rst_cdelay_wreq = '1' then
          rf2_rst_cdelay_offset_reg <= wr_dat_d0(6 downto 0);
        end if;
        rf2_rst_cdelay_wack <= rf2_rst_cdelay_wreq;
      end if;
    end if;
  end process;

  -- Register rf2_ch_0_csr
  rf2_ch_0_csr_delay_oen_o <= rf2_ch_0_csr_delay_oen_reg;
  rf2_ch_0_csr_mux_sel_o <= rf2_ch_0_csr_mux_sel_reg;
  rf2_ch_0_csr_trig_rst_o <= rf2_ch_0_csr_trig_rst_reg;
  rf2_ch_0_csr_delay_latch_o <= rf2_ch_0_csr_delay_latch_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf2_ch_0_csr_delay_oen_reg <= '0';
        rf2_ch_0_csr_mux_sel_reg <= '0';
        rf2_ch_0_csr_trig_rst_reg <= '1';
        rf2_ch_0_csr_delay_latch_reg <= '1';
        rf2_ch_0_csr_wack <= '0';
      else
        if rf2_ch_0_csr_wreq = '1' then
          rf2_ch_0_csr_delay_oen_reg <= wr_dat_d0(0);
          rf2_ch_0_csr_mux_sel_reg <= wr_dat_d0(1);
          rf2_ch_0_csr_trig_rst_reg <= wr_dat_d0(2);
          rf2_ch_0_csr_delay_latch_reg <= wr_dat_d0(3);
        end if;
        rf2_ch_0_csr_wack <= rf2_ch_0_csr_wreq;
      end if;
    end if;
  end process;

  -- Register rf2_ch_1_csr
  rf2_ch_1_csr_delay_oen_o <= rf2_ch_1_csr_delay_oen_reg;
  rf2_ch_1_csr_mux_sel_o <= rf2_ch_1_csr_mux_sel_reg;
  rf2_ch_1_csr_trig_rst_o <= rf2_ch_1_csr_trig_rst_reg;
  rf2_ch_1_csr_delay_latch_o <= rf2_ch_1_csr_delay_latch_reg;
  process (clk_i) begin
    if rising_edge(clk_i) then
      if rst_n_i = '0' then
        rf2_ch_1_csr_delay_oen_reg <= '0';
        rf2_ch_1_csr_mux_sel_reg <= '0';
        rf2_ch_1_csr_trig_rst_reg <= '1';
        rf2_ch_1_csr_delay_latch_reg <= '1';
        rf2_ch_1_csr_wack <= '0';
      else
        if rf2_ch_1_csr_wreq = '1' then
          rf2_ch_1_csr_delay_oen_reg <= wr_dat_d0(0);
          rf2_ch_1_csr_mux_sel_reg <= wr_dat_d0(1);
          rf2_ch_1_csr_trig_rst_reg <= wr_dat_d0(2);
          rf2_ch_1_csr_delay_latch_reg <= wr_dat_d0(3);
        end if;
        rf2_ch_1_csr_wack <= rf2_ch_1_csr_wreq;
      end if;
    end if;
  end process;

  -- Process for write requests.
  process (wr_adr_d0, wr_req_d0, rf_trigger_ff_delay_wack, rf1_common_wack,
           rf1_t1_sync_progdelay_wack, rf1_rst_cdelay_wack, rf1_ch_0_csr_wack,
           rf1_ch_1_csr_wack, rf2_common_wack, rf2_t1_sync_progdelay_wack,
           rf2_rst_cdelay_wack, rf2_ch_0_csr_wack, rf2_ch_1_csr_wack) begin
    rf_trigger_ff_delay_wreq <= '0';
    rf1_common_wreq <= '0';
    rf1_t1_sync_progdelay_wreq <= '0';
    rf1_rst_cdelay_wreq <= '0';
    rf1_ch_0_csr_wreq <= '0';
    rf1_ch_1_csr_wreq <= '0';
    rf2_common_wreq <= '0';
    rf2_t1_sync_progdelay_wreq <= '0';
    rf2_rst_cdelay_wreq <= '0';
    rf2_ch_0_csr_wreq <= '0';
    rf2_ch_1_csr_wreq <= '0';
    case wr_adr_d0(5 downto 1) is
    when "00000" =>
      -- Reg rf_trigger_ff_delay
      rf_trigger_ff_delay_wreq <= wr_req_d0;
      wr_ack_int <= rf_trigger_ff_delay_wack;
    when "01000" =>
      -- Reg rf1_common
      rf1_common_wreq <= wr_req_d0;
      wr_ack_int <= rf1_common_wack;
    when "01001" =>
      -- Reg rf1_t1_sync_progdelay
      rf1_t1_sync_progdelay_wreq <= wr_req_d0;
      wr_ack_int <= rf1_t1_sync_progdelay_wack;
    when "01010" =>
      -- Reg rf1_rst_cdelay
      rf1_rst_cdelay_wreq <= wr_req_d0;
      wr_ack_int <= rf1_rst_cdelay_wack;
    when "01100" =>
      -- Reg rf1_ch_0_csr
      rf1_ch_0_csr_wreq <= wr_req_d0;
      wr_ack_int <= rf1_ch_0_csr_wack;
    when "01101" =>
      -- Reg rf1_ch_1_csr
      rf1_ch_1_csr_wreq <= wr_req_d0;
      wr_ack_int <= rf1_ch_1_csr_wack;
    when "10000" =>
      -- Reg rf2_common
      rf2_common_wreq <= wr_req_d0;
      wr_ack_int <= rf2_common_wack;
    when "10001" =>
      -- Reg rf2_t1_sync_progdelay
      rf2_t1_sync_progdelay_wreq <= wr_req_d0;
      wr_ack_int <= rf2_t1_sync_progdelay_wack;
    when "10010" =>
      -- Reg rf2_rst_cdelay
      rf2_rst_cdelay_wreq <= wr_req_d0;
      wr_ack_int <= rf2_rst_cdelay_wack;
    when "10100" =>
      -- Reg rf2_ch_0_csr
      rf2_ch_0_csr_wreq <= wr_req_d0;
      wr_ack_int <= rf2_ch_0_csr_wack;
    when "10101" =>
      -- Reg rf2_ch_1_csr
      rf2_ch_1_csr_wreq <= wr_req_d0;
      wr_ack_int <= rf2_ch_1_csr_wack;
    when others =>
      wr_ack_int <= wr_req_d0;
    end case;
  end process;

  -- Process for read requests.
  process (adr_int, rd_req_int, rf_trigger_ff_delay_reg, rf1_common_mixer_en_reg,
           rf1_common_mux_sel_reg, rf1_common_iqdac_reset_reg,
           rf1_common_start_lpbk_reg, rf1_t1_sync_progdelay_cdelay_reg,
           rf1_t1_sync_progdelay_fdelay_reg,
           rf1_t1_sync_progdelay_odelay_reg, rf1_rst_cdelay_offset_reg,
           rf1_ch_0_csr_delay_oen_reg, rf1_ch_0_csr_mux_sel_reg,
           rf1_ch_0_csr_trig_rst_reg, rf1_ch_0_csr_delay_latch_reg,
           rf1_ch_1_csr_delay_oen_reg, rf1_ch_1_csr_mux_sel_reg,
           rf1_ch_1_csr_trig_rst_reg, rf1_ch_1_csr_delay_latch_reg,
           rf2_common_mixer_en_reg, rf2_common_mux_sel_reg,
           rf2_common_iqdac_reset_reg, rf2_common_start_lpbk_reg,
           rf2_t1_sync_progdelay_cdelay_reg,
           rf2_t1_sync_progdelay_fdelay_reg,
           rf2_t1_sync_progdelay_odelay_reg, rf2_rst_cdelay_offset_reg,
           rf2_ch_0_csr_delay_oen_reg, rf2_ch_0_csr_mux_sel_reg,
           rf2_ch_0_csr_trig_rst_reg, rf2_ch_0_csr_delay_latch_reg,
           rf2_ch_1_csr_delay_oen_reg, rf2_ch_1_csr_mux_sel_reg,
           rf2_ch_1_csr_trig_rst_reg, rf2_ch_1_csr_delay_latch_reg) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case adr_int(5 downto 1) is
    when "00000" =>
      -- Reg rf_trigger_ff_delay
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0 <= rf_trigger_ff_delay_reg;
    when "01000" =>
      -- Reg rf1_common
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(0) <= rf1_common_mixer_en_reg;
      rd_dat_d0(2 downto 1) <= rf1_common_mux_sel_reg;
      rd_dat_d0(3) <= rf1_common_iqdac_reset_reg;
      rd_dat_d0(4) <= rf1_common_start_lpbk_reg;
      rd_dat_d0(15 downto 5) <= (others => '0');
    when "01001" =>
      -- Reg rf1_t1_sync_progdelay
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(6 downto 0) <= rf1_t1_sync_progdelay_cdelay_reg;
      rd_dat_d0(10 downto 7) <= rf1_t1_sync_progdelay_fdelay_reg;
      rd_dat_d0(15 downto 11) <= rf1_t1_sync_progdelay_odelay_reg;
    when "01010" =>
      -- Reg rf1_rst_cdelay
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(6 downto 0) <= rf1_rst_cdelay_offset_reg;
      rd_dat_d0(15 downto 7) <= (others => '0');
    when "01100" =>
      -- Reg rf1_ch_0_csr
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(0) <= rf1_ch_0_csr_delay_oen_reg;
      rd_dat_d0(1) <= rf1_ch_0_csr_mux_sel_reg;
      rd_dat_d0(2) <= rf1_ch_0_csr_trig_rst_reg;
      rd_dat_d0(3) <= rf1_ch_0_csr_delay_latch_reg;
      rd_dat_d0(15 downto 4) <= (others => '0');
    when "01101" =>
      -- Reg rf1_ch_1_csr
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(0) <= rf1_ch_1_csr_delay_oen_reg;
      rd_dat_d0(1) <= rf1_ch_1_csr_mux_sel_reg;
      rd_dat_d0(2) <= rf1_ch_1_csr_trig_rst_reg;
      rd_dat_d0(3) <= rf1_ch_1_csr_delay_latch_reg;
      rd_dat_d0(15 downto 4) <= (others => '0');
    when "10000" =>
      -- Reg rf2_common
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(0) <= rf2_common_mixer_en_reg;
      rd_dat_d0(2 downto 1) <= rf2_common_mux_sel_reg;
      rd_dat_d0(3) <= rf2_common_iqdac_reset_reg;
      rd_dat_d0(4) <= rf2_common_start_lpbk_reg;
      rd_dat_d0(15 downto 5) <= (others => '0');
    when "10001" =>
      -- Reg rf2_t1_sync_progdelay
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(6 downto 0) <= rf2_t1_sync_progdelay_cdelay_reg;
      rd_dat_d0(10 downto 7) <= rf2_t1_sync_progdelay_fdelay_reg;
      rd_dat_d0(15 downto 11) <= rf2_t1_sync_progdelay_odelay_reg;
    when "10010" =>
      -- Reg rf2_rst_cdelay
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(6 downto 0) <= rf2_rst_cdelay_offset_reg;
      rd_dat_d0(15 downto 7) <= (others => '0');
    when "10100" =>
      -- Reg rf2_ch_0_csr
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(0) <= rf2_ch_0_csr_delay_oen_reg;
      rd_dat_d0(1) <= rf2_ch_0_csr_mux_sel_reg;
      rd_dat_d0(2) <= rf2_ch_0_csr_trig_rst_reg;
      rd_dat_d0(3) <= rf2_ch_0_csr_delay_latch_reg;
      rd_dat_d0(15 downto 4) <= (others => '0');
    when "10101" =>
      -- Reg rf2_ch_1_csr
      rd_ack_d0 <= rd_req_int;
      rd_dat_d0(0) <= rf2_ch_1_csr_delay_oen_reg;
      rd_dat_d0(1) <= rf2_ch_1_csr_mux_sel_reg;
      rd_dat_d0(2) <= rf2_ch_1_csr_trig_rst_reg;
      rd_dat_d0(3) <= rf2_ch_1_csr_delay_latch_reg;
      rd_dat_d0(15 downto 4) <= (others => '0');
    when others =>
      rd_ack_d0 <= rd_req_int;
    end case;
  end process;
end syn;
