-- A stupid core

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library UNISIM;
use UNISIM.Vcomponents.ALL;


entity iqdac_wrap is
    
    port (
        clk250m_i          : in  std_logic;
        
        rf1_dac_idata_i    : in  std_logic_vector(15 downto 0);
        rf1_dac_qdata_i    : in  std_logic_vector(15 downto 0);        
        rf1_iqdac_data_p_o : out std_logic_vector(15 downto 0);
        rf1_iqdac_data_n_o : out std_logic_vector(15 downto 0);                
        rf1_iqdac_dci_p_o  : out std_logic;
        rf1_iqdac_dci_n_o  : out std_logic;        

        rf2_dac_idata_i    : in  std_logic_vector(15 downto 0);
        rf2_dac_qdata_i    : in  std_logic_vector(15 downto 0);        
        rf2_iqdac_data_p_o : out std_logic_vector(15 downto 0);
        rf2_iqdac_data_n_o : out std_logic_vector(15 downto 0);                
        rf2_iqdac_dci_p_o  : out std_logic;
        rf2_iqdac_dci_n_o  : out std_logic );
    
end entity;

architecture rtl of iqdac_wrap is

    signal rf1_dac_idata   : unsigned(15 downto 0) := (others => '0');
    signal rf1_dac_qdata   : unsigned(15 downto 0) := (others => '0');    
    signal rf2_dac_idata   : unsigned(15 downto 0) := (others => '0');
    signal rf2_dac_qdata   : unsigned(15 downto 0) := (others => '0');    

    signal zero        : std_logic := '0';
    
begin
    
    -- Dummy clk process to prevent optimisation..
    process (clk250m_i) is
    begin
        if rising_edge(clk250m_i) then
            rf1_dac_idata <= rf1_dac_idata + 3;
            rf1_dac_qdata <= rf1_dac_qdata + 5;
            rf2_dac_idata <= rf2_dac_idata + 7;
            rf2_dac_qdata <= rf2_dac_qdata + 11;            
        end if;
    end process;
            
    rf1_iqdac_io : entity  work.iqdac_io
        generic map (
            dpins          =>  16 )
        port map (
            clk_i          => clk250m_i,
            reset_io_i     => zero,
            iqdac_idata_i  => std_logic_vector(rf1_dac_idata),
            iqdac_qdata_i  => std_logic_vector(rf1_dac_qdata),
            iqdac_data_p_o => rf1_iqdac_data_p_o,
            iqdac_data_n_o => rf1_iqdac_data_n_o,
            iqdac_dc_p_o   => rf1_iqdac_dci_p_o,
            iqdac_dc_n_o   => rf1_iqdac_dci_n_o );

    rf2_iqdac_io : entity  work.iqdac_io
        generic map (
            dpins          =>  16 )
        port map (
            clk_i          => clk250m_i,
            reset_io_i     => zero,
            iqdac_idata_i  => std_logic_vector(rf2_dac_idata),
            iqdac_qdata_i  => std_logic_vector(rf2_dac_qdata),
            iqdac_data_p_o => rf2_iqdac_data_p_o,
            iqdac_data_n_o => rf2_iqdac_data_n_o,
            iqdac_dc_p_o   => rf2_iqdac_dci_p_o,
            iqdac_dc_n_o   => rf2_iqdac_dci_n_o );
        
end architecture;
