module tdpram #(
    parameter dwidth    = 32,
    parameter log2depth = 8,
    parameter tcq       = 1 )
   (
    input   wire                 a_clk,
    input   wire                 a_wr,
    input   wire [log2depth-1:0] a_addr,
    input   wire [dwidth-1:0]    a_din,
    output  wire [dwidth-1:0]    a_dout,

    input   wire                 b_clk,
    input   wire                 b_wr,
    input   wire [log2depth-1:0] b_addr,
    input   wire [dwidth-1:0]    b_din,
    output  wire [dwidth-1:0]    b_dout
    );

reg [dwidth-1:0] mem [(2**log2depth)-1:0];
reg [dwidth-1:0] a_dout_r;
reg [dwidth-1:0] a_dout_h;
reg [dwidth-1:0] b_dout_r;
reg [dwidth-1:0] b_dout_h;

   always @(posedge a_clk) 
   begin

      if (a_wr) 
      begin
	 mem[a_addr] <= #tcq a_din;
	 a_dout_r    <= #tcq mem[a_addr];
      end
      else
      begin
	 a_dout_r    <= #tcq mem[a_addr];
      end
      a_dout_h       <= #tcq a_dout_r;
   end

   always @(posedge b_clk) 
   begin
      if (b_wr) 
      begin
	 mem[b_addr] <= #tcq b_din;
	 b_dout_r    <= #tcq mem[b_addr];
      end
      else
      begin
	 b_dout_r    <= #tcq mem[b_addr];
      end
      b_dout_h       <= #tcq b_dout_r;

   end

   assign a_dout = a_dout_h;
   assign b_dout = b_dout_h;

endmodule
