Repository for the wr2rf vme board.

project page: https://ohwr.org/project/vme-rf-wr-bobr

=====
RFNCO
=====
RFNCO is a forked version of BE-RF-PLDesign. This is a pain, but it allows us to have local
changes.
 - check that RFNCO is up to date.
 - checkout the submodules that are required. MemMap and RFFrameTransceiver...
 - Change the build target, Vivado/Options/build.tcl to "set target_device xc7k160tfbg676-2"
 - cd dependencies/RFNCO/Vivado
 - vivado -source Options/build.tcl
 - Once the project has instantiated + annotated the block design: click "Run Synthesis", takes ~1.5 hours
 - When finished, open "Synthesized Design"
 - Export an RTL netlist: File->Export->Netlist
 - Export a block design Wrappers:

To build wr2rf-vme it references, via hdl/rtl/rfnco/Manifest.py two files. They must be present otherwise it won't work...

Origin: https://gitlab.cern.ch/BE-RF-PLDesign/Libraries/xilinx/RFNCO.git

In case of TCL error by vivado on run_ippack.tcl, cf:
  https://support.xilinx.com/s/article/76960?language=en_US


==================
nonIQModInterp2FIR
==================
nonIQModInterp2FIR is a forked version of BE-RF-PLDesign. This is a pain, but it allows us to have local
changes.
 - check that nonIQModInterp2FIR is up to date with the upstream BE-RF-PLDesign...
 - no submodules are required
 - Change the build target, Vivado/Options/build.tcl to "set target_device xc7k160tfbg676-2"
 - cd dependencies/nonIQModInterp2FIR/Vivado
 - vivado -source Options/build.tcl
 - Once the project has instantiated + annotated the block design: click "Run Synthesis", takes ~20 mins
 - When finished, open "Synthesized Design"
 - Export an RTL netlist: File->Export->Netlist
 - Export a block design Wrappers:
      set_property target_language VHDL [current_project]
      make_wrapper -files [get_files Work/nonIQModInterp2FIR.srcs/sources_1/bd/nonIQModInterp2FIR/nonIQModInterp2FIR.bd] -top

To build wr2rf-vme it references, via hdl/rtl/noniqmodinterp2fir/Manifest.py two files. They must be present otherwise it won't work...
