Commit f18cd81c authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

adding wrs-pts written by INCAA

parent f034d941
This diff is collapsed.
[global]
board = SPEC
serial = 000000
extra-serial = 000000
test_path = tests/
log_path = logs/
sequence = ['00', '02', '03']
repeat = 10
randomize = True
#! /usr/bin/env python
# coding: utf8
class PtsException(Exception):
pass
class PtsCritical(PtsException):
"""critical error, abort the whole test suite"""
pass
class PtsError(PtsException):
"""error, continue remaining tests in test suite"""
pass
class PtsUser(PtsException):
"""error, user intervention required"""
pass
class PtsWarning(PtsException):
"""warning, a cautionary message should be displayed"""
pass
class PtsInvalid(PtsException):
"""reserved: invalid parameters"""
class PtsNoBatch(PtsInvalid):
"""reserved: a suite was created without batch of tests to run"""
pass
class PtsBadTestNo(PtsInvalid):
"""reserved: a bad test number was given"""
pass
if __name__ == '__main__':
pass
*******************************************************************************
WRS tests for PTS environment
*******************************************************************************
CERN, 2017
Author: INCAA Computers
Licence: GPL v2 or later.
Website: http://www.ohwr.org/projects/pts
This batch of tests tests the solderings of the WRS:
- test00: flash testfw (user)
- test01: ddr2 test
- test02: hwinfo (user)
- test03: init hardware
- test04: fpga/cpu bus test
- test05: fans (user)
- test06: leds (user)
- test07: general button
- test08: sfp lines (user)
- test09: voltage levels
- test10: dataflash
- test11: nand
- test12: ad9516
- test13: clocks
- test14: smc connectors
- test15: usb's + rs232
- test16: temperatures
- test17: flash finalfw -> check boot afterwards with pexpect
This tests are made to work stand-alone too. So, it is possible to call each one using 'sudo python ./test0x.py'
For installation details see ./doc/ubuntu_setup_note.txt
This note explains how to setup an Ubuntu PC for a WhiteRabbitSwitch production test suite.
Ubuntu version must be 11.04 (2.6.38)
http://old-releases.ubuntu.com/releases/11.04/ubuntu-11.04-desktop-i386.iso
Add within synaptic the following repositories
http://old-releases.ubuntu.com/ubuntu natty main+multiverse+universe+restricted
The following packages must be installed:
git
python
python-dev
python-pip
sudo pip install pexpect numpy pyro4 ptyprocess
dnsmasq
nfs-kernel-server
Copy PTS git repository:
cd ~
git clone git://ohwr.org/misc/pts.git
cd pts
git checkout wrs
Make sure these files are executable:
~/pts/test/wrs/python/flash-wrs
~/pts/test/wrs/python/hwinfo/gensdbfs
~/pts/test/wrs/python/hwinfo/wrs_hwinfo
~/pts/test/wrs/lib/pts_com_test
~/pts/wrs.sh
~/pts/wrs-select.sh
~/pts/wrs-non_destructive.sh
Prepare tftp directory
sudo mkdir /tftpboot
cd ~/pts/test/wrs/python
sudo python test000.py
Configure dnsmasq (https://wiki.debian.org/HowTo/dnsmasq)
edit /etc/dnsmasq.conf
uncomment interface=eth0
uncomment dhcp-range=x.x.x.x,x.x.x.x.x,12h (choose range)
uncomment enable-tftp
uncomment tftp-root=/tftpboot
Configure nfs
edit /etc/exports
add /tftpboot/ *(rw,no_subtree_check,no_root_squash)
Compile usb-loader
cd ~/pts/test/wrs/python/usb-loader
make
Compile usbtmc stuff:
cd ~/pts/usbdriver
make
Create a script file to launch the test program:
cd ~
touch run_ptsWRS.sh
chmod +x run_ptsWRS.sh
Edit the script file as follow:
#!/bin/sh
echo " "
echo " "
echo "********************************************************************************"
echo "* WhiteRabbitSwitch Test program *"
echo "********************************************************************************"
echo " "
cd ~/pts && sudo ./wrs.sh
Create an alias to be able to launch the test program by typing "testWRS".
Add the following to ~/.bashrc
alias testWRS='~/run_ptsWRS.sh'
Define bash as the default shell:
chsh -s /bin/bash <username>
In "System > Preferences > Startup Applications" add the following to
automatically open a terminal at startup:
Command: gnome-terminal
#!/bin/sh
## Please type Ctrl+D to Save-and-exit or Ctrl+C to Exit
## eth0.ethaddr corresponds to the MAC address of the switch, it can also be
## changes using flasher
# eth0.ethaddr=
## macaddr is the base MAC address to assign to the first switch port. All
## the other ports are sequentially assigned
# macaddr=
## You can set your networking parameters here
## If unset, then boot-script will use dhcp
## This is shipped as unset ("if false" below)
if false; then
eth0.serverip=192.168.1.1
eth0.ipaddr=192.168.1.2
eth0.netmask=255.255.255.0
eth0.gateway=192.168.1.254
fi
## Timeout and select default entry in autoboot menu
autoboot_timeout="5";
autoboot_select="1";
#!/bin/sh
## Please type Ctrl+D to Save-and-exit or Ctrl+C to Exit
## eth0.ethaddr corresponds to the MAC address of the switch, it can also be
## changes using flasher
# eth0.ethaddr=
## macaddr is the base MAC address to assign to the first switch port. All
## the other ports are sequentially assigned
# macaddr=
## You can set your networking parameters here
## If unset, then boot-script will use dhcp
## This is shipped as unset ("if false" below)
if false; then
eth0.serverip=192.168.1.1
eth0.ipaddr=192.168.1.2
eth0.netmask=255.255.255.0
eth0.gateway=192.168.1.254
fi
## Timeout and select default entry in autoboot menu
autoboot_timeout="5";
autoboot_select="2";
#
# Automatically generated file; DO NOT EDIT.
# White Rabbit Switch configuration
#
# CONFIG_DOTCONF_SOURCE_LOCAL is not set
# CONFIG_DOTCONF_SOURCE_REMOTE is not set
# CONFIG_DOTCONF_SOURCE_FORCE_DHCP is not set
CONFIG_DOTCONF_SOURCE_TRY_DHCP=y
CONFIG_BR2_CONFIGFILE="wrs_release_br2_config"
CONFIG_PPSI=y
#
# Local Network Configuration
#
CONFIG_ETH0_DHCP=y
# CONFIG_ETH0_DHCP_ONCE is not set
# CONFIG_ETH0_STATIC is not set
CONFIG_HOSTNAME_DHCP=y
# CONFIG_HOSTNAME_STATIC is not set
#
# Root Password
#
# CONFIG_ROOT_PWD_IS_ENCRYPTED is not set
CONFIG_ROOT_PWD_CLEAR=""
CONFIG_NTP_SERVER=""
CONFIG_DNS_SERVER=""
CONFIG_DNS_DOMAIN=""
CONFIG_REMOTE_SYSLOG_SERVER=""
CONFIG_REMOTE_SYSLOG_UDP=y
CONFIG_WRS_LOG_HAL="daemon.info"
CONFIG_WRS_LOG_LEVEL_HAL=""
CONFIG_WRS_LOG_RTU="daemon.info"
CONFIG_WRS_LOG_LEVEL_RTU=""
CONFIG_WRS_LOG_PTP="daemon.info"
CONFIG_WRS_LOG_LEVEL_PTP=""
CONFIG_WRS_LOG_SNMPD="Swd"
CONFIG_WRS_LOG_MONIT="syslog"
CONFIG_WRS_LOG_OTHER="daemon.info"
CONFIG_WRS_LOG_LEVEL_OTHER=""
# CONFIG_KEEP_ROOTFS is not set
#
# Port Timing Configuration
#
CONFIG_PORT01_PARAMS="name=wri1,proto=raw,tx=223897,rx=226273,role=slave,fiber=0"
CONFIG_PORT02_PARAMS="name=wri2,proto=raw,tx=224037,rx=226377,role=master,fiber=0"
CONFIG_PORT03_PARAMS="name=wri3,proto=raw,tx=224142,rx=226638,role=master,fiber=0"
CONFIG_PORT04_PARAMS="name=wri4,proto=raw,tx=224313,rx=226471,role=master,fiber=0"
CONFIG_PORT05_PARAMS="name=wri5,proto=raw,tx=224455,rx=227679,role=master,fiber=0"
CONFIG_PORT06_PARAMS="name=wri6,proto=raw,tx=224603,rx=227891,role=master,fiber=0"
CONFIG_PORT07_PARAMS="name=wri7,proto=raw,tx=224761,rx=228055,role=master,fiber=0"
CONFIG_PORT08_PARAMS="name=wri8,proto=raw,tx=224898,rx=228178,role=master,fiber=0"
CONFIG_PORT09_PARAMS="name=wri9,proto=raw,tx=225069,rx=228277,role=master,fiber=0"
CONFIG_PORT10_PARAMS="name=wri10,proto=raw,tx=225245,rx=228435,role=master,fiber=0"
CONFIG_PORT11_PARAMS="name=wri11,proto=raw,tx=225463,rx=228963,role=master,fiber=0"
CONFIG_PORT12_PARAMS="name=wri12,proto=raw,tx=225645,rx=229107,role=master,fiber=0"
CONFIG_PORT13_PARAMS="name=wri13,proto=raw,tx=225801,rx=229225,role=master,fiber=0"
CONFIG_PORT14_PARAMS="name=wri14,proto=raw,tx=225983,rx=229463,role=master,fiber=0"
CONFIG_PORT15_PARAMS="name=wri15,proto=raw,tx=226208,rx=229850,role=master,fiber=0"
CONFIG_PORT16_PARAMS="name=wri16,proto=raw,tx=226393,rx=229907,role=master,fiber=0"
CONFIG_PORT17_PARAMS="name=wri17,proto=raw,tx=226594,rx=230106,role=master,fiber=0"
CONFIG_PORT18_PARAMS="name=wri18,proto=raw,tx=226737,rx=230273,role=master,fiber=0"
#
# SFP and Media Timing Configuration
#
CONFIG_SFP00_PARAMS="vn=Axcen Photonics,pn=AXGE-1254-0531,tx=0,rx=0,wl_txrx=1310+1490"
CONFIG_SFP01_PARAMS="vn=Axcen Photonics,pn=AXGE-3454-0531,tx=0,rx=0,wl_txrx=1490+1310"
CONFIG_SFP02_PARAMS="vn=APAC Opto,pn=LS38-C3S-TC-N-B9,tx=761,rx=557,wl_txrx=1310+1490"
CONFIG_SFP03_PARAMS="vn=APAC Opto,pn=LS48-C3S-TC-N-B4,tx=-29,rx=507,wl_txrx=1490+1310"
CONFIG_SFP04_PARAMS="vn=ZyXEL,pn=SFP-BX1490-10-D,tx=0,rx=0,wl_txrx=1490+1310"
CONFIG_SFP05_PARAMS="vn=ZyXEL,pn=SFP-BX1310-10-D,tx=0,rx=0,wl_txrx=1310+1490"
CONFIG_SFP06_PARAMS="vn=Molex Inc.,pn=74720-0501,tx=0,rx=0,wl_txrx=1000+1500"
CONFIG_SFP07_PARAMS=""
CONFIG_SFP08_PARAMS=""
CONFIG_SFP09_PARAMS=""
CONFIG_FIBER00_PARAMS="alpha_1310_1490=2.6787e-04"
CONFIG_FIBER01_PARAMS="alpha_1310_1490=2.6787e-04"
CONFIG_FIBER02_PARAMS="alpha_1310_1490=2.6787e-04"
CONFIG_FIBER03_PARAMS="alpha_1310_1490=2.6787e-04"
# CONFIG_TIME_GM is not set
# CONFIG_TIME_FM is not set
CONFIG_TIME_BC=y
CONFIG_PTP_PORT_PARAMS=y
# CONFIG_PTP_CUSTOM is not set
# CONFIG_PTP_REMOTE_CONF is not set
#
# Management configuration
#
CONFIG_SNMP_TRAPSINK_ADDRESS=""
CONFIG_SNMP_TRAP2SINK_ADDRESS=""
CONFIG_SNMP_RO_COMMUNITY="public"
CONFIG_SNMP_RW_COMMUNITY="private"
CONFIG_SNMP_TEMP_THOLD_FPGA=80
CONFIG_SNMP_TEMP_THOLD_PLL=80
CONFIG_SNMP_TEMP_THOLD_PSL=80
CONFIG_SNMP_TEMP_THOLD_PSR=80
# CONFIG_SNMP_SWCORESTATUS_DISABLE is not set
#
# External clk2 clock signal configuration
#
CONFIG_WRSAUXCLK_FREQ="10"
CONFIG_WRSAUXCLK_DUTY="0.5"
CONFIG_WRSAUXCLK_CSHIFT="36"
CONFIG_WRSAUXCLK_SIGDEL="0"
CONFIG_WRSAUXCLK_PPSHIFT="0"
#
# NIC throttling configuration
#
# CONFIG_NIC_THROTTLING_ENABLED is not set
#
# Custom boot script configuration
#
# CONFIG_CUSTOM_BOOT_SCRIPT_ENABLED is not set
#
# Developer options
#
# CONFIG_MONIT_DISABLE is not set
#
# Fan speed control
#
# CONFIG_FAN_HYSTERESIS is not set
# CONFIG_READ_SFP_DIAG_ENABLE is not set
#
# RTU HP mask
#
# CONFIG_RTU_HP_MASK_ENABLE is not set
#
# VLANs
#
# CONFIG_VLANS_ENABLE is not set
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := pts_scb.xise
ISE_CRAP := *.b pts_scb_top_summary.html *.tcl pts_scb_top.bld pts_scb_top.cmd_log *.drc pts_scb_top.lso *.ncd pts_scb_top.ngc pts_scb_top.ngd pts_scb_top.ngr pts_scb_top.pad pts_scb_top.par pts_scb_top.pcf pts_scb_top.prj pts_scb_top.ptwx pts_scb_top.stx pts_scb_top.syr pts_scb_top.twr pts_scb_top.twx pts_scb_top.gise pts_scb_top.unroutes pts_scb_top.ut pts_scb_top.xpi pts_scb_top.xst pts_scb_top_bitgen.xwbt pts_scb_top_envsettings.html pts_scb_top_guide.ncd pts_scb_top_map.map pts_scb_top_map.mrp pts_scb_top_map.ncd pts_scb_top_map.ngm pts_scb_top_map.xrpt pts_scb_top_ngdbuild.xrpt pts_scb_top_pad.csv pts_scb_top_pad.txt pts_scb_top_par.xrpt pts_scb_top_summary.xml pts_scb_top_usage.xml pts_scb_top_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
target = "xilinx"
action = "synthesis"
fetchto = "../../ip_cores"
#syn_tool = "ise"
#top_module = "scb_top_synthesis"
syn_device = "xc6vlx240t"
syn_grade = "-1"
syn_package = "ff1156"
syn_top = "pts_scb_top"
syn_project = "pts_scb.xise"
modules = { "local" : [ "../../top/pts_scb",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores" ] }
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This source diff could not be displayed because it is too large. You can view the blob instead.
Release 14.6 - Bitgen P.68d (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Loading device for application Rf_Device from file '6vlx240t.nph' in environment
/opt/Xilinx/14.6/ISE_DS/ISE/.
"pts_scb_top" is an NCD, version 3.2, device xc6vlx240t, package ff1156,
speed -1
Opened constraints file pts_scb_top.pcf.
Thu Mar 9 11:31:05 2017
/opt/Xilinx/14.6/ISE_DS/ISE/bin/lin64/unwrapped/bitgen -intstyle ise -w -d -g Binary:yes -g Compress -g CRC:Enable -g ConfigRate:50 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g InitPin:Pullup -g CsPin:Pullup -g DinPin:Pullup -g BusyPin:Pullup -g RdWrPin:Pullup -g HswapenPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g Disable_JTAG:No -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ConfigFallback:Enable -g BPI_page_size:1 -g OverTempPowerDown:Disable -g USR_ACCESS:None -g next_config_addr:None -g JTAG_SysMon:Enable -g DCIUpdateMode:Quiet -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No -g Encrypt:No pts_scb_top.ncd
INFO:Bitgen:40 - Replacing "Auto" with "NoWait" for option "Match_cycle". Most
commonly, bitgen has determined and will use a specific value instead of the
generic command-line value of "Auto". Alternately, this message appears if
the same option is specified multiple times on the command-line. In this
case, the option listed last will be used.
Summary of Bitgen Options:
+----------------------+----------------------+
| Option Name | Current Setting |
+----------------------+----------------------+
| Compress | (Enabled) |
+----------------------+----------------------+
| Readback | (Not Specified)* |
+----------------------+----------------------+
| CRC | Enable** |
+----------------------+----------------------+
| DebugBitstream | No* |
+----------------------+----------------------+
| ConfigRate | 50 |
+----------------------+----------------------+
| StartupClk | Cclk** |
+----------------------+----------------------+
| CclkPin | Pullup** |
+----------------------+----------------------+
| DonePin | Pullup* |
+----------------------+----------------------+
| HswapenPin | Pullup** |
+----------------------+----------------------+
| M0Pin | Pullup** |
+----------------------+----------------------+
| M1Pin | Pullup** |
+----------------------+----------------------+
| M2Pin | Pullup** |
+----------------------+----------------------+
| ProgPin | Pullup** |
+----------------------+----------------------+
| InitPin | Pullup** |
+----------------------+----------------------+
| CsPin | Pullup** |
+----------------------+----------------------+
| DinPin | Pullup** |
+----------------------+----------------------+
| BusyPin | Pullup** |
+----------------------+----------------------+
| RdWrPin | Pullup** |
+----------------------+----------------------+
| TckPin | Pullup** |
+----------------------+----------------------+
| TdiPin | Pullup** |
+----------------------+----------------------+
| TdoPin | Pullup** |
+----------------------+----------------------+
| TmsPin | Pullup** |
+----------------------+----------------------+
| UnusedPin | Pulldown** |
+----------------------+----------------------+
| GWE_cycle | 6** |
+----------------------+----------------------+
| GTS_cycle | 5** |
+----------------------+----------------------+
| OverTempPowerDown | Disable** |
+----------------------+----------------------+
| LCK_cycle | NoWait* |
+----------------------+----------------------+
| Match_cycle | NoWait |
+----------------------+----------------------+
| DONE_cycle | 4** |
+----------------------+----------------------+
| Persist | No* |
+----------------------+----------------------+
| DriveDone | No** |
+----------------------+----------------------+
| DonePipe | No** |
+----------------------+----------------------+
| Security | None** |
+----------------------+----------------------+
| UserID | 0xFFFFFFFF** |
+----------------------+----------------------+
| ActiveReconfig | No* |
+----------------------+----------------------+
| Encrypt | No** |
+----------------------+----------------------+
| EncryptKeySelect | bbram* |
+----------------------+----------------------+
| Key0 | pick* |
+----------------------+----------------------+
| StartCBC | pick* |
+----------------------+----------------------+
| HKey | pick* |
+----------------------+----------------------+
| KeyFile | (Not Specified)* |
+----------------------+----------------------+
| DCIUpdateMode | Quiet** |
+----------------------+----------------------+
| ConfigFallback | Enable** |
+----------------------+----------------------+
| SelectMAPAbort | Enable* |
+----------------------+----------------------+
| BPI_page_size | 1** |
+----------------------+----------------------+
| BPI_1st_read_cycle | 1* |
+----------------------+----------------------+
| next_config_addr | None** |
+----------------------+----------------------+
| DoneSignalsPowerDown | Disable* |
+----------------------+----------------------+
| InitSignalsError | Enable* |
+----------------------+----------------------+
| ICAP_Encryption | Disable* |
+----------------------+----------------------+
| SysmonPartialReconfig | Disable* |
+----------------------+----------------------+
| SecAll | No* |
+----------------------+----------------------+
| SecError | No* |
+----------------------+----------------------+
| SecStatus | No* |
+----------------------+----------------------+
| JTAG_SysMon | Enable** |
+----------------------+----------------------+
| Disable_JTAG | No** |
+----------------------+----------------------+
| Partial | (Not Specified)* |
+----------------------+----------------------+
| TIMER_CFG | None* |
+----------------------+----------------------+
| TIMER_USR | None* |
+----------------------+----------------------+
| USR_ACCESS | None** |
+----------------------+----------------------+
| TimeStamp | Default* |
+----------------------+----------------------+
| IEEE1532 | No* |
+----------------------+----------------------+
| Binary | Yes |
+----------------------+----------------------+
* Default setting.
** The specified setting matches the default setting.
There were 0 CONFIG constraint(s) processed from pts_scb_top.pcf.
INFO:Security:56 - Part 'xc6vlx240t' is not a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
Creating bit map...
Saving bit stream in "pts_scb_top.bit".
Bitstream compression saved 19035392 bits.
Saving bit stream in "pts_scb_top.bin".
Bitstream generation is complete.
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.6">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
</document>
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="cgReport" timeStamp="Wed Mar 8 16:17:20 2017">
<section name="Intelligent Clock Gating (CooolGate)" visible="true">
<item name="Statistics">
<property name="Slice Registers gated" value="25102" type="CGStatistics"/>
<property name="Bram ports gated" value="320" type="CGStatistics"/>
<property name="Processed CE nets" value="2673" type="CGStatistics"/>
<property name="Num added FF" value="1" type="CGStatistics"/>
<property name="Num enables dropped due to constraints" value="0" type="CGStatistics"/>
<property name="Num flops dropped due to constraints" value="0" type="CGStatistics"/>
</item>
</section>
</application>
</document>
files = [
"pts_scb_top.ucf",
"pts_scb_top.vhd",
"swcore_pll.vhd",
"pts_scb_top_bare.vhd",
"pts_wb_cpu_bridge.vhd",
#"wb_cpu_bridge.vhd",
"scb_top_sim.vhd",
"wrsw_top_pkg.vhd",
"wrs_sdb_pkg.vhd",
"synthesis_descriptor.vhd",
"xwrsw_syst_mon.vhd",
"syst_mon.vhd",
"xwrsw_sandbox.vhd",
"freq_wbgen2_pkg.vhd",
"wb_freq_regs.vhd",
"xwrsw_freq_measure.vhd"
];
modules = { "local" : [ "../../" ] };
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for PTS Frequency Measurement Result Registers
---------------------------------------------------------------------------------------
-- File : freq_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wb_freq_regs.wb
-- Created : Wed Feb 15 11:13:39 2017
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_freq_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package freq_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_freq_in_registers is record
f_dmtd_clk_freq_i : std_logic_vector(27 downto 0);
f_clk10mhz_ext_freq_i : std_logic_vector(27 downto 0);
f_fpga_main_clk_freq_i : std_logic_vector(27 downto 0);
f_aux_clk_freq_i : std_logic_vector(27 downto 0);
f_serdes_clk_freq_i : std_logic_vector(27 downto 0);
f_ref_clk_freq_i : std_logic_vector(27 downto 0);
end record;
constant c_freq_in_registers_init_value: t_freq_in_registers := (
f_dmtd_clk_freq_i => (others => '0'),
f_clk10mhz_ext_freq_i => (others => '0'),
f_fpga_main_clk_freq_i => (others => '0'),
f_aux_clk_freq_i => (others => '0'),
f_serdes_clk_freq_i => (others => '0'),
f_ref_clk_freq_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_freq_out_registers is record
dummy : std_logic;
end record;
constant c_freq_out_registers_init_value: t_freq_out_registers := (
dummy => '0'
);
function "or" (left, right: t_freq_in_registers) return t_freq_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body freq_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_freq_in_registers) return t_freq_in_registers is
variable tmp: t_freq_in_registers;
begin
tmp.f_dmtd_clk_freq_i := f_x_to_zero(left.f_dmtd_clk_freq_i) or f_x_to_zero(right.f_dmtd_clk_freq_i);
tmp.f_clk10mhz_ext_freq_i := f_x_to_zero(left.f_clk10mhz_ext_freq_i) or f_x_to_zero(right.f_clk10mhz_ext_freq_i);
tmp.f_fpga_main_clk_freq_i := f_x_to_zero(left.f_fpga_main_clk_freq_i) or f_x_to_zero(right.f_fpga_main_clk_freq_i);
tmp.f_aux_clk_freq_i := f_x_to_zero(left.f_aux_clk_freq_i) or f_x_to_zero(right.f_aux_clk_freq_i);
tmp.f_serdes_clk_freq_i := f_x_to_zero(left.f_serdes_clk_freq_i) or f_x_to_zero(right.f_serdes_clk_freq_i);
tmp.f_ref_clk_freq_i := f_x_to_zero(left.f_ref_clk_freq_i) or f_x_to_zero(right.f_ref_clk_freq_i);
return tmp;
end function;
end package body;
#!/usr/bin/python
##-----------------------------------------------------------------------------
## Title : SDB Synthesis info autogen
## Project : White Rabbit Switch
##-----------------------------------------------------------------------------
## File : gen_sdbsyn.py
## Author : Grzegorz Daniluk
## Company : CERN BE-CO-HT
## Created : 2014-09-17
## Last update: 2014-09-17
## Platform : FPGA-generic
## Standard : VHDL
##-----------------------------------------------------------------------------
## Description:
## Script for auto-generation of VHDL package with t_sdb_synthesis and
## t_sdb_repo_url info. Should be called every time before the synthesis is done
##-----------------------------------------------------------------------------
##
## Copyright (c) 2014 CERN / BE-CO-HT
##
## This source file is free software; you can redistribute it
## and/or modify it under the terms of the GNU Lesser General
## Public License as published by the Free Software Foundation;
## either version 2.1 of the License, or (at your option) any
## later version.
##
## This source is distributed in the hope that it will be
## useful, but WITHOUT ANY WARRANTY; without even the implied
## warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
## PURPOSE. See the GNU Lesser General Public License for more
## details.
##
## You should have received a copy of the GNU Lesser General
## Public License along with this source; if not, download it
## from http://www.gnu.org/licenses/lgpl-2.1.html
##
##-----------------------------------------------------------------------------
import sys
import argparse
import subprocess
import datetime
#MODULE_NAME = "WRS 8p"
#TOOL_NAME = "ISE"
#TOOL_VERSION = "14.5"
PKG_FILE = "synthesis_descriptor.vhd"
PKG_HEADER = """-- package generated automatically by gen_sdbsyn.py script --
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is\n"""
PKG_TAIL = "\nend package;";
REPO_URL = "constant c_sdb_repo_url : t_sdb_repo_url := (\n"
MAIN_SYN = "top"
# from t_sdb_synthesis record
SDB_URL = "repo_url"
URL_LEN = 63
NAME_LEN = 16
COMMIT_LEN = 32
TOOL_LEN = 8
USER_LEN = 15
# git commands
GIT_DIRTY = "git describe --always --dirty=+"
# write t_sdb_synthesis record to opened file
def write_sdb_info(f, r_name, m_name, commit, dirty, tool, toolv, date, user):
# mark dirty if necessary
if len(m_name)<NAME_LEN and dirty:
m_name = m_name + '+'
elif len(m_name)>=NAME_LEN and dirty:
m_name = m_name[:NAME_LEN-1] + '+'
f.write("constant c_sdb_" + r_name.replace("-", "_") + "_syn_info : t_sdb_synthesis := (\n")
f.write("syn_module_name => \"" + m_name[:NAME_LEN].ljust(NAME_LEN) + "\",\n")
f.write("syn_commit_id => \"" + commit.ljust(COMMIT_LEN) + "\",\n")
f.write("syn_tool_name => \"" + tool[:TOOL_LEN].ljust(TOOL_LEN) + "\",\n")
f.write("syn_tool_version => x\""+ hex(toolv)[2:].zfill(8) + "\",\n")
f.write("syn_date => x\"" + hex(date)[2:].zfill(8) + "\",\n")
f.write("syn_username => \"" + user[:USER_LEN].ljust(USER_LEN) + "\");\n")
def git_username():
# gets username from git config
temp = subprocess.Popen("git config user.name", stdout=subprocess.PIPE, shell=True)
user = temp.stdout.read().split()
if len(user) == 1:
#is a single word, so we just use it
return user[0]
#otherwise use initials with last name
uname = ""
for n in user[:-1]:
uname = uname + n[0]
if len(user):
uname = uname + user[-1]
return uname
def main():
### runtime arguments
parser = argparse.ArgumentParser(description='Script for generating sdb metadata of HDL projects')
parser.add_argument('--user', default=git_username(), help='User who makes the synthesis')
parser.add_argument('--project', default="", required=True, help='Friendly project name')
parser.add_argument('--tool', default="ISE", help='Name of the synthesis tool')
parser.add_argument('--ver', default="14.5", help='Synthesis tool version')
parser.add_argument('-o', default=".", help='location of output file')
args = parser.parse_args()
if args.o[-1]!='/':
args.o = args.o + '/'
#######
temp = subprocess.Popen("git rev-parse --show-toplevel", stdout=subprocess.PIPE, shell=True)
toplevel = temp.stdout.read()[0:-1] #remove trailing \n
f = open(args.o + PKG_FILE, 'w')
f.write(PKG_HEADER)
### Make the first constant which is repo url
f.write(REPO_URL)
temp = subprocess.Popen("git config remote.origin.url", stdout=subprocess.PIPE, shell=True)
url = temp.stdout.read()[0:-1]
f.write(SDB_URL + " => \"" + url[:URL_LEN].ljust(URL_LEN) + "\");\n") #truncate or expand string
### Now generate synthesis info for main repository
# get commit id
temp = subprocess.Popen("git log --always --pretty=format:'%H' -n 1", stdout=subprocess.PIPE, shell=True)
commit_id = temp.stdout.read()[:8]
dirty = False
temp = subprocess.Popen(GIT_DIRTY, stdout=subprocess.PIPE, shell=True)
if temp.stdout.read()[-2] == '+':
dirty = True #commit_id = commit_id + '+'
# get date
day = datetime.datetime.today().day
mon = datetime.datetime.today().month
year = datetime.datetime.today().year
date = int(str(year*10000 + mon*100 + day), 16) # strange, I know, but I want to have something like x"20140917"
# convert version
ver = int(args.ver.translate(None, '.,'), 16)
# fill this all to the structure
write_sdb_info(f, MAIN_SYN, args.project, commit_id, dirty, args.tool, ver, date, args.user)
### Now generate synthesis info for each submodule
temp = subprocess.Popen("(cd "+toplevel+"; git submodule status)", stdout=subprocess.PIPE, shell=True)
submodules = temp.stdout.read()
submodules = submodules.split('\n')
for module in submodules[:-1]:
mod_splited = module.split()
name = mod_splited[1].split('/')[-1]
# if submodule is ahead of a set commit it displays additional _+_ at the
# beginning, get rid of that:
commit_id = mod_splited[0].translate(None, '+')[:8]
# check if dirty
dirty = False
temp = subprocess.Popen("(cd "+toplevel+"/"+mod_splited[1]+ ";" + GIT_DIRTY +")",
stdout=subprocess.PIPE, shell=True)
if temp.stdout.read()[-2] == '+':
dirty = True
write_sdb_info(f, name, name, commit_id, dirty, " ", 0, 0, " ")
f.write(PKG_TAIL)
f.close()
if __name__ == '__main__':
main()
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------------------------------------------------------------------------------
-- Title : Atmel EBI asynchronous bus <-> Wishbone bridge
-- Project : White Rabbit Switch
------------------------------------------------------------------------------
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-05-18
-- Last update: 2017-02-08
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: An interface between AT91SAM9x-series ARM CPU External Bus Interface
-- and FPGA-internal Wishbone bus:
-- - does clock domain synchronisation
-- - provides configurable number of independent WB master ports at fixed base addresses
-- TODO:
-- - implement write queueing and read prefetching (for speed improvement)
-------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-05-18 1.0 twlostow Created
-------------------------------------------------------------------------------
-- 2017-02-08 1.1 INCAA Computers Added ACK timeout
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity wb_cpu_bridge is
generic (
g_simulation : integer := 0;
g_cpu_addr_width : integer := 19;
g_wishbone_addr_width : integer := 19;
g_ACK_TIMEOUT : positive := 100 -- Wishbone ACK timeout (in wb_clk cycles)
);
port(
sys_rst_n_i : in std_logic; -- global reset
-------------------------------------------------------------------------------
-- Atmel EBI bus
-------------------------------------------------------------------------------
cpu_clk_i : in std_logic; -- clock (not used now)
-- async chip select, active LOW
cpu_cs_n_i : in std_logic;
-- async write, active LOW
cpu_wr_n_i : in std_logic;
-- async read, active LOW
cpu_rd_n_i : in std_logic;
-- byte select, active LOW (not used due to weird CPU pin layout - NBS2 line is
-- shared with 100 Mbps Ethernet PHY)
cpu_bs_n_i : in std_logic_vector(3 downto 0);
-- address input
cpu_addr_i : in std_logic_vector(g_cpu_addr_width-1 downto 0);
-- data bus (bidirectional)
cpu_data_b : inout std_logic_vector(31 downto 0);
-- async wait, active LOW
cpu_nwait_o : out std_logic;
-------------------------------------------------------------------------------
-- Wishbone master I/F
-------------------------------------------------------------------------------
-- wishbone clock input (refclk/2)
wb_clk_i : in std_logic;
-- wishbone master address output (m->s, common for all slaves)
wb_addr_o : out std_logic_vector(g_wishbone_addr_width - 1 downto 0);
-- wishbone master data output (m->s, common for all slaves)
wb_data_o : out std_logic_vector(31 downto 0);
-- wishbone cycle strobe (m->s, common for all slaves)
wb_stb_o : out std_logic;
-- wishbone write enable (m->s, common for all slaves)
wb_we_o : out std_logic;
-- wishbone byte select output (m->s, common for all slaves)
wb_sel_o : out std_logic_vector(3 downto 0);
-- wishbone cycle select (m->s, individual)
wb_cyc_o : out std_logic;
-- wishbone master data input (s->m, individual)
wb_data_i : in std_logic_vector(31 downto 0);
-- wishbone ACK input (s->m, individual)
wb_ack_i : in std_logic
);
end wb_cpu_bridge;
architecture behavioral of wb_cpu_bridge is
signal rw_sel, cycle_in_progress, cs_synced, rd_pulse, wr_pulse : std_logic;
signal cpu_data_reg : std_logic_vector(31 downto 0);
signal ack_muxed : std_logic;
signal data_in_muxed : std_logic_vector(31 downto 0);
signal long_cycle : std_logic;
signal wb_cyc_int : std_logic;
signal wb_ack_timeout_cnt : unsigned(log2_ceil(g_ACK_TIMEOUT)-1 downto 0);
signal wb_ack_timeout : std_logic;
begin
gen_sync_chains_nosim : if(g_simulation = 0) generate
sync_ffs_cs : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map
(rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_cs_n_i,
synced_o => cs_synced,
npulse_o => open
);
sync_ffs_wr : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_wr_n_i,
synced_o => open,
npulse_o => wr_pulse
);
sync_ffs_rd : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => '1',
clk_i => wb_clk_i,
data_i => cpu_rd_n_i,
synced_o => open,
npulse_o => rd_pulse
);
end generate gen_sync_chains_nosim;
gen_sim : if(g_simulation = 1) generate
wr_pulse <= not cpu_wr_n_i;
rd_pulse <= not cpu_rd_n_i;
cs_synced <= cpu_cs_n_i;
end generate gen_sim;
ack_muxed <= wb_ack_i;
data_in_muxed <= wb_data_i;
process(wb_clk_i)
begin
if(rising_edge(wb_clk_i)) then
if(sys_rst_n_i = '0') then
cpu_data_reg <= (others => '0');
cycle_in_progress <= '0';
rw_sel <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
wb_addr_o <= (others => '0');
wb_data_o <= (others => '0');
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
wb_cyc_int <= '0';
else
if(cs_synced = '0') then
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
if(cycle_in_progress = '1') then
if((ack_muxed = '1') or (wb_ack_timeout = '1')) then
if(rw_sel = '0') then
cpu_data_reg <= data_in_muxed;
end if;
cycle_in_progress <= '0';
wb_cyc_int <= '0';
wb_sel_o <= (others => '1');
wb_stb_o <= '0';
wb_we_o <= '0';
cpu_nwait_o <= '1';
long_cycle <= '0';
else
cpu_nwait_o <= not long_cycle;
long_cycle <= '1';
end if;
elsif(rd_pulse = '1' or wr_pulse = '1') then
wb_we_o <= wr_pulse;
rw_sel <= wr_pulse;
wb_cyc_int <= '1';
wb_stb_o <= '1';
wb_addr_o <= cpu_addr_i(g_wishbone_addr_width-1 downto 0);
long_cycle <= '0';
if(wr_pulse = '1') then
wb_data_o <= cpu_data_b;
end if;
cycle_in_progress <= '1';
end if;
end if;
end if;
end if;
end process;
process(cpu_cs_n_i, cpu_rd_n_i, cpu_data_reg)
begin
if(cpu_cs_n_i = '0' and cpu_rd_n_i = '0') then
cpu_data_b <= cpu_data_reg;
else
cpu_data_b <= (others => 'Z');
end if;
end process;
wb_cyc_o <= wb_cyc_int;
-- ACK timeout
p_wb_ack_timeout_cnt : process (wb_clk_i, sys_rst_n_i)
begin
if rising_edge(wb_clk_i) then
if (sys_rst_n_i = '0') then
wb_ack_timeout_cnt <= (others => '1');
else
if (cycle_in_progress = '1') then
if wb_ack_timeout_cnt /= 0 then
wb_ack_timeout_cnt <= wb_ack_timeout_cnt - 1;
end if;
else
wb_ack_timeout_cnt <= (others => '1');
end if;
end if;
end if;
end process p_wb_ack_timeout_cnt;
p_ack_timeout : process (wb_clk_i, sys_rst_n_i)
begin
if rising_edge(wb_clk_i) then
if (sys_rst_n_i = '0') then
wb_ack_timeout <= '0';
else
if (wb_ack_timeout_cnt = 0) then
wb_ack_timeout <= '1';
else
wb_ack_timeout <= '0';
end if;
end if;
end if;
end process p_ack_timeout;
end behavioral;
-------------------------------------------------------------------------------
-- Title : WR Switch bare top level for simulation
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : scb_top_sim.vhd
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2014-02-05
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Bare switch top module, without GTX transceivers and CPU bridge. Used as a
-- simulation top module.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2014 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
use work.wrsw_top_pkg.all;
use work.disparity_gen_pkg.all;
entity scb_top_sim is
generic(
g_num_ports : integer := 6;
g_with_TRU : boolean := true;
g_with_TATSU: boolean := true;
g_with_HWIU : boolean := true);
port (
sys_rst_n_i : in std_logic; -- global reset
-- Startup 25 MHz clock (from onboard 25 MHz oscillator)
clk_startup_i : in std_logic;
-- 125 MHz timing reference (from the AD9516 PLL output QDRII_CLK)
clk_ref_i : in std_logic;
-- 125+ MHz DMTD offset clock (from the CDCM62001 PLL output DMTDCLK_MAIN)
clk_dmtd_i : in std_logic;
-- 62.5 MHz system clock (from the AD9516 PLL output QDRII_200CLK)
-- clk_sys_i : in std_logic;
-- 200MHz clock to run the core of Multiport Memory in SWcore
clk_aux_i : in std_logic;
-------------------------------------------------------------------------------
-- Master wishbone bus (from the CPU bridge)
-------------------------------------------------------------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_irq_o : out std_logic;
-------------------------------------------------------------------------------
-- Timing I/O
-------------------------------------------------------------------------------
pps_i : in std_logic;
pps_o : out std_logic;
-- DAC Drive
dac_helper_sync_n_o : out std_logic;
dac_helper_sclk_o : out std_logic;
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_n_o : out std_logic;
pll_reset_n_o : out std_logic;
uart_txd_o : out std_logic;
uart_rxd_i : in std_logic;
-------------------------------------------------------------------------------
-- Clock fanout control
-------------------------------------------------------------------------------
clk_en_o : out std_logic;
clk_sel_o : out std_logic;
---------------------------------------------------------------------------
-- GTX ports
---------------------------------------------------------------------------
td_o : out std_logic_vector(18 * g_num_ports-1 downto 0);
rd_i : in std_logic_vector(18 * g_num_ports-1 downto 0);
rbclk_i : in std_logic_vector(g_num_ports-1 downto 0);
phys_rdy_i : in std_logic_vector(g_num_ports-1 downto 0);
led_link_o : out std_logic_vector(g_num_ports-1 downto 0);
led_act_o : out std_logic_vector(g_num_ports-1 downto 0);
mbl_scl_b : inout std_logic_vector(1 downto 0);
mbl_sda_b : inout std_logic_vector(1 downto 0)
);
end scb_top_sim;
architecture rtl of scb_top_sim is
type t_8b10b_disparity_array is array (integer range <>) of t_8b10b_disparity;
signal cur_disp : t_8b10b_disparity_array(g_num_ports-1 downto 0);
signal cpu_wb_in : t_wishbone_slave_in;
signal cpu_wb_out : t_wishbone_slave_out;
signal phys_out : t_phyif_output_array(g_num_ports-1 downto 0);
signal phys_in : t_phyif_input_array(g_num_ports-1 downto 0);
signal cpu_irq_n : std_logic;
signal i2c_scl_oen : std_logic_vector(2 downto 0);
signal i2c_scl_out : std_logic_vector(2 downto 0);
signal i2c_scl_in : std_logic_vector(2 downto 0);
signal i2c_sda_oen : std_logic_vector(2 downto 0);
signal i2c_sda_out : std_logic_vector(2 downto 0);
signal i2c_sda_in : std_logic_vector(2 downto 0);
begin -- rtl
gen_i2c_tribufs : for i in 0 to 1 generate
mbl_scl_b(i) <= i2c_scl_out(i) when i2c_scl_oen(i) = '0' else 'Z';
mbl_sda_b(i) <= i2c_sda_out(i) when i2c_sda_oen(i) = '0' else 'Z';
end generate gen_i2c_tribufs;
cpu_wb_in.adr <= wb_adr_i;
cpu_wb_in.dat <= wb_dat_i;
cpu_wb_in.cyc <= wb_cyc_i;
cpu_wb_in.sel <= wb_sel_i;
cpu_wb_in.we <= wb_we_i;
cpu_wb_in.stb <= wb_stb_i;
wb_ack_o <= cpu_wb_out.ack;
wb_stall_o <= cpu_wb_out.stall;
wb_irq_o <= not cpu_irq_n;
wb_dat_o <= cpu_wb_out.dat;
U_Wrapped_SCBCore : scb_top_bare
generic map (
g_num_ports => g_num_ports,
g_simulation => true,
g_without_network => false,
g_with_TRU => g_with_TRU,
g_with_TATSU => g_with_TATSU,
g_with_HWIU => g_with_HWIU,
g_with_watchdog => true)
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_startup_i,
clk_ref_i => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
-- clk_sys_i => clk_sys_i,
clk_aux_i => clk_aux_i,
clk_ext_mul_i => '0',
clk_ext_mul_locked_i=> '1',
cpu_wb_i => cpu_wb_in,
cpu_wb_o => cpu_wb_out,
cpu_irq_n_o => cpu_irq_n,
pps_i => pps_i,
pps_o => pps_o,
dac_helper_sync_n_o => dac_helper_sync_n_o,
dac_helper_sclk_o => dac_helper_sclk_o,
dac_helper_data_o => dac_helper_data_o,
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
pll_status_i => pll_status_i,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
pll_cs_n_o => pll_cs_n_o,
pll_sync_n_o => pll_sync_n_o,
pll_reset_n_o => pll_reset_n_o,
uart_txd_o => uart_txd_o,
uart_rxd_i => uart_rxd_i,
clk_en_o => clk_en_o,
clk_sel_o => clk_sel_o,
phys_o => phys_out,
phys_i => phys_in,
led_link_o => led_link_o,
led_act_o => led_act_o,
gpio_o => open,
gpio_i => (others => '0'),
i2c_scl_oen_o => i2c_scl_oen,
i2c_scl_o => i2c_scl_out,
i2c_scl_i => i2c_scl_in,
i2c_sda_oen_o => i2c_sda_oen,
i2c_sda_o => i2c_sda_out,
i2c_sda_i => i2c_sda_in
);
gen_phys : for i in 0 to g_num_ports-1 generate
td_o(18 * i + 15 downto 18 * i) <= phys_out(i).tx_data;
td_o(18 * i + 17 downto 18 * i + 16) <= phys_out(i).tx_k;
phys_in(i).ref_clk <= clk_ref_i;
phys_in(i).rx_data <= rd_i(18 * i + 15 downto 18 * i);
phys_in(i).rx_k <= rd_i(18 * i + 17 downto 18 * i + 16);
phys_in(i).rx_clk <= rbclk_i(i);
phys_in(i).tx_enc_err <= '0';
phys_in(i).rx_enc_err <= '0';
phys_in(i).rdy <= phys_rdy_i(i);
p_gen_tx_disparity : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
if phys_out(i).rst = '1' then
cur_disp(i) <= RD_MINUS;
else
cur_disp(i) <= f_next_8b10b_disparity16(cur_disp(i), phys_out(i).tx_k, phys_out(i).tx_data);
end if;
end if;
end process;
phys_in(i).tx_disparity <= to_std_logic(cur_disp(i));
end generate gen_phys;
end rtl;
-- file: swcore_pll.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1___187.500______0.000______50.0______266.979____459.961
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary____________62.5____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity swcore_pll is
port
(-- Clock in ports
clk_sys_i : in std_logic;
-- Clock out ports
clk_aux_o : out std_logic
);
end swcore_pll;
architecture xilinx of swcore_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "swcore_pll,clk_wiz_v4_1,{component_name=swcore_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=16.000,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : BUFG
port map
(O => clkin1,
I => clk_sys_i);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCM_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 4,
CLKFBOUT_MULT_F => 63.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 5.250,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_unused,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
-- Output buffering
-------------------------------------
clkout1_buf : BUFG
port map
(O => clk_aux_o,
I => clkout0);
end xilinx;
-- package generated automatically by gen_sdbsyn.py script --
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package synthesis_descriptor is
constant c_sdb_repo_url : t_sdb_repo_url := (
repo_url => "git://ohwr.org/white-rabbit/wr-switch-hdl.git ");
constant c_sdb_top_syn_info : t_sdb_synthesis := (
syn_module_name => "WRS_18p ",
syn_commit_id => "1d500455 ",
syn_tool_name => "ISE ",
syn_tool_version => x"00000146",
syn_date => x"20170120",
syn_username => "Rene Bakker ");
constant c_sdb_general_cores_syn_info : t_sdb_synthesis := (
syn_module_name => "general-cores ",
syn_commit_id => "9c2a6c16 ",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
constant c_sdb_wr_cores_syn_info : t_sdb_synthesis := (
syn_module_name => "wr-cores ",
syn_commit_id => "3c2a6c72 ",
syn_tool_name => " ",
syn_tool_version => x"00000000",
syn_date => x"00000000",
syn_username => " ");
end package;
\ No newline at end of file
-- file: syst_mon.vhd
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity syst_mon is
port (
DADDR_IN : in STD_LOGIC_VECTOR (6 downto 0); -- Address bus for the dynamic reconfiguration port
DCLK_IN : in STD_LOGIC; -- Clock input for the dynamic reconfiguration port
DEN_IN : in STD_LOGIC; -- Enable Signal for the dynamic reconfiguration port
DI_IN : in STD_LOGIC_VECTOR (15 downto 0); -- Input data bus for the dynamic reconfiguration port
DWE_IN : in STD_LOGIC; -- Write Enable for the dynamic reconfiguration port
RESET_IN : in STD_LOGIC; -- Reset signal for the System Monitor control logic
VAUXP0 : in STD_LOGIC; -- Auxiliary Channel 0
VAUXN0 : in STD_LOGIC;
VAUXP1 : in STD_LOGIC; -- Auxiliary Channel 1
VAUXN1 : in STD_LOGIC;
VAUXP2 : in STD_LOGIC; -- Auxiliary Channel 2
VAUXN2 : in STD_LOGIC;
VAUXP3 : in STD_LOGIC; -- Auxiliary Channel 3
VAUXN3 : in STD_LOGIC;
VAUXP4 : in STD_LOGIC; -- Auxiliary Channel 4
VAUXN4 : in STD_LOGIC;
VAUXP5 : in STD_LOGIC; -- Auxiliary Channel 5
VAUXN5 : in STD_LOGIC;
VAUXP6 : in STD_LOGIC; -- Auxiliary Channel 6
VAUXN6 : in STD_LOGIC;
VAUXP7 : in STD_LOGIC; -- Auxiliary Channel 7
VAUXN7 : in STD_LOGIC;
BUSY_OUT : out STD_LOGIC; -- ADC Busy signal
CHANNEL_OUT : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
DO_OUT : out STD_LOGIC_VECTOR (15 downto 0); -- Output data bus for dynamic reconfiguration port
DRDY_OUT : out STD_LOGIC; -- Data ready signal for the dynamic reconfiguration port
EOC_OUT : out STD_LOGIC; -- End of Conversion Signal
EOS_OUT : out STD_LOGIC; -- End of Sequence Signal
VP_IN : in STD_LOGIC; -- Dedicated Analog Input Pair
VN_IN : in STD_LOGIC
);
end syst_mon;
architecture xilinx of syst_mon is
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of xilinx : architecture is "sysmon_wiz_v2_1, Coregen 12.4";
signal aux_channel_p : std_logic_vector (15 downto 0);
signal aux_channel_n : std_logic_vector (15 downto 0);
begin
aux_channel_p(0) <= VAUXP0;
aux_channel_n(0) <= VAUXN0;
aux_channel_p(1) <= VAUXP1;
aux_channel_n(1) <= VAUXN1;
aux_channel_p(2) <= VAUXP2;
aux_channel_n(2) <= VAUXN2;
aux_channel_p(3) <= VAUXP3;
aux_channel_n(3) <= VAUXN3;
aux_channel_p(4) <= VAUXP4;
aux_channel_n(4) <= VAUXN4;
aux_channel_p(5) <= VAUXP5;
aux_channel_n(5) <= VAUXN5;
aux_channel_p(6) <= VAUXP6;
aux_channel_n(6) <= VAUXN6;
aux_channel_p(7) <= VAUXP7;
aux_channel_n(7) <= VAUXN7;
aux_channel_p(8) <= '0';
aux_channel_n(8) <= '0';
aux_channel_p(9) <= '0';
aux_channel_n(9) <= '0';
aux_channel_p(10) <= '0';
aux_channel_n(10) <= '0';
aux_channel_p(11) <= '0';
aux_channel_n(11) <= '0';
aux_channel_p(12) <= '0';
aux_channel_n(12) <= '0';
aux_channel_p(13) <= '0';
aux_channel_n(13) <= '0';
aux_channel_p(14) <= '0';
aux_channel_n(14) <= '0';
aux_channel_p(15) <= '0';
aux_channel_n(15) <= '0';
SYSMON_INST : SYSMON
generic map(
INIT_40 => X"1000", -- config reg 0
INIT_41 => X"20ff", -- config reg 1
INIT_42 => X"0d00", -- config reg 2
INIT_48 => X"0701", -- Sequencer channel selection
INIT_49 => X"00ff", -- Sequencer channel selection
INIT_4A => X"0700", -- Sequencer Average selection
INIT_4B => X"00ff", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"b5ed", -- Temp alarm trigger
INIT_51 => X"5999", -- Vccint upper alarm limit
INIT_52 => X"e000", -- Vccaux upper alarm limit
INIT_53 => X"ca33", -- Temp alarm OT upper
INIT_54 => X"a93a", -- Temp alarm reset
INIT_55 => X"5111", -- Vccint lower alarm limit
INIT_56 => X"caaa", -- Vccaux lower alarm limit
INIT_57 => X"ae4e", -- Temp alarm OT reset
SIM_DEVICE => "VIRTEX6",
SIM_MONITOR_FILE => "design.txt"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR(6 downto 0) => DADDR_IN(6 downto 0),
DCLK => DCLK_IN,
DEN => DEN_IN,
DI(15 downto 0) => DI_IN(15 downto 0),
DWE => DWE_IN,
RESET => RESET_IN,
VAUXN(15 downto 0) => aux_channel_n(15 downto 0),
VAUXP(15 downto 0) => aux_channel_p(15 downto 0),
ALM(2) => open,
ALM(1) => open,
ALM(0) => open,
BUSY => BUSY_OUT,
CHANNEL(4 downto 0) => CHANNEL_OUT(4 downto 0),
DO(15 downto 0) => DO_OUT(15 downto 0),
DRDY => DRDY_OUT,
EOC => EOC_OUT,
EOS => EOS_OUT,
JTAGBUSY => open,
JTAGLOCKED => open,
JTAGMODIFIED => open,
OT => open,
VN => VP_IN,
VP => VN_IN
);
end xilinx;
#!/bin/bash
wbgen2 -D ./wb_freq_regs.html -V wb_freq_regs.vhd --hstyle record -p freq_wbgen2_pkg.vhd wb_freq_regs.wb
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#!/bin/sh
ipinfo="$eth0.ipaddr:$eth0.serverip:$eth0.gateway:$eth0.netmask:wrs:eth0"
bootargs="console=ttyS0,115200 panic=10 mem=64m"
bootargs="$bootargs root=/dev/nfs nfsroot=/tftpboot/rootfs/ rw ip=$ipinfo"
tftp zImage /dev/mem.kernel
bootz /dev/mem.kernel
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/* PTS COM port test
*
* COM port replyer for WRS hardware PTS
*
* Created on: January, 2017
* Authors:
* - INCAA Computers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed for the WRS PTS
*
* You should have received a copy of the GNU General Public License...
*/
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
int main(int argc, char **argv)
{
if (strcmp(argv[1], "CAFEBABE") == 0)
printf("DEADBEEF\n");
else
printf("error\n");
return 0;
}
\ No newline at end of file
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int ad9516_set_output_divider(int output, int ratio, int phase_offset);
int ad9516_init(void);
void ad9516_set_reg(int reg, int val);
int ad9516_read_reg(int reg);
\ No newline at end of file
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from Utilities import *
from Item import *
"""This class manages a generic waveform generator."""
class Generator(Item):
def get(self, what):
"""Get an attribute value. Supports Pyro4."""
return self.__getattribute__(what)
def set(self, what, how):
"""Set an attribute value. Supports Pyro4."""
self.__setattr__(what, how)
# this dictionary is used to map data types into function which can
# translate such type of data into something the generator can understand.
adaptDict = {}
def adaptKeys(self):
"""Returns all data types supported."""
return self.adaptDict.keys()
def adapt(self, wave, *args, **kwargs):
"""Adapt a wave to the generator"""
return self.adaptDict[type(wave)](wave, *args, **kwargs)
def __init__(self, *args, **kwargs):
Item.__init__(self, *args, **kwargs)
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scb_serial: 214
scb_batch: 3
fpga_type: LX240T
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