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White Rabbit Switch - Software
Commit e0469d52 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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softpll: update header file to follow latest changes in ext SPLL

parent cbe4d923
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Showing with 263 additions and 199 deletions
kernel/wbgen-regs/softpll-regs.h
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kernel/wbgen-regs/softpll-regs.wb
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...@@ -9,16 +9,15 @@ peripheral { ...@@ -9,16 +9,15 @@ peripheral {
name = "SPLL Control/Status Register"; name = "SPLL Control/Status Register";
prefix = "CSR"; prefix = "CSR";
field {
align = 8;
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = CONSTANT;
value = 0;
};
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field { field {
align = 8; align = 8;
...@@ -41,11 +40,11 @@ peripheral { ...@@ -41,11 +40,11 @@ peripheral {
}; };
field { field {
name = "Enable Period Measurement"; name = "Debug queue supported";
prefix = "PER_EN"; prefix = "DBG_SUPPORTED";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_ONLY;
access_dev = READ_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
...@@ -55,17 +54,15 @@ peripheral { ...@@ -55,17 +54,15 @@ peripheral {
reg { reg {
name = "External Clock Control Register"; name = "External Clock Control Register";
prefix = "ECCR"; prefix = "ECCR";
field { field {
name = "Enable External Clock BB Detector"; name = "Enable External Clock PLL";
prefix = "EXT_EN"; prefix = "EXT_EN";
type = BIT; type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_ONLY;
}; };
field { field {
name = "External Clock Input Available"; name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\ description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
...@@ -76,28 +73,6 @@ peripheral { ...@@ -76,28 +73,6 @@ peripheral {
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field { field {
name = "External Clock Reference Present"; name = "External Clock Reference Present";
description = "1: Reference clock present on the input\ description = "1: Reference clock present on the input\
...@@ -107,73 +82,98 @@ peripheral { ...@@ -107,73 +82,98 @@ peripheral {
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
}; };
--------------------------------------------- reg {
-- DMTD gating/undersampling configuration name = "Aligner Control Register";
--------------------------------------------- prefix = "AL_CR";
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
field { field {
name = "DMTD Clock Undersampling Divider"; name = "Aligner sample valid/select on channel";
prefix = "GATE_DIV"; prefix = "VALID";
size = 6; type = SLV;
type = SLV; size = 9;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_WRITE;
}; load = LOAD_EXT;
}; };
field {
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg { reg {
name = "Reference Channel Undersampling Enable Register"; name = "Aligner Counter REF register";
prefix = "RCGER"; prefix = "AL_CREF";
field { field {
name = "Reference Channel Undersampling Enable"; name = "Aligner reference counter";
prefix = "GATE_SEL"; type = SLV;
size = 32; size = 32;
type = PASS_THROUGH; access_bus = READ_ONLY;
}; access_dev = WRITE_ONLY;
};
}; };
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg { reg {
name = "Output Channel Control Register"; name = "DMTD VCO Frequency";
prefix = "OCCR"; prefix = "F_DMTD";
field { field {
align = 8; name = "FREQ";
name = "Output Channel HW enable flag"; prefix = "FREQ";
prefix = "OUT_EN";
type = SLV; type = SLV;
size = 8; size = 28;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
}; };
field { field {
name = "Output Channel locked flag"; name = "VALID";
prefix = "OUT_LOCK"; prefix = "VALID";
type = SLV; type = BIT;
size = 8;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_ONLY; access_dev = READ_WRITE;
load = LOAD_EXT;
}; };
}; };
reg { reg {
name = "Reference Channel Enable Register"; name = "REF VCO Frequency";
prefix = "RCER"; prefix = "F_REF";
field { field {
name = "Reference Channel Enable"; name = "FREQ";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\ prefix = "FREQ";
write 0: disables tag generation";
type = SLV; type = SLV;
size = 32; size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
...@@ -181,47 +181,87 @@ peripheral { ...@@ -181,47 +181,87 @@ peripheral {
}; };
reg { reg {
name = "Output Channel Enable Register"; name = "EXT VCO Frequency";
prefix = "OCER"; prefix = "F_EXT";
field { field {
name = "Output Channel Enable"; name = "FREQ";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\ prefix = "FREQ";
write 0: disables tag generation";
type = SLV; type = SLV;
size = 8; size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE; access_bus = READ_WRITE;
access_dev = READ_WRITE; access_dev = READ_WRITE;
load = LOAD_EXT; load = LOAD_EXT;
}; };
}; };
reg { reg {
name = "HPLL Period Error"; align = 4;
prefix = "PER_HPLL"; name = "Output Channel Control Register";
prefix = "OCCR";
field { field {
name = "Period error value"; align = 8;
prefix = "ERROR"; name = "Output Channel HW enable flag";
prefix = "OUT_EN";
type = SLV; type = SLV;
size = 16; size = 8;
access_bus = READ_ONLY; access_bus = READ_ONLY;
access_dev = WRITE_ONLY; access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
}; };
field { field {
name = "Period Error Valid"; name = "Output Channel locked flag";
prefix = "VALID"; prefix = "OUT_LOCK";
type = BIT; type = SLV;
access_bus = READ_ONLY; size = 8;
access_dev = WRITE_ONLY; access_bus = READ_WRITE;
}; access_dev = READ_ONLY;
};
}; };
reg { reg {
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
align = 8;
name = "Helper DAC Output"; name = "Helper DAC Output";
prefix = "DAC_HPLL"; prefix = "DAC_HPLL";
...@@ -253,7 +293,7 @@ peripheral { ...@@ -253,7 +293,7 @@ peripheral {
}; };
reg { reg {
name = "Deglitcher threshold"; name = "DDMTD Deglitcher threshold";
prefix = "DEGLITCH_THR"; prefix = "DEGLITCH_THR";
field { field {
...@@ -284,12 +324,15 @@ peripheral { ...@@ -284,12 +324,15 @@ peripheral {
}; };
}; };
fifo_reg { fifo_reg {
name = "Debug FIFO Register - Host side"; name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST"; prefix = "DFR_HOST";
direction = CORE_TO_BUS; direction = CORE_TO_BUS;
size = 8192; size = 8192;
optional = "g_with_debug_fifo";
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT}; flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
...@@ -340,7 +383,6 @@ peripheral { ...@@ -340,7 +383,6 @@ peripheral {
}; };
irq { irq {
name = "Got a tag"; name = "Got a tag";
prefix = "TAG"; prefix = "TAG";
......
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