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White Rabbit Switch - Software
Commit e0469d52 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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softpll: update header file to follow latest changes in ext SPLL

parent cbe4d923
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kernel/wbgen-regs/softpll-regs.h
View file @ e0469d52
/*
Register definitions for slave core: WR Softcore PLL
* File : softpll-regs.h
* Author : auto-generated by wbgen2 from softpll-regs.wb
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from spll_wb_slave.wb
* Created : Mon Jul 21 13:49:11 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE softpll-regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SOFTPLL
#define __WBGEN2_REGDEFS_SOFTPLL
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#ifndef __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#define __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -37,88 +33,106 @@
/* definitions for register: SPLL Control/Status Register */
/* definitions for field: Period detector reference select in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_SEL_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_CSR_PER_SEL_SHIFT 0
#define SPLL_CSR_PER_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_CSR_PER_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for field: Unused (kept for software compatibility). in reg: SPLL Control/Status Register */
#define SPLL_CSR_UNUSED0_MASK WBGEN2_GEN_MASK(8, 6)
#define SPLL_CSR_UNUSED0_SHIFT 8
#define SPLL_CSR_UNUSED0_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define SPLL_CSR_UNUSED0_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Number of reference channels (max: 32) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_REF_MASK WBGEN2_GEN_MASK(8, 6)
#define SPLL_CSR_N_REF_SHIFT 8
#define SPLL_CSR_N_REF_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define SPLL_CSR_N_REF_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
#define SPLL_CSR_N_REF_MASK WBGEN2_GEN_MASK(16, 6)
#define SPLL_CSR_N_REF_SHIFT 16
#define SPLL_CSR_N_REF_W(value) WBGEN2_GEN_WRITE(value, 16, 6)
#define SPLL_CSR_N_REF_R(reg) WBGEN2_GEN_READ(reg, 16, 6)
/* definitions for field: Number of output channels (max: 8) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_OUT_MASK WBGEN2_GEN_MASK(16, 3)
#define SPLL_CSR_N_OUT_SHIFT 16
#define SPLL_CSR_N_OUT_W(value) WBGEN2_GEN_WRITE(value, 16, 3)
#define SPLL_CSR_N_OUT_R(reg) WBGEN2_GEN_READ(reg, 16, 3)
#define SPLL_CSR_N_OUT_MASK WBGEN2_GEN_MASK(24, 3)
#define SPLL_CSR_N_OUT_SHIFT 24
#define SPLL_CSR_N_OUT_W(value) WBGEN2_GEN_WRITE(value, 24, 3)
#define SPLL_CSR_N_OUT_R(reg) WBGEN2_GEN_READ(reg, 24, 3)
/* definitions for field: Enable Period Measurement in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_EN WBGEN2_GEN_MASK(19, 1)
/* definitions for field: Debug queue supported in reg: SPLL Control/Status Register */
#define SPLL_CSR_DBG_SUPPORTED WBGEN2_GEN_MASK(27, 1)
/* definitions for register: External Clock Control Register */
/* definitions for field: Enable External Clock BB Detector in reg: External Clock Control Register */
/* definitions for field: Enable External Clock PLL in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Clock Input Available in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_SUPPORTED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Enable PPS/phase alignment in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_EN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: External Clock Reference Present in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_REF_PRESENT WBGEN2_GEN_MASK(2, 1)
/* definitions for field: PPS/phase alignment done in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Aligner Control Register */
/* definitions for field: External Clock Reference Present in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_REF_PRESENT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Aligner sample valid/select on channel in reg: Aligner Control Register */
#define SPLL_AL_CR_VALID_MASK WBGEN2_GEN_MASK(0, 9)
#define SPLL_AL_CR_VALID_SHIFT 0
#define SPLL_AL_CR_VALID_W(value) WBGEN2_GEN_WRITE(value, 0, 9)
#define SPLL_AL_CR_VALID_R(reg) WBGEN2_GEN_READ(reg, 0, 9)
/* definitions for register: DMTD Clock Control Register */
/* definitions for field: Aligner required on channel in reg: Aligner Control Register */
#define SPLL_AL_CR_REQUIRED_MASK WBGEN2_GEN_MASK(9, 9)
#define SPLL_AL_CR_REQUIRED_SHIFT 9
#define SPLL_AL_CR_REQUIRED_W(value) WBGEN2_GEN_WRITE(value, 9, 9)
#define SPLL_AL_CR_REQUIRED_R(reg) WBGEN2_GEN_READ(reg, 9, 9)
/* definitions for field: DMTD Clock Undersampling Divider in reg: DMTD Clock Control Register */
#define SPLL_DCCR_GATE_DIV_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_DCCR_GATE_DIV_SHIFT 0
#define SPLL_DCCR_GATE_DIV_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_DCCR_GATE_DIV_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for register: Aligner Counter REF register */
/* definitions for register: Reference Channel Undersampling Enable Register */
/* definitions for register: Aligner Counter IN register */
/* definitions for field: Reference Channel Undersampling Enable in reg: Reference Channel Undersampling Enable Register */
#define SPLL_RCGER_GATE_SEL_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_RCGER_GATE_SEL_SHIFT 0
#define SPLL_RCGER_GATE_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SPLL_RCGER_GATE_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: DMTD VCO Frequency */
/* definitions for register: Output Channel Control Register */
/* definitions for field: FREQ in reg: DMTD VCO Frequency */
#define SPLL_F_DMTD_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
#define SPLL_F_DMTD_FREQ_SHIFT 0
#define SPLL_F_DMTD_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SPLL_F_DMTD_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Output Channel HW enable flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_EN_MASK WBGEN2_GEN_MASK(0, 8)
#define SPLL_OCCR_OUT_EN_SHIFT 0
#define SPLL_OCCR_OUT_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SPLL_OCCR_OUT_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: VALID in reg: DMTD VCO Frequency */
#define SPLL_F_DMTD_VALID WBGEN2_GEN_MASK(28, 1)
/* definitions for field: Output Channel locked flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_LOCK_MASK WBGEN2_GEN_MASK(8, 8)
#define SPLL_OCCR_OUT_LOCK_SHIFT 8
#define SPLL_OCCR_OUT_LOCK_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define SPLL_OCCR_OUT_LOCK_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: REF VCO Frequency */
/* definitions for field: FREQ in reg: REF VCO Frequency */
#define SPLL_F_REF_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
#define SPLL_F_REF_FREQ_SHIFT 0
#define SPLL_F_REF_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SPLL_F_REF_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for register: Reference Channel Enable Register */
/* definitions for field: VALID in reg: REF VCO Frequency */
#define SPLL_F_REF_VALID WBGEN2_GEN_MASK(28, 1)
/* definitions for register: Output Channel Enable Register */
/* definitions for register: EXT VCO Frequency */
/* definitions for register: HPLL Period Error */
/* definitions for field: FREQ in reg: EXT VCO Frequency */
#define SPLL_F_EXT_FREQ_MASK WBGEN2_GEN_MASK(0, 28)
#define SPLL_F_EXT_FREQ_SHIFT 0
#define SPLL_F_EXT_FREQ_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define SPLL_F_EXT_FREQ_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Period error value in reg: HPLL Period Error */
#define SPLL_PER_HPLL_ERROR_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_PER_HPLL_ERROR_SHIFT 0
#define SPLL_PER_HPLL_ERROR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_PER_HPLL_ERROR_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: VALID in reg: EXT VCO Frequency */
#define SPLL_F_EXT_VALID WBGEN2_GEN_MASK(28, 1)
/* definitions for field: Period Error Valid in reg: HPLL Period Error */
#define SPLL_PER_HPLL_VALID WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Output Channel Control Register */
/* definitions for field: Output Channel HW enable flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_EN_MASK WBGEN2_GEN_MASK(8, 8)
#define SPLL_OCCR_OUT_EN_SHIFT 8
#define SPLL_OCCR_OUT_EN_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define SPLL_OCCR_OUT_EN_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: Output Channel locked flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_LOCK_MASK WBGEN2_GEN_MASK(16, 8)
#define SPLL_OCCR_OUT_LOCK_SHIFT 16
#define SPLL_OCCR_OUT_LOCK_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define SPLL_OCCR_OUT_LOCK_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for register: Reference Channel Tagging Enable Register */
/* definitions for register: Output Channel Tagging Enable Register */
/* definitions for register: Helper DAC Output */
......@@ -136,7 +150,7 @@
#define SPLL_DAC_MAIN_DAC_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define SPLL_DAC_MAIN_DAC_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for register: Deglitcher threshold */
/* definitions for register: DDMTD Deglitcher threshold */
/* definitions for register: Debug FIFO Register - SPLL side */
......@@ -229,45 +243,53 @@ PACKED struct SPLL_WB {
uint32_t CSR;
/* [0x4]: REG External Clock Control Register */
uint32_t ECCR;
/* [0x8]: REG DMTD Clock Control Register */
uint32_t DCCR;
/* [0xc]: REG Reference Channel Undersampling Enable Register */
uint32_t RCGER;
/* [0x10]: REG Output Channel Control Register */
/* [0x8]: REG Aligner Control Register */
uint32_t AL_CR;
/* [0xc]: REG Aligner Counter REF register */
uint32_t AL_CREF;
/* [0x10]: REG Aligner Counter IN register */
uint32_t AL_CIN;
/* [0x14]: REG DMTD VCO Frequency */
uint32_t F_DMTD;
/* [0x18]: REG REF VCO Frequency */
uint32_t F_REF;
/* [0x1c]: REG EXT VCO Frequency */
uint32_t F_EXT;
/* [0x20]: REG Output Channel Control Register */
uint32_t OCCR;
/* [0x14]: REG Reference Channel Enable Register */
/* [0x24]: REG Reference Channel Tagging Enable Register */
uint32_t RCER;
/* [0x18]: REG Output Channel Enable Register */
/* [0x28]: REG Output Channel Tagging Enable Register */
uint32_t OCER;
/* [0x1c]: REG HPLL Period Error */
uint32_t PER_HPLL;
/* [0x20]: REG Helper DAC Output */
/* padding to: 16 words */
uint32_t __padding_0[5];
/* [0x40]: REG Helper DAC Output */
uint32_t DAC_HPLL;
/* [0x24]: REG Main DAC Output */
/* [0x44]: REG Main DAC Output */
uint32_t DAC_MAIN;
/* [0x28]: REG Deglitcher threshold */
/* [0x48]: REG DDMTD Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* [0x2c]: REG Debug FIFO Register - SPLL side */
/* [0x4c]: REG Debug FIFO Register - SPLL side */
uint32_t DFR_SPLL;
/* padding to: 16 words */
uint32_t __padding_0[4];
/* [0x40]: REG Interrupt disable register */
/* padding to: 24 words */
uint32_t __padding_1[4];
/* [0x60]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
/* [0x64]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x48]: REG Interrupt mask register */
/* [0x68]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x4c]: REG Interrupt status register */
/* [0x6c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x50]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
/* [0x70]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
uint32_t DFR_HOST_R0;
/* [0x54]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
/* [0x74]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
uint32_t DFR_HOST_R1;
/* [0x58]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
/* [0x78]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
uint32_t DFR_HOST_CSR;
/* [0x5c]: REG FIFO 'Tag Readout Register' data output register 0 */
/* [0x7c]: REG FIFO 'Tag Readout Register' data output register 0 */
uint32_t TRR_R0;
/* [0x60]: REG FIFO 'Tag Readout Register' control/status register */
/* [0x80]: REG FIFO 'Tag Readout Register' control/status register */
uint32_t TRR_CSR;
};
......
kernel/wbgen-regs/softpll-regs.wb
View file @ e0469d52
......@@ -9,16 +9,15 @@ peripheral {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Unused (kept for software compatibility).";
prefix = "UNUSED0";
size = 6;
type = CONSTANT;
value = 0;
};
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
......@@ -41,11 +40,11 @@ peripheral {
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
name = "Debug queue supported";
prefix = "DBG_SUPPORTED";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -55,17 +54,15 @@ peripheral {
reg {
name = "External Clock Control Register";
prefix = "ECCR";
prefix = "ECCR";
field {
name = "Enable External Clock BB Detector";
field {
name = "Enable External Clock PLL";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
......@@ -76,28 +73,6 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
......@@ -107,73 +82,98 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
reg {
name = "Aligner Control Register";
prefix = "AL_CR";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
type = SLV;
field {
name = "Aligner sample valid/select on channel";
prefix = "VALID";
type = SLV;
size = 9;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Aligner required on channel";
prefix = "REQUIRED";
type = SLV;
size = 9;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
name = "Aligner Counter REF register";
prefix = "AL_CREF";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Aligner Counter IN register";
prefix = "AL_CIN";
field {
name = "Aligner reference counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Output Channel Control Register";
prefix = "OCCR";
name = "DMTD VCO Frequency";
prefix = "F_DMTD";
field {
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 8;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Reference Channel Enable Register";
prefix = "RCER";
name = "REF VCO Frequency";
prefix = "F_REF";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 32;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
......@@ -181,47 +181,87 @@ peripheral {
};
reg {
name = "Output Channel Enable Register";
prefix = "OCER";
name = "EXT VCO Frequency";
prefix = "F_EXT";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
name = "FREQ";
prefix = "FREQ";
type = SLV;
size = 8;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "VALID";
prefix = "VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
align = 4;
name = "Output Channel Control Register";
prefix = "OCCR";
field {
name = "Period error value";
prefix = "ERROR";
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
type = SLV;
size = 16;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
reg {
name = "Reference Channel Tagging Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Tagging Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
align = 8;
name = "Helper DAC Output";
prefix = "DAC_HPLL";
......@@ -253,7 +293,7 @@ peripheral {
};
reg {
name = "Deglitcher threshold";
name = "DDMTD Deglitcher threshold";
prefix = "DEGLITCH_THR";
field {
......@@ -284,12 +324,15 @@ peripheral {
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
optional = "g_with_debug_fifo";
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
......@@ -340,7 +383,6 @@ peripheral {
};
irq {
name = "Got a tag";
prefix = "TAG";
......
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