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White Rabbit Switch - Software
Commit c7cc124f authored by Alessandro Rubini's avatar Alessandro Rubini
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patches: horrible hack to make at91boot work

parent 52827212
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patches/at91boot/v3.3/0001-board-9g45ek-fix-ddr-config-for-WRS-V3.patch
View file @ c7cc124f
......@@ -23,3 +23,54 @@ index d6b10db..8569231 100644
--
1.5.6.5
--- ./include/AT91SAM9G45_inc.h.orig 2012-03-05 23:42:32.000000000 +0100
+++ ./include/AT91SAM9G45_inc.h 2012-03-05 23:45:23.000000000 +0100
@@ -267,7 +267,7 @@
#define AT91C_DDRC2_NC_DDR10_SDR9 (0x1) // (HDDRSDRC2) DDR 10 Bits | SDR 9 Bits
#define AT91C_DDRC2_NC_DDR11_SDR10 (0x2) // (HDDRSDRC2) DDR 11 Bits | SDR 10 Bits
#define AT91C_DDRC2_NC_DDR12_SDR11 (0x3) // (HDDRSDRC2) DDR 12 Bits | SDR 11 Bits
-#define AT91C_DDRC2_NR (0x3 << 2) // (HDDRSDRC2) Number of Row Bits
+#define AT91C_DDRC2_NR AT91C_DDRC2_NR_13 // (HDDRSDRC2) Number of Row Bits
#define AT91C_DDRC2_NR_11 (0x0 << 2) // (HDDRSDRC2) 11 Bits
#define AT91C_DDRC2_NR_12 (0x1 << 2) // (HDDRSDRC2) 12 Bits
#define AT91C_DDRC2_NR_13 (0x2 << 2) // (HDDRSDRC2) 13 Bits
--- ./driver/ddramc.c.orig 2012-03-05 23:57:36.000000000 +0100
+++ ./driver/ddramc.c 2012-03-05 23:57:40.000000000 +0100
@@ -126,7 +126,7 @@
write_ddramc(ddram_controller_address, HDDRSDRC2_MR,
AT91C_DDRC2_MODE_EXT_LMR_CMD);
/* Perform a write access to DDR address so that BA[1] is set to 1 and BA[0] is set to 0. */
- *((unsigned int *)(ddram_address + (0x2 << ba_offset))) = 0;
+ *((unsigned int *)(ddram_address + 0x4000000 /* (0x2 << ba_offset) */)) = 0;
// wait 2 cycles min (of tCK) = 15 ns min
Wait(2);
@@ -135,7 +135,7 @@
/* Perform a write access to DDR address so that BA[1] is set to 1 and BA[0] is set to 1. */
write_ddramc(ddram_controller_address, HDDRSDRC2_MR,
AT91C_DDRC2_MODE_EXT_LMR_CMD);
- *((unsigned int *)(ddram_address + (0x3 << ba_offset))) = 0;
+ *((unsigned int *)(ddram_address + 0x6000000 /* (0x3 << ba_offset) */)) = 0;
// wait 2 cycles min (of tCK) = 15 ns min
Wait(2);
@@ -144,7 +144,7 @@
/* Perform a write access to DDR address so that BA[1] is set to 0 and BA[0] is set to 1. */
write_ddramc(ddram_controller_address, HDDRSDRC2_MR,
AT91C_DDRC2_MODE_EXT_LMR_CMD);
- *((unsigned int *)(ddram_address + (0x1 << ba_offset))) = 0;
+ *((unsigned int *)(ddram_address + 0x2000000 /* (0x1 << ba_offset) */)) = 0;
// wait 200 cycles min (of tCK) = 1500 ns min
Wait(100);
--- ./crt0_gnu.S.orig 2012-03-06 00:08:35.000000000 +0100
+++ ./crt0_gnu.S 2012-03-06 00:08:49.000000000 +0100
@@ -56,7 +56,7 @@
b swi_vector /* Software Interrupt */
b pabt_vector /* Prefetch Abort */
b dabt_vector /* Data Abort */
-.word _edata /* Size of the image for SAM-BA */
+.word _edata - _exception_vectors /* Size of the image for SAM-BA */
b irq_vector /* IRQ : read the AIC */
b fiq_vector /* FIQ */
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