Commit b9e7a568 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Alessandro Rubini

added softpll debug tool (softpll_dbg_proxy)

parent c8fcda89
CC = $(CROSS_COMPILE)gcc
OBJS = spll_dbg_proxy.o
BINARY = spll_dbg_proxy
# We must include stuff from wr_ipc, which is installed.
# If this is build under build scripts, it's $WRS_OUTPUT_DIR/images/wr
WR_INSTALL_ROOT ?= /usr/lib/white-rabbit
WR_INCLUDE = $(WR_INSTALL_ROOT)/include
WR_LIB = $(WR_INSTALL_ROOT)/lib
CFLAGS = -g -Wall -DDEBUG \
-I. -I../../../ptp-noposix-v3/libwripc -I../include -I../3rdparty/include -I$(WR_INCLUDE)
LDFLAGS = -L$(WR_INSTALL_ROOT)/lib -L../3rdparty/lib -L$(WR_LIB) \
-L../../../ptp-noposix-v3 -L../libswitchhw \
-lwripc -llua -lm -ldl -lswitchhw
all: $(BINARY)
$(BINARY): $(OBJS)
$(CC) -o $@ $^ $(LDFLAGS)
scp: all
scp $(BINARY) root@pts-test03:/tftpboot/192.168.1.2/root
clean:
rm -f $(BINARY) $(OBJS)
\ No newline at end of file
/*
Register definitions for slave core: WR Softcore PLL
* File : softpll_regs.h
* Author : auto-generated by wbgen2 from spll_wb_slave.wb
* Created : Wed Mar 7 11:09:46 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spll_wb_slave.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#define __WBGEN2_REGDEFS_SPLL_WB_SLAVE_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: SPLL Control/Status Register */
/* definitions for field: Period detector reference select in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_SEL_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_CSR_PER_SEL_SHIFT 0
#define SPLL_CSR_PER_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_CSR_PER_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for field: Number of reference channels (max: 32) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_REF_MASK WBGEN2_GEN_MASK(8, 6)
#define SPLL_CSR_N_REF_SHIFT 8
#define SPLL_CSR_N_REF_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define SPLL_CSR_N_REF_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Number of output channels (max: 8) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_OUT_MASK WBGEN2_GEN_MASK(16, 3)
#define SPLL_CSR_N_OUT_SHIFT 16
#define SPLL_CSR_N_OUT_W(value) WBGEN2_GEN_WRITE(value, 16, 3)
#define SPLL_CSR_N_OUT_R(reg) WBGEN2_GEN_READ(reg, 16, 3)
/* definitions for field: Enable Period Measurement in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_EN WBGEN2_GEN_MASK(19, 1)
/* definitions for register: DMTD Clock Control Register */
/* definitions for field: DMTD Clock Gate Divider in reg: DMTD Clock Control Register */
#define SPLL_DCCR_GATE_DIV_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_DCCR_GATE_DIV_SHIFT 0
#define SPLL_DCCR_GATE_DIV_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_DCCR_GATE_DIV_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for register: Reference Channel Gating Enable Register */
/* definitions for field: Reference Channel Gating Enable in reg: Reference Channel Gating Enable Register */
#define SPLL_RCGER_GATE_SEL_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_RCGER_GATE_SEL_SHIFT 0
#define SPLL_RCGER_GATE_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SPLL_RCGER_GATE_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Output Channel Control Register */
/* definitions for field: Output Channel HW enable flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_EN_MASK WBGEN2_GEN_MASK(0, 8)
#define SPLL_OCCR_OUT_EN_SHIFT 0
#define SPLL_OCCR_OUT_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SPLL_OCCR_OUT_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Output Channel locked flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_LOCK_MASK WBGEN2_GEN_MASK(8, 8)
#define SPLL_OCCR_OUT_LOCK_SHIFT 8
#define SPLL_OCCR_OUT_LOCK_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define SPLL_OCCR_OUT_LOCK_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: Reference Channel Enable Register */
/* definitions for register: Output Channel Enable Register */
/* definitions for register: HPLL Period Error */
/* definitions for field: Period error value in reg: HPLL Period Error */
#define SPLL_PER_HPLL_ERROR_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_PER_HPLL_ERROR_SHIFT 0
#define SPLL_PER_HPLL_ERROR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_PER_HPLL_ERROR_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Period Error Valid in reg: HPLL Period Error */
#define SPLL_PER_HPLL_VALID WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Helper DAC Output */
/* definitions for register: Main DAC Output */
/* definitions for field: DAC value in reg: Main DAC Output */
#define SPLL_DAC_MAIN_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_DAC_MAIN_VALUE_SHIFT 0
#define SPLL_DAC_MAIN_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_DAC_MAIN_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: DAC select in reg: Main DAC Output */
#define SPLL_DAC_MAIN_DAC_SEL_MASK WBGEN2_GEN_MASK(16, 4)
#define SPLL_DAC_MAIN_DAC_SEL_SHIFT 16
#define SPLL_DAC_MAIN_DAC_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define SPLL_DAC_MAIN_DAC_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for register: Deglitcher threshold */
/* definitions for register: Debug FIFO Register - SPLL side */
/* definitions for field: Debug Value in reg: Debug FIFO Register - SPLL side */
#define SPLL_DFR_SPLL_VALUE_MASK WBGEN2_GEN_MASK(0, 31)
#define SPLL_DFR_SPLL_VALUE_SHIFT 0
#define SPLL_DFR_SPLL_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define SPLL_DFR_SPLL_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: End-of-Sample in reg: Debug FIFO Register - SPLL side */
#define SPLL_DFR_SPLL_EOS_MASK WBGEN2_GEN_MASK(31, 1)
#define SPLL_DFR_SPLL_EOS_SHIFT 31
#define SPLL_DFR_SPLL_EOS_W(value) WBGEN2_GEN_WRITE(value, 31, 1)
#define SPLL_DFR_SPLL_EOS_R(reg) WBGEN2_GEN_READ(reg, 31, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: Got a tag in reg: Interrupt disable register */
#define SPLL_EIC_IDR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Got a tag in reg: Interrupt enable register */
#define SPLL_EIC_IER_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Got a tag in reg: Interrupt mask register */
#define SPLL_EIC_IMR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Got a tag in reg: Interrupt status register */
#define SPLL_EIC_ISR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Debug FIFO Register - Host side' data output register 0 */
/* definitions for field: Value in reg: FIFO 'Debug FIFO Register - Host side' data output register 0 */
#define SPLL_DFR_HOST_R0_VALUE_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_DFR_HOST_R0_VALUE_SHIFT 0
#define SPLL_DFR_HOST_R0_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SPLL_DFR_HOST_R0_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Debug FIFO Register - Host side' data output register 1 */
/* definitions for field: Seq ID in reg: FIFO 'Debug FIFO Register - Host side' data output register 1 */
#define SPLL_DFR_HOST_R1_SEQ_ID_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_DFR_HOST_R1_SEQ_ID_SHIFT 0
#define SPLL_DFR_HOST_R1_SEQ_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_DFR_HOST_R1_SEQ_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Debug FIFO Register - Host side' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Debug FIFO Register - Host side' control/status register */
#define SPLL_DFR_HOST_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Debug FIFO Register - Host side' control/status register */
#define SPLL_DFR_HOST_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Debug FIFO Register - Host side' control/status register */
#define SPLL_DFR_HOST_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 13)
#define SPLL_DFR_HOST_CSR_USEDW_SHIFT 0
#define SPLL_DFR_HOST_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 13)
#define SPLL_DFR_HOST_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 13)
/* definitions for register: FIFO 'Tag Readout Register' data output register 0 */
/* definitions for field: Tag value in reg: FIFO 'Tag Readout Register' data output register 0 */
#define SPLL_TRR_R0_VALUE_MASK WBGEN2_GEN_MASK(0, 24)
#define SPLL_TRR_R0_VALUE_SHIFT 0
#define SPLL_TRR_R0_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define SPLL_TRR_R0_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Channel ID in reg: FIFO 'Tag Readout Register' data output register 0 */
#define SPLL_TRR_R0_CHAN_ID_MASK WBGEN2_GEN_MASK(24, 7)
#define SPLL_TRR_R0_CHAN_ID_SHIFT 24
#define SPLL_TRR_R0_CHAN_ID_W(value) WBGEN2_GEN_WRITE(value, 24, 7)
#define SPLL_TRR_R0_CHAN_ID_R(reg) WBGEN2_GEN_READ(reg, 24, 7)
/* definitions for field: Discontinuous bit in reg: FIFO 'Tag Readout Register' data output register 0 */
#define SPLL_TRR_R0_DISC WBGEN2_GEN_MASK(31, 1)
/* definitions for register: FIFO 'Tag Readout Register' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'Tag Readout Register' control/status register */
#define SPLL_TRR_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
PACKED struct SPLL_WB {
/* [0x0]: REG SPLL Control/Status Register */
uint32_t CSR;
/* [0x4]: REG DMTD Clock Control Register */
uint32_t DCCR;
/* [0x8]: REG Reference Channel Gating Enable Register */
uint32_t RCGER;
/* [0xc]: REG Output Channel Control Register */
uint32_t OCCR;
/* [0x10]: REG Reference Channel Enable Register */
uint32_t RCER;
/* [0x14]: REG Output Channel Enable Register */
uint32_t OCER;
/* [0x18]: REG HPLL Period Error */
uint32_t PER_HPLL;
/* [0x1c]: REG Helper DAC Output */
uint32_t DAC_HPLL;
/* [0x20]: REG Main DAC Output */
uint32_t DAC_MAIN;
/* [0x24]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* [0x28]: REG Debug FIFO Register - SPLL side */
uint32_t DFR_SPLL;
/* padding to: 16 words */
uint32_t __padding_0[5];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x50]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
uint32_t DFR_HOST_R0;
/* [0x54]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
uint32_t DFR_HOST_R1;
/* [0x58]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
uint32_t DFR_HOST_CSR;
/* [0x5c]: REG FIFO 'Tag Readout Register' data output register 0 */
uint32_t TRR_R0;
/* [0x60]: REG FIFO 'Tag Readout Register' control/status register */
uint32_t TRR_CSR;
};
#endif
/* SoftPLL debug proxy
Reads out the debug FIFO datastream from the SoftPLL and proxies it
via TCP connection to the application running on an outside host, where
the can be plotted, analyzed, etc.
The debug stream contains run-time signals coming in/out the SoftPLL - for example,
the phase/frequency errors on each channel, DAC drive values, phase tags.
Todo: poll the hardware FIFO through a driver with interrupt support
*/
#include <stdio.h>
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <signal.h>
#include <fcntl.h>
#include <sys/socket.h>
#include <arpa/inet.h>
#include "hw/fpga_regs.h"
#include "softpll_regs.h"
/* TCP Port to listen on */
#define MY_PORT 12345
/* Size of the software FIFO ring buffer */
#define RING_BUFFER_ENTRIES 1048576
#define ENTRIES_PER_PACKET 128
__attribute__((packed)) struct fifo_entry {
uint32_t value;
uint16_t seq_id;
};
/*
Simple ring buffer implementation. WARNING: NOT thread-safe
*/
struct ring_buffer {
void *base;
int entry_size, num_entries;
int wr_ptr, rd_ptr, count;
};
int rbuf_init(struct ring_buffer *rbuf, int num_entries, int entry_size)
{
rbuf->base = malloc(num_entries * entry_size);
if(!rbuf->base)
return -1;
rbuf->entry_size = entry_size;
rbuf->num_entries = num_entries;
rbuf->wr_ptr = 0;
rbuf->rd_ptr = 0;
rbuf->count = 0;
return 0;
}
void rbuf_push(struct ring_buffer *rbuf, void *what)
{
if(rbuf->count >= rbuf->num_entries-1) /* buffer full */
return;
rbuf->count++;
memcpy(rbuf->base + rbuf->wr_ptr*rbuf->entry_size, what, rbuf->entry_size);
rbuf->wr_ptr++;
}
int rbuf_pop(struct ring_buffer *rbuf, void *dst)
{
if(!rbuf->count) /* buffer empty */
return 0;
rbuf->count--;
memcpy(dst, rbuf->base + rbuf->rd_ptr*rbuf->entry_size, rbuf->entry_size);
rbuf->rd_ptr++;
return 1;
}
void rbuf_release(struct ring_buffer *rbuf)
{
free(rbuf->base);
}
#define SPLL_BASE 0x10100
struct ring_buffer spll_trace;
static struct SPLL_WB *_spll_regs = (struct SPLL_WB*) SPLL_BASE;
#define REG(x) ((uint32_t)(&_spll_regs->x))
void poll_spll_fifo()
{
while(1) {
/* Move the following lines (and the ring buffering code) to the driver.
for the SPLL: IRQ = 3 (asserted when FIFO != empty)
base : check DFR_HOST register in softpll_regs.h
device: /dev/spfifoX
parameters: base_addr, num_regs (r0, r1), irq
ioctls:
*/
uint32_t csr = _fpga_readl(REG(DFR_HOST_CSR));
struct fifo_entry ent;
// fprintf(stderr,"CSR %x\n", csr);
if(csr & SPLL_DFR_HOST_CSR_EMPTY) break;
ent.value = _fpga_readl(REG(DFR_HOST_R0));
ent.seq_id = _fpga_readl(REG(DFR_HOST_R1)) & 0xffff;
// fprintf(stderr, "v: %x\n", ent.value);
rbuf_push(&spll_trace, (void *)&ent);
}
}
static int proxy_done = 0;
void sighandler(int sig)
{
if(sig == SIGPIPE)
{
fprintf(stderr,"Connection broken. Killing proxy\n");
proxy_done = 1;
}
}
void proxy_stuff(int fd)
{
if( rbuf_init(&spll_trace, RING_BUFFER_ENTRIES, sizeof(struct fifo_entry)) < 0)
{
perror("rbuf_init()");
return -1;
}
fprintf(stderr,"Connection accepted.\n");
proxy_done = 0;
signal(SIGPIPE, sighandler);
for(;;)
{
poll_spll_fifo();
while(spll_trace.count > ENTRIES_PER_PACKET)
{
struct fifo_entry tx_buf[ENTRIES_PER_PACKET];
int i;
for(i=0;i<ENTRIES_PER_PACKET;i++)
rbuf_pop(&spll_trace, &tx_buf[i]); /* fixme: make endian-independent */
if(proxy_done)
{
rbuf_release(&spll_trace);
return;
}
if(send(fd, tx_buf, sizeof(tx_buf), 0) <= 0)
{
fprintf(stderr,"Connection closed.\n");
rbuf_release(&spll_trace);
return;
}
}
// fprintf(stderr,"Count :%d\n", spll_trace.count);
usleep(10000);
}
}
extern void shw_fpga_mmap_init();
int main(int argc, char *argv[])
{
int sock_fd;
struct sockaddr_in sin;
shw_fpga_mmap_init();
if((sock_fd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP)) < 0)
{
perror("socket()");
return -1;
}
int yes = 1;
if (setsockopt(sock_fd,SOL_SOCKET,SO_REUSEADDR,&yes,sizeof(yes)) < 0) {
perror("setsockopt()");
return -1;
}
sin.sin_family = AF_INET; /* Internet address family */
sin.sin_addr.s_addr = htonl(INADDR_ANY); /* Any incoming interface */
sin.sin_port = htons(MY_PORT);
if (bind(sock_fd, (struct sockaddr *) &sin, sizeof(sin)) < 0)
{
perror("bind()");
return -1;
}
if (listen(sock_fd, 1) < 0)
{
perror("listen()");
return -1;
}
for(;;)
{
struct sockaddr_in client_addr;
socklen_t client_len = sizeof(client_addr);
int client_fd;
if((client_fd = accept(sock_fd, (struct sockaddr *) &client_addr, &client_len)) > 0)
proxy_stuff(client_fd);
}
return 0;
}
\ No newline at end of file
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