Commit b6a2e5c4 authored by Alessandro Rubini's avatar Alessandro Rubini

on-switch-tests: removed most of them as obsolete

parent 719b76b7
...@@ -133,12 +133,9 @@ editing this file, please add your name in all the proper places. ...@@ -133,12 +133,9 @@ editing this file, please add your name in all the proper places.
@item on-switch-tests/ @item on-switch-tests/
Tests that are meant to be run on the switch itself. Tests that are meant to be run on the switch itself.
The directory has been copied from @code{software/tests} As of March 2012 only a few tests remain, as older ones
as it appeared in the @i{svn} repository; it has not been only applied to V2, and the switch testing is not a
recompiled or verified in any way. In this version, only different project.
wr_mon had been made to compile, the other tests still include
@code{build.sh} that sources @code{../../settings}, in the old
way that is now deprecated.
@item robustness/ @item robustness/
The robustness demo program, copied from @i{svn} and The robustness demo program, copied from @i{svn} and
......
This directory includes tests that are meant to be run on the switch This directory used to include tests that are meant to be run on the
itself. switch itself. Now only rtu_test remains, even though it's not
included in the Makefile rules.
The directory has been copied from @code{software/tests} as it If you "make" here, only libwripc and wr_mon are compiled, but
appeared in the @i{svn} repository; it has not been recompiled or wr_mon must be ported to V3.
verified in any way. In this version, only wr_mon had been made to
compile, the other tests still include @code{build.sh} that sources
@code{../../settings}, in the old way that is now deprecated.
If you "make" here, only libwripc and wr_mon is compiled.
\ No newline at end of file
CC=$(CROSS_COMPILE)gcc
OBJS = ad9516_test.o
LDFLAGS = -lswitchhw -L../../libswitchhw
CFLAGS = -I. -O2 -I../../include -DDEBUG
OUTPUT = ad9516_test
EXTRAFILES = regs.txt
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run:: all
scp $(OUTPUT) $(EXTRAFILES) root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#include <stdio.h>
#include <hw/switch_hw.h>
#define NUM_LEDS 4
uint32_t clkgen_rval(void *clkctl, unsigned int addr);
#define AD9516_MAX_REGS 1024
struct ad9516_regs {
struct {
uint16_t addr;
uint8_t value;
} regs[AD9516_MAX_REGS];
int nregs;
};
int ad9516_load_regset(const char *filename, struct ad9516_regs *regs)
{
FILE *f;
char str[1024], tmp[100];
int start_read = 0, n = 0;
uint32_t addr, val;
f = fopen(filename ,"rb");
if(!f)
{
TRACE(TRACE_ERROR, "can't open AD9516 regset file: %s", filename);
return -1;
}
while(!feof(f))
{
fgets(str, 1024, f);
// printf("%s\n",str);
if(!strncmp(str, "Addr(Hex)", 8)) start_read = 1;
if(start_read)
{
if( sscanf(str, "%04x %08s %02x\n", &addr, tmp, &val) == 3)
{
TRACE(TRACE_INFO, " -> ad9516_reg[0x%x]=0x%x", addr, val);
regs->regs[n].addr = addr;
regs->regs[n].value = val;
n++;
}
}
}
regs->nregs = n;
fclose(f);
return 0;
}
int ad9516_set_state(struct ad9516_regs *regs)
{
int i;
TRACE(TRACE_INFO, "Loading AD9516 state (%d registers)", regs->nregs);
for(i=0;i<regs->nregs;i++)
clkgen_write(NULL, regs->regs[i].addr, regs->regs[i].value);
clkgen_write(NULL, 0x232, 1);
for(i=0;i<regs->nregs;i++)
{
uint8_t v = clkgen_rval(NULL, regs->regs[i].addr);
if(regs->regs[i].value != v) printf("%x:%x/%x\n", regs->regs[i].addr, regs->regs[i].value, v);
}
}
main()
{
char s[2000];
int addr;
int val;
unsigned int i=1;
trace_log_stderr();
shw_init();
ad9516_spi_init();
struct ad9516_regs r;
// shw_pio_set0(PIN_ad9516_refsel);
ad9516_load_regset("/tmp/regs.txt", &r);
ad9516_set_state(&r);
}
#!/bin/sh
. ../../../settings
t=`pwd`
cd ../../libswitchhw
./build.sh clean
./build.sh
cd $t
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
AD9516/17/18 Register Map File, Rev 1.0
Addr(Hex) Value(Bin) Value(Hex)
0000 00011000 18
0001 00000000 00
0002 00010000 10
0003 11000011 C3
0004 00000000 00
0010 01111100 7C
0011 00000001 01
0012 00000000 00
0013 00000110 06
0014 00001000 08
0015 00000000 00
0016 00000100 04
0017 00000000 00
0018 00000111 07
0019 00000000 00
001A 00000000 00
001B 00000000 00
001C 00000110 06
001D 00000000 00
001E 00000000 00
001F 00001110 0E
00A0 00000001 01
00A1 00000000 00
00A2 00000000 00
00A3 00000001 01
00A4 00000000 00
00A5 00000000 00
00A6 00000001 01
00A7 00000000 00
00A8 00000000 00
00A9 00000001 01
00AA 00000000 00
00AB 00000000 00
00F0 00001010 0A
00F1 00001010 0A
00F2 00001010 0A
00F3 00001010 0A
00F4 00001010 0A
00F5 00001000 08
0140 01000010 42
0141 01000010 42
0142 01000010 42
0143 01011010 5A
0190 00000000 00
0191 10000000 80
0192 00000000 00
0193 00110010 32
0194 00000000 00
0195 00000000 00
0196 00110010 32
0197 00000000 00
0198 00000000 00
0199 00110010 32
019A 00000000 00
019B 00010001 11
019C 00100000 20
019D 00000000 00
019E 00110010 32
019F 00000000 00
01A0 00010001 11
01A1 00100000 20
01A2 00000000 00
01A3 00000000 00
01E0 00000000 00
01E1 00000010 02
0230 00000000 00
0231 00000000 00
0232 00000000 00
CC=$(CROSS_COMPILE)gcc
OBJS = blink_leds.o
LDFLAGS = -lswitchhw -L../../libswitchhw
CFLAGS = -I. -O2 -I../../include -DDEBUG
OUTPUT = blink_leds
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#include <stdio.h>
#include <hw/switch_hw.h>
#define NUM_LEDS 8
main()
{
unsigned int i=0,di=1,previ=0;
trace_log_stderr();
shw_request_fpga_firmware(FPGA_ID_MAIN, "board_test");
shw_init();
for(;;)
{
shw_set_fp_led(previ, LED_OFF);
shw_set_fp_led(i, LED_GREEN);
usleep(30000);
shw_set_fp_led(i, LED_RED);
usleep(30000);
previ=i;
i+=di;
if(i == 0 || i==(NUM_LEDS-1)) di=-di;
}
}
#!/bin/sh
. ../../../settings
#cd ../../libswitchhw
#./build.sh
#cd ../tests/blink_leds
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
include ../../../Makedefs
CC=$(CROSS_COMPILE_ARM)gcc
OBJS = calibrator_test.o term.o
LDFLAGS = -lswitchhw -L../../libswitchhw
CFLAGS = -I. -O2 -I../../include -DDEBUG -I../../../kernel/include
OUTPUT = calibrator_test
all: $(OBJS)
make -C ../../libswitchhw
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) ../../drivers/bin/*.ko root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#!/bin/sh
. ../../../settings
make CROSS_COMPILE=$CROSS_COMPI_CPU $1 $2 $3 $4
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <sys/time.h>
#include <signal.h>
#include <hw/switch_hw.h>
#include <hw/clkb_io.h>
#include <hw/minic_regs.h>
#include <hw/endpoint_regs.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <arpa/inet.h>
//#include <net/if.h>
#include <asm/types.h>
#include <linux/if_packet.h>
#include <linux/if_ether.h>
#include <linux/if_arp.h>
#include <linux/net_tstamp.h>
#include <linux/sockios.h>
#include <linux/errqueue.h>
#include <sys/ioctl.h>
#include <sys/socket.h>
#include <sys/time.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <errno.h>
#include <hw/dmtd_calibrator_regs.h>
#include <hw/endpoint_regs.h>
#include <hw/phy_calibration.h>
main()
{
int i, rval;
system("/sbin/rmmod /tmp/wr_minic.ko");
system("/sbin/rmmod /tmp/wr_vic.ko");
trace_log_stderr();
shw_init();
system("/sbin/insmod /tmp/wr_vic.ko");
system("/sbin/insmod /tmp/wr_minic.ko");
system("/sbin/ifconfig wru1 hw ether 00:50:fc:96:9b:0e");
system("/sbin/ifconfig wru1 up 192.168.100.100");
_fpga_writel(FPGA_BASE_MINIC_UP0 + (1<<14) + EP_REG_PHIO, EP_PHIO_ENABLE);
_fpga_writel(FPGA_BASE_MINIC_UP1 + (1<<14) + EP_REG_PHIO, EP_PHIO_ENABLE);
shw_hpll_switch_reference("wru1");
while(!shw_hpll_check_lock());
shw_dmpll_switch_reference("wru1");
while(!shw_dmpll_check_lock());
shw_cal_enable_feedback("wru1", 1, PHY_CALIBRATE_RX);
double phase_rx;
for(;;)
{
while(!(rval = shw_cal_measure(&phase_rx)));
if(rval < 0)
{
printf("error measuring RX delay\n");
return -1;
}
printf("rval = %d, deltaRX(uncorrected) = %.3f ns\n", rval, phase_rx);
}
}
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include <poll.h>
struct termios oldkey, newkey;
int term_restore()
{
tcsetattr(STDIN_FILENO,TCSANOW,&oldkey);
}
void term_init()
{
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
tcgetattr(STDIN_FILENO,&oldkey);
memcpy(&newkey, &oldkey, sizeof(struct termios));
newkey.c_cflag = B9600 | CRTSCTS | CS8 | CLOCAL | CREAD;
newkey.c_iflag = IGNPAR;
newkey.c_oflag = OPOST |ONLCR;
newkey.c_lflag = 0;
newkey.c_cc[VMIN]=1;
newkey.c_cc[VTIME]=0;
tcflush(STDIN_FILENO, TCIFLUSH);
tcsetattr(STDIN_FILENO,TCSANOW,&newkey);
atexit(term_restore);
}
int term_poll()
{
struct pollfd pfd;
pfd.fd = STDIN_FILENO;
pfd.events = POLLIN | POLLPRI;
if(poll(&pfd,1,0)>0)return 1;
return 0;
}
int term_get()
{
unsigned char c;
int q;
if(read(STDIN_FILENO, &c, 1 ) == 1)
{
q=c;
} else q=-1;
return q;
}
void clear_screen()
{
printf("\033[2J\033[1;1H");
}
\ No newline at end of file
include ../../../Makedefs
CC=$(CROSS_COMPILE_ARM)gcc
OBJS = dmpll_test.o term.o
LDFLAGS = -lswitchhw -L../../libswitchhw
CFLAGS = -I. -O2 -I../../include -DDEBUG -I../../../kernel/include
OUTPUT = dmpll_test
all: $(OBJS)
make -C ../../libswitchhw
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) ../../drivers/bin/*.ko root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#!/bin/sh
. ../../../settings
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
#include <stdio.h>
#include <stdlib.h>
#include <hw/dmpll_regs.h>
int sign_extend(uint32_t val, int nbits)
{
if(val & (1<<(nbits-1))) return (0xffffffff ^ ((1<<nbits)-1)) | val; else return val;
}
main(int argc, char *argv[])
{
if(argc < 3) return -1;
FILE *fin, *fout;
uint32_t r0, r1,r2,r3;
int npoints;
int i = 0;
fin = fopen(argv[1], "rb");
fout = fopen(argv[2], "wb");
npoints = atoi(argv[3]);
while(!feof(fin) && (++i < npoints))
{
fread(&r0, 4, 1, fin);
fread(&r1, 4, 1, fin);
fread(&r2, 4, 1, fin);
fread(&r3, 4, 1, fin);
fprintf(fout, "%d %d %d %d\n", i,
sign_extend(DMPLL_RFIFO_R0_ERR_VAL_R(r0), 18),
DMPLL_RFIFO_R3_DAC_VAL_R(r3),
// DMPLL_RFIFO_R1_TAG_REF_R(r1) - DMPLL_RFIFO_R2_TAG_FB_R(r2),
r0 & DMPLL_RFIFO_R2_FP_MODE ? 60000 : 0);
}
}
\ No newline at end of file
#include <stdio.h>
#include <inttypes.h>
#include <sys/time.h>
#include <signal.h>
#include <hw/switch_hw.h>
#include <hw/clkb_io.h>
#include <hw/dmpll_regs.h>
#define MAX_MEAS 120000
#define DMPLL_CHANNEL_LOCAL 0
#define DMPLL_CHANNEL_UP0 1
#define DMPLL_CHANNEL_UP1 2
uint32_t rec_buf[MAX_MEAS * 4];
int n_meas = 0;
static void dmpll_purge_rfifo()
{
for(;;)
{
shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_RFIFO_R0);
}
}
static void dmpll_poll_rfifo()
{
for(;;)
{
if(shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_RFIFO_CSR) & DMPLL_RFIFO_CSR_EMPTY) return;
if(n_meas < MAX_MEAS) {
rec_buf[4*n_meas] = shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_RFIFO_R0);
rec_buf[4*n_meas+1] = shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_RFIFO_R1);
rec_buf[4*n_meas+2] = shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_RFIFO_R2);
rec_buf[4*n_meas+3] = shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_RFIFO_R3);
n_meas++;
}
}
}
static void dmpll_setup_deglitcher(uint32_t reg, int hi, int lo, int glitch)
{
shw_clkb_write_reg(CLKB_BASE_DMPLL + reg, DMPLL_DGCR_IN0_THR_HI_W(hi) |
DMPLL_DGCR_IN0_THR_LO_W(lo) |
DMPLL_DGCR_IN0_THR_GLITCH_W(glitch));
}
static void dmpll_set_phase_shift(int channel, int ps_shift)
{
switch(channel)
{
#if 0
case DMPLL_CHANNEL_LOCAL:
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_LOCAL, ps_shift);
break;
case DMPLL_CHANNEL_UP0:
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_0, ps_shift);
break;
#endif
case DMPLL_CHANNEL_UP1:
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN0, ps_shift);
break;
}
}
static int dmpll_shifter_busy(int channel)
{
switch(channel)
{
/* case DMPLL_CHANNEL_LOCAL:
return shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_LOCAL) & (1<<31);
case DMPLL_CHANNEL_UP0:
return shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_UP0) & (1<<31);*/
case DMPLL_CHANNEL_UP1:
return shw_clkb_read_reg(CLKB_BASE_DMPLL + DMPLL_REG_PSCR_IN0) & DMPLL_PSCR_IN0_BUSY;
}
return 0;
}
void sighandler(int sig)
{
fprintf(stderr,"Saving: %d", n_meas);
FILE *f=fopen("/tmp/dmpll_meas.dat","wb");
fwrite(rec_buf, 8, n_meas, f);
fclose(f);
exit(0);
}
main()
{
int i;
int ps_shift = 16000;
int ps_new_shift = 0;
trace_log_stderr();
shw_init();
printf("Waiting for Helper PLL lock...\n");
while(!shw_hpll_check_lock()) usleep(10000);
/*
for(i=0;i<30;i++)
{
shw_hpll_update(); usleep(100000);
}*/
printf("Initializing the DMPLL.\n");
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PCR, 0);
dmpll_setup_deglitcher(DMPLL_REG_DGCR_IN0, 150, 150, 60);
dmpll_setup_deglitcher(DMPLL_REG_DGCR_FB, 150, 150, 60);
// gain
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_FBGR, DMPLL_FBGR_F_KP_W(100) | DMPLL_FBGR_F_KI_W(600));
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PBGR, DMPLL_PBGR_P_KP_W(-2000) | DMPLL_PBGR_P_KI_W(-40));
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_LDCR, DMPLL_LDCR_LD_THR_W(300) | DMPLL_LDCR_LD_SAMP_W(2000));
fprintf(stderr,"X=exit\n");
dmpll_purge_rfifo();
fprintf(stderr,"X=exit\n");
shw_clkb_write_reg(CLKB_BASE_DMPLL + DMPLL_REG_PCR, DMPLL_PCR_ENABLE | DMPLL_PCR_REFSEL_W(0) | DMPLL_PCR_DAC_CLKSEL_W(2) | DMPLL_PCR_PS_SPEED_W(100) | DMPLL_PCR_SWRST);
//term_init();
// signal(SIGINT, sighandler);
//signal(SIGTERM, sighandler);
//signal(SIGKILL, sighandler);
fprintf(stderr,"X=exit\n");
dmpll_set_phase_shift(DMPLL_CHANNEL_UP1, 16400);
for(;;)
{
/* int c=term_get();
if(c=='x') break;
if(c=='a') { ps_shift += 200; ps_new_shift = 1; }
if(c=='z') { ps_shift -= 200; ps_new_shift = 1; }
// uint32_t psr = shw_clkb_read_reg(CLKB_BASE_DMPLL+ DMPLL_REG_PSR);
// fprintf(stderr,"PhLk: %d FrLk: %d\n", psr & DMPLL_PSR_PHASE_LK ? 1 : 0, psr & DMPLL_PSR_FREQ_LK ? 1 : 0);
if(ps_new_shift)// && !dmpll_shifter_busy(DMPLL_CHANNEL_UP1))
{
fprintf(stderr,"Setting PS = %d\n", ps_shift);
ps_new_shift = 0;
dmpll_set_phase_shift(DMPLL_CHANNEL_UP1, ps_shift);
}
*/
// dmpll_poll_rfifo();
}
//term_restore();
}
#!/bin/bash
IP=192.168.1.6
scp root@$IP:/tmp/dmpll_meas.dat ./
gcc convert_meas.c -o convert_meas -I../../include
./convert_meas dmpll_meas.dat dmpll_plotdata.dat 40000
gnuplot -e "set xlabel 'time'; set y2label 'DAC value'; set ylabel 'Phase/freq error'; set yrange [-10000:10000]; set y2range [0:65540]; plot 'dmpll_plotdata.dat' using 1:2 title 'Phase/freq error' with lines axis x1y1, \
'dmpll_plotdata.dat' using 1:3 title 'DAC drive' with lines axis x1y2, \
'dmpll_plotdata.dat' using 1:4 title 'Freq/Phase mode' with lines axis x1y2; \
"
#, plot "dmpll_plotdata.dat" using 1:3 title "integral value" with lines, plot "dmpll_plotdata.dat" using 1:4 title "DAC drive" with lines'
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include <poll.h>
struct termios oldkey, newkey;
int term_restore()
{
tcsetattr(STDIN_FILENO,TCSANOW,&oldkey);
}
void term_init()
{
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
tcgetattr(STDIN_FILENO,&oldkey);
memcpy(&newkey, &oldkey, sizeof(struct termios));
newkey.c_cflag = B9600 | CRTSCTS | CS8 | CLOCAL | CREAD;
newkey.c_iflag = IGNPAR;
newkey.c_oflag = OPOST |ONLCR;
newkey.c_lflag = 0;
newkey.c_cc[VMIN]=1;
newkey.c_cc[VTIME]=0;
tcflush(STDIN_FILENO, TCIFLUSH);
tcsetattr(STDIN_FILENO,TCSANOW,&newkey);
atexit(term_restore);
}
int term_poll()
{
struct pollfd pfd;
pfd.fd = STDIN_FILENO;
pfd.events = POLLIN | POLLPRI;
if(poll(&pfd,1,0)>0)return 1;
return 0;
}
int term_get()
{
unsigned char c;
int q;
if(read(STDIN_FILENO, &c, 1 ) == 1)
{
q=c;
} else q=-1;
return q;
}
include ../../../Makedefs
CC=$(CROSS_COMPILE_ARM)gcc
OBJS = ep_stats.o term.o
LDFLAGS = -lswitchhw -L../../libswitchhw -L../../libwripc -L../../libptpnetif -lwripc -lptpnetif
CFLAGS = -I. -O2 -I../../include -DDEBUG -I../../../kernel/include -I../../libptpnetif -I../../wrsw_hal -I../../libwripc -g
OUTPUT = ep_stats
all: $(OBJS)
make -C ../../libswitchhw
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
- scp $(OUTPUT) root@192.168.1.6:/tmp
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hw/fpga_regs.h>
#include <hw/endpoint_regs.h>
#include <hal_client.h>
#define RTU_BANK_SIZE 65536
static const struct {
char name[5];
uint32_t base_addr;
} endpoints_map[]= {
{"wru0", FPGA_BASE_MINIC_UP0 + 0x4000},
{"wru1", FPGA_BASE_MINIC_UP1 + 0x4000},
{NULL, 0}
};
static const struct {
char name[64];
int offset;
} rmon_counters[] = {
{"RX PCS sync lost events", 0},
{"RX PCS invalid 8b10b codes", 1},
{"RX PCS FIFO overruns", 2},
{"TX PCS FIFO underruns", 3},
{"RX CRC errors", 4},
{"RX valid frames", 5},
{"RX runt frames", 6},
{"RX giant frames",7},
{"RX errors reported by PCS", 8},
{"RX buffer drops", 9},
{"Received PAUSEs", 10},
{"Sent PAUSEs", 11},
{NULL, 0},
};
int show_stats(char *if_name)
{
uint32_t base_addr = 0;
int i;
for(i=0; endpoints_map[i].name; i++)
if(!strcmp(endpoints_map[i].name, if_name))
{
base_addr = endpoints_map[i].base_addr;
break;
}
if(!base_addr) return -1;
printf("\033[2J\033[1;1H");
printf("Stats for interface: %s\n-----------------------\n\n", if_name);
for(i=0;i<12;i++)
printf("%-40s: %d\n", rmon_counters[i].name, _fpga_readl(base_addr + 0x80 + rmon_counters[i].offset * 4));
return 0;
}
void init()
{
if(halexp_client_init() < 0)
{
printf("Oops... Looks like the HAL is not running :( \n\n");
exit(-1);
}
shw_fpga_mmap_init();
}
main(int argc, char *argv[])
{
init();
for(;;)
{
if(show_stats(argv[1]) < 0)
break;
usleep(100000);
}
return 0;
}
\ No newline at end of file
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include <poll.h>
struct termios oldkey, newkey;
int term_restore()
{
tcsetattr(STDIN_FILENO,TCSANOW,&oldkey);
}
void term_init()
{
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
tcgetattr(STDIN_FILENO,&oldkey);
memcpy(&newkey, &oldkey, sizeof(struct termios));
newkey.c_cflag = B9600 | CRTSCTS | CS8 | CLOCAL | CREAD;
newkey.c_iflag = IGNPAR;
newkey.c_oflag = OPOST |ONLCR;
newkey.c_lflag = 0;
newkey.c_cc[VMIN]=1;
newkey.c_cc[VTIME]=0;
tcflush(STDIN_FILENO, TCIFLUSH);
tcsetattr(STDIN_FILENO,TCSANOW,&newkey);
atexit(term_restore);
}
int term_poll()
{
struct pollfd pfd;
pfd.fd = STDIN_FILENO;
pfd.events = POLLIN | POLLPRI;
if(poll(&pfd,1,0)>0)return 1;
return 0;
}
int term_get()
{
unsigned char c;
int q;
if(read(STDIN_FILENO, &c, 1 ) == 1)
{
q=c;
} else q=-1;
return q;
}
"Norma Jean"
"/home/wrdev/WR_buildroot/WR_Switch/fpgaboot/mblaster.c" 1217
nil
nil
CC=$(CROSS_COMPILE)gcc
OBJS = cpu_io.o mb_io.o mblaster.o main.o
CFLAGS = -I. -O3
OUTPUT = fpgaboot
all: $(OBJS)
${CC} -s -o $(OUTPUT) $(OBJS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
install-image:
cp $(OUTPUT) ../root/usr/sbin
install: all
scp $(OUTPUT) root@192.168.1.2:/root
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
/*
* arch/arm/mach-at91/include/mach/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif
/*
* arch/arm/mach-at91/include/mach/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock Enable [some SAM9 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
#define AT91_PMC_CSSMCK_CSS (0 << 8)
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
#endif
/*
* arch/arm/mach-at91/include/mach/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#endif
#!/bin/sh
. ../../../settings
make CROSS_COMPILE=$CC_CPU $1
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/mman.h>
#include <inttypes.h>
#include <fcntl.h>
#include "cpu_io.h"
static volatile uint8_t *sys_base;
static volatile uint8_t *pio_base[NUM_PIO_BANKS];
int io_init()
{
int fd = open("/dev/mem", O_RDWR);
if(!fd) return -1;
sys_base = mmap(NULL, 0x2000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, AT91_BASE_SYS);
if(sys_base == NULL)
{
perror("mmap()");
close(fd);
return -1;
}
// fprintf(stderr,"AT91_SYS mmapped to: 0x%08x\n", sys_base);
pio_base[0] = sys_base + AT91_PIOA;
pio_base[1] = sys_base + AT91_PIOB;
pio_base[2] = sys_base + AT91_PIOC;
pio_base[3] = sys_base + AT91_PIOD;
pio_base[4] = sys_base + AT91_PIOE;
return 0;
}
void pio_set_state(int port, int pin, int state)
{
if(state)
_writel(pio_base[port] + PIO_SODR, (1<<pin))
else
_writel(pio_base[port] + PIO_CODR, (1<<pin))
}
void pio_set_mode(int port, int pin, int mode, int dir)
{
_writel(pio_base[port] + PIO_IDR, (1<<pin)); // disable irq
if(mode & PIN_MODE_PULLUP)
_writel(pio_base[port] + PIO_PUER, (1<<pin)) // enable pullup
else
_writel(pio_base[port] + PIO_PUDR, (1<<pin)) // disable pullup
switch(mode & 0x3)
{
case PIN_MODE_GPIO:
_writel(pio_base[port] + PIO_PER, (1<<pin)); // enable gpio mode
break;
case PIN_MODE_PERIPH_A:
_writel(pio_base[port] + PIO_PDR, (1<<pin)); // disable gpio mode
_writel(pio_base[port] + PIO_ASR, (1<<pin)); // select peripheral A
break;
case PIN_MODE_PERIPH_B:
_writel(pio_base[port] + PIO_PDR, (1<<pin)); // disable gpio mode
_writel(pio_base[port] + PIO_BSR, (1<<pin)); // select peripheral B
break;
}
if(dir)
_writel(pio_base[port] + PIO_OER, (1<<pin)) // select output
else
_writel(pio_base[port] + PIO_ODR, (1<<pin)); // select input
}
static const struct {
int port;
int pin;
int mode;
} pck_port_mapping[] =
{
{PIOA, 13, PIN_MODE_PERIPH_B},
{PIOB, 10, PIN_MODE_PERIPH_B},
{PIOA, 6, PIN_MODE_PERIPH_B},
{PIOE, 11, PIN_MODE_PERIPH_B}
};
int pck_enable(int pck_num, int prescaler, int source)
{
if(pck_num > 3) return -1;
pio_set_mode(pck_port_mapping[pck_num].port, pck_port_mapping[pck_num].pin, pck_port_mapping[pck_num].mode, 1);
_writel(sys_base + AT91_PMC_PCKR(pck_num), source | prescaler);
// enable the PCK output
_writel(sys_base + AT91_PMC_SCER, (1<< (8+pck_num)));
return 0;
}
int pio_get_state(int port, int pin)
{
return (_readl(pio_base[port] + PIO_PDSR) & (1<<pin)) ? 1: 0;
}
volatile uint8_t *io_get_sys_base()
{
return sys_base;
}
volatile uint8_t *pio_get_port_addr(int port)
{
return pio_base[port];
}
#ifndef __CPU_IO_H
#define __CPU_IO_H
#include <sys/types.h>
#include <inttypes.h>
#include <at91/at91sam9263.h>
#include <at91/at91_pio.h>
#include <at91/at91_pmc.h>
#define NUM_PIO_BANKS 5
#define PIOA 0
#define PIOB 1
#define PIOC 2
#define PIOD 3
#define PIOE 4
#define PIN_MODE_GPIO 0
#define PIN_MODE_PERIPH_A 1
#define PIN_MODE_PERIPH_B 2
#define PIN_MODE_PULLUP 0x80
#define _writel(reg, val){ *(volatile uint32_t *)(reg) = (val); }
#define _readl(reg) (*(volatile uint32_t *)(reg))
int io_init();
void pio_set_state(int port, int pin, int state);
void pio_set_mode(int port, int pin, int mode, int dir);
int pck_enable(int pck_num, int prescaler, int source);
int pio_get_state(int port, int pin);
volatile uint8_t *io_get_sys_base();
volatile uint8_t *pio_get_port_addr(int port);
#endif
#include <stdio.h>
#include <unistd.h>
#include "cpu_io.h"
#include "mb_io.h"
#define N_LEDS 8
struct {
int port;
int pin;
} leds[] = {
{PIOC, 5},
{PIOC, 12},
{PIOC, 7},
{PIOC, 19},
{PIOC, 9},
{PIOC, 17},
{PIOC, 14},
{PIOC, 6},
{0, 0}
};
void blink_leds()
{
int i;
for(i=0;i<N_LEDS;i++)
pio_set_mode(leds[i].port, leds[i].pin, PIN_MODE_GPIO, 1);
i=0;
for(;;)
{
int prevled=((i-1)<0)?(N_LEDS-1):i-1;
pio_set_state(leds[prevled].port, leds[prevled].pin, 0);
pio_set_state(leds[i].port, leds[i].pin, 1);
i++; if(i>=N_LEDS) i = 0;
usleep(100000);
}
}
extern int mblaster_boot_fpga(const char *filename, int fpga_sel);
main(int argc, char *argv[])
{
int fpga_sel = -1;
io_init();
pck_enable(0, AT91_PMC_CSS_PLLA, AT91_PMC_PRES_2);
if(argc<3)
{
fprintf(stderr,"Usage: %s <bitstream_file> <MAIN/CLKB>\n\n",argv[0]);
return -1;
}
if(!strcasecmp(argv[2], "main"))
fpga_sel = FPGA_MAIN;
else if(!strcasecmp(argv[2], "clkb"))
fpga_sel = FPGA_CLKB;
fprintf(stderr,"FPGAsel: %d\n", fpga_sel);
mblaster_boot_fpga(argv[1], fpga_sel);
return 0;
}
/****************************************************************************/
/* */
/* Module: mb_io.c (MicroBlaster) */
/* */
/* Copyright (C) Altera Corporation 2004 */
/* */
/* Descriptions: Defines all IO control functions. operating system */
/* is defined here. Functions are operating system */
/* dependant. */
/* */
/* Revisions: 1.0 12/10/01 Sang Beng Ng */
/* Supports Altera ByteBlaster hardware download cable */
/* on Windows NT. */
/* 1.1 05/28/04 Chuin Tein Ong */
/* Supports both Altera ByteBlaster II and ByteBlaster MV */
/* download cables on Windows NT. */
/* */
/****************************************************************************/
#include "mb_io.h"
#include <stdio.h>
int fopen_rbf( char argv[], char* mode)
{
FILE* file_id;
file_id = fopen( argv, mode );
return (int) file_id;
}
int fclose_rbf( int file_id)
{
fclose( (FILE*) file_id);
return 0;
}
int fseek_rbf( int finputid, int start, int end )
{
int seek_position;
seek_position = fseek( (FILE*) finputid, start, end );
return seek_position;
}
int ftell_rbf( int finputid )
{
int file_size;
file_size = ftell( (FILE*) finputid );
return file_size;
}
int fgetc_rbf( int finputid )
{
int one_byte;
one_byte = fgetc( (FILE*) finputid );
return one_byte;
}
void delay ( int factor)
{
int i;
for (i=0;i<factor;i++) asm volatile("nop");
}
\ No newline at end of file
/****************************************************************************/
/* */
/* Module: mb_io.h (MicroBlaster) */
/* */
/* Copyright (C) Altera Corporation 2004 */
/* */
/* Descriptions: Defines all IO control functions. operating system */
/* is defined here. Functions are operating system */
/* dependant. */
/* */
/* Revisions: 1.0 12/10/01 Sang Beng Ng */
/* Supports Altera ByteBlaster hardware download cable */
/* on Windows NT. */
/* 1.1 05/28/04 Chuin Tein Ong */
/* Supports both Altera ByteBlaster II and ByteBlaster MV */
/* download cables on Windows NT. */
/* */
/****************************************************************************/
#ifndef INC_MB_IO_H
#define INC_MB_IO_H
#define EMBEDDED 2
/*///////////////////////*/
/* Functions Prototyping */
/*///////////////////////*/
int ReadByteBlaster ( int port );
void WriteByteBlaster ( int port, int data, int test );
#define FPGA_MAIN 0
#define FPGA_CLKB 1
#endif /* INC_MB_IO_H */
This diff is collapsed.
CC=$(CROSS_COMPILE)gcc
OBJS = cpu_io.o mb_io.o mblaster.o main.o
CFLAGS = -I. -O3
OUTPUT = fpgaboot
all: $(OBJS)
${CC} -s -o $(OUTPUT) $(OBJS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
install: all
scp $(OUTPUT) root@192.168.1.2:/root
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
/*
* arch/arm/mach-at91/include/mach/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif
/*
* arch/arm/mach-at91/include/mach/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock Enable [some SAM9 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [some SAM9, CAP9] */
#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */
#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */
#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_USB (AT91_PMC + 0x38) /* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */
#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */
#define AT91_PMC_CSSMCK_CSS (0 << 8)
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9, AT91CAP9 only] */
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
#endif
/*
* arch/arm/mach-at91/include/mach/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7 /* USART 0 */
#define AT91SAM9263_ID_US1 8 /* USART 1 */
#define AT91SAM9263_ID_US2 9 /* USART 2 */
#define AT91SAM9263_ID_MCI0 10 /* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11 /* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12 /* CAN */
#define AT91SAM9263_ID_TWI 13 /* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14 /* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15 /* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16 /* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17 /* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18 /* AC97 Controller */
#define AT91SAM9263_ID_TCB 19 /* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20 /* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21 /* Ethernet */
#define AT91SAM9263_ID_2DGE 23 /* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24 /* USB Device Port */
#define AT91SAM9263_ID_ISI 25 /* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26 /* LCD Controller */
#define AT91SAM9263_ID_DMA 27 /* DMA Controller */
#define AT91SAM9263_ID_UHP 29 /* USB Host port */
#define AT91SAM9263_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000 /* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K) /* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000 /* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000 /* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
#endif
#!/bin/sh
. ../build.settings
make CROSS_COMPILE=$CC_PATH/$CC_PREFIX $1
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/mman.h>
#include <inttypes.h>
#include <fcntl.h>
#include "cpu_io.h"
static volatile uint8_t *sys_base;
static volatile uint8_t *pio_base[NUM_PIO_BANKS];
int io_init()
{
int fd = open("/dev/mem", O_RDWR);
if(!fd) return -1;
sys_base = mmap(NULL, 0x2000, PROT_READ | PROT_WRITE, MAP_SHARED, fd, AT91_BASE_SYS);
if(sys_base == NULL)
{
perror("mmap()");
close(fd);
return -1;
}
fprintf(stderr,"AT91_SYS mmapped to: 0x%08x\n", sys_base);
pio_base[0] = sys_base + AT91_PIOA;
pio_base[1] = sys_base + AT91_PIOB;
pio_base[2] = sys_base + AT91_PIOC;
pio_base[3] = sys_base + AT91_PIOD;
pio_base[4] = sys_base + AT91_PIOE;
return 0;
}
void pio_set_state(int port, int pin, int state)
{
if(state)
_writel(pio_base[port] + PIO_SODR, (1<<pin))
else
_writel(pio_base[port] + PIO_CODR, (1<<pin))
}
void pio_set_mode(int port, int pin, int mode, int dir)
{
_writel(pio_base[port] + PIO_IDR, (1<<pin)); // disable irq
if(mode & PIN_MODE_PULLUP)
_writel(pio_base[port] + PIO_PUER, (1<<pin)) // enable pullup
else
_writel(pio_base[port] + PIO_PUDR, (1<<pin)) // disable pullup
switch(mode & 0x3)
{
case PIN_MODE_GPIO:
_writel(pio_base[port] + PIO_PER, (1<<pin)); // enable gpio mode
break;
case PIN_MODE_PERIPH_A:
_writel(pio_base[port] + PIO_PDR, (1<<pin)); // disable gpio mode
_writel(pio_base[port] + PIO_ASR, (1<<pin)); // select peripheral A
break;
case PIN_MODE_PERIPH_B:
_writel(pio_base[port] + PIO_PDR, (1<<pin)); // disable gpio mode
_writel(pio_base[port] + PIO_BSR, (1<<pin)); // select peripheral B
break;
}
if(dir)
_writel(pio_base[port] + PIO_OER, (1<<pin)) // select output
else
_writel(pio_base[port] + PIO_ODR, (1<<pin)); // select input
}
static const struct {
int port;
int pin;
int mode;
} pck_port_mapping[] =
{
{PIOA, 13, PIN_MODE_PERIPH_B},
{PIOB, 10, PIN_MODE_PERIPH_B},
{PIOA, 6, PIN_MODE_PERIPH_B},
{PIOE, 11, PIN_MODE_PERIPH_B}
};
int pck_enable(int pck_num, int prescaler, int source)
{
if(pck_num > 3) return -1;
pio_set_mode(pck_port_mapping[pck_num].port, pck_port_mapping[pck_num].pin, pck_port_mapping[pck_num].mode, 1);
_writel(sys_base + AT91_PMC_PCKR(pck_num), source | prescaler);
// enable the PCK output
_writel(sys_base + AT91_PMC_SCER, (1<< (8+pck_num)));
return 0;
}
int pio_get_state(int port, int pin)
{
return (_readl(pio_base[port] + PIO_PDSR) & (1<<pin)) ? 1: 0;
}
volatile uint8_t *io_get_sys_base()
{
return sys_base;
}
volatile uint8_t *pio_get_port_addr(int port)
{
return pio_base[port];
}
#ifndef __CPU_IO_H
#define __CPU_IO_H
#include <sys/types.h>
#include <inttypes.h>
#include <at91/at91sam9263.h>
#include <at91/at91_pio.h>
#include <at91/at91_pmc.h>
#define NUM_PIO_BANKS 5
#define PIOA 0
#define PIOB 1
#define PIOC 2
#define PIOD 3
#define PIOE 4
#define PIN_MODE_GPIO 0
#define PIN_MODE_PERIPH_A 1
#define PIN_MODE_PERIPH_B 2
#define PIN_MODE_PULLUP 0x80
#define _writel(reg, val){ *(volatile uint32_t *)(reg) = (val); }
#define _readl(reg) (*(volatile uint32_t *)(reg))
int io_init();
void pio_set_state(int port, int pin, int state);
void pio_set_mode(int port, int pin, int mode, int dir);
int pck_enable(int pck_num, int prescaler, int source);
int pio_get_state(int port, int pin);
volatile uint8_t *io_get_sys_base();
volatile uint8_t *pio_get_port_addr(int port);
#endif
#include <stdio.h>
#include <unistd.h>
#include "cpu_io.h"
#define N_LEDS 8
struct {
int port;
int pin;
} leds[] = {
{PIOC, 5},
{PIOC, 12},
{PIOC, 7},
{PIOC, 19},
{PIOC, 9},
{PIOC, 17},
{PIOC, 14},
{PIOC, 6},
{0, 0}
};
void blink_leds()
{
int i;
for(i=0;i<N_LEDS;i++)
pio_set_mode(leds[i].port, leds[i].pin, PIN_MODE_GPIO, 1);
i=0;
for(;;)
{
int prevled=((i-1)<0)?(N_LEDS-1):i-1;
pio_set_state(leds[prevled].port, leds[prevled].pin, 0);
pio_set_state(leds[i].port, leds[i].pin, 1);
i++; if(i>=N_LEDS) i = 0;
usleep(100000);
}
}
extern int mblaster_boot_fpga(const char *filename);
main(int argc, char *argv[])
{
io_init();
pck_enable(0, AT91_PMC_CSS_PLLA, AT91_PMC_PRES_2);
if(argc<2)
{
fprintf(stderr,"Filename missing!\n");
return -1;
}
mblaster_boot_fpga(argv[1]);
}
/****************************************************************************/
/* */
/* Module: mb_io.c (MicroBlaster) */
/* */
/* Copyright (C) Altera Corporation 2004 */
/* */
/* Descriptions: Defines all IO control functions. operating system */
/* is defined here. Functions are operating system */
/* dependant. */
/* */
/* Revisions: 1.0 12/10/01 Sang Beng Ng */
/* Supports Altera ByteBlaster hardware download cable */
/* on Windows NT. */
/* 1.1 05/28/04 Chuin Tein Ong */
/* Supports both Altera ByteBlaster II and ByteBlaster MV */
/* download cables on Windows NT. */
/* */
/****************************************************************************/
#include "mb_io.h"
#include <stdio.h>
int fopen_rbf( char argv[], char* mode)
{
FILE* file_id;
file_id = fopen( argv, mode );
return (int) file_id;
}
int fclose_rbf( int file_id)
{
fclose( (FILE*) file_id);
return 0;
}
int fseek_rbf( int finputid, int start, int end )
{
int seek_position;
seek_position = fseek( (FILE*) finputid, start, end );
return seek_position;
}
int ftell_rbf( int finputid )
{
int file_size;
file_size = ftell( (FILE*) finputid );
return file_size;
}
int fgetc_rbf( int finputid )
{
int one_byte;
one_byte = fgetc( (FILE*) finputid );
return one_byte;
}
void delay ( int factor)
{
int i;
for (i=0;i<factor;i++) asm volatile("nop");
}
\ No newline at end of file
/****************************************************************************/
/* */
/* Module: mb_io.h (MicroBlaster) */
/* */
/* Copyright (C) Altera Corporation 2004 */
/* */
/* Descriptions: Defines all IO control functions. operating system */
/* is defined here. Functions are operating system */
/* dependant. */
/* */
/* Revisions: 1.0 12/10/01 Sang Beng Ng */
/* Supports Altera ByteBlaster hardware download cable */
/* on Windows NT. */
/* 1.1 05/28/04 Chuin Tein Ong */
/* Supports both Altera ByteBlaster II and ByteBlaster MV */
/* download cables on Windows NT. */
/* */
/****************************************************************************/
#ifndef INC_MB_IO_H
#define INC_MB_IO_H
#define EMBEDDED 2
/*///////////////////////*/
/* Functions Prototyping */
/*///////////////////////*/
int ReadByteBlaster ( int port );
void WriteByteBlaster ( int port, int data, int test );
#endif /* INC_MB_IO_H */
\ No newline at end of file
This diff is collapsed.
CC=gcc
OBJS = gen_pll_coefs.o
LDFLAGS =
CFLAGS =
OUTPUT = gen_pll_coefs
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
static const struct ad9516_regs ad9516_regs_tcxo = {
{
{ 0x0000, 0x18},
{ 0x0001, 0x00},
{ 0x0002, 0x10},
{ 0x0003, 0xc3},
{ 0x0004, 0x00},
{ 0x0010, 0x7c},
{ 0x0011, 0x01},
{ 0x0012, 0x00},
{ 0x0013, 0x06},
{ 0x0014, 0x08},
{ 0x0015, 0x00},
{ 0x0016, 0x04},
{ 0x0017, 0x00},
{ 0x0018, 0x07},
{ 0x0019, 0x00},
{ 0x001a, 0x00},
{ 0x001b, 0x00},
{ 0x001c, 0x06},
{ 0x001d, 0x00},
{ 0x001e, 0x00},
{ 0x001f, 0x0e},
{ 0x00a0, 0x01},
{ 0x00a1, 0x00},
{ 0x00a2, 0x00},
{ 0x00a3, 0x01},
{ 0x00a4, 0x00},
{ 0x00a5, 0x00},
{ 0x00a6, 0x01},
{ 0x00a7, 0x00},
{ 0x00a8, 0x00},
{ 0x00a9, 0x01},
{ 0x00aa, 0x00},
{ 0x00ab, 0x00},
{ 0x00f0, 0x0a},
{ 0x00f1, 0x0a},
{ 0x00f2, 0x0a},
{ 0x00f3, 0x0a},
{ 0x00f4, 0x0a},
{ 0x00f5, 0x08},
{ 0x0140, 0x42},
{ 0x0141, 0x42},
{ 0x0142, 0x42},
{ 0x0143, 0x5a},
{ 0x0190, 0x00},
{ 0x0191, 0x80},
{ 0x0192, 0x00},
{ 0x0193, 0x32},
{ 0x0194, 0x00},
{ 0x0195, 0x00},
{ 0x0196, 0x32},
{ 0x0197, 0x00},
{ 0x0198, 0x00},
{ 0x0199, 0x32},
{ 0x019a, 0x00},
{ 0x019b, 0x11},
{ 0x019c, 0x20},
{ 0x019d, 0x00},
{ 0x019e, 0x32},
{ 0x019f, 0x00},
{ 0x01a0, 0x11},
{ 0x01a1, 0x20},
{ 0x01a2, 0x00},
{ 0x01a3, 0x00},
{ 0x01e0, 0x00},
{ 0x01e1, 0x02},
{ 0x0230, 0x00},
{ 0x0231, 0x00},
{ 0x0232, 0x00},
{ 0x0232, 0x00},
{0}},
69
};
\ No newline at end of file
#include <stdio.h>
#include <inttypes.h>
#define AD9516_MAX_REGS 1024
struct ad9516_regs {
struct {
uint16_t addr;
uint8_t value;
} regs[AD9516_MAX_REGS];
int nregs;
};
int ad9516_load_regset(const char *filename, struct ad9516_regs *regs)
{
FILE *f;
char str[1024], tmp[100];
int start_read = 0, n = 0;
uint32_t addr, val;
f = fopen(filename ,"rb");
if(!f)
{
return -1;
}
while(!feof(f))
{
if(fgets(str, 1024, f) == EOF) break;
// printf("%s\n",str);
if(!strncmp(str, "Addr(Hex)", 8)) start_read = 1;
if(start_read)
{
if( sscanf(str, "%04x %08s %02x\n", &addr, tmp, &val) == 3)
{
regs->regs[n].addr = addr;
regs->regs[n].value = val;
n++;
}
}
}
regs->nregs = n;
fclose(f);
return 0;
}
main(int argc, char *argv[])
{
struct ad9516_regs r;
int i;
ad9516_load_regset(argv[1], &r);
printf("static const struct ad9516_regs %s = {\n", argv[2]);
printf("{\n");
for(i=0;i<r.nregs;i++)
{
printf( " { 0x%04x, 0x%02x},\n", r.regs[i].addr, r.regs[i].value);
}
printf("\n{0}},\n %d\n};", r.nregs);
return 0;
}
AD9516/17/18 Register Map File, Rev 1.0
Addr(Hex) Value(Bin) Value(Hex)
0000 00011000 18
0001 00000000 00
0002 00010000 10
0003 11000011 C3
0004 00000000 00
0010 01111100 7C
0011 00000001 01
0012 00000000 00
0013 00000110 06
0014 00001000 08
0015 00000000 00
0016 00000100 04
0017 00000000 00
0018 00000111 07
0019 00000000 00
001A 00000000 00
001B 00000000 00
001C 00000110 06
001D 00000000 00
001E 00000000 00
001F 00001110 0E
00A0 00000001 01
00A1 00000000 00
00A2 00000000 00
00A3 00000001 01
00A4 00000000 00
00A5 00000000 00
00A6 00000001 01
00A7 00000000 00
00A8 00000000 00
00A9 00000001 01
00AA 00000000 00
00AB 00000000 00
00F0 00001010 0A
00F1 00001010 0A
00F2 00001010 0A
00F3 00001010 0A
00F4 00001010 0A
00F5 00001000 08
0140 01000010 42
0141 01000010 42
0142 01000010 42
0143 01011010 5A
0190 00000000 00
0191 10000000 80
0192 00000000 00
0193 00110010 32
0194 00000000 00
0195 00000000 00
0196 00110010 32
0197 00000000 00
0198 00000000 00
0199 00110010 32
019A 00000000 00
019B 00010001 11
019C 00100000 20
019D 00000000 00
019E 00110010 32
019F 00000000 00
01A0 00010001 11
01A1 00100000 20
01A2 00000000 00
01A3 00000000 00
01E0 00000000 00
01E1 00000010 02
0230 00000000 00
0231 00000000 00
0232 00000000 00
include ../../../Makedefs
CC=$(CROSS_COMPILE_ARM)gcc
OBJS = hal_client.o
LDFLAGS = -lswitchhw -L../../libswitchhw -L../../libwripc -lwripc
CFLAGS = -I. -O2 -I../../include -I../../wrsw_hal -I../../libwripc -DDEBUG
OUTPUT = hal_client
all: $(OBJS)
make -C ../../libswitchhw
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) ../../drivers/bin/*.ko root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#include <stdio.h>
#include <stdlib.h>
#include <wr_ipc.h>
#include <wrsw_hal.h>
static wripc_handle_t hal_cli;
int halcli_check_running()
{
int rval;
wripc_call(hal_cli, "halexp_check_running", &rval, 0);
return rval;
}
main()
{
hal_cli = wripc_connect("wrsw_hal");
if(hal_cli < 0)
{
printf("Unable to connect to HAL\n");
return -1;
}
printf("HAL status: %s\n", halcli_check_running() ? "running" : "inactive");
}
CC=$(CROSS_COMPILE)gcc
OBJS = hello.o
LDFLAGS =
CFLAGS = -I. -O2 -I../../include -DDEBUG
OUTPUT = hello
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run:: all
scp $(OUTPUT) root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#!/bin/sh
. ../../../settings
t=`pwd`
cd ../../libswitchhw
./build.sh clean
./build.sh
cd $t
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
main() { printf("dupa!"); };
\ No newline at end of file
CC=$(CROSS_COMPILE)gcc
OBJS = hpll_wishbone_test.o term.o
LDFLAGS = -lswitchhw -L../../libswitchhw
CFLAGS = -I. -O2 -I../../include -DDEBUG
OUTPUT = hpll_wishbone_test
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#!/bin/sh
. ../../../settings
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
#include <stdio.h>
#include <stdlib.h>
#include <hw/hpll_regs.h>
int sign_extend(uint32_t val, int nbits)
{
if(val & (1<<(nbits-1))) return (0xffffffff ^ ((1<<nbits)-1)) | val; else return val;
}
main(int argc, char *argv[])
{
if(argc < 3) return -1;
FILE *fin, *fout;
uint32_t r0;
int npoints;
int i = 0;
fin = fopen(argv[1], "rb");
fout = fopen(argv[2], "wb");
npoints = atoi(argv[3]);
while(!feof(fin) && (++i < npoints))
{
fread(&r0, 4, 1, fin);
fprintf(fout, "%d %d %d %d\n", i,
sign_extend(HPLL_RFIFO_R0_ERR_VAL_R(r0), 12),
HPLL_RFIFO_R0_DAC_VAL_R(r0),
r0 & HPLL_RFIFO_R0_FP_MODE ? 60000 : 0);
}
}
\ No newline at end of file
#include <stdio.h>
#include <inttypes.h>
#include <sys/time.h>
#include <hw/switch_hw.h>
main()
{
trace_log_stderr();
shw_init();
// force the PHY enable/sync enable line HI
_fpga_writel(FPGA_BASE_GIGASPY_UP1 | GSPY_REG_GSTESTCTL, GSPY_GSTESTCTL_PHYIO_ENABLE | GSPY_GSTESTCTL_PHYIO_SYNCEN);
// set up the crosspoint to pass the data from PHY to SFPs
xpoint_configure();
shw_hpll_init();
for(;;)
{
printf("Locked: %d\n", shw_hpll_check_lock() ? 1: 0);
shw_hpll_update();
}
}
#!/bin/bash
IP=192.168.1.6
scp root@$IP:/tmp/hpll_meas.dat ./
./convert_meas hpll_meas.dat hpll_plotdata.dat 100000
gnuplot -e "set xlabel 'time'; set ylabel 'DAC value'; set y2label 'Phase/freq error'; set yrange [-10000:10000]; set y2range [0:65540]; plot 'hpll_plotdata.dat' using 1:2 title 'Phase/freq error' with lines axis x1y1, \
'hpll_plotdata.dat' using 1:3 title 'DAC drive' with lines axis x1y2, \
'hpll_plotdata.dat' using 1:4 title 'Freq/Phase mode' with lines axis x1y2; \
"
#, plot "hpll_plotdata.dat" using 1:3 title "integral value" with lines, plot "hpll_plotdata.dat" using 1:4 title "DAC drive" with lines'
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include <poll.h>
struct termios oldkey, newkey;
int term_restore()
{
tcsetattr(STDIN_FILENO,TCSANOW,&oldkey);
}
void term_init()
{
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
tcgetattr(STDIN_FILENO,&oldkey);
memcpy(&newkey, &oldkey, sizeof(struct termios));
newkey.c_cflag = B9600 | CRTSCTS | CS8 | CLOCAL | CREAD;
newkey.c_iflag = IGNPAR;
newkey.c_oflag = OPOST |ONLCR;
newkey.c_lflag = 0;
newkey.c_cc[VMIN]=1;
newkey.c_cc[VTIME]=0;
tcflush(STDIN_FILENO, TCIFLUSH);
tcsetattr(STDIN_FILENO,TCSANOW,&newkey);
atexit(term_restore);
}
int term_poll()
{
struct pollfd pfd;
pfd.fd = STDIN_FILENO;
pfd.events = POLLIN | POLLPRI;
if(poll(&pfd,1,0)>0)return 1;
return 0;
}
int term_get()
{
unsigned char c;
int q;
if(read(STDIN_FILENO, &c, 1 ) == 1)
{
q=c;
} else q=-1;
return q;
}
CC=$(CROSS_COMPILE)gcc
OBJS = minic_test.o term.o gigaspy.o
LDFLAGS = -lswitchhw -L../../libswitchhw
CFLAGS = -I. -O2 -I../../include -DDEBUG -I../../../kernel/include
OUTPUT = minic_test
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
${CC} -o timestamping timestamping.c $(CFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) ../../drivers/bin/*.ko root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT)"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#!/bin/sh
. ../../../settings
cd ../../libswitchhw
./build.sh
cd ../tests/minic_test
cd ../../drivers/wr_minic
./build.sh
cd ../../tests/minic_test
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <hw/switch_hw.h>
#include <hw/gigaspy_regs.h>
#include "gigaspy.h"
static inline void _gspy_writel(shw_gigaspy_context_t *gspy, uint32_t reg, uint32_t val)
{
*(volatile uint32_t *) (gspy->base + reg) = val;
}
static inline uint32_t _gspy_readl(shw_gigaspy_context_t *gspy, uint32_t reg)
{
uint32_t tmp = *(volatile uint32_t *)(gspy->base+reg);
return tmp;
}
shw_gigaspy_context_t *shw_gigaspy_init(uint32_t base_addr, int buffer_size)
{
shw_gigaspy_context_t *ctx;
ctx = shw_malloc(sizeof(shw_gigaspy_context_t));
ctx->base = (void*)_fpga_base_virt + base_addr;
ctx->buf_size = buffer_size;
return ctx;
}
void shw_gigaspy_configure(shw_gigaspy_context_t *gspy, int mode, int trig_source, int trig0, int trig1, int num_samples)
{
uint32_t gsctl = 0;
_gspy_writel(gspy, GSPY_REG_GSNSAMPLES, num_samples);
gspy->cur_nsamples = num_samples;
if(trig0 == TRIG_UNUSED && trig1 == TRIG_UNUSED)
_gspy_writel(gspy, GSPY_REG_GSTRIGCTL, 0); // no trigger (free-running mode)
else if (trig1 == TRIG_UNUSED)
_gspy_writel(gspy, GSPY_REG_GSTRIGCTL, trig0 | GSPY_GSTRIGCTL_TRIG0_EN(1));
else
_gspy_writel(gspy, GSPY_REG_GSTRIGCTL,
trig0 | GSPY_GSTRIGCTL_TRIG0_EN(1) |
(trig1<<16) | GSPY_GSTRIGCTL_TRIG1_EN(1));
gsctl = GSPY_GSCTL_CH0_ENABLE(1) | GSPY_GSCTL_CH1_ENABLE(1);
if(trig_source == GIGASPY_CH0)
gsctl |= GSPY_GSCTL_LOAD_TRIG0(1);// | GSPY_GSCTL_SLAVE0_ENABLE(1);
else
gsctl |= GSPY_GSCTL_LOAD_TRIG1(1);// | GSPY_GSCTL_SLAVE1_ENABLE(1);
gspy->cur_trig_src = trig_source;
printf("gsctl = %x\n", gsctl);
printf("trigctl = %x\n", _gspy_readl(gspy, GSPY_REG_GSTRIGCTL));
_gspy_writel(gspy, GSPY_REG_GSCTL, gsctl);
}
void shw_gigaspy_arm(shw_gigaspy_context_t *gspy)
{
uint32_t gsctl = _gspy_readl(gspy, GSPY_REG_GSCTL);
gsctl |= GSPY_GSCTL_RESET_TRIG0(1) | GSPY_GSCTL_RESET_TRIG1(1);
_gspy_writel(gspy, GSPY_REG_GSCTL, gsctl);
}
int shw_gigaspy_poll(shw_gigaspy_context_t *gspy)
{
uint32_t gsstat = _gspy_readl(gspy, GSPY_REG_GSSTAT);
// printf("GSSTAT: %x\n", gsstat);
if(gspy->cur_trig_src == GIGASPY_CH0)
return GSPY_GSSTAT_TRIG_DONE0(gsstat);
else
return GSPY_GSSTAT_TRIG_DONE1(gsstat);
}
static void read_gsbuf(shw_gigaspy_context_t *gspy, int ch, uint32_t addr, int n, uint32_t *buf)
{
uint32_t p, base = (ch == GIGASPY_CH0 ? (4*gspy->buf_size): (8*gspy->buf_size));
int i;
printf("baseaddr %x\n", base);
for(i=0;i<n;i++)
{
p = addr+i*4;
p &= ((4*gspy->buf_size)-1);
buf[i]=_gspy_readl(gspy, base+p);
}
}
static void hexprint(int start_addr, uint32_t *buf, int size)
{
int nempty = 0;
int n=0,i=0;
nempty = (start_addr % 16);
while(n<size)
{
if((i%16)==0)printf("\n%03x: ", start_addr + n);
if(nempty)
{
printf(" ");
nempty--;
} else {
int pos = (n+start_addr)&0x1fff;
printf(" %c%02x", buf[pos]&0x100?'K':' ', buf[pos]&0xff);
n++;
}
i++;
}
printf("\n");
}
static void dump_packet(int offs, int n, uint32_t *buf)
{
hexprint(offs, buf, n);
}
#define buf_get(x) buf[(offs+(x))&0x1fff]
static void dump_packet_ether(int offs, int n, uint32_t *buf)
{
int sfd_pos=-1;
int efd_pos=-1;
int i;
int fstart=0;
for(i=0;i<n;i++)
{
if((buf_get(i) == 0x1fb) && (sfd_pos<0)) sfd_pos = i;
if((buf_get(i) == 0x1fd) && (efd_pos<0)) efd_pos = i;
}
if(efd_pos < 0) {printf("dump_frame(): no EPD\n");return ; }
if(sfd_pos < 0) {printf("dump_frame(): no SFD\n");return ; }
if(sfd_pos >= efd_pos){printf("dump_frame(): SFD>EPD\n");return ; }
for(i=sfd_pos+1; i<sfd_pos+6;i++) if(buf_get(i)!=0x55) { printf("Adump_frame(): invalid preamble\n");return ; }
if((buf_get(sfd_pos+6) == 0x55) && (buf_get(sfd_pos+7) == 0xd5))fstart = sfd_pos+8;
if((buf_get(sfd_pos+6) == 0xd5)) fstart = sfd_pos+7;
if(!fstart) { printf("Bdump_frame(): invalid preamble\n"); return ;}
printf("ETHER DSTMac=%02x:%02x:%02x:%02x:%02x:%02x SRCMac=%02x:%02x:%02x:%02x:%02x:%02x Ethertype=0x%04x\n",
buf_get(sfd_pos+8), buf_get(sfd_pos+9),buf_get(sfd_pos+10),buf_get(sfd_pos+11),buf_get(sfd_pos+12),buf_get(sfd_pos+13),
buf_get(sfd_pos+14), buf_get(sfd_pos+15),buf_get(sfd_pos+16),buf_get(sfd_pos+17),buf_get(sfd_pos+18),buf_get(sfd_pos+19),
(buf_get(sfd_pos+20) << 8) + buf_get(sfd_pos+21));
}
void shw_gigaspy_dump(shw_gigaspy_context_t *gspy, int pretrigger, int num_samples, int mode, int channels)
{
uint32_t buf_ch0[GIGASPY_MAX_MEM_SIZE];
uint32_t buf_ch1[GIGASPY_MAX_MEM_SIZE];
uint32_t gstrigaddr = _gspy_readl(gspy, GSPY_REG_GSTRIGADDR);
uint32_t addr_ch0 = GSPY_GSTRIGADDR_CH0(gstrigaddr);
uint32_t addr_ch1 = GSPY_GSTRIGADDR_CH1(gstrigaddr);
read_gsbuf(gspy, GIGASPY_CH0, 0, gspy->buf_size, buf_ch0);
read_gsbuf(gspy, GIGASPY_CH1, 0, gspy->buf_size, buf_ch1);
if(channels & GIGASPY_CH0)
{
printf("---> CH0 dump: ");
if(mode == GIGASPY_DUMP_RAW)
// dump_packet(0, pretrigger + num_samples, buf_ch0 );
dump_packet((addr_ch0-gspy->cur_nsamples-pretrigger)&(gspy->buf_size-1), pretrigger+num_samples, buf_ch0 );
else
dump_packet_ether((addr_ch0-gspy->cur_nsamples-pretrigger)&0x1fff, pretrigger+num_samples, buf_ch0 );
}
if(channels & GIGASPY_CH1)
{
printf("---> CH1 dump: ");
if(mode == GIGASPY_DUMP_RAW)
dump_packet((addr_ch1-gspy->cur_nsamples-pretrigger)&0x1fff, pretrigger+num_samples, buf_ch1 );
else
dump_packet_ether((addr_ch1-gspy->cur_nsamples-pretrigger)&0x1fff, pretrigger+num_samples, buf_ch1 );
}
}
#ifndef __GIGASPY_H
#define __GIGASPY_H
#include <stdio.h>
#include <stdlib.h>
#include <sys/time.h>
#include <hw/switch_hw.h>
#define GIGASPY_CH0 0x1
#define GIGASPY_CH1 0x2
#define GIGASPY_KD(k,d) (((k)?(1<<8):0) | ((d) & 0xff))
#define GIGASPY_MAX_MEM_SIZE 16384
#define GIGASPY_DUMP_RAW 0
#define GIGASPY_DUMP_ETHER 1
#define TRIG_UNUSED -1
typedef struct {
int buf_size;
volatile void *base;
int cur_trig_src;
int cur_port;
int cur_nsamples;
} shw_gigaspy_context_t;
shw_gigaspy_context_t *shw_gigaspy_init(uint32_t base_addr, int buffer_size);
void shw_gigaspy_configure(shw_gigaspy_context_t *gspy, int mode, int trig_source, int trig0, int trig1, int num_samples);
void shw_gigaspy_arm(shw_gigaspy_context_t *gspy);
int shw_gigaspy_poll(shw_gigaspy_context_t *gspy);
void shw_gigaspy_dump(shw_gigaspy_context_t *gspy, int pretrigger, int num_samples, int mode, int channels);
#endif
#include <stdio.h>
#include <string.h>
#include <inttypes.h>
#include <sys/time.h>
#include <signal.h>
#include <hw/switch_hw.h>
#include <hw/clkb_io.h>
#include <hw/minic_regs.h>
#include <hw/endpoint_regs.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <arpa/inet.h>
//#include <net/if.h>
#include <asm/types.h>
#include <linux/if_packet.h>
#include <linux/if_ether.h>
#include <linux/if_arp.h>
#include <linux/net_tstamp.h>
#include <linux/sockios.h>
#include <linux/errqueue.h>
#include <sys/ioctl.h>
#include <sys/socket.h>
#include <sys/time.h>
#include <sys/ioctl.h>
#include <fcntl.h>
#include <errno.h>
#define MINIC_PBUF_SIZE_LOG2 (12)
#define MINIC_PBUF_SIZE (1<<MINIC_PBUF_SIZE_LOG2)
#define MINIC_BASE_ENDPOINT (1<<(MINIC_PBUF_SIZE_LOG2+2))
static inline void _ep_writel(uint32_t reg, uint32_t value)
{
_fpga_writel(FPGA_BASE_MINIC_UP1 + MINIC_BASE_ENDPOINT + reg, value);
}
static inline uint32_t _ep_readl(uint32_t reg)
{
return _fpga_readl(FPGA_BASE_MINIC_UP1 + MINIC_BASE_ENDPOINT + reg);
}
void endpoint_init()
{
// printf("Endpoint_init, base addr = %x\n", MINIC_BASE_ENDPOINT);
_ep_writel(EP_REG_ECR, 0); // ECR = 0?
_ep_writel(EP_REG_TCR, EP_TCR_EN_FRA | EP_TCR_EN_PCS); // enable TX framer + PCS
_ep_writel(EP_REG_RCR, EP_RCR_EN_FRA | EP_RCR_EN_PCS); // enable RX framer + PCS
_ep_writel(EP_REG_RFCR, 3 << EP_RFCR_QMODE_SHIFT); // QMODE = UNQUALIFIED
_ep_writel(EP_REG_MACH, 0xaabb); // assign a dummy MAC address
_ep_writel(EP_REG_MACL, 0xccddeeff);
_ep_writel(EP_REG_TSCR, 0);
_ep_writel(EP_REG_PHIO, EP_PHIO_ENABLE | EP_PHIO_SYNCEN); // enable the PHY
shw_pio_set0(PIN_up1_sfp_tx_disable); // enable the SFP
shw_pio_set0(PIN_up0_sfp_tx_disable); // enable the SFP
fprintf(stderr,"EP: waiting for sync...\n");
// while(!(_ep_readl(EP_REG_RCR) & EP_RCR_SYNCED));
// _ep_writel(EP_REG_TCR, EP_TCR_TX_CAL); // enable TX framer + PCS
// printf("LCW: %x\n", ep_rx_lcw(0));
// printf("LCW: %x\n", ep_rx_lcw(0));
return ;
}
int shw_ad9516_set_output_delay(int output, float delay_ns, int bypass);
void dump_counters()
{
const char *cntr_names[] = {
"0x0 : TX PCS buffer underruns",
"0x4 : RX PCS invalid 8b10b codes",
"0x8 : RX PCS sync lost events",
"0xc : RX PCS buffer overruns",
"0x10: RX CRC errors",
"0x14: RX valid frames",
"0x18: RX runt frames",
"0x1c: RX giant frames",
"0x20: RX PCS errors",
"0x24: RX dropped frames"
};
int i;
for(i=0;i<10;i++) printf("%-30s: %d\n", cntr_names[i], _ep_readl(0x80 + 4*i));
}
uint64_t get_tics()
{
struct timezone tz = {0,0};
struct timeval tv;
gettimeofday(&tv, &tz);
return (uint64_t) tv.tv_sec * 1000000ULL + (uint64_t) tv.tv_usec;
}
#define SO_TXTS_FRAME_TAG 38
static int poll_tx_timestamp(int sock, uint32_t *raw_ts)
{
char data[2048];
struct msghdr msg;
struct iovec entry;
struct sockaddr_ll from_addr;
struct {
struct cmsghdr cm;
char control[512];
} control;
int res;
memset(&msg, 0, sizeof(msg));
msg.msg_iov = &entry;
msg.msg_iovlen = 1;
entry.iov_base = data;
entry.iov_len = sizeof(data);
msg.msg_name = (caddr_t)&from_addr;
msg.msg_namelen = sizeof(from_addr);
msg.msg_control = &control;
msg.msg_controllen = sizeof(control);
res = recvmsg(sock, &msg, MSG_ERRQUEUE | MSG_DONTWAIT);
if(res >= 0)
{
fprintf(stderr,"GotErrQ\n");
}
return 0;
}
int test_tx_timestamps()
{
uint64_t tstart;
struct hwtstamp_config hwconfig;
struct sockaddr_ll sll, dest_addr;
struct ifreq f;
const char *if_name = "wru1";
const uint16_t if_ethertype = 0x88f7;
int enable;
int fd;
int ts_flags;
const uint8_t broadcast_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
const uint8_t my_mac[] = {0x00 ,0x50, 0xfc, 0x96, 0x9b, 0x0e};
fd = socket(AF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
if(fd < 0) { perror("socket()"); return -1; }
// strcpy(f.ifr_name, if_name);
// if(ioctl(fd, SIOCGIFFLAGS,&f) < 0) { perror("ioctl()"); return NULL; }
// f.ifr_flags |= IFF_PROMISC;
// if(ioctl(fd, SIOCSIFFLAGS,&f) < 0) { perror("ioctl()"); return NULL; }
strcpy(f.ifr_name, if_name);
ioctl(fd, SIOCGIFINDEX, &f);
sll.sll_ifindex = f.ifr_ifindex;
sll.sll_family = AF_PACKET;
sll.sll_protocol = htons(if_ethertype);
sll.sll_halen = 6;
if(bind(fd, (struct sockaddr *)&sll, sizeof(struct sockaddr_ll)) < 0)
{
close(fd);
perror("bind()");
return NULL;
}
fcntl(fd, F_SETFL, O_NONBLOCK);
hwconfig.tx_type = HWTSTAMP_TX_ON;
hwconfig.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
memset(&f, 0, sizeof(struct ifreq));
f.ifr_data = &hwconfig;
strncpy(f.ifr_name, if_name, sizeof(f.ifr_name));
if (ioctl(fd, SIOCSHWTSTAMP, &f) < 0) { perror("ioctl"); return -1; }
enable = 1;
if(setsockopt(fd, SOL_SOCKET, SO_TIMESTAMP, &enable, sizeof(enable)) < 0)
{ perror("setsockopt()"); return -1; }
if(setsockopt(fd, SOL_SOCKET, SO_TIMESTAMPNS, &enable, sizeof(enable)) < 0)
{ perror("setsockopt()"); return -1; }
ts_flags = SOF_TIMESTAMPING_TX_HARDWARE | SOF_TIMESTAMPING_RX_HARDWARE | SOF_TIMESTAMPING_RAW_HARDWARE;
if(setsockopt(fd, SOL_SOCKET, SO_TIMESTAMPING, &ts_flags, sizeof(ts_flags)) < 0)
{ perror("setsockopt()"); return -1; }
tstart =get_tics();
for(;;)
{
uint64_t t = get_tics();
// fprintf(stderr,"T-tstart %ld\n", t-tstart);
if(t - tstart > 1000000ULL)
{
char buf[64];
fprintf(stderr, "Send!");
tstart= t;
sll.sll_family = AF_PACKET;
sll.sll_protocol = htons(if_ethertype);
sll.sll_pkttype = PACKET_BROADCAST ;
sll.sll_halen = 6;
memcpy(buf, broadcast_addr, 6);
memcpy(buf+6, my_mac, 6);
buf[12] = if_ethertype >> 8;
buf[13] = if_ethertype & 0xff;
write(fd, buf, 64);
// send_with_ts(fd, buf, 64, &sll);
}
poll_tx_timestamp(fd, NULL);
}
}
main()
{
int i;
system("/sbin/rmmod /tmp/wr-minic.ko");
system("/sbin/rmmod /tmp/whiterabbit_vic.ko");
trace_log_stderr();
shw_init();
xpoint_configure();
endpoint_init();
// shw_ad9516_set_output_delay(6, 0, 0);
shw_ad9516_set_output_delay(9, 2, 0);
system("/sbin/insmod /tmp/whiterabbit_vic.ko");
system("/sbin/insmod /tmp/wr-minic.ko");
system("/sbin/ifconfig wru1 hw ether 00:50:fc:96:9b:0e");
system("/sbin/ifconfig wru1 up 192.168.100.100");
// test_rxts_fifo();
// test_tx_timestamps();
}
CC=$(CROSS_COMPILE)gcc
OBJS = ptpd_netif_mch.o ptpd_netif_test.o
LDFLAGS = -lswitchhw -L../../../libswitchhw
CFLAGS = -I. -O2 -I../../../include -DDEBUG -I../../../../kernel/include
OUTPUT = dupa
all: $(OBJS)
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
scp $(OUTPUT) root@$(T):/tmp
- ssh -t root@$(T) "/tmp/$(OUTPUT) wru1"
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
#!/bin/sh
. ../../../../settings
make CROSS_COMPILE=$CC_CPU $1 $2 $3 $4
// Network API for WR-PTPd
#ifndef __PTPD_NETIF_H
#define __PTPD_NETIF_H
#include <stdio.h>
#include <inttypes.h>
#define PTPD_SOCK_RAW_ETHERNET 1
#define PTPD_SOCK_UDP 2
#define PTPD_FLAGS_MULTICAST 0x1
#define PTPD_FLAGS_BIND_TO_PHYS_PORT 0x2
// error codes (to be extended)
#define PTPD_NETIF_OK 0
#define PTPD_NETIF_ERROR -1
#define PTPD_NETIF_NOT_READY -2
#define PTPD_NETIF_NOT_FOUND -3
// GCC-specific
#define PACKED __attribute__((packed))
#define PHYS_PORT_ANY (0xffff)
// Some system-independent definitions
typedef uint8_t mac_addr_t[6];
typedef uint32_t ipv4_addr_t;
// WhiteRabbit socket - it's void pointer as the real socket structure is private and probably platform-specific.
typedef void *wr_socket_t;
// Socket address for ptp_netif_ functions
typedef struct {
// Network interface name (eth0, ...)
char *if_name;
// Socket family (RAW ethernet/UDP)
int family;
// MAC address
mac_addr_t mac;
// Destination MASC address, filled by recvfrom() function on interfaces bound to multiple addresses
mac_addr_t mac_dest;
// IP address
ipv4_addr_t ip;
// UDP port
uint16_t port;
// RAW ethertype
uint16_t ethertype;
// physical port to bind socket to
uint16_t physical_port;
} wr_sockaddr_t;
// PTP 10-byte timestamp
PACKED struct _wr_timestamp {
struct {
uint16_t hi;
uint32_t lo;
} seconds; //seconds field (u48)
uint32_t nanoseconds; //nanoseconds field(u32)
struct {
uint32_t f_cntr;
uint32_t r_cntr;
} wr; // whiterabbit raw hardware timestamp
};
typedef struct _wr_timestamp wr_timestamp_t;
// Frame tag type used for gathering TX timestamps
typedef uint32_t wr_frame_tag_t;
/* OK. These functions we'll develop along with network card driver. You can write your own UDP-based stubs for testing purposes. */
// Initialization of network interface:
// - opens devices
// - does necessary ioctls()
int ptpd_netif_init();
// Creates UDP or Ethernet RAW socket (determined by sock_type) bound to bind_addr. If PTPD_FLAG_MULTICAST is set, the socket is
// automatically added to multicast group. User can specify physical_port field to bind the socket to specific switch port only.
wr_socket_t *ptpd_netif_create_socket(int sock_type, int flags, wr_sockaddr_t *bind_addr);
// Sends a UDP/RAW packet (data, data_length) to address provided in wr_sockaddr_t.
// For raw frames, mac/ethertype needs to be provided, for UDP - ip/port.
// Every transmitted frame has assigned a tag value, stored at tag parameter. This value is later used
// for recovering the precise transmit timestamp. If user doesn't need it, tag parameter can be left NULL.
int ptpd_netif_sendto(wr_socket_t *sock, wr_sockaddr_t *to, void *data, size_t data_length, wr_frame_tag_t *tag);
// Polls for transmit timestamp of previously sent frame having tag value specified by tag parameter. Timestamp value is stored in tx_timestamp.
// Return value:
// PTPD_NETIF_OK: tx timestamp gathered correctly
// PTPD_NETIF_NOT_READY: tx timestamp hasn't been yet received from endpoint
// PTPD_NETIF_NOT_FOUND: no timestamp information for frame having given tag
int ptpd_netif_poll_tx_timestamp(wr_socket_t *sock, wr_frame_tag_t tag, wr_timestamp_t *tx_timestamp);
// Receives an UDP/RAW packet. Data is written to (data) and length is returned. Maximum buffer length can be specified
// by data_length parameter. Sender information is stored in structure specified in 'from'. All RXed packets are timestamped and the timestamp
// is stored in rx_timestamp (unless it's NULL).
int ptpd_netif_recvfrom(wr_socket_t *sock, wr_sockaddr_t *from, void *data, size_t data_length, wr_timestamp_t *rx_timestamp);
// Closes the socket.
int ptpd_netif_close_socket(wr_socket_t *sock);
#endif
This diff is collapsed.
// Similation of real WR network interface with hardware timestamping. Supports only raw ethernet now.
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "ptpd_netif.h"
char *format_mac_addr(mac_addr_t mac)
{
char buf[32];
snprintf(buf,32,"%02x:%02x:%02x:%02x:%02x:%02x", mac[0],mac[1],mac[2],mac[3],mac[4],mac[5]);
return strdup(buf);
}
char *format_wr_timestamp(wr_timestamp_t ts)
{
char buf[64];
snprintf(buf,64, "rising: %09d nsec, failling: %03d nsec", ts.wr.r_cntr * 8, ts.wr.f_cntr * 8);
return strdup(buf);
}
// peer delay multicast address
const mac_addr_t PTP_MULTICAST_PDELAY[6] = {0x01, 0x80, 0xc2, 0x00, 0x00, 0x0e};
main(int argc, char *argv[])
{
wr_sockaddr_t bindaddr, to_addr, from_addr;
wr_socket_t *sock;
char buf[1518];
int len;
if(argc < 2)
{
printf("usage: %s network_interface. Run me as root!\n\n", argv[0]);
return -1;
}
// Initialize the netif library
ptpd_netif_init();
// Create a PTP socket:
bindaddr.if_name = strdup(argv[1]); // network intarface
bindaddr.family = PTPD_SOCK_RAW_ETHERNET; // socket type
bindaddr.ethertype = 0x88f7; // PTPv2
memset(bindaddr.mac, 0, 6); // bind to any address (e.g. accepting everything which has 88f7 type)
// Create the socket
sock = ptpd_netif_create_socket(PTPD_SOCK_RAW_ETHERNET, 0, &bindaddr);
// Set destination address
memcpy(to_addr.mac, PTP_MULTICAST_PDELAY, 6);
// and ethertype
to_addr.ethertype = 0x88f7;
for(;;)
{
wr_frame_tag_t tag;
wr_timestamp_t tx_ts, rx_ts;
// Send a frame and get its TX timestamp
ptpd_netif_sendto(sock, &to_addr, buf, 64, &tag);
if(ptpd_netif_poll_tx_timestamp(sock, tag, &tx_ts) == PTPD_NETIF_OK) {
fprintf(stderr, "TX timestamp: %s\n", format_wr_timestamp(tx_ts));
}
sleep(1);
// receive any incoming frames and their timestamps
while( (len = ptpd_netif_recvfrom(sock, &from_addr, buf, 1518, &rx_ts)) > 0)
{
printf("RX frame: from=%s, to=%s, type=0x%04x, timestamp: %s\n",
format_mac_addr(from_addr.mac),
format_mac_addr(from_addr.mac_dest),
from_addr.ethertype,
format_wr_timestamp(rx_ts));
}
}
return 0;
}
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <termios.h>
#include <poll.h>
struct termios oldkey, newkey;
int term_restore()
{
tcsetattr(STDIN_FILENO,TCSANOW,&oldkey);
}
void term_init()
{
fcntl(STDIN_FILENO, F_SETFL, O_NONBLOCK);
tcgetattr(STDIN_FILENO,&oldkey);
memcpy(&newkey, &oldkey, sizeof(struct termios));
newkey.c_cflag = B9600 | CRTSCTS | CS8 | CLOCAL | CREAD;
newkey.c_iflag = IGNPAR;
newkey.c_oflag = OPOST |ONLCR;
newkey.c_lflag = 0;
newkey.c_cc[VMIN]=1;
newkey.c_cc[VTIME]=0;
tcflush(STDIN_FILENO, TCIFLUSH);
tcsetattr(STDIN_FILENO,TCSANOW,&newkey);
atexit(term_restore);
}
int term_poll()
{
struct pollfd pfd;
pfd.fd = STDIN_FILENO;
pfd.events = POLLIN | POLLPRI;
if(poll(&pfd,1,0)>0)return 1;
return 0;
}
int term_get()
{
unsigned char c;
int q;
if(read(STDIN_FILENO, &c, 1 ) == 1)
{
q=c;
} else q=-1;
return q;
}
void clear_screen()
{
printf("\033[2J\033[1;1H");
}
\ No newline at end of file
This diff is collapsed.
include ../../../Makedefs
CC=$(CROSS_COMPILE_ARM)gcc
OBJS = rtu_test.o
LDFLAGS = -lswitchhw -L../../libswitchhw -L../../libwripc -L../../libptpnetif -lwripc -lptpnetif
CFLAGS = -I. -O2 -I../../include -DDEBUG -I../../../kernel/include -I../../libptpnetif -I../../wrsw_hal -I../../libwripc -g
OUTPUT = rtu_test
all: $(OBJS)
make -C ../../libswitchhw
${CC} -o $(OUTPUT) $(OBJS) $(LDFLAGS)
%.o: %.c
${CC} -c $^ $(CFLAGS)
run: all
- scp $(OUTPUT) root@192.168.1.6:/tmp
- scp $(OUTPUT) root@192.168.1.13:/tmp
install: all
mkdir -p ../../rootfs_override/root/tests
cp $(OUTPUT) ../../rootfs_override/root/tests
clean:
rm -f $(OUTPUT) $(OBJS)
\ No newline at end of file
/*
-------------------------------------------------------------------------------
-- Title : Routing Table Unit Test Interface
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : rtu_test.c
-- Authors : Maciej Lipinski (maciej.lipinski@cern.ch)
-- Company : CERN BE-CO-HT
-- Created : 2010-06-30
-- Last update: 2010-06-30
-- Description: This file stores entire test interface, which includes:
-- - functions used of data entry (VLAN, HCAM, HTAB, CONFIG) in both:
-- simulation and hardware
-- - functions used for request management
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <hw/switch_hw.h>
#include <hal_client.h>
#include "wrsw_rtu.h"
#include "rtu_testunit.h"
static volatile struct RTU_WB *RTU;
static volatile struct RTT_WB *RTT;
#define RTU_BANK_SIZE 65536
struct rtu_state {
uint32_t htab[2][RTU_BANK_SIZE];
int current_bank;
};
void zbt_write(uint32_t base, uint32_t *data, size_t nwords)
{
while(RTU->MFIFO_CSR & RTU_MFIFO_CSR_FULL);
RTU->MFIFO_R0 = RTU_MFIFO_R0_AD_SEL;
RTU->MFIFO_R1 = base;
while(nwords--)
{
while(RTU->MFIFO_CSR & RTU_MFIFO_CSR_FULL);
RTU->MFIFO_R0 = 0;
RTU->MFIFO_R1 = *data++;
}
}
void zbt_clear()
{
const int n_words = 65530;
uint32_t *tmp;
tmp = malloc(n_words * 4);
memset(tmp, 0, n_words * 4);
zbt_write(0, tmp, n_words);
free(tmp);
}
void poll_ufifo()
{
if(! (RTU->UFIFO_CSR & RTU_UFIFO_CSR_EMPTY))
{
uint32_t r0, r1, r2, r3, r4;
r0 = RTU->UFIFO_R0;
r1 = RTU->UFIFO_R1;
r2 = RTU->UFIFO_R2;
r3 = RTU->UFIFO_R3;
r4 = RTU->UFIFO_R4;
printf("UFIFO: port %d DstMac %02x:%02x:%02x:%02x:%02x:%02x SrcMac %02x:%02x:%02x:%02x:%02x:%02x ",
RTU_UFIFO_R4_PID_R(r4),
(r1 >> 8) & 0xff,
(r1 >> 0) & 0xff,
(r0 >> 24) & 0xff,
(r0 >> 16) & 0xff,
(r0 >> 8) & 0xff,
(r0 >> 0) & 0xff,
(r3 >> 8) & 0xff,
(r3 >> 0) & 0xff,
(r2 >> 24) & 0xff,
(r2 >> 16) & 0xff,
(r2 >> 8) & 0xff,
(r2 >> 0) & 0xff);
if(r4 & RTU_UFIFO_R4_HAS_VID)
printf("VLAN: %d ", RTU_UFIFO_R4_VID_R(r4));
if(r4 & RTU_UFIFO_R4_HAS_PRIO)
printf("Priority: %d ", RTU_UFIFO_R4_PRIO_R(r4));
printf("\n");
}
}
void poll_test_unit()
{
uint32_t fpr = RTT -> FPR;
uint32_t mask ,port;
for(port = 0, mask = 1; port < 10; port++, mask<<=1)
{
if(! (fpr & mask))
{
volatile uint32_t *rfifo = ((volatile uint32_t *) &RTT->RFIFO_CH0_R0) + port;
volatile uint32_t ent;
while(! (RTT->FPR & mask))
{
ent = *rfifo;
printf("RSP [port %d DPM=%08x prio=%d drop=%d\n", port, RTT_RFIFO_CH0_R0_DPM_R(ent), RTT_RFIFO_CH0_R0_PRIO_R(ent), ent & RTT_RFIFO_CH0_R0_DROP ? 1: 0);
}
}
}
};
void init()
{
if(halexp_client_init() < 0)
{
printf("Oops... Looks like the HAL is not running :( \n\n");
exit(-1);
}
shw_fpga_mmap_init();
RTU = _fpga_base_virt + FPGA_BASE_RTU;
RTT = _fpga_base_virt + FPGA_BASE_RTU_TESTUNIT;
RTU->GCR = RTU_GCR_HT_BSEL | RTU_GCR_G_ENA;
zbt_clear();
RTU->GCR = RTU_GCR_G_ENA;
RTU->PCR0 = RTU_PCR0_LEARN_EN | RTU_PCR0_PASS_ALL | RTU_PCR0_B_UNREC | RTU_PCR0_PRIO_VAL_W(3) | RTU_PCR0_FIX_PRIO;
RTU->PCR1 = RTU_PCR0_LEARN_EN | RTU_PCR0_PASS_ALL | RTU_PCR0_B_UNREC | RTU_PCR0_PRIO_VAL_W(3) | RTU_PCR0_FIX_PRIO;
}
main()
{
init();
for(;;)
{
poll_ufifo();
poll_test_unit();
}
}
\ No newline at end of file
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