Phase shift of 10 MHz output to prevent jitter

88e9424d · José López Jiménez · 0d49c996 · 88e9424d · 88e9424d
Commit 88e9424d authored Jun 25, 2020 by José López Jiménez
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rt_cpu.elf binaries/rt_cpu.elf +0 -0

wrs_release_defconfig configs/wrs_release_defconfig +2 -2

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--- a/binaries/rt_cpu.elf
+++ b/binaries/rt_cpu.elf
--- a/configs/wrs_release_defconfig
+++ b/configs/wrs_release_defconfig
@@ -104,8 +104,8 @@ CONFIG_SNMP_TEMP_THOLD_PSR=80
 #
 CONFIG_WRSAUXCLK_FREQ="10"
 CONFIG_WRSAUXCLK_DUTY="0.5"
-CONFIG_WRSAUXCLK_CSHIFT="36"
-CONFIG_WRSAUXCLK_SIGDEL="0"
+CONFIG_WRSAUXCLK_CSHIFT="30"
+CONFIG_WRSAUXCLK_SIGDEL="5"
 CONFIG_WRSAUXCLK_PPSHIFT="0"

 #