Commit 78719448 authored by Benoit Rat's avatar Benoit Rat Committed by Alessandro Rubini

build, userspace: supporting LX130T & LX240T FPGAs

* flash-wrs: add gateware selection to only use 2 HDL binaries because the RAM size is not big enough to extract 4 HDLs during flashing
* build: add the new gatewares with PWM and LX240T support for 18ports & 8ports
* userspace: Select the proper gateware to load on fpga using the shw_ver tool and the i2c dip switch on miniBP
parent 89322f34
......@@ -19,8 +19,8 @@ linux-2.6.39.tar.bz2 1aab7a741abe08d42e8eccf20de61e05 \
http://www.kernel.org/pub/linux/kernel/v2.6/linux-2.6.39.tar.bz2
# our gateware binaries
wrs3-gw-v3.0-20120801.tar.gz 28a7ac3ec004d3e441c232fa125d820a \
http://www.ohwr.org/attachments/download/1485/wrs3-gw-v3.0-20120801.tar.gz
wrs3-gw-v3.3-20130213.tar.gz f7cd4323aa4de317d3fa8a0fd8c82479 \
http://www.ohwr.org/attachments/download/1909/wrs3-gw-v3.3-20130213.tar.gz
# buildroot core and packages
buildroot-2011.11.tar.bz2 7b852f4ef17c63857ca7b9388b782070 \
......
......@@ -25,6 +25,7 @@ showhelp()
printf "Options: \n"
printf " -h|--help\t Show this help message\n"
printf " -m|--mode\t can be: default (df and nf), df (dataflash),\n\t\t nf (nandflash), ddr (ddr memories).\n"
printf " -g|--gateware\t Select the gateware: 18p (18 ports, default), 8p (8 ports), LX130T (small FPGA), LX240T (big FGPA)\n"
printf " -e \t\t Completely erase the memory (Can erase your configuration)\n"
printf " -b|--build\t Use files that you have built in the WRS_OUTPUT_DIR\n"
printf " -m1|--mac1\t Default MAC address for the ethernet port on board\n"
......@@ -107,6 +108,10 @@ MAC1=$MAC1_DEF
MAC2_DEF="02:34:56:78:9A:00"
MAC2=$MAC2_DEF
# By default we select the gateware only for 18ports because 8ports are
# only used by developper.
gateware="18p*.bin"
DEV=""
FLAGS=""
......@@ -156,6 +161,19 @@ while [ $# -ge 1 ]; do
fi
memmode="$2"
shift; shift;;
-g|--gateware)
# Obtain which gateware type we want to keep for flash
if [ "$2" = "18p" ] || [ "$2" = "8p" ]; then
gateware="$2*.bin";
elif [ "$2" = "LX240T" ] || [ "$2" = "LX130T" ]; then
gateware="*-$2.bin";
else
echo "Error: Invalid gateware selection \"$2\""
showhelp
exit 1
fi
shift; shift;;
/* ) DEV="-s $1"; shift ;;
......@@ -269,6 +287,9 @@ if [ $nf ]; then
TMPSCRIPT=$TMPDIR/wrsrootfs-script
cat > $TMPSCRIPT << EOF
tar --directory $TMPFS -xzf $rootfsgz
# Remove the unnecessary HDL files, by default we keep 18 ports HDL for both FPGA type
# (There is not enough place in DDR to extract 4 HDLs, be carefull if you add custom files)
find $TMPFS/wr/lib/firmware/ -type f \( ! -name ''${gateware}'' \) -a \( ! -name '*rt_cpu.bin' \) -exec rm -f {} \;
mkfs.jffs2 --little-endian --eraseblock=0x20000 -n --pad -d $TMPFS -o $rootfsjffs2
......
......@@ -21,11 +21,13 @@ else
fi
if [ "$WRS_HW_DIR" != "" ]; then
wrs_echo "Copying binaries from $WRS_HW_DIR"
cp ${WRS_HW_DIR}/syn/scb_8ports/scb_top_synthesis.bin $FWDIR/8ports_mb.bin
cp ${WRS_HW_DIR}/syn/scb_18ports/scb_top_synthesis.bin $FWDIR/18ports_mb.bin
wrs_echo "Copying binaries from $WRS_HW_DIR"
cp ${WRS_HW_DIR}/syn/scb_8ports/scb_top_synthesis.bin $FWDIR/8p_mb-LX130T.bin
cp ${WRS_HW_DIR}/syn/scb_18ports/scb_top_synthesis.bin $FWDIR/18p_mb-LX130T.bin
# cp ${WRS_HW_DIR}/syn/scb_8ports/scb_top_synthesis.bin $FWDIR/8p_mb-LX240T.bin
# cp ${WRS_HW_DIR}/syn/scb_18ports/scb_top_synthesis.bin $FWDIR/18p_mb-LX240T.bin
else
tarname="wrs3-gw-v3.0-20120801.tar.gz"
tarname="wrs3-gw-v3.3-20130213.tar.gz"
wrs_echo "Using pre-build binaries from $tarname"
wrs_download $tarname
tar xzf $WRS_DOWNLOAD_DIR/$tarname -C $FWDIR
......
......@@ -9,8 +9,10 @@ for arg in $(cat /proc/cmdline); do
fi;
done
# Obtain the type of FPGA (LX130XT or LX240XT)
tfpga=$($WR_HOME/bin/shw_ver -f)
$WR_HOME/bin/load-virtex $WR_HOME/lib/firmware/18ports_mb.bin
$WR_HOME/bin/load-virtex $WR_HOME/lib/firmware/18p_mb-${tfpga}.bin
$WR_HOME/bin/load-lm32 $WR_HOME/lib/firmware/rt_cpu.bin
insmod $WR_HOME/lib/modules/at91_softpwm.ko
insmod $WR_HOME/lib/modules/wr_vic.ko
......
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