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White Rabbit Switch - Software
Commit 670794fe authored by Maciej Lipinski's avatar Maciej Lipinski
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Update endpoint headers in kernel/wbgen-regs 

the update includes
- some new registers that were added long time ago to HDL but
  the headers in SW were not updated
- Low Phase Drift configuration in MDIO/PCS and EP regs
parent de84eab3
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Showing with 313 additions and 56 deletions
kernel/wbgen-regs/endpoint-mdio.h
View file @ 670794fe
......@@ -13,12 +13,16 @@
#ifndef __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#define __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -371,6 +375,33 @@
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 5)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 5)
/* definitions for register: MDIO Extended Control Register */
/* definitions for field: Loopback - detailed in reg: MDIO Extended Control Register */
#define MDIO_ECTRL_LPBCK_VEC_MASK WBGEN2_GEN_MASK(0, 3)
#define MDIO_ECTRL_LPBCK_VEC_SHIFT 0
#define MDIO_ECTRL_LPBCK_VEC_W(value) WBGEN2_GEN_WRITE(value, 0, 3)
#define MDIO_ECTRL_LPBCK_VEC_R(reg) WBGEN2_GEN_READ(reg, 0, 3)
/* definitions for field: SFP TX Fault Status in reg: MDIO Extended Control Register */
#define MDIO_ECTRL_SFP_TX_FAULT WBGEN2_GEN_MASK(3, 1)
/* definitions for field: SFP LOS in reg: MDIO Extended Control Register */
#define MDIO_ECTRL_SFP_LOSS WBGEN2_GEN_MASK(4, 1)
/* definitions for field: SFP TX Disable in reg: MDIO Extended Control Register */
#define MDIO_ECTRL_SFP_TX_DISABLE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: tx_prbs_sel in reg: MDIO Extended Control Register */
#define MDIO_ECTRL_TX_PRBS_SEL_MASK WBGEN2_GEN_MASK(8, 3)
#define MDIO_ECTRL_TX_PRBS_SEL_SHIFT 8
#define MDIO_ECTRL_TX_PRBS_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define MDIO_ECTRL_TX_PRBS_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for register: Low phase drift calibration status register */
/* definitions for register: Low phase drift calibration control register */
PACKED struct MDIO_WB {
/* [0x0]: REG MDIO Control Register */
uint32_t MCR;
......@@ -392,6 +423,12 @@ PACKED struct MDIO_WB {
uint32_t ESTATUS;
/* [0x40]: REG WhiteRabbit-specific Configuration Register */
uint32_t WR_SPEC;
/* [0x44]: REG MDIO Extended Control Register */
uint32_t ECTRL;
/* [0x48]: REG Low phase drift calibration status register */
uint32_t LPC_PHY_STAT;
/* [0x4c]: REG Low phase drift calibration control register */
uint32_t LPC_PHY_CTRL;
};
#endif
kernel/wbgen-regs/endpoint-mdio.wb
View file @ 670794fe
......@@ -36,6 +36,7 @@
peripheral {
name = "WR Endpoint 1000base-X TBI PCS register block";
description = "WR Endpoint 1000base-X TBI PCS register block";
hdl_entity = "ep_pcs_tbi_mdio_wb";
prefix = "MDIO";
......@@ -153,15 +154,15 @@ peripheral {
field {
name = "Loopback";
description = "1 = enable loopback mode \
0 = disable loopback mode \
With the TBI version, loopback bit is connected to PHY loopback enable pin. When set to 1, indicates to the external PHY to enter loopback mode";
description = "1 enable loopback mode \
0 = disable loopback mode \
With the TBI version, loopback bit is connected to PHY loopback enable pin. When set to 1, indicates to the external PHY to enter loopback mode";
prefix = "loopback";
align = 14;
align = 14;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
......@@ -720,5 +721,99 @@ peripheral {
clock = "rx_clk_i";
};
};
reg {
name = "MDIO Extended Control Register";
prefix = "ECTRL";
field {
name = "Loopback - detailed";
description = "Loopback vector for Xilinx PHYs: \
100 = far end loopback mode \
000 = normal mode \
See also Transceiver documentation (for example Xilinx UG476 Table 2-37 and Figure 2-23 \
LOOPBACK bit set to 1 in MCR register may override LPBCK_VEC depending on the PHY wrapper implementation";
prefix = "lpbck_vec";
align = 0;
size = 3;
value = 0;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SFP TX Fault Status";
description = "1 = Some kind of laser failure\
0 = SFP Laser okay";
prefix = "sfp_tx_fault";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "SFP LOS";
description = "1 = Loss of signal\
0 = SFP Receiver signal strength okay";
prefix = "sfp_loss";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "SFP TX Disable";
description = "Disables the SFP Transmitter \
1 = SFP TX Disabled\
0 = SFP TX Enabled";
prefix = "sfp_tx_disable";
type = BIT;
value = 0;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx_prbs_sel";
description = "PRBS selection \
000 = Normal mode\
0010 = PRBS-7";
prefix = "tx_prbs_sel";
align = 8;
size = 3;
value = 0;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Low phase drift calibration status register";
description = "Low phase drift calibration status register - dependent on calibrated PHY";
prefix = "LPC_PHY_STAT";
field {
name = "Control word 0";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Low phase drift calibration control register";
description = "Low phase drift calibration control register - dependent on calibrated PHY";
prefix = "LPC_PHY_CTRL";
field {
name = "Control word 0";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
kernel/wbgen-regs/endpoint-regs.h
View file @ 670794fe
......@@ -13,12 +13,16 @@
#ifndef __WBGEN2_REGDEFS_ENDPOINT
#define __WBGEN2_REGDEFS_ENDPOINT
#ifdef __KERNEL__
#include <linux/types.h>
#else
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -52,6 +56,9 @@
/* definitions for field: Receive path enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Generate preamble shrinkage in reg: Endpoint Control Register */
#define EP_ECR_TXSHRIN_EN WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Feature present: VLAN tagging in reg: Endpoint Control Register */
#define EP_ECR_FEAT_VLAN WBGEN2_GEN_MASK(24, 1)
......@@ -64,6 +71,9 @@
/* definitions for field: Feature present: DPI packet classifier in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DPI WBGEN2_GEN_MASK(27, 1)
/* definitions for field: Feature present: low phase drift calibration in reg: Endpoint Control Register */
#define EP_ECR_FEAT_LPC WBGEN2_GEN_MASK(28, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
......@@ -84,7 +94,6 @@
/* definitions for field: RX timestamper calibration result flag in reg: Timestamping Control Register */
#define EP_TSCR_RX_CAL_RESULT WBGEN2_GEN_MASK(5, 1)
/* definitions for register: RX Deframer Control Register */
/* definitions for field: RX accept runts in reg: RX Deframer Control Register */
......@@ -189,12 +198,18 @@
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
/* definitions for field: RX Pause 802.3 enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
/* definitions for field: TX Pause 802.3 enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Rx Pause 802.1Q enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE_802_1Q WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Tx Pause 802.1Q enable (not implemented) in reg: Flow Control Register */
#define EP_FCR_TXPAUSE_802_1Q WBGEN2_GEN_MASK(3, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
......@@ -276,9 +291,35 @@
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
/* definitions for register: PCK Injection CTRL */
/* definitions for field: Config: Interframe GAP in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_CONF_IFG_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_INJ_CTRL_PIC_CONF_IFG_SHIFT 0
#define EP_INJ_CTRL_PIC_CONF_IFG_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_INJ_CTRL_PIC_CONF_IFG_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Config: packet pattern sel id in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_CONF_SEL_MASK WBGEN2_GEN_MASK(16, 3)
#define EP_INJ_CTRL_PIC_CONF_SEL_SHIFT 16
#define EP_INJ_CTRL_PIC_CONF_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 3)
#define EP_INJ_CTRL_PIC_CONF_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 3)
/* definitions for field: Config: valid in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_CONF_VALID WBGEN2_GEN_MASK(19, 1)
/* definitions for field: Mode: packet generate mode in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_MODE_ID_MASK WBGEN2_GEN_MASK(20, 3)
#define EP_INJ_CTRL_PIC_MODE_ID_SHIFT 20
#define EP_INJ_CTRL_PIC_MODE_ID_W(value) WBGEN2_GEN_WRITE(value, 20, 3)
#define EP_INJ_CTRL_PIC_MODE_ID_R(reg) WBGEN2_GEN_READ(reg, 20, 3)
/* definitions for field: Mode: valid in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_MODE_VALID WBGEN2_GEN_MASK(23, 1)
/* definitions for field: Frame Generation Enabled in reg: PCK Injection CTRL */
#define EP_INJ_CTRL_PIC_ENA WBGEN2_GEN_MASK(24, 1)
PACKED struct EP_WB {
/* [0x0]: REG Endpoint Control Register */
......@@ -315,10 +356,8 @@ PACKED struct EP_WB {
uint32_t DMCR;
/* [0x40]: REG DMTD Status register */
uint32_t DMSR;
/* padding to: 32 words */
uint32_t __padding_0[15];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
/* [0x44]: REG PCK Injection CTRL */
uint32_t INJ_CTRL;
};
#endif
kernel/wbgen-regs/endpoint-regs.wb
View file @ 670794fe
......@@ -86,6 +86,17 @@ peripheral {
type = BIT;
};
field {
name = "Generate preamble shrinkage";
prefix = "TXSHRIN_en";
description = "1: TX preamble shrinkage enabled\
0: TX preamble shrinkage disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Feature present: VLAN tagging";
description = "1: this implementation of WR Endpoint supports VLAN processing \
......@@ -130,6 +141,16 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: low phase drift calibration";
description = "1: this port can be calibrated for low phase uncertainty on link up\
0: this is a standard WR port with regular performance";
prefix = "FEAT_LPC";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -179,6 +200,24 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "tx_clk_i";
};
field {
name = "Start calibration of RX timestamper";
prefix = "RX_CAL_START";
description = "write 1: start calibration.\
write 0: no effect";
type = MONOSTABLE;
clock = "rx_clk_i";
};
field {
name = "RX timestamper calibration result flag";
prefix = "RX_CAL_RESULT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
......@@ -258,7 +297,6 @@ peripheral {
11: unqualified port - passes all traffic regardless of VLAN configuration";
type = SLV;
size = 2;
align = 2;
prefix = "Qmode";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
......@@ -404,38 +442,50 @@ peripheral {
prefix = "FCR";
field {
name = "RX Pause enable";
description = "1: enable reception of pause frames and TX path throttling \
0: disable reception of pause frames";
name = "RX Pause 802.3 enable";
description = "1: enable reception of pause frames defined in 802.3 (all priorities) and TX path throttling \
0: disable reception of pause frames defined in 802.3";
prefix = "RXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
load = LOAD_EXT;
};
field {
name = "TX Pause enable";
name = "TX Pause 802.3 enable";
description = "1: enable transmission of pause frames and RX path throttling \
0: disable transmission of pause frames";
prefix = "TXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Rx Pause 802.1Q enable";
description = "1: enable reception of priority-based pause frames (IEEE 802.1Q-2012 Flow Control) \
0: disable reception of priority-based pause frames";
prefix = "RXPAUSE_802_1Q";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Tx Pause 802.1Q enable (not implemented)";
description = "1: enable transmission of priority-based pause frames (IEEE 802.1Q-2012) Flow Control \
0: disable transmission of priority-based pause frames";
prefix = "TXPAUSE_802_1Q";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
load = LOAD_EXT;
};
field {
name = "TX pause threshold";
description = "Defines the percentage of space occupied in the RX buffer which triggers the transmission of a PAUSE frame. 0 = empty buffer, 255 = full buffer";
prefix = "TX_THR";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 8;
align = 8;
load = LOAD_EXT;
};
field {
......@@ -443,11 +493,10 @@ peripheral {
description = "Defines the quanta value carried bypause frames sent by the Endpoint";
prefix = "TX_QUANTA";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
align = 16;
load = LOAD_EXT;
};
};
......@@ -598,7 +647,7 @@ peripheral {
prefix = "EN";
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
load = LOAD_EXT;
};
field {
......@@ -610,7 +659,7 @@ peripheral {
align = 16;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
load = LOAD_EXT;
};
};
......@@ -636,30 +685,67 @@ peripheral {
access_bus = READ_WRITE;
};
};
reg {
name = "PCK Injection CTRL";
prefix = "INJ_CTRL";
field {
name = "Config: Interframe GAP";
prefix = "PIC_CONF_IFG";
size = 16;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
ram {
name = "Event counters memory";
description = "RMON event counters:\
0x0 : TX PCS buffer underruns\
0x4 : RX PCS invalid 8b10b codes\
0x8 : RX PCS sync lost events\
0xc : RX PCS buffer overruns\
0x10: RX CRC errors\
0x14: RX valid frames\
0x18: RX runt frames\
0x1c: RX giant frames\
0x20: RX PCS errors\
0x24: RX dropped frames";
size = 32;
width = 32;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
field {
name = "Config: packet pattern sel id";
prefix = "PIC_CONF_SEL";
size = 3;
type = SLV;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Config: valid";
prefix = "PIC_CONF_VALID";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Mode: packet generate mode";
prefix = "PIC_MODE_ID";
size = 3;
type = SLV;
align= 4;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
prefix = "rmon_ram";
};
field {
name = "Mode: valid";
prefix = "PIC_MODE_VALID";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Frame Generation Enabled";
prefix = "PIC_ENA";
type = BIT;
align = 4;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
};
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