Skip to content

W
White Rabbit Switch - Software
Commit 2a3c8ce1 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

little header cleanup, removed all references to UTC time (it's not really UTC)

parent 5ec76ea1
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 217 additions and 1480 deletions
userspace/.gitignore
View file @ 2a3c8ce1
......@@ -3,3 +3,7 @@ wrsw_rtud/wrsw_rtud
spll_dbg_proxy/spll_dbg_proxy
wr_mon/wr_mon
rtu_stat/rtu_stat
wr_phytool/wr_phytool
build.sh
*#
.#*
\ No newline at end of file
userspace/include/hw/ad9516.h deleted 100644 → 0
View file @ 5ec76ea1
/**
* @file ad9516o.h
*
* @brief AD9516-O clock generator definitions
*
* The AD9516-O is controller through an SPI interface. This file
* provides definitions for the different addresses of the module
* to make its configuration easier to read.
*
* Copyright (c) 2009 CERN
* @author Emilio G. Cota <emilio.garcia.cota@cern.ch>
*
* @section license_sec License
* Released under the GPL v2. (and only v2, not any later version)
*/
#ifndef _AD9516O_H_
#define _AD9516O_H_
/*
* AD9516-O Adress Map
*/
#define AD9516_SERIALPORT 0x00
#define AD9516_READBACK 0x04
#define AD9516_PDF_CP 0x10
#define AD9516_RCOUNT_LSB 0x11
#define AD9516_RCOUNT_MSB 0x12
#define AD9516_ACOUNT 0x13
#define AD9516_BCOUNT_LSB 0x14
#define AD9516_BCOUNT_MSB 0x15
#define AD9516_PLL1 0x16
#define AD9516_PLL2 0x17
#define AD9516_PLL3 0x18
#define AD9516_PLL4 0x19
#define AD9516_PLL5 0x1A
#define AD9516_PLL6 0x1B
#define AD9516_PLL7 0x1C
#define AD9516_PLL8 0x1D
#define AD9516_PLL9 0x1E
#define AD9516_PLLREADBACK 0x1F
/* Fine Delay Adjust: OUT6 to OUT9 */
#define AD9516_OUT6DELAY_BP 0xA0
#define AD9516_OUT6DELAY_FS 0xA1
#define AD9516_OUT6DELAY_FR 0xA2
#define AD9516_OUT7DELAY_BP 0xA3
#define AD9516_OUT7DELAY_FS 0xA4
#define AD9516_OUT7DELAY_FR 0xA5
#define AD9516_OUT8DELAY_BP 0xA6
#define AD9516_OUT8DELAY_FS 0xA7
#define AD9516_OUT8DELAY_FR 0xA8
#define AD9516_OUT9DELAY_BP 0xA9
#define AD9516_OUT9DELAY_FS 0xAA
#define AD9516_OUT9DELAY_FR 0xAB
/* LVPECL Outputs */
#define AD9516_LVPECL_OUT0 0xF0
#define AD9516_LVPECL_OUT1 0xF1
#define AD9516_LVPECL_OUT2 0xF2
#define AD9516_LVPECL_OUT3 0xF3
#define AD9516_LVPECL_OUT4 0xF4
#define AD9516_LVPECL_OUT5 0xF5
/* LVDS/CMOS Outputs */
#define AD9516_LVCMOS_OUT6 0x140
#define AD9516_LVCMOS_OUT7 0x141
#define AD9516_LVCMOS_OUT8 0x142
#define AD9516_LVCMOS_OUT9 0x143
/* LVPECL Channel Dividers */
#define AD9516_PECLDIV0_1 0x190
#define AD9516_PECLDIV0_2 0x191
#define AD9516_PECLDIV0_3 0x192
#define AD9516_PECLDIV1_1 0x193
#define AD9516_PECLDIV1_2 0x194
#define AD9516_PECLDIV1_3 0x195
#define AD9516_PECLDIV2_1 0x196
#define AD9516_PECLDIV2_2 0x197
#define AD9516_PECLDIV2_3 0x198
/* LVDS/CMOS Channel Dividers */
#define AD9516_CMOSDIV3_1 0x199
#define AD9516_CMOSDIV3_PHO 0x19A
#define AD9516_CMOSDIV3_2 0x19B
#define AD9516_CMOSDIV3_BYPASS 0x19C
#define AD9516_CMOSDIV3_DCCOFF 0x19D
#define AD9516_CMOSDIV4_1 0x19E
#define AD9516_CMOSDIV4_PHO 0x19F
#define AD9516_CMOSDIV4_2 0x1A0
#define AD9516_CMOSDIV4_BYPASS 0x1A1
#define AD9516_CMOSDIV4_DCCOFF 0x1A2
/* VCO Divider and CLK Input */
#define AD9516_VCO_DIVIDER 0x1E0
#define AD9516_INPUT_CLKS 0x1E1
/* System */
#define AD9516_POWDOWN_SYNC 0x230
/* Update All Registers */
#define AD9516_UPDATE_ALL 0x232
int shw_ad9516_init();
int shw_use_external_reference(int enable);
#endif /* _AD9516O_H_ */
userspace/include/hw/clkb_io.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef __CLKB_H
#define __CLKB_H
#include <inttypes.h>
#define _CLKB_WB_BUS(x) ((x)<<8)
/* Base addresses of the Timing FPGA wishbone peripherals */
#define CLKB_BASE_REVID _CLKB_WB_BUS(0)
#define CLKB_BASE_HPLL _CLKB_WB_BUS(1)
#define CLKB_BASE_GPIO _CLKB_WB_BUS(2)
#define CLKB_BASE_DMPLL _CLKB_WB_BUS(3)
#define CLKB_BASE_CALIBRATOR _CLKB_WB_BUS(4)
#define CLKB_REG_IDCODE 0
int shw_clkb_init();
int shw_clkb_init_cmi();
//void shw_clkb_dac_write(int dac, int val);
#endif
userspace/include/hw/dmpll.h deleted 100644 → 0
View file @ 5ec76ea1
/* FIXME: rewrite this _properly_ */
#ifndef __DMPLL_H
#define __DMPLL_H
#include <hw/dmpll_regs.h>
#define DMPLL_CHANNEL_EXT_REF 2
#define DMPLL_CHANNEL_UP0 0
#define DMPLL_CHANNEL_UP1 1
int shw_dmpll_init();
int shw_dmpll_check_lock();
int shw_dmpll_lock(const char *source);
int shw_dmpll_phase_shift(const char *source, int phase_shift);
int shw_dmpll_shifter_busy(const char *source);
typedef struct {
int deglitch_threshold;
double f_n;
double eta;
int ki;
int kp;
int channel;
double phase_setpoint[4];
} dmpll_params_t;
#endif
userspace/include/hw/dmpll_regs.h deleted 100644 → 0
View file @ 5ec76ea1
This diff is collapsed.
userspace/include/hw/dmtd_calibrator_regs.h deleted 100644 → 0
View file @ 5ec76ea1
/*
Register definitions for slave core: DMTD PHY Calibrator
* File : ../../../software/include/hw/dmtd_calibrator_regs.h
* Author : auto-generated by wbgen2 from wrsw_calibrator_dmtd.wb
* Created : Mon Aug 23 14:38:14 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_calibrator_dmtd.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_CALIBRATOR_DMTD_WB
#define __WBGEN2_REGDEFS_WRSW_CALIBRATOR_DMTD_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Enable in reg: Control Register */
#define DPC_CR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Compare clock select in reg: Control Register */
#define DPC_CR_IN_SEL_MASK WBGEN2_GEN_MASK(8, 4)
#define DPC_CR_IN_SEL_SHIFT 8
#define DPC_CR_IN_SEL_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define DPC_CR_IN_SEL_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for field: DMTD averaging samples in reg: Control Register */
#define DPC_CR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define DPC_CR_N_AVG_SHIFT 16
#define DPC_CR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define DPC_CR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: Status register */
/* definitions for field: Phase shift value in reg: Status register */
#define DPC_SR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define DPC_SR_PS_VAL_SHIFT 0
#define DPC_SR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define DPC_SR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Phase shift value ready in reg: Status register */
#define DPC_SR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* [0x0]: REG Control Register */
#define DPC_REG_CR 0x00000000
/* [0x4]: REG Status register */
#define DPC_REG_SR 0x00000004
#endif
userspace/include/hw/endpoint_mdio.h
View file @ 2a3c8ce1
......@@ -14,7 +14,7 @@
#ifndef __WBGEN2_REGDEFS_PCS_REGS_WB
#define __WBGEN2_REGDEFS_PCS_REGS_WB
#include <inttypes.h>
#include <stdint.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......
userspace/include/hw/endpoint_regs.h
View file @ 2a3c8ce1
......@@ -14,7 +14,7 @@
#ifndef __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#define __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
#include <inttypes.h>
#include <stdint.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......
userspace/include/hw/fpga_regs.h
View file @ 2a3c8ce1
#ifndef __FPGA_IO_H
#define __FPGA_IO_H
#include <sys/types.h>
#include <inttypes.h>
#include "pio.h"
#include <stdint.h>
#define FPGA_BASE_ADDR _fpga_base_virt
/* Base addresses of all FPGA peripherals used in libswitchhw */
/* PPS Generator */
#define FPGA_BASE_PPS_GEN 0x10500
/* Routing Table */
#define FPGA_BASE_RTU 0x60000
#define FPGA_BASE_ADDR _fpga_base_virt
extern volatile uint8_t *_fpga_base_virt;
#define _fpga_writel(reg, val){ *(volatile uint32_t *)(FPGA_BASE_ADDR + (reg)) = (val); }
#define _fpga_readl(reg) (*(volatile uint32_t *)(FPGA_BASE_ADDR + (reg)))
#define FPGA_BASE_PPS_GEN 0x10500
#define FPGA_BASE_RTU 0x60000
#endif
userspace/include/hw/fpgaboot.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef __FPGABOOT_H
#define __FPGABOOT_H
#include <inttypes.h>
#define FPGA_ID_MAIN 0
#define FPGA_ID_CLKB 1
#define DEFAULT_FPGA_IMAGE "/fpga/fpga.img"
#define REVISION_ANY -1
static const char FPGA_IMAGE_MAGIC[4] = { 'w','r','f','i' };
/* Global header of the firmware file */
struct fpga_image_header {
char magic[4];
uint32_t num_fpgas;
};
/* FPGA bitstream entry definition in the firmware file */
struct fpga_image_entry {
char *fpga_name; // name of the FPGA (for example: MAIN, CLKB)
char *fw_name; // name of the firmware (for example: board_test, rtu_test).
uint32_t hash_reg; // MD5 hash of the firmware ID.
uint32_t revision;
uint32_t size;
uint32_t compressed_size;
uint8_t *image_buf;
};
int mblaster_init();
int shw_fpgaboot_init();
int shw_load_fpga_bitstream(int fpga_id, uint8_t *bitstream, uint32_t bitstream_size);
int shw_request_fpga_firmware(int fpga_id, const char *firmware_name);
int shw_boot_fpga(int fpga_id);
int shw_set_fpga_firmware_path(const char *path);
void shw_fpga_force_firmware_reload();
#endif
userspace/include/hw/gigaspy_regs.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef __GIGASPY_REGS_H
#define __GIGASPY_REGS_H
// GigaSpy wishbone registers
#define GSPY_REG_GSCTL 0x0
#define GSPY_REG_GSTRIGCTL 0x4
#define GSPY_REG_GSSTAT 0x8
#define GSPY_REG_GSNSAMPLES 0xc
#define GSPY_REG_GSTRIGADDR 0x10
#define GSPY_REG_GSTESTCTL 0x14
#define GSPY_REG_GSTESTCNT 0x18
#define GSPY_REG_GSCLKFREQ 0x1c
#define GSPY_GSCTL_CH0_ENABLE(x) ((x)?(1<<0):(0))
#define GSPY_GSCTL_CH1_ENABLE(x) ((x)?(1<<1):(0))
#define GSPY_GSCTL_SLAVE0_ENABLE(x) ((x)?(1<<2):(0))
#define GSPY_GSCTL_SLAVE1_ENABLE(x) ((x)?(1<<3):(0))
#define GSPY_GSCTL_LOAD_TRIG0(x) ((x)?(1<<4):(0))
#define GSPY_GSCTL_LOAD_TRIG1(x) ((x)?(1<<5):(0))
#define GSPY_GSCTL_RESET_TRIG0(x) ((x)?(1<<6):(0))
#define GSPY_GSCTL_RESET_TRIG1(x) ((x)?(1<<7):(0))
#define GSPY_GSTRIGCTL_TRIG0_VAL(k,v) (((k)?(1<<8):0) | ((v) & 0xff))
#define GSPY_GSTRIGCTL_TRIG1_VAL(k,v) (((k)?(1<<24):0) | (((v) & 0xff)<<16))
#define GSPY_GSTRIGCTL_TRIG0_EN(x) (((x)?(1<<15):0))
#define GSPY_GSTRIGCTL_TRIG1_EN(x) (((x)?(1<<31):0))
#define GSPY_GSNSAMPLES(x) ((x)&0x1fff)
#define GSPY_GSSTAT_TRIG_DONE0(reg) ((reg)&(1<<0)?1:0)
#define GSPY_GSSTAT_TRIG_DONE1(reg) ((reg)&(1<<1)?1:0)
#define GSPY_GSSTAT_TRIG_SLAVE0(reg) ((reg)&(1<<2)?1:0)
#define GSPY_GSSTAT_TRIG_SLAVE1(reg) ((reg)&(1<<3)?1:0)
#define GSPY_GSTRIGADDR_CH0(reg) ((reg)&0x1fff)
#define GSPY_GSTRIGADDR_CH1(reg) (((reg)>>16)&0x1fff)
#define GSPY_GSTESTCTL_ENABLE 0x1
#define GSPY_GSTESTCTL_RST_CNTR 0x2
#define GSPY_GSTESTCTL_CONNECT 0x4
#define GSPY_GSTESTCTL_PHYIO_ENABLE 0x100
#define GSPY_GSTESTCTL_PHYIO_SYNCEN 0x200
#define GSPY_GSTESTCTL_PHYIO_LOOPEN 0x400
#define GSPY_GSTESTCTL_PHYIO_PRBSEN 0x800
#endif
userspace/include/hw/hpll.h deleted 100644 → 0
View file @ 5ec76ea1
// definitions for DMTD helper PLL
#ifndef __HPLL_H
#define __HPLL_H
#include <inttypes.h>
#include <hw/hpll_regs.h>
// Phase detector gating:
#define HPLL_PD_GATE_512 0
#define HPLL_PD_GATE_1K 1
#define HPLL_PD_GATE_2K 2
#define HPLL_PD_GATE_4K 3
#define HPLL_PD_GATE_8K 4
#define HPLL_PD_GATE_16K 5
#define HPLL_PD_GATE_32K 6
#define HPLL_PD_GATE_64K 7
// Frequency detector gating:
#define HPLL_FD_GATE_16K 0
#define HPLL_FD_GATE_32K 1
#define HPLL_FD_GATE_64K 2
#define HPLL_FD_GATE_128K 3
#define HPLL_FD_GATE_256K 4
#define HPLL_FD_GATE_512K 5
#define HPLL_FD_GATE_1M 6
#define HPLL_FD_GATE_2M 7
#define HPLL_REFSEL_UP0_RBCLK 2
#define HPLL_REFSEL_UP1_RBCLK 1
#define HPLL_REFSEL_LOCAL 0
typedef struct {
float ki_freq, kp_freq; // Kp/Ki for the frequency branch
float ki_phase, kp_phase; // Phase gain (target)
int phase_gain_steps; // number of phase gain (start to end) transition steps
uint64_t phase_gain_step_delay; // step delay for phase gain adjustment (in microseconds)
int N, delta; // divider settings: output_freq = input_freq * (N / (N+delta))
int freq_gating; // frequency detector gating
int phase_gating; // phase detector gating
int ref_sel; // reference clock select
int force_freqmode; // force frequency lock mode
double ki_phase_cur, kp_phase_cur; // Phase gain (current)
} hpll_params_t;
int shw_hpll_init();
//void shw_hpll_update();
int shw_hpll_check_lock();
//void shw_hpll_set_reference(int ref_clk);
void shw_hpll_reset();
void shw_hpll_load_regs(const hpll_params_t *params);
int shw_hpll_switch_reference(const char *if_name);
int shw_hpll_get_divider();
//void shw_hpll_start_recording(uint32_t *buffer, int params);
#endif
userspace/include/hw/hpll_regs.h deleted 100644 → 0
View file @ 5ec76ea1
/*
Register definitions for slave core: DMTD Helper PLL
* File : ../../../software/include/hw/hpll_regs.h
* Author : auto-generated by wbgen2 from hpll_wb.wb
* Created : Mon Jun 21 14:16:43 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE hpll_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_HPLL_WB_WB
#define __WBGEN2_REGDEFS_HPLL_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: HPLL Control Register */
/* definitions for field: PLL Enable in reg: HPLL Control Register */
#define HPLL_PCR_ENABLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PLL Force Freq mode in reg: HPLL Control Register */
#define HPLL_PCR_FORCE_F WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DAC serial clock select in reg: HPLL Control Register */
#define HPLL_PCR_DAC_CLKSEL_MASK WBGEN2_GEN_MASK(4, 3)
#define HPLL_PCR_DAC_CLKSEL_SHIFT 4
#define HPLL_PCR_DAC_CLKSEL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define HPLL_PCR_DAC_CLKSEL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Phase detector gating period in reg: HPLL Control Register */
#define HPLL_PCR_PD_GATE_MASK WBGEN2_GEN_MASK(8, 3)
#define HPLL_PCR_PD_GATE_SHIFT 8
#define HPLL_PCR_PD_GATE_W(value) WBGEN2_GEN_WRITE(value, 8, 3)
#define HPLL_PCR_PD_GATE_R(reg) WBGEN2_GEN_READ(reg, 8, 3)
/* definitions for field: Reference clock input select in reg: HPLL Control Register */
#define HPLL_PCR_REFSEL_MASK WBGEN2_GEN_MASK(11, 2)
#define HPLL_PCR_REFSEL_SHIFT 11
#define HPLL_PCR_REFSEL_W(value) WBGEN2_GEN_WRITE(value, 11, 2)
#define HPLL_PCR_REFSEL_R(reg) WBGEN2_GEN_READ(reg, 11, 2)
/* definitions for field: PLL Reset in reg: HPLL Control Register */
#define HPLL_PCR_SWRST WBGEN2_GEN_MASK(31, 1)
/* definitions for register: HPLL Divider Register */
/* definitions for field: Reference divider in reg: HPLL Divider Register */
#define HPLL_DIVR_DIV_REF_MASK WBGEN2_GEN_MASK(0, 16)
#define HPLL_DIVR_DIV_REF_SHIFT 0
#define HPLL_DIVR_DIV_REF_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_DIVR_DIV_REF_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Feedback divider in reg: HPLL Divider Register */
#define HPLL_DIVR_DIV_FB_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_DIVR_DIV_FB_SHIFT 16
#define HPLL_DIVR_DIV_FB_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_DIVR_DIV_FB_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: HPLL Frequency Branch Gain Register */
/* definitions for field: Proportional gain (Kp) in reg: HPLL Frequency Branch Gain Register */
#define HPLL_FBGR_F_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define HPLL_FBGR_F_KP_SHIFT 0
#define HPLL_FBGR_F_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_FBGR_F_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Integral gain (Ki) in reg: HPLL Frequency Branch Gain Register */
#define HPLL_FBGR_F_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_FBGR_F_KI_SHIFT 16
#define HPLL_FBGR_F_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_FBGR_F_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: HPLL Phase Branch Gain Register */
/* definitions for field: Proportional gain (Kp) in reg: HPLL Phase Branch Gain Register */
#define HPLL_PBGR_P_KP_MASK WBGEN2_GEN_MASK(0, 16)
#define HPLL_PBGR_P_KP_SHIFT 0
#define HPLL_PBGR_P_KP_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define HPLL_PBGR_P_KP_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Integral gain (Ki) in reg: HPLL Phase Branch Gain Register */
#define HPLL_PBGR_P_KI_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_PBGR_P_KI_SHIFT 16
#define HPLL_PBGR_P_KI_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_PBGR_P_KI_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: HPLL Lock Detect Control Register */
/* definitions for field: Phase Lock detect threshold in reg: HPLL Lock Detect Control Register */
#define HPLL_LDCR_LD_THR_MASK WBGEN2_GEN_MASK(0, 8)
#define HPLL_LDCR_LD_THR_SHIFT 0
#define HPLL_LDCR_LD_THR_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define HPLL_LDCR_LD_THR_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Lock detect samples in reg: HPLL Lock Detect Control Register */
#define HPLL_LDCR_LD_SAMP_MASK WBGEN2_GEN_MASK(8, 8)
#define HPLL_LDCR_LD_SAMP_SHIFT 8
#define HPLL_LDCR_LD_SAMP_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define HPLL_LDCR_LD_SAMP_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: HPLL Frequency branch control register */
/* definitions for field: Frequency detector gating period in reg: HPLL Frequency branch control register */
#define HPLL_FBCR_FD_GATE_MASK WBGEN2_GEN_MASK(0, 3)
#define HPLL_FBCR_FD_GATE_SHIFT 0
#define HPLL_FBCR_FD_GATE_W(value) WBGEN2_GEN_WRITE(value, 0, 3)
#define HPLL_FBCR_FD_GATE_R(reg) WBGEN2_GEN_READ(reg, 0, 3)
/* definitions for field: Frequency error setpoint in reg: HPLL Frequency branch control register */
#define HPLL_FBCR_FERR_SET_MASK WBGEN2_GEN_MASK(4, 12)
#define HPLL_FBCR_FERR_SET_SHIFT 4
#define HPLL_FBCR_FERR_SET_W(value) WBGEN2_GEN_WRITE(value, 4, 12)
#define HPLL_FBCR_FERR_SET_R(reg) WBGEN2_GEN_READ(reg, 4, 12)
/* definitions for register: HPLL Status Register */
/* definitions for field: Frequency lock in reg: HPLL Status Register */
#define HPLL_PSR_FREQ_LK WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Phase lock in reg: HPLL Status Register */
#define HPLL_PSR_PHASE_LK WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Loss-of-lock indicator in reg: HPLL Status Register */
#define HPLL_PSR_LOCK_LOST WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
/* definitions for field: Freq/phase error in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_ERR_VAL_MASK WBGEN2_GEN_MASK(0, 12)
#define HPLL_RFIFO_R0_ERR_VAL_SHIFT 0
#define HPLL_RFIFO_R0_ERR_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define HPLL_RFIFO_R0_ERR_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Freq/phase mode in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_FP_MODE WBGEN2_GEN_MASK(15, 1)
/* definitions for field: DAC output in reg: FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_RFIFO_R0_DAC_VAL_MASK WBGEN2_GEN_MASK(16, 16)
#define HPLL_RFIFO_R0_DAC_VAL_SHIFT 16
#define HPLL_RFIFO_R0_DAC_VAL_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define HPLL_RFIFO_R0_DAC_VAL_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FIFO 'HPLL Phase/Output record FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'HPLL Phase/Output record FIFO' control/status register */
#define HPLL_RFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG HPLL Control Register */
#define HPLL_REG_PCR 0x00000000
/* [0x4]: REG HPLL Divider Register */
#define HPLL_REG_DIVR 0x00000004
/* [0x8]: REG HPLL Frequency Branch Gain Register */
#define HPLL_REG_FBGR 0x00000008
/* [0xc]: REG HPLL Phase Branch Gain Register */
#define HPLL_REG_PBGR 0x0000000c
/* [0x10]: REG HPLL Lock Detect Control Register */
#define HPLL_REG_LDCR 0x00000010
/* [0x14]: REG HPLL Frequency branch control register */
#define HPLL_REG_FBCR 0x00000014
/* [0x18]: REG HPLL Status Register */
#define HPLL_REG_PSR 0x00000018
/* [0x1c]: REG FIFO 'HPLL Phase/Output record FIFO' data output register 0 */
#define HPLL_REG_RFIFO_R0 0x0000001c
/* [0x20]: REG FIFO 'HPLL Phase/Output record FIFO' control/status register */
#define HPLL_REG_RFIFO_CSR 0x00000020
#endif
userspace/include/hw/minic_regs.h deleted 100644 → 0
View file @ 5ec76ea1
/*
Register definitions for slave core: Mini NIC for WhiteRabbit
* File : ../../../software/include/hw/minic_regs.h
* Author : auto-generated by wbgen2 from mini_nic.wb
* Created : Fri Aug 13 02:17:20 2010
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_MINI_NIC_WB
#define __WBGEN2_REGDEFS_MINI_NIC_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: miNIC Control Register */
/* definitions for field: TX DMA start in reg: miNIC Control Register */
#define MINIC_MCR_TX_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX DMA idle in reg: miNIC Control Register */
#define MINIC_MCR_TX_IDLE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX DMA error in reg: miNIC Control Register */
#define MINIC_MCR_TX_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX DMA ready in reg: miNIC Control Register */
#define MINIC_MCR_RX_READY WBGEN2_GEN_MASK(8, 1)
/* definitions for field: RX DMA buffer full in reg: miNIC Control Register */
#define MINIC_MCR_RX_FULL WBGEN2_GEN_MASK(9, 1)
/* definitions for field: RX DMA enable in reg: miNIC Control Register */
#define MINIC_MCR_RX_EN WBGEN2_GEN_MASK(10, 1)
/* definitions for register: TX DMA Address */
/* definitions for register: RX DMA Address */
/* definitions for register: RX buffer size register */
/* definitions for register: Debug register */
/* definitions for field: interrupt counter in reg: Debug register */
#define MINIC_DBGR_IRQ_CNT_MASK WBGEN2_GEN_MASK(0, 24)
#define MINIC_DBGR_IRQ_CNT_SHIFT 0
#define MINIC_DBGR_IRQ_CNT_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define MINIC_DBGR_IRQ_CNT_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: status of wb_irq_o line in reg: Debug register */
#define MINIC_DBGR_WB_IRQ_VAL WBGEN2_GEN_MASK(24, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt disable register */
#define MINIC_EIC_IDR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt disable register */
#define MINIC_EIC_IDR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt enable register */
#define MINIC_EIC_IER_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt enable register */
#define MINIC_EIC_IER_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: TX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt mask register */
#define MINIC_EIC_IMR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt mask register */
#define MINIC_EIC_IMR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: TX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_TX WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX DMA interrupt in reg: Interrupt status register */
#define MINIC_EIC_ISR_RX WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX timestamp available in reg: Interrupt status register */
#define MINIC_EIC_ISR_TXTS WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 0 */
/* definitions for field: Timestamp value in reg: FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_TSFIFO_R0_TSVAL_MASK WBGEN2_GEN_MASK(0, 32)
#define MINIC_TSFIFO_R0_TSVAL_SHIFT 0
#define MINIC_TSFIFO_R0_TSVAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define MINIC_TSFIFO_R0_TSVAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'TX timestamp FIFO' data output register 1 */
/* definitions for field: Port ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define MINIC_TSFIFO_R1_PID_SHIFT 0
#define MINIC_TSFIFO_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MINIC_TSFIFO_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_TSFIFO_R1_FID_MASK WBGEN2_GEN_MASK(5, 16)
#define MINIC_TSFIFO_R1_FID_SHIFT 5
#define MINIC_TSFIFO_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 5, 16)
#define MINIC_TSFIFO_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 5, 16)
/* definitions for register: FIFO 'TX timestamp FIFO' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_TSFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* [0x0]: REG miNIC Control Register */
#define MINIC_REG_MCR 0x00000000
/* [0x4]: REG TX DMA Address */
#define MINIC_REG_TX_ADDR 0x00000004
/* [0x8]: REG RX DMA Address */
#define MINIC_REG_RX_ADDR 0x00000008
/* [0xc]: REG RX buffer size register */
#define MINIC_REG_RX_AVAIL 0x0000000c
/* [0x10]: REG Debug register */
#define MINIC_REG_DBGR 0x00000010
/* [0x20]: REG Interrupt disable register */
#define MINIC_REG_EIC_IDR 0x00000020
/* [0x24]: REG Interrupt enable register */
#define MINIC_REG_EIC_IER 0x00000024
/* [0x28]: REG Interrupt mask register */
#define MINIC_REG_EIC_IMR 0x00000028
/* [0x2c]: REG Interrupt status register */
#define MINIC_REG_EIC_ISR 0x0000002c
/* [0x30]: REG FIFO 'TX timestamp FIFO' data output register 0 */
#define MINIC_REG_TSFIFO_R0 0x00000030
/* [0x34]: REG FIFO 'TX timestamp FIFO' data output register 1 */
#define MINIC_REG_TSFIFO_R1 0x00000034
/* [0x38]: REG FIFO 'TX timestamp FIFO' control/status register */
#define MINIC_REG_TSFIFO_CSR 0x00000038
#endif
userspace/include/hw/phy_calibration.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef __PHY_CALIBRATION_H
#define __PHY_CALIBRATION_H
#define PHY_CALIBRATE_TX 0
#define PHY_CALIBRATE_RX 1
int shw_cal_init();
int shw_cal_enable_feedback(const char *if_name, int enable, int lane);
int shw_cal_measure(uint32_t *phase); // picoseconds!
int shw_cal_enable_pattern(const char *if_name, int enable);
int shw_poll_dmtd(const char *if_name, uint32_t *phase_ps);
void xpoint_cal_feedback(int on, int port, int txrx);
int xpoint_configure();
#endif
userspace/include/hw/pps_gen.h deleted 100644 → 0
View file @ 5ec76ea1
/* PPS Generator driver */
#ifndef __PPS_GEN_H
#define __PPS_GEN_H
#include <stdio.h>
#include <inttypes.h>
int shw_pps_gen_init();
int shw_pps_gen_adjust_nsec(int32_t how_much);
int shw_pps_gen_adjust_utc(int64_t how_much);
int shw_pps_gen_busy();
int shw_pps_gen_enable_output(int enable);
#endif
userspace/include/hw/pps_gen_regs.h
View file @ 2a3c8ce1
......@@ -14,7 +14,7 @@
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <inttypes.h>
#include <stdint.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -53,15 +53,15 @@
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: SEC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: SEC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: SEC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: SEC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
......@@ -71,22 +71,22 @@
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
/* definitions for field: Timecode output(SEC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG UTC Counter register (least-significant part) */
#define PPSG_REG_CNTR_UTCLO 0x00000008
/* [0xc]: REG UTC Counter register (most-significant part) */
#define PPSG_REG_CNTR_UTCHI 0x0000000c
/* [0x8]: REG SEC Counter register (least-significant part) */
#define PPSG_REG_CNTR_SECLO 0x00000008
/* [0xc]: REG SEC Counter register (most-significant part) */
#define PPSG_REG_CNTR_SECHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG UTC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
/* [0x14]: REG SEC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_SECLO 0x00000014
/* [0x18]: REG SEC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_SECHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
#endif
userspace/include/hw/rtu_regs.h
View file @ 2a3c8ce1
......@@ -14,7 +14,7 @@
#ifndef __WBGEN2_REGDEFS_RTU_WISHBONE_SLAVE_WB
#define __WBGEN2_REGDEFS_RTU_WISHBONE_SLAVE_WB
#include <inttypes.h>
#include <stdint.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......
userspace/include/hw/switch_hw.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef __SWITCH_HW_H
#define __SWITCH_HW_H
#include "pio.h"
#include "fpga_regs.h"
#include "trace.h"
#include "ad9516.h"
#include "fpgaboot.h"
#include "hpll.h"
#include "watchdog.h"
#include "pps_gen.h"
int shw_init();
#endif
userspace/include/hw/watchdog.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef __WATCHDOG_H
#define __WATCHDOG_H
#include <stdio.h>
#include <hw/switch_hw.h>
#include <hw/pio.h>
#define MBL_LED_LINK 0
#define MBL_LED_ACT 1
#define MBL_LED_OFF 0
#define MBL_LED_ON 1
#define MBL_LED_BLINK_SLOW 2
#define MBL_LED_BLINK_FAST 3
#define MBL_FEEDBACK_TX 1
#define MBL_FEEDBACK_RX 2
#define MBL_FEEDBACK_OFF 3
void shw_mbl_set_leds(int port, int led, int mode);
void shw_mbl_cal_feedback(int port, int cmd);
int shw_watchdog_init();
#endif
userspace/include/hw/pio.h → userspace/include/pio.h
View file @ 2a3c8ce1
#ifndef __CPU_IO_H
#define __CPU_IO_H
#include <sys/types.h>
#include <inttypes.h>
#include <stdint.h>
#include <at91/at91sam9g45.h>
#include <at91/at91_pio.h>
#include <at91/at91_pmc.h>
#include <hw/trace.h>
#define NUM_PIO_BANKS 6
......@@ -40,10 +35,10 @@ typedef struct pio_pin
int dir;
} pio_pin_t;
#define REG_BASE 0
#define REG_CODR 1
#define REG_SODR 2
#define REG_PDSR 3
#define IDX_REG_BASE 0
#define IDX_REG_CODR 1
#define IDX_REG_SODR 2
#define IDX_REG_PDSR 3
#define FPGA_PIO_REG_CODR 0x0
#define FPGA_PIO_REG_SODR 0x4
......@@ -68,38 +63,41 @@ static inline void shw_pio_set(const pio_pin_t *pin, int state)
{
if(state)
_writel(_pio_base[REG_SODR][pin->port], (1<<pin->pin));
_writel(_pio_base[IDX_REG_SODR][pin->port], (1<<pin->pin));
else
_writel(_pio_base[REG_CODR][pin->port], (1<<pin->pin));
_writel(_pio_base[IDX_REG_CODR][pin->port], (1<<pin->pin));
}
static inline void shw_pio_set1(const pio_pin_t *pin)
{
//TRACE(TRACE_INFO,"pio_set1 %x\n", _pio_base[REG_SODR][pin->port]);
_writel(_pio_base[REG_SODR][pin->port], (1<<pin->pin));
_writel(_pio_base[IDX_REG_SODR][pin->port], (1<<pin->pin));
}
static inline void shw_pio_set0(const pio_pin_t *pin)
{
_writel(_pio_base[REG_CODR][pin->port], (1<<pin->pin));
_writel(_pio_base[IDX_REG_CODR][pin->port], (1<<pin->pin));
}
static inline int shw_pio_get(const pio_pin_t *pin)
{
return (_readl(_pio_base[REG_PDSR][pin->port]) & (1<<pin->pin)) ? 1 : 0;
return (_readl(_pio_base[IDX_REG_PDSR][pin->port]) & (1<<pin->pin)) ? 1 : 0;
}
static inline int shw_pio_setdir(const pio_pin_t *pin, int dir)
{
if(dir == PIO_OUT)
_writel((_pio_base[REG_BASE][pin->port] + PIO_OER), (1<<pin->pin));
_writel((_pio_base[IDX_REG_BASE][pin->port] + PIO_OER), (1<<pin->pin));
else
_writel((_pio_base[REG_BASE][pin->port] + PIO_ODR), (1<<pin->pin));
_writel((_pio_base[IDX_REG_BASE][pin->port] + PIO_ODR), (1<<pin->pin));
return 0;
}
#include "pio_pins.h"
#endif
int shw_pio_mmap_init();
void shw_pio_toggle_pin(pio_pin_t* pin, uint32_t udelay);
void shw_pio_configure_all();
void shw_pio_configure(const pio_pin_t *pin);
#endif //PIO_H
\ No newline at end of file
userspace/include/pps_gen.h 0 → 100644
View file @ 2a3c8ce1
/* PPS Generator - a.k.a. WR Real-time clock driver */
#ifndef __PPS_GEN_H
#define __PPS_GEN_H
#include <stdio.h>
#include <inttypes.h>
#define PPSG_ADJUST_SEC 0x1
#define PPSG_ADJUST_NSEC 0x2
/* Initializes the PPS Generator. 0 on success, negative on failure. */
int shw_pps_gen_init();
/* Adjusts the <counter> (PPSG_ADJUST_SEC/NSEC) by (how_much) seconds/nanoseconds */
int shw_pps_gen_adjust(int counter, int64_t how_much);
/* Returns 1 when the PPS is busy adjusting its time counters, 0 if PPS gen idle */
int shw_pps_gen_busy();
/* Enables/disables PPS Generator PPS output */
int shw_pps_gen_enable_output(int enable);
/* Reads the current time and stores at <seconds,nanoseconds>. */
void shw_pps_gen_read_time(uint64_t *seconds, uint32_t *nanoseconds);
#endif
userspace/include/switch_hw.h 0 → 100644
View file @ 2a3c8ce1
#ifndef __SWITCH_HW_H
#define __SWITCH_HW_H
#include "pio.h"
#include "trace.h"
#include "pps_gen.h"
/* Some global, very important constants */
/* System reference clock period, in picoseconds. 62.5 MHz clock in V3 gives 16000 ps period */
#define REF_CLOCK_PERIOD_PS 16000
/* System reference clock rate (in Hertz). Update together with REF_CLOCK_PERIOD_PS */
#define REF_CLOCK_RATE_HZ 62500000
int shw_init();
#endif
userspace/libswitchhw/build.sh deleted 100755 → 0
View file @ 5ec76ea1
#!/bin/sh
. ../../settings
make CROSS_COMPILE=$CC_CPU $1
userspace/libswitchhw/fpga_io.c
View file @ 2a3c8ce1
......@@ -9,13 +9,13 @@
#include <fcntl.h>
#include <poll.h>
#include <hw/switch_hw.h>
#include <switch_hw.h>
#include <hw/fpga_regs.h>
#define SMC_CS0_BASE 0x10000000
#define SMC_CS0_SIZE 0x200000
#define SPI_CLKDIV_VAL 20 // clock divider for CMI SPI bus clock
/* Virtual base address of the Main FPGA address space. */
volatile uint8_t *_fpga_base_virt;
......
userspace/libswitchhw/i2c_bitbang.c
View file @ 2a3c8ce1
......@@ -4,16 +4,11 @@
#include <stdlib.h>
#include <string.h>
#include <hw/util.h> //for shw_udelay();
#include <util.h>
#include "i2c_bitbang.h"
#include <sys/time.h>
#include <unistd.h>
int i2c_bitbang_init_bus(struct i2c_bus *bus)
{
struct i2c_bitbang *priv;
......
userspace/libswitchhw/i2c_bitbang.h
View file @ 2a3c8ce1
......@@ -6,8 +6,7 @@
#ifndef I2C_CPU_BB_H
#define I2C_CPU_BB_H
#include <hw/pio.h>
#include <pio.h>
#include "i2c.h"
struct i2c_bitbang {
......@@ -17,14 +16,8 @@ struct i2c_bitbang {
int timeout;
};
int i2c_bitbang_init_bus(struct i2c_bus *bus);
int32_t i2c_bitbang_transfer(struct i2c_bus* bus, uint32_t address, uint32_t to_write, uint32_t to_read, uint8_t* data);
int32_t i2c_bitbang_scan(struct i2c_bus* bus, uint32_t address);
void mi2c_pin_out(pio_pin_t* pin, int state);
#endif //I2C_CPU_BB_H
userspace/libswitchhw/i2c_fpga_reg.c
View file @ 2a3c8ce1
......@@ -4,11 +4,10 @@
#include <stdlib.h>
#include <string.h>
#include <hw/util.h> //for shw_udelay();
#include <util.h> //for shw_udelay();
#include "i2c_fpga_reg.h"
int i2c_fpga_reg_init_bus(struct i2c_bus *bus)
{
i2c_fpga_reg_t *priv;
......
userspace/libswitchhw/i2c_fpga_reg.h
View file @ 2a3c8ce1
......@@ -6,11 +6,7 @@
#ifndef I2C_FPGA_REG_H
#define I2C_FPGA_REG_H
#include <hw/pio.h>
#include <hw/fpga_regs.h>
#include "i2c.h"
#define FPGA_I2C_REG_PREL 0x00
......@@ -39,13 +35,8 @@ typedef struct
uint32_t prescaler;
} i2c_fpga_reg_t;
int i2c_fpga_reg_init_bus(struct i2c_bus *bus);
int32_t i2c_fpga_reg_transfer(struct i2c_bus* bus, uint32_t address, uint32_t to_write, uint32_t to_read, uint8_t* data);
int32_t i2c_fpga_reg_scan(struct i2c_bus* bus, uint32_t i2c_address);
#endif //I2C_FPGA_REG_H
userspace/libswitchhw/i2c_sfp.c
View file @ 2a3c8ce1
......@@ -13,11 +13,11 @@
#include <lauxlib.h>
#include <lualib.h>
#include "i2c.h"
#include "pio.h"
#include <pio.h>
#include <trace.h>
#include "i2c.h"
#include "i2c_sfp.h"
#include "i2c_bitbang.h"
#include "i2c_fpga_reg.h"
......
userspace/libswitchhw/i2c_sfp.h
View file @ 2a3c8ce1
......@@ -3,7 +3,7 @@
#include "i2c.h"
#include <hw/sfp_lib.h>
#include <sfp_lib.h>
//address from AT24C01 datasheet (1k, all address lines shorted to the ground)
#define I2C_SFP_ADDRESS 0x50
......
userspace/libswitchhw/i2cscan.c deleted 100644 → 0
View file @ 5ec76ea1
/*
* i2cscan.c
* CERN 2012 B.Bielawski
*/
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "i2c.h"
#include "pio.h"
#include "i2c_bitbang.h"
#include "i2c_fpga_reg.h"
#include "i2c_sfp.h"
#include <hw/sfp_lib.h>
#include "libshw_i2c.h"
#define ARRAY_SIZE(a) \
(sizeof(a) / sizeof(*(a)))
int main()
{
int ret;
uint32_t i;
unsigned char dev_map[16];
int detect;
struct shw_sfp_header head;
printf("Initing HW...\n");
memset(&head, 0, sizeof(head));
shw_init();
if (shw_sfp_buses_init() < 0) {
printf("Failed to initialize buses\n");
return 1;
}
shw_sfp_read_db("sfpdb.lua");
shw_sfp_bus_scan(WR_FPGA_BUS0, dev_map);
shw_sfp_bus_scan(WR_FPGA_BUS1, dev_map);
shw_sfp_bus_scan(WR_MUX_BUS, dev_map);
shw_sfp_bus_scan(WR_SFP0_BUS, dev_map);
shw_sfp_bus_scan(WR_SFP1_BUS, dev_map);
#if 0
shw_sfp_gpio_init();
pio_pin_t *sda = ((struct i2c_bitbang *)i2c_buses[WR_MUX_BUS].type_specific)->sda;
while (1) {
mi2c_pin_out(sda, 1);
mi2c_pin_out(sda, 0);
for (i = 0; i < 18; i++) {
shw_sfp_set_led_link(i, 1);
}
usleep(100);
for (i = 0; i < 18; i++) {
shw_sfp_set_led_link(i, 0);
}
usleep(100);
}
#endif
struct shw_sfp_caldata *d;
printf("\nScanning SFPs:\n");
for (i = 0; i < 18; i++) {
memset(&head, 0, sizeof(struct shw_sfp_header));
ret = shw_sfp_read(i, 0x50, 0x0, sizeof(head), (uint8_t *)&head);
if (ret == I2C_DEV_NOT_FOUND || ret < 0) {
printf("SFP %d: NOT PRESENT\n", i);
continue;
}
printf("SFP %d: PRESENT\n", i);
shw_sfp_header_dump(&head);
shw_sfp_print_header(&head);
d = NULL;
d = shw_sfp_get_cal_data(i);
if (d)
printf("Callibration (%s): alpha = %lf, dtx = %d, drx = %d\n",
(d->flags & SFP_FLAG_CLASS_DATA) ? "CLASS" : "DEVICE",
d->alpha, d->delta_tx, d->delta_rx);
printf("\n");
}
#if 0
for (i = 0; i < 18; i++) {
memset(&head, 0, sizeof(struct shw_sfp_header));
printf("SFP_SCAN: %08x\n", shw_sfp_scan());
ret = shw_sfp_read(i, 0x50, 0x0, sizeof(head), (uint8_t *)&head);
if (ret == I2C_DEV_NOT_FOUND) {
printf("SFP %d: NOT PRESENT\n", i);
continue;
}
printf("SFP %d: PRESENT\n", i);
printf("\n");
shw_sfp_header_dump(&head);
shw_sfp_print_header(&head);
}
#endif
return 0;
}
userspace/libswitchhw/init.c
View file @ 2a3c8ce1
......@@ -3,7 +3,7 @@
#include <stdio.h>
#include <stdlib.h>
#include <hw/switch_hw.h>
#include <switch_hw.h>
#include "i2c_sfp.h"
#define assert_init(proc) { int ret; if((ret = proc) < 0) return ret; }
......
userspace/libswitchhw/pio.c
View file @ 2a3c8ce1
......@@ -6,10 +6,12 @@
#include <inttypes.h>
#include <fcntl.h>
#include <hw/pio.h> //why does it not include right header?
#include <at91/at91sam9g45.h>
#include <at91/at91_pmc.h>
#include "pio.h"
#include <at91/at91_pio.h>
#include <pio.h>
#include <trace.h>
volatile uint8_t *_pio_base[4][NUM_PIO_BANKS+1];
volatile uint8_t *_sys_base;
......@@ -62,17 +64,17 @@ int shw_pio_mmap_init()
// printf("PIOA offset %08X\n", AT91C_BASE_PIOA_RAW - AT91C_BASE_SYS_RAW);
// printf("Sys base: %08X\n", _sys_base);
_pio_base[REG_BASE][PIOA] = _sys_base + AT91C_BASE_PIOA_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[REG_BASE][PIOB] = _sys_base + AT91C_BASE_PIOB_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[REG_BASE][PIOC] = _sys_base + AT91C_BASE_PIOC_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[REG_BASE][PIOD] = _sys_base + AT91C_BASE_PIOD_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[REG_BASE][PIOE] = _sys_base + AT91C_BASE_PIOE_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[IDX_REG_BASE][PIOA] = _sys_base + AT91C_BASE_PIOA_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[IDX_REG_BASE][PIOB] = _sys_base + AT91C_BASE_PIOB_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[IDX_REG_BASE][PIOC] = _sys_base + AT91C_BASE_PIOC_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[IDX_REG_BASE][PIOD] = _sys_base + AT91C_BASE_PIOD_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
_pio_base[IDX_REG_BASE][PIOE] = _sys_base + AT91C_BASE_PIOE_RAW - AT91C_BASE_SYS_RAW; //offset counting from AT91C_BASE_SYS
for (i=1; i<=5; i++)
{
_pio_base [REG_CODR][i] = _pio_base[REG_BASE][i] + PIO_CODR;
_pio_base [REG_SODR][i] = _pio_base[REG_BASE][i] + PIO_SODR;
_pio_base [REG_PDSR][i] = _pio_base[REG_BASE][i] + PIO_PDSR;
_pio_base [IDX_REG_CODR][i] = _pio_base[IDX_REG_BASE][i] + PIO_CODR;
_pio_base [IDX_REG_SODR][i] = _pio_base[IDX_REG_BASE][i] + PIO_SODR;
_pio_base [IDX_REG_PDSR][i] = _pio_base[IDX_REG_BASE][i] + PIO_PDSR;
}
return 0;
......@@ -106,7 +108,7 @@ void shw_pio_configure(const pio_pin_t *pin)
{
uint32_t mask = (1<<pin->pin);
uint32_t ddr;
volatile uint8_t *base = (_pio_base[REG_BASE][pin->port]);
volatile uint8_t *base = (_pio_base[IDX_REG_BASE][pin->port]);
switch (pin->port)
{
......
userspace/libswitchhw/pio.h deleted 100644 → 0
View file @ 5ec76ea1
#ifndef PIO_H
#define PIO_H
#include <hw/pio.h>
int shw_pio_mmap_init();
void shw_pio_toggle_pin(pio_pin_t* pin, uint32_t udelay);
void shw_pio_configure_all();
void shw_pio_configure(const pio_pin_t *pin);
#endif //PIO_H
\ No newline at end of file
userspace/libswitchhw/pio_pins.c
View file @ 2a3c8ce1
/* GPIO pin definitions */
#include <hw/pio.h>
#include <pio.h>
#define LED_OFF 0
#define LED_RED 1
......@@ -8,7 +8,6 @@
// definitions of commonly used pins
// reset signal for main FPGA
//const pio_pin_t PIN_main_fpga_nrst[] = {{ PIOA, 5, PIO_MODE_GPIO, PIO_OUT }, {0}};
......@@ -24,15 +23,3 @@ const pio_pin_t * _all_cpu_gpio_pins[] =
/*const pio_pin_t * _all_fpga_gpio_pins[] =
{
PIN_up_ctrl_sda,
PIN_up_ctrl_scl,
PIN_down_ctrl_sda,
PIN_down_ctrl_scl,
0
};
*/
userspace/libswitchhw/pps_gen.c
View file @ 2a3c8ce1
......@@ -5,10 +5,11 @@
#include <inttypes.h>
#include <sys/time.h>
#include <hw/clkb_io.h>
#include <hw/fpga_regs.h>
#include <hw/pps_gen_regs.h>
#include <hw/switch_hw.h>
#include <hw/trace.h>
#include <switch_hw.h>
#include <trace.h>
/* Default width (in 8ns units) of the pulses on the PPS output */
#define PPS_WIDTH 100000
......@@ -22,8 +23,8 @@ int shw_pps_gen_init()
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, cr);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCLO, 1285700840);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECLO, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, cr | PPSG_CR_CNT_SET);
......@@ -32,29 +33,26 @@ int shw_pps_gen_init()
}
/* Adjusts the nanosecond (refclk cycle) counter by atomically adding (how_much) cycles. */
int shw_pps_gen_adjust_nsec(int32_t how_much)
int shw_pps_gen_adjust(int counter, int64_t how_much)
{
uint32_t cr;
TRACE(TRACE_INFO, "AdjustPPS: %d cycles", how_much);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCLO, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, how_much);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH) | PPSG_CR_CNT_ADJ);
}
/* Adjusts the seconds (UTC/TAI) counter by adding (how_much) in an atomic way */
int shw_pps_gen_adjust_utc(int64_t how_much)
{
uint32_t cr;
TRACE(TRACE_INFO, "AdjustUTC: %lld seconds", how_much);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCLO, (uint32_t) (how_much & 0xffffffffLL));
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_UTCHI, (uint32_t) (how_much >> 32));
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, PPSG_CR_CNT_EN | PPSG_CR_PWIDTH_W(PPS_WIDTH) | PPSG_CR_CNT_ADJ);
TRACE(TRACE_INFO, "Adjust: counter = %s [%c%lld]",
counter == PPSG_ADJUST_SEC ? "seconds" : "nanoseconds", how_much<0?'-':'+', abs(how_much));
if(counter == PPSG_ADJUST_NSEC)
{
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECLO, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECHI, 0);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, how_much);
} else {
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECLO, (uint32_t ) (how_much & 0xffffffffLL));
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_SECHI, (uint32_t ) (how_much >> 32) & 0xff);
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_ADJ_NSEC, 0);
}
_fpga_writel(FPGA_BASE_PPS_GEN + PPSG_REG_CR, _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CR) | PPSG_CR_CNT_ADJ);
return 0;
}
/* Returns 1 when the adjustment operation is not yet finished */
......@@ -75,3 +73,18 @@ int shw_pps_gen_enable_output(int enable)
return 0;
}
void shw_pps_gen_read_time(uint64_t *seconds, uint32_t *nanoseconds)
{
uint32_t ns_cnt;
uint64_t sec1, sec2;
do {
sec1 = (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECLO) | (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECHI) << 32;
ns_cnt = _fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_NSEC);
sec2 = (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECLO) | (uint64_t)_fpga_readl(FPGA_BASE_PPS_GEN + PPSG_REG_CNTR_SECHI) << 32;
} while(sec2 != sec1);
if(seconds) *seconds = sec2;
if(nanoseconds) *nanoseconds = ns_cnt;
}
\ No newline at end of file
userspace/libswitchhw/sfpdb.lua deleted 100644 → 0
View file @ 5ec76ea1
-- The VENDOR_SERIAL field can be set to an empty string to provide class-level
-- information as opposed to device-level information.
sfpdb = {
--{ PART_NUM, VENDOR_SERIAL, ALPHA, DELTA_TX, DELTA_RX }
{
part_num = "MGBT1",
part_serial = "FSZ15311600",
alpha = 5.055223,
delta_tx = 6,
delta_rx = 7
}
}
userspace/libswitchhw/trace.c
View file @ 2a3c8ce1
......@@ -3,7 +3,7 @@
#include <stdarg.h>
#include <string.h>
#include <hw/trace.h>
#include <trace.h>
static FILE *trace_file = NULL;
static int trace_to_stderr = 0;
......
userspace/libswitchhw/util.c
View file @ 2a3c8ce1
......@@ -2,8 +2,8 @@
#include <stdlib.h>
#include <sys/time.h>
#include <hw/trace.h>
#include <hw/util.h>
#include <trace.h>
#include <util.h>
void shw_udelay(uint32_t microseconds)
{
......
userspace/wrsw_hal/Makefile
View file @ 2a3c8ce1
......@@ -24,7 +24,7 @@ $(BINARY): $(OBJS)
$(CC) -o $@ $^ $(LDFLAGS)
install: all
install -d $(WR_INSTALL_ROOT)/bin
install -d $(WR_INSTALL_ROOT)/bin
install $(BINARY) $(WR_INSTALL_ROOT)/bin
install hal_exports.h wrsw_hal.h $(WR_INSTALL_ROOT)/include
......
userspace/wrsw_hal/gps_resync/gps_resync.c
View file @ 2a3c8ce1
......@@ -8,7 +8,7 @@
#include "serial.h"
#include "nmea.h"
#include <hw/switch_hw.h>
#include <switch_hw.h>
void read_nmea_msg(char *msgbuf, int len)
{
......@@ -38,22 +38,22 @@ static int nmea_read_tai(const char *dev_name, int64_t *t_out)
return -1;
TRACE(TRACE_INFO, "NMEA time: %d/%d/%d %02d:%02d:%02d.%02d\n", gprmc.utc.year + 1900,gprmc.utc.mon+1,gprmc.utc.day,gprmc.utc.hour, gprmc.utc.min, gprmc.utc.sec,gprmc.utc.hsec);
TRACE(TRACE_INFO, "NMEA time: %d/%d/%d %02d:%02d:%02d.%02d\n", gprmc.time.year + 1900,gprmc.time.mon+1,gprmc.time.day,gprmc.time.hour, gprmc.time.min, gprmc.time.sec,gprmc.time.hsec);
*t_out = nmea_time_to_tai(gprmc.utc);
*t_out = nmea_time_to_tai(gprmc.time);
return 0;
}
void nmea_resync_ppsgen(const char *dev_name)
{
uint32_t utc, nsec;
int64_t tai;
uint32_t nsec;
uint64_t cur_tai, new_tai;
nmea_read_tai("/dev/ttyS2", &tai);
shw_pps_gen_read_time( &utc, &nsec);
nmea_read_tai("/dev/ttyS2", (int64_t *)&new_tai);
shw_pps_gen_read_time( &cur_tai, &nsec);
shw_pps_gen_adjust_utc(tai - utc);
shw_pps_gen_adjust(PPSG_ADJUST_SEC, (int64_t) new_tai - (int64_t) cur_tai);
while(!shw_pps_gen_busy()) usleep(100000);
}
......
userspace/wrsw_hal/gps_resync/nmea.c
View file @ 2a3c8ce1
......@@ -299,7 +299,7 @@ int nmea_parse_gprmc(const char *buff, int buff_sz, nmea_gprmc_t *pack)
&(time_buff[0]),
&(pack->status), &(pack->lat), &(pack->ns), &(pack->lon), &(pack->ew),
&(pack->speed), &(pack->direction),
&(pack->utc.day), &(pack->utc.mon), &(pack->utc.year),
&(pack->time.day), &(pack->time.mon), &(pack->time.year),
&(pack->declination), &(pack->declin_ew), &(pack->mode));
if(nsen != 13 && nsen != 14)
......@@ -307,14 +307,14 @@ int nmea_parse_gprmc(const char *buff, int buff_sz, nmea_gprmc_t *pack)
return 0;
}
if(0 != _nmea_parse_time(&time_buff[0], (int)strlen(&time_buff[0]), &(pack->utc)))
if(0 != _nmea_parse_time(&time_buff[0], (int)strlen(&time_buff[0]), &(pack->time)))
{
return 0;
}
if(pack->utc.year < 90)
pack->utc.year += 100;
pack->utc.mon -= 1;
if(pack->time.year < 90)
pack->time.year += 100;
pack->time.mon -= 1;
return 1;
}
......
userspace/wrsw_hal/gps_resync/nmea.h
View file @ 2a3c8ce1
......@@ -31,7 +31,8 @@ typedef struct
*/
typedef struct
{
nmea_time_t utc; /**< UTC of position */
nmea_time_t time; /**< Current time */
char status; /**< Status (A = active or V = void) */
double lat; /**< Latitude in NDEG - [degree][min].[sec/60] */
char ns; /**< [N]orth or [S]outh */
......
userspace/wrsw_hal/hal_config.c
View file @ 2a3c8ce1
......@@ -7,7 +7,8 @@
#include <lua.h>
#include <lauxlib.h>
#include <lualib.h>
#include <hw/trace.h>
#include <trace.h>
#define HAL_CONFIG_FILE "/wr/etc/wrsw_hal.conf"
......
userspace/wrsw_hal/hal_exports.c
View file @ 2a3c8ce1
......@@ -3,9 +3,8 @@
#include <stdio.h>
#include <stdlib.h>
#include <hw/trace.h>
#include <hw/pps_gen.h> /* for direct access to DMPLL and PPS generator */
#include <hw/dmpll.h>
#include <trace.h>
#include <pps_gen.h> /* for direct access to DMPLL and PPS generator */
#include "wrsw_hal.h"
#include "rt_ipc.h"
......@@ -87,11 +86,11 @@ int halexp_pps_cmd(int cmd, hexp_pps_params_t *params)
return rts_adjust_phase(0, params->adjust_phase_shift) ? 0 : -1;
case HEXP_PPSG_CMD_ADJUST_NSEC:
shw_pps_gen_adjust_nsec((int64_t)params->adjust_nsec * 1000LL / (int64_t)REF_CLOCK_PERIOD_PS);
shw_pps_gen_adjust(PPSG_ADJUST_NSEC, params->adjust_nsec);
return 0;
case HEXP_PPSG_CMD_ADJUST_UTC:
shw_pps_gen_adjust_utc(params->adjust_utc);
case HEXP_PPSG_CMD_ADJUST_SEC:
shw_pps_gen_adjust(PPSG_ADJUST_SEC, params->adjust_sec);
return 0;
/* Returns non-zero if the PPS/PLL adjustment is in progress.
......
userspace/wrsw_hal/hal_exports.h
View file @ 2a3c8ce1
......@@ -35,7 +35,7 @@
#define HEXP_PPSG_CMD_GET 0
#define HEXP_PPSG_CMD_ADJUST_PHASE 1
#define HEXP_PPSG_CMD_ADJUST_UTC 2
#define HEXP_PPSG_CMD_ADJUST_SEC 2
#define HEXP_PPSG_CMD_ADJUST_NSEC 3
#define HEXP_PPSG_CMD_POLL 4
#define HEXP_PPSG_CMD_SET_VALID 5
......@@ -43,9 +43,6 @@
#define HEXP_ON 1
#define HEXP_OFF 0
#define HEXP_HPLL 0
#define HEXP_DMPLL 1
#define HEXP_FREQ 0
#define HEXP_PHASE 1
......@@ -72,10 +69,10 @@ typedef struct {
uint32_t current_phase_shift;
int32_t adjust_phase_shift;
int64_t adjust_utc;
int64_t adjust_sec;
int32_t adjust_nsec;
uint64_t current_utc;
uint64_t current_sec;
uint32_t current_nsec;
} hexp_pps_params_t;
......
userspace/wrsw_hal/hal_main.c
View file @ 2a3c8ce1
......@@ -10,20 +10,16 @@
#include <sys/types.h>
#include <sys/stat.h>
//#include <minipc.h>
#include <hw/trace.h>
#include <hw/switch_hw.h>
#include <trace.h>
#include <switch_hw.h>
#include "wrsw_hal.h"
#include "rt_ipc.h"
#define MAX_CLEANUP_CALLBACKS 16
#define assert_init(proc) { int ret; if((ret = proc) < 0) return ret; }
static int daemon_mode= 0;
static hal_cleanup_callback_t cleanup_cb[MAX_CLEANUP_CALLBACKS];
......@@ -56,7 +52,6 @@ static void call_cleanup_cbs()
int hal_setup_fpga_images()
{
char fpga_dir[128];
char fw_name[128];
/* query the path to the firmware directory in the config file */
if( hal_config_get_string("global.hal_firmware_path", fpga_dir, sizeof(fpga_dir)) < 0)
......@@ -159,7 +154,6 @@ void hal_deamonize();
/* Main initialization function */
int hal_init()
{
int enable;
char sfp_db_path[1024];
trace_log_stderr();
......@@ -180,11 +174,14 @@ int hal_init()
// assert_init(hal_setup_fpga_images());
if(!hal_config_get_string("global.sfp_database_path", sfp_db_path, sizeof(sfp_db_path)))
if(shw_sfp_read_db(sfp_db_path) < 0)
{
if(shw_sfp_read_db(sfp_db_path) < 0) {
TRACE(TRACE_ERROR, "Can't read SFP database (%s)", sfp_db_path)
else
} else {
TRACE(TRACE_INFO, "Loaded SFP database (%s)", sfp_db_path);
}
}
/* Perform a low-level hardware init, load bitstreams, initialize non-kernel drivers */
assert_init(shw_init());
......
userspace/wrsw_hal/hal_ports.c
View file @ 2a3c8ce1
......@@ -16,14 +16,13 @@
#include <linux/if.h>
/* LOTs of hardware includes */
#include <hw/switch_hw.h>
#include <switch_hw.h>
#include <trace.h>
#include <pio.h>
#include <sfp_lib.h>
#include <hw/trace.h>
#include <hw/pio.h>
#include <hw/pio_pins.h>
#include <hw/fpga_regs.h>
#include <hw/endpoint_regs.h>
#include <hw/sfp_lib.h>
#include "wrsw_hal.h"
#include "timeout.h"
......@@ -694,22 +693,6 @@ int halexp_get_port_state(hexp_port_state_t *state, const char *port_name)
return 0;
}
/* Returns 1 if any of the switch's ports is currently being calibrated */
static int any_port_calibrating()
{
int i;
for(i=0; i<HAL_MAX_PORTS;i++)
if(ports[i].state == HAL_PORT_STATE_CALIBRATION && ports[i].in_use)
return 1;
return 0;
}
/* Public function for controlling the calibration process. Called by the PTPd during WR Link setup. */
/* No more calibration in V3 */
/* Public API function - returns the array of names of all WR network interfaces */
int halexp_query_ports(hexp_port_list_t *list)
{
......
userspace/wrsw_hal/hal_timing.c
View file @ 2a3c8ce1
......@@ -4,8 +4,9 @@
#include <stdlib.h>
#include <string.h>
#include <stdint.h>
#include <unistd.h>
#include <hw/switch_hw.h>
#include <switch_hw.h>
#include "wrsw_hal.h"
#include "timeout.h"
......
userspace/wrsw_hal/rt_ipc.h
View file @ 2a3c8ce1
......@@ -91,6 +91,9 @@ struct rts_pll_state {
/* API */
/* Connects to the RT CPU */
int rts_connect();
/* Queries the RT CPU PLL state */
int rts_get_state(struct rts_pll_state *state);
......
userspace/wrsw_hal/wrsw_hal.h
View file @ 2a3c8ce1
......@@ -3,7 +3,7 @@
#include <inttypes.h>
#include <hw/sfp_lib.h>
#include <sfp_lib.h>
typedef void (*hal_cleanup_callback_t)();
......@@ -13,9 +13,6 @@ typedef void (*hal_cleanup_callback_t)();
#define DEFAULT_T2_PHASE_TRANS 0
#define DEFAULT_T4_PHASE_TRANS 0
#define REF_CLOCK_PERIOD_PS 16000
/* Port delay calibration parameters */
typedef struct {
......
userspace/wrsw_rtud/rtu_drv.c
View file @ 2a3c8ce1
......@@ -38,12 +38,16 @@
#include <unistd.h>
#include <fcntl.h>
#include <stdlib.h>
#include <sys/ioctl.h>
#include <hw/switch_hw.h>
#include <hw/rtu_regs.h>
#include <switch_hw.h>
#include <hal_client.h>
#include <hw/fpga_regs.h>
#include <hw/rtu_regs.h>
#include "rtu_drv.h"
#include "wr_rtu.h"
......
userspace/wrsw_rtud/rtu_fd.c
View file @ 2a3c8ce1
......@@ -36,8 +36,10 @@
#include <unistd.h>
#include <pthread.h>
#include <hw/fpga_regs.h>
#include <hw/rtu_regs.h>
#include <hw/trace.h>
#include <trace.h>
#include "rtu_fd.h"
#include "rtu_drv.h"
......
userspace/wrsw_rtud/rtu_hash.c
View file @ 2a3c8ce1
......@@ -27,12 +27,9 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <hw/trace.h>
#include "rtu.h"
#include "rtu_hash.h"
/**
* \brief Polynomial used to calculate the MAC entry hash code.
*/
......@@ -43,7 +40,6 @@ static uint16_t crc16(uint16_t const init_crc, uint16_t const message);
void rtu_hash_set_poly(uint16_t poly)
{
hash_poly = ((0x10000 | poly) << 3 );
TRACE(TRACE_INFO, "poly hw = %x, poly sw = %x\n", poly, hash_poly);
}
uint16_t rtu_hash(uint8_t mac[ETH_ALEN], uint8_t fid)
......
userspace/wrsw_rtud/rtud.c
View file @ 2a3c8ce1
......@@ -35,7 +35,8 @@
#include <pthread.h>
#include <signal.h>
#include <hw/switch_hw.h>
#include <trace.h>
#include <switch_hw.h>
#include <hal_client.h>
#include "rtu.h"
......
userspace/wrsw_rtud/rtud_exports.c
View file @ 2a3c8ce1
......@@ -31,7 +31,7 @@
#include <stdint.h>
#include <errno.h>
#include <hw/trace.h>
#include <trace.h>
#include "minipc.h"
#include "rtu.h"
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment