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Commit 0a7acbd8 authored by Adam Wujek's avatar Adam Wujek 💬
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userspace/include: fix indentation in hal_exports.h 

No technical change
Signed-off-by: Adam Wujek's avatarAdam Wujek <adam.wujek@cern.ch>
parent 694cc4a2
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Showing with 66 additions and 75 deletions
userspace/include/hal/hal_exports.h
View file @ 0a7acbd8
......@@ -19,8 +19,6 @@
// requests a measurement of RX delta
#define HEXP_CAL_CMD_RX_MEASURE 5
#define HEXP_CAL_RESP_BUSY 1
#define HEXP_CAL_RESP_OK 0
#define HEXP_CAL_RESP_ERROR -1
......@@ -54,26 +52,24 @@
#define HEXP_EXTSRC_STATUS_NOSRC 2
/////////////////////////////////////
#define HAL_TIMING_MODE_GRAND_MASTER 0
#define HAL_TIMING_MODE_FREE_MASTER 1
#define HAL_TIMING_MODE_BC 2
typedef struct {
char port_name[16];
char port_name[16];
int pps_valid;
uint32_t current_phase_shift;
int32_t adjust_phase_shift;
uint32_t current_phase_shift;
int32_t adjust_phase_shift;
int64_t adjust_sec;
int32_t adjust_nsec;
int64_t adjust_sec;
int32_t adjust_nsec;
uint64_t current_sec;
uint32_t current_nsec;
uint64_t current_sec;
uint32_t current_nsec;
} hexp_pps_params_t;
......@@ -83,7 +79,6 @@ typedef struct {
#define HEXP_PORT_MODE_WR_SLAVE 2
#define HEXP_PORT_MODE_NON_WR 3
#define FIX_ALPHA_FRACBITS 40
/*
#define HEXP_PORT_TSC_RISING 1
......@@ -91,58 +86,58 @@ typedef struct {
*/
typedef struct hexp_port_state {
/* When non-zero: port state is valid */
int valid;
/* When non-zero: port state is valid */
int valid;
/* WR-PTP role of the port (Master, Slave, etc.) */
int mode;
/* WR-PTP role of the port (Master, Slave, etc.) */
int mode;
/* TX and RX delays (combined, big Deltas from the link model in the spec) */
uint32_t delta_tx;
uint32_t delta_rx;
/* TX and RX delays (combined, big Deltas from the link model in the spec) */
uint32_t delta_tx;
uint32_t delta_rx;
/* DDMTD raw phase value in picoseconds */
uint32_t phase_val;
/* DDMTD raw phase value in picoseconds */
uint32_t phase_val;
/* When non-zero: phase_val contains a valid phase readout */
int phase_val_valid;
/* When non-zero: phase_val contains a valid phase readout */
int phase_val_valid;
/* When non-zero: link is up */
int up;
/* When non-zero: link is up */
int up;
/* When non-zero: TX path is calibrated (delta_tx contains valid value) */
int tx_calibrated;
/* When non-zero: TX path is calibrated (delta_tx contains valid value) */
int tx_calibrated;
/* When non-zero: RX path is calibrated (delta_rx contains valid value) */
int rx_calibrated;
int tx_tstamp_counter;
int rx_tstamp_counter;
int is_locked;
int lock_priority;
/* When non-zero: RX path is calibrated (delta_rx contains valid value) */
int rx_calibrated;
int tx_tstamp_counter;
int rx_tstamp_counter;
int is_locked;
int lock_priority;
// timestamp linearization paramaters
// timestamp linearization paramaters
uint32_t phase_setpoint; // DMPLL phase setpoint (picoseconds)
uint32_t phase_setpoint; // DMPLL phase setpoint (picoseconds)
uint32_t clock_period; // reference lock period in picoseconds
uint32_t t2_phase_transition; // approximate DMTD phase value (on slave port) at which RX timestamp (T2) counter transistion occurs (picoseconds)
uint32_t clock_period; // reference lock period in picoseconds
uint32_t t2_phase_transition; // approximate DMTD phase value (on slave port) at which RX timestamp (T2) counter transistion occurs (picoseconds)
uint32_t t4_phase_transition; // approximate phase value (on master port) at which RX timestamp (T4) counter transistion occurs (picoseconds)
uint32_t t4_phase_transition; // approximate phase value (on master port) at which RX timestamp (T4) counter transistion occurs (picoseconds)
uint8_t hw_addr[6];
int hw_index;
int32_t fiber_fix_alpha;
uint8_t hw_addr[6];
int hw_index;
int32_t fiber_fix_alpha;
} hexp_port_state_t;
typedef struct hexp_port_list {
int num_ports; /* Number of ports in the list */
int num_physical_ports; /* Number of physical ports compiled into the FPGA bitstream */
char port_names[HAL_MAX_PORTS][16];
int num_ports; /* Number of ports in the list */
int num_physical_ports; /* Number of physical ports compiled into the FPGA bitstream */
char port_names[HAL_MAX_PORTS][16];
} hexp_port_list_t;
typedef struct {
int timing_mode; /* Free-running Master/GM/BC */
int locked_port;
int timing_mode; /* Free-running Master/GM/BC */
int locked_port;
} hexp_timing_state_t;
......@@ -155,7 +150,6 @@ extern int halexp_get_port_state(hexp_port_state_t *state, const char *port_name
extern int halexp_pps_cmd(int cmd, hexp_pps_params_t *params);
extern int halexp_get_timing_state(hexp_timing_state_t *state);
/* Export structures, shared by server and client for argument matching */
#ifdef HAL_EXPORT_STRUCTURES
......@@ -164,8 +158,8 @@ struct minipc_pd __rpcdef_check_running = {
.name = "check_running",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_END,
},
MINIPC_ARG_END,
},
};
//int halexp_reset_port(const char *port_name);
......@@ -173,9 +167,9 @@ struct minipc_pd __rpcdef_reset_port = {
.name = "reset_port",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_END,
},
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_END,
},
};
//int halexp_calibration_cmd(const char *port_name, int command, int on_off);
......@@ -183,11 +177,11 @@ struct minipc_pd __rpcdef_calibration_cmd = {
.name = "calibration_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_END,
},
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_END,
},
};
//int halexp_lock_cmd(const char *port_name, int command, int priority);
......@@ -195,11 +189,11 @@ struct minipc_pd __rpcdef_lock_cmd = {
.name = "lock_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_END,
},
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_END,
},
};
//int halexp_get_port_state(hexp_port_state_t *state, const char *port_name);
......@@ -207,9 +201,9 @@ struct minipc_pd __rpcdef_get_port_state = {
.name = "get_port_state",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_port_state_t),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_END,
},
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRING, char *),
MINIPC_ARG_END,
},
};
//int halexp_pps_cmd(int cmd, hexp_pps_params_t *params);
......@@ -217,23 +211,20 @@ struct minipc_pd __rpcdef_pps_cmd = {
.name = "pps_cmd",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
.args = {
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_pps_params_t),
MINIPC_ARG_END,
},
MINIPC_ARG_ENCODE(MINIPC_ATYPE_INT, int),
MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_pps_params_t),
MINIPC_ARG_END,
},
};
struct minipc_pd __rpcdef_get_timing_state = {
.name = "get_timing_state",
.retval = MINIPC_ARG_ENCODE(MINIPC_ATYPE_STRUCT, hexp_timing_state_t),
.args = {
MINIPC_ARG_END,
},
MINIPC_ARG_END,
},
};
#endif /* HAL_EXPORT_STRUCTURES */
#endif
ppsi @ fa133200
Subproject commit d724bd8f100aa227d5aa01ccace3ed023b140a8b
Subproject commit fa1332004d01384a667fad3057f1307baf58af3b
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