diff --git a/rt/dev/ad9516.c b/rt/dev/ad9516.c
index 7b6038ff483082a05af10a75c30beaa7426da627..02086194ab75837470f62f40d1d66517a19f5032 100644
--- a/rt/dev/ad9516.c
+++ b/rt/dev/ad9516.c
@@ -11,15 +11,22 @@
#include "syscon.h"
#include "gpio.h"
-
-#include "ad9516.h"
-
#include "rt_ipc.h"
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
#endif
+static inline void writel(uint32_t data, void *where)
+{
+ * (volatile uint32_t *)where = data;
+}
+
+static inline uint32_t readl(void *where)
+{
+ return * (volatile uint32_t *)where;
+}
+
struct ad9516_reg {
uint16_t reg;
uint8_t val;
diff --git a/rt/dev/uart.c b/rt/dev/uart.c
index 4596c2de093449c1011a71fd49f8a3b5425701c2..28cb00756e33a189eb0e74363f6d8b7daffc4fb4 100644
--- a/rt/dev/uart.c
+++ b/rt/dev/uart.c
@@ -1,8 +1,7 @@
-#include "defs.h"
#include "board.h"
#include "uart.h"
-#include <hw/wb_uart.h>
+#include <hw/wb_vuart.h>
#define CALC_BAUD(baudrate) \
( ((( (unsigned long long)baudrate * 8ULL) << (16 - 7)) + \
@@ -38,4 +37,4 @@ int uart_poll()
int uart_read_byte()
{
return uart ->RDR & 0xff;
-}
\ No newline at end of file
+}
diff --git a/rt/include/ad9516.h b/rt/include/ad9516.h
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/rt/include/defs.h b/rt/include/defs.h
deleted file mode 100644
index e2727173e3344ff436f7f3d8916e7ace60ce8a99..0000000000000000000000000000000000000000
--- a/rt/include/defs.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __DEFS_H
-#define __DEFS_H
-
-#include <stdint.h>
-
-static inline void writel(uint32_t data, void *where)
-{
- * (volatile uint32_t *)where = data;
-}
-
-static inline uint32_t readl(void *where)
-{
- return * (volatile uint32_t *)where;
-}
-
-
-#endif
diff --git a/rt/include/hw/wb_uart.h b/rt/include/hw/wb_uart.h
deleted file mode 100644
index 05f06c0c9ab5ab50db9edb5b85ff8658b0c9ac4b..0000000000000000000000000000000000000000
--- a/rt/include/hw/wb_uart.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- Register definitions for slave core: Simple Wishbone UART
-
- * File : ../../../../software/include/hw/wb_uart.h
- * Author : auto-generated by wbgen2 from uart.wb
- * Created : Mon Feb 21 22:25:02 2011
- * Standard : ANSI C
-
- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE uart.wb
- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
-
-*/
-
-#ifndef __WBGEN2_REGDEFS_UART_WB
-#define __WBGEN2_REGDEFS_UART_WB
-
-#include <stdint.h>
-
-#if defined( __GNUC__)
-#define PACKED __attribute__ ((packed))
-#else
-#error "Unsupported compiler?"
-#endif
-
-#ifndef __WBGEN2_MACROS_DEFINED__
-#define __WBGEN2_MACROS_DEFINED__
-#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
-#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
-#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
-#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
-#endif
-
-
-/* definitions for register: Status Register */
-
-/* definitions for field: TX busy in reg: Status Register */
-#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
-
-/* definitions for field: RX ready in reg: Status Register */
-#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
-
-/* definitions for register: Baudrate control register */
-
-/* definitions for register: Transmit data regsiter */
-
-/* definitions for field: Transmit data in reg: Transmit data regsiter */
-#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
-#define UART_TDR_TX_DATA_SHIFT 0
-#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
-#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
-
-/* definitions for register: Receive data regsiter */
-
-/* definitions for field: Received data in reg: Receive data regsiter */
-#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
-#define UART_RDR_RX_DATA_SHIFT 0
-#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
-#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
-/* [0x0]: REG Status Register */
-#define UART_REG_SR 0x00000000
-/* [0x4]: REG Baudrate control register */
-#define UART_REG_BCR 0x00000004
-/* [0x8]: REG Transmit data regsiter */
-#define UART_REG_TDR 0x00000008
-/* [0xc]: REG Receive data regsiter */
-#define UART_REG_RDR 0x0000000c
-
-PACKED struct UART_WB {
- /* [0x0]: REG Status Register */
- uint32_t SR;
- /* [0x4]: REG Baudrate control register */
- uint32_t BCR;
- /* [0x8]: REG Transmit data regsiter */
- uint32_t TDR;
- /* [0xc]: REG Receive data regsiter */
- uint32_t RDR;
-};
-
-#endif
diff --git a/rt/include/hw/wb_vuart.h b/rt/include/hw/wb_vuart.h
new file mode 100644
index 0000000000000000000000000000000000000000..930dae5e66bad56fdcec513a80dea82ea7927579
--- /dev/null
+++ b/rt/include/hw/wb_vuart.h
@@ -0,0 +1,96 @@
+/*
+ Register definitions for slave core: Virtual UART
+
+ * File : wb_vuart.h
+ * Author : auto-generated by wbgen2 from wb_virtual_uart.wb
+ * Created : Wed Apr 6 23:02:01 2011
+ * Standard : ANSI C
+
+ THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_virtual_uart.wb
+ DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+
+*/
+
+#ifndef __WBGEN2_REGDEFS_WB_VIRTUAL_UART_WB
+#define __WBGEN2_REGDEFS_WB_VIRTUAL_UART_WB
+
+#include <inttypes.h>
+
+#if defined( __GNUC__)
+#define PACKED __attribute__ ((packed))
+#else
+#error "Unsupported compiler?"
+#endif
+
+#ifndef __WBGEN2_MACROS_DEFINED__
+#define __WBGEN2_MACROS_DEFINED__
+#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
+#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
+#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
+#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
+#endif
+
+/* definitions for register: Status Register */
+
+/* definitions for field: TX busy in reg: Status Register */
+#define UART_SR_TX_BUSY WBGEN2_GEN_MASK(0, 1)
+
+/* definitions for field: RX ready in reg: Status Register */
+#define UART_SR_RX_RDY WBGEN2_GEN_MASK(1, 1)
+
+/* definitions for register: Baudrate control register */
+
+/* definitions for register: Transmit data regsiter */
+
+/* definitions for field: Transmit data in reg: Transmit data regsiter */
+#define UART_TDR_TX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
+#define UART_TDR_TX_DATA_SHIFT 0
+#define UART_TDR_TX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_TDR_TX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: Receive data regsiter */
+
+/* definitions for field: Received data in reg: Receive data regsiter */
+#define UART_RDR_RX_DATA_MASK WBGEN2_GEN_MASK(0, 8)
+#define UART_RDR_RX_DATA_SHIFT 0
+#define UART_RDR_RX_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_RDR_RX_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: FIFO 'UART TX FIFO' data output register 0 */
+
+/* definitions for field: Char sent by UART to TX in reg: FIFO 'UART TX FIFO' data output register 0 */
+#define UART_DEBUG_R0_TX_MASK WBGEN2_GEN_MASK(0, 8)
+#define UART_DEBUG_R0_TX_SHIFT 0
+#define UART_DEBUG_R0_TX_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_DEBUG_R0_TX_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+/* definitions for register: FIFO 'UART TX FIFO' control/status register */
+
+/* definitions for field: FIFO full flag in reg: FIFO 'UART TX FIFO' control/status register */
+#define UART_DEBUG_CSR_FULL WBGEN2_GEN_MASK(16, 1)
+
+/* definitions for field: FIFO empty flag in reg: FIFO 'UART TX FIFO' control/status register */
+#define UART_DEBUG_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
+
+/* definitions for field: FIFO counter in reg: FIFO 'UART TX FIFO' control/status register */
+#define UART_DEBUG_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
+#define UART_DEBUG_CSR_USEDW_SHIFT 0
+#define UART_DEBUG_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
+#define UART_DEBUG_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
+
+PACKED struct UART_WB {
+ /* [0x0]: REG Status Register */
+ uint32_t SR;
+ /* [0x4]: REG Baudrate control register */
+ uint32_t BCR;
+ /* [0x8]: REG Transmit data regsiter */
+ uint32_t TDR;
+ /* [0xc]: REG Receive data regsiter */
+ uint32_t RDR;
+ /* [0x10]: REG FIFO 'UART TX FIFO' data output register 0 */
+ uint32_t DEBUG_R0;
+ /* [0x14]: REG FIFO 'UART TX FIFO' control/status register */
+ uint32_t DEBUG_CSR;
+};
+
+#endif
diff --git a/rt/include/stdint.h b/rt/include/stdint.h
deleted file mode 100644
index 515622418f27ff9a6c3453b2d8e618d629dd8ac9..0000000000000000000000000000000000000000
--- a/rt/include/stdint.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __ARCH_LM32_STDINT_H__
-#define __ARCH_LM32_STDINT_H__
-
-/*
- * We miss a stdint.h in our compiler, so provide some types here,
- * knowing the CPU is 32-bits and uses LP32 model
- */
-
-typedef unsigned char uint8_t;
-typedef unsigned short uint16_t;
-typedef unsigned long uint32_t;
-typedef unsigned long long uint64_t;
-
-typedef signed char int8_t;
-typedef signed short int16_t;
-typedef signed long int32_t;
-typedef signed long long int64_t;
-
-#endif /* __ARCH_LM32_STDINT_H__ */
diff --git a/rt/include/syscon.h b/rt/include/syscon.h
index 64e4a4fc93d9d9151b0b408e1b2e9224013cf59b..c8bcc12dfcd33974954955534a2f18bfa74ca6b7 100644
--- a/rt/include/syscon.h
+++ b/rt/include/syscon.h
@@ -1,7 +1,7 @@
#ifndef __SYSCON_H
#define __SYSCON_H
-#include "defs.h"
+#include <stdint.h>
#define TICS_PER_SECOND 100000
diff --git a/rt/include/wrc.h b/rt/include/wrc.h
index 4fdc8ba84cf9c6a01d0e2614a936b7d260fae8f4..aee580b3f1392063948a0d5055ffec4f8387b2e1 100644
--- a/rt/include/wrc.h
+++ b/rt/include/wrc.h
@@ -1,7 +1,6 @@
#ifndef __WRC_H
#define __WRC_H
-#include "defs.h"
#include "syscon.h"
#define PPS_WIDTH (10 * 1000 * 1000 / 16) /* 10ms */
diff --git a/rt/main.c b/rt/main.c
index 5a6037317bef4c4230619fec30b9949a95ba114c..0291d7b1285a124a2b887c450a9a7a9cd2ec7370 100644
--- a/rt/main.c
+++ b/rt/main.c
@@ -1,4 +1,3 @@
-#include "defs.h"
#include "uart.h"
#include "syscon.h"