-- -*- Mode: LUA; tab-width: 2 -*-

peripheral {
	 name = "Routing Table Unit (RTU)";
   prefix = "rtu";

	 hdl_entity="rtu_wishbone_slave";
	 
-- Port Configuration Register
	 reg {
			name = "RTU Global Control Register";
			description = "Control register containing global (port-independent) settings of the RTU.";
			prefix = "GCR";

			field {
				 name = "RTU Global Enable";
				 description = "Global RTU enable bit. Overrides all port settings.\
                        0: RTU is disabled. All packets are dropped.\
                        1: RTU is enabled.";

				 type = BIT;
				 prefix = "G_ENA";
				 access_dev = READ_ONLY;
				 access_bus = READ_WRITE;
         clock = "clk_match_i";

			};

      field {
         name = "MFIFO Trigger";
         description = "write 1: triggers a flush of MFIFO into the hash table (blocks the RTU for a few cycles)\
         write 0: no effect\
         read 1: MFIFO is busy\
         read 0: MFIFO is idle";

         prefix = "MFIFOTRIG";
         
         type = BIT;
         load = LOAD_EXT;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         clock = "clk_match_i";

      };

			field {
				 name = "Hash Poly";
				 description = "Determines the polynomial used for hash computation. Currently available:  0x1021, 0x8005, 0x0589 ";

 				 type = SLV;
				 prefix = "POLY_VAL";
			 	 align = 8;
				 size = 16 ;
				 access_dev = READ_ONLY;
				 access_bus = READ_WRITE;
         clock = "clk_match_i";

			};

			field {
				 name = "Version";
				 description = "Information about the version of RTU gateware";

 				 type = SLV;
				 prefix = "RTU_VERSION";
			 	 align = 8;
				 size = 4 ;
				 access_dev = WRITE_ONLY;
				 access_bus = READ_ONLY;
			};
	 };

   reg {
      name = "Port Select Register";
      description = "Selects the port to control through the PCR register";
      prefix = "PSR";

      field {
         name = "Port Select";
         prefix = "PORT_SEL";
         description = "Selected Port";
         size = 8;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         name = "Number of ports";
         prefix = "N_PORTS";
         description = "Number of RTU ports compiled in.";
         size = 8;
         type = SLV;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };

   reg {
      name = "Port Control Register";
      description = "Register controlling the mode of the RTU port selected by PSELR register.";
      prefix = "PCR";

      field {
         name = "Learning enable";
         description = "1: enables learning process on this port. Unrecognized requests will be put into UFIFO\
         0: disables learning. Unrecognized requests will be either broadcast or dropped.";
         prefix = "LEARN_EN";
         
         type = BIT;
         access_dev = READ_WRITE;
         access_bus = READ_WRITE;
         load = LOAD_EXT;
      };
      
      field {
         name = "Pass all packets";
         description = "1: all packets are passed (depending on the rules in RT table). \
         0: all packets are dropped on this port.";

         prefix = "PASS_ALL";
         
         type = BIT;
         access_dev = READ_WRITE;
         access_bus = READ_WRITE;
         load = LOAD_EXT;
      };

      field {
         name = "Pass BPDUs";
         description = "1: BPDU packets (with dst MAC 01:80:c2:00:00:00) are passed according to RT rules. This setting overrides PASS_ALL.\
         0: BPDU packets are passed according to RTU rules only if PASS_ALL is set.[ML by modified]";

         prefix = "PASS_BPDU";
         
         type = BIT;
         access_dev = READ_WRITE;
         access_bus = READ_WRITE;
         load = LOAD_EXT;

      };

      field {
         name = "Fix priority";
         description = "1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint\
         0: Use priority from the endpoint";

         prefix = "FIX_PRIO";

         type = BIT;
         access_dev = READ_WRITE;
         access_bus = READ_WRITE;
         load = LOAD_EXT;
      };


      field {
         name = "Priority value";
         description = "Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1";

         prefix = "PRIO_VAL";
         
         type = SLV;
         align = 4;
         size =3 ;
         access_dev = READ_WRITE;
         access_bus = READ_WRITE;
         load = LOAD_EXT;
      };


      field {
         name = "Unrecognized request behaviour";
         description = "Sets the port behaviour for all unrecognized requests:\
         0: packet is dropped\
         1: packet is broadcast";
         prefix = "B_UNREC";
         
         type = BIT;

         access_dev = READ_WRITE;
         access_bus = READ_WRITE;
         load = LOAD_EXT;
      };
   };

   reg {
      name = "VLAN Table Register 1";
      prefix = "VTR1";
      
      field {
         prefix = "VID";
         name = "VLAN ID";
         size = 12;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
     };

      field {
         prefix = "FID";
         name = "Filtering Database ID";
         description = "Assigns the VID to a particular filtering database";
         size = 8;
         type = SLV;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         prefix = "DROP";
         name = "Drop";
         description = "1: drop all packets belonging to this VLAN";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         prefix = "HAS_PRIO";
         name = "Has user-defined priority";
         description = "1: VLAN has user-defined priority";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         prefix = "PRIO_OVERRIDE";
         name = "Override endpoint-assigned priority";
         description = "1: always take the priority from the PRIO field, regardless of the priority value assigned at the endpoint. ";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         prefix = "PRIO";
         name = "Priority value";
         type = SLV;
         size = 3;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         prefix = "UPDATE";
         name = "Force VLAN table entry update";
         description = "write 1: flush VTR1 and VTR2 registers to VLAN table entry designated in VTR1.VID";
         type = MONOSTABLE;
      }
   };

   reg {
      prefix = "VTR2";
      name = "VLAN Table Register 2";
      
      field {
         name = "Port Mask";
         prefix = "PORT_MASK";
         type = SLV;
         size = 32;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };

   
	
	fifo_reg {
		 name = "Unrecognized request FIFO (UFIFO)";
		 description = "FIFO containing all RTU requests for which matching entries haven't been found. CPU reads these requests,\
		                evaluates them and updates the RTU tables accordingly.";

		 prefix = "UFIFO";
		 direction = CORE_TO_BUS;
		 size = 128;

		 flags_dev = {FIFO_FULL, FIFO_EMPTY};
		 flags_bus = {FIFO_EMPTY, FIFO_COUNT};

		 --clock = "clk_match_i";
		  -- clock = ""; - make it asynchronous if you want

		 field {
				name = "Destination MAC address least-significant part";
				description = "Bits [31:0] of packet destination MAC address";
				prefix = "DMAC_LO";

				type = SLV;
				size = 32;
		 };

	 field {
				name = "Destination MAC address most-significant part";
				description = "Bits [47:32] of packet destination MAC address";
				prefix = "DMAC_HI";

				type = SLV;
				size = 16;
		 };

		 field {
				name = "Source MAC address least-significant part";
				description = "Bits [31:0] of packet source MAC address";
				prefix = "SMAC_LO";

				type = SLV;
				size = 32;
		 };


		 field {
				name = "Source MAC address most-significant part";
				description = "Bits [47:32] of packet source MAC address";
				prefix = "SMAC_HI";

				type = SLV;
				size = 16;
		 };

		 field {
				name = "VLAN Identifier";
				description = "VLAN ID of the packet (from the endpoint)";
				prefix = "VID";
				size = 12;
				type = SLV;
				align = 32;
		 };

		 field {
				name = "Priority";
				description = "Priority value (from the endpoint)";
				prefix = "PRIO";
				size = 3;
				align = 4;
				type = SLV;
		 };

		 field {
				name = "Port ID";
				description = "Identifier of RTU port to which came the request.";
				prefix = "PID";
				size = 8;
				align = 8;
				type = SLV;
		 };

		 field {
				name = "VID valid";
				description = "1: VID value is valid\
                       0: packet had no VLAN ID";
				prefix = "HAS_VID";
			
				align = 4;
				type = BIT;
		 };

		 field {
				name = "PRIO valid";
				description = "1: PRIO value is valid\
                       0: packet had no priority assigned";
				prefix = "HAS_PRIO";
			
				type = BIT;
		 };
	};




	fifo_reg {
		 name = "Main hashtable CPU access FIFO (MFIFO)";
		 description = "FIFO for writing to main hashtable";
		 prefix = "MFIFO";
		 direction = BUS_TO_CORE;
		 size = 64;

		 flags_dev = {FIFO_EMPTY, FIFO_COUNT};
		 flags_bus = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT};

		 
		 field {
				name = "Address/data select";
				description = "1: AD_VAL contains new memory address\
				               0: AD_VAL contains data word to be written at current memory address. Then, the address is incremented";
				prefix = "AD_SEL";
				type = BIT;
		 };

		 field {
				name = "Address/data value";
				description = "Value of new memory address (when AD_SEL = 1) or data word to be written (when AD_SEL = 0)";
				prefix = "AD_VAL";
				type = SLV;
				align =32;
				size = 32;
		 };

		 clock = "clk_match_i";

	};

   reg {
      prefix = "RX_CTR";
      name = "RTU Extension: Control Register";
      field {
         name = "Fast Forward for Broadcast";
         description = "The feature is:\
                 0: Disabled,\
                 1: Enabled.";
         prefix = "FF_MAC_BR";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Fast Forward for MAC Range";
         description = "The feature is:\
                 0: Disabled,\
                 1: Enabled.";
         prefix = "FF_MAC_RANGE";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Fast Forward for MAC Single Entries";
         description = "The feature is:\
                 0: Disabled,\
                 1: Enabled.";
         prefix = "FF_MAC_SINGLE";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Fast Forward for Link-Limited (Reserved) MACs";
         description = "The feature is:\
                 0: Disabled,\
                 1: Enabled.";
         prefix = "FF_MAC_LL";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Fast Forward for PTP frames (PTP over IEEE 802.3 /Ethernet)";
         description = "The feature is:\
                 0: Disabled,\
                 1: Enabled.";
         prefix = "FF_MAC_PTP";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Port Mirror Enable";
         description = "Enable port mirroring as defined by proper configurition\
                 0: Disable,\
                 1: Enable.";
         prefix = "MR_ENA";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         name = "Drop/Forward on FullMatch Full";
         description = "In case that a new Frame arrives on Ingress when the previous is still handed (FullMatch process, or SWcore):\
                 0: Drop currently processed frame (default),\
                 1: Broadcast currently processed frame.";
         prefix = "AT_FMATCH_TOO_SLOW";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "HP Priorities Mask";
         description="Mask which defines which priorities of the Fast Forward traffic are considered High Priority (used also by SWcore)";
         prefix = "PRIO_MASK";
         type = SLV;
         size = 8;
         align = 8;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         name = "HP forward to CPU";
         description = "Enables/disables forwarding of recognized HP frames to CPU (Network InterFace) - disabling forwarding can prevent flooding of switch CPU with unnecessary traffic, allowing forwarding can be enabled to snoop on network traffic). It uses HW-set (generic) mask which indicates port number of CPU - can be verified by reading\
                 0: Disabled [default] - does not forward HP frames to CPU,\
                 1: Enabled  - forwards HP frames to CPU.";
         prefix = "HP_FW_CPU_ENA";
         align = 8;
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Urecognized forward to CPU";
         description = "Allows to enable/disable forwarding of unrecognized frames (with unrecognized dstMAC) which are broadcast (when b_unrec enabled) CPU (Network InterFace) - disabled to prevent flooding of switch CPU with unnecessary traffic.It uses Link-Limited Frames Fast Forward Mask to know to which port CPU is connected.\
                 0: Disabled [default] - does not forward unrecognized braodcast (b_unrec) frames to CPU,\
                 1: Enabled  - forwards unrecognized braodcast (b_unrec) frames to CPU.";
         prefix = "UREC_FW_CPU_ENA";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

      field {
         name = "Learn Destination MAC enable";
         description = "Allows to enable/disable learning based on Destination MAC address (works only if learning is enabled on a port, i.e. LEARN_EN=1) .\
                 0: Disabled [default] - frames with unrecognizd destinatin MAC do not trigger writes to UFIFO, i.e. ureq in software (unrecognized request),\
                 1: Enabled  - frames with unrecognizd destinatin MAC trigger writes to UFIFO, i.e. ureq in software.";
         prefix = "LEARN_DST_ENA";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "DBG: Force Fast Match only";
         description = "Forces RTU to use only Fast Match for forwarding decisions (useful for debugging).\
                 0: Disabled [default]\
                 1: Enabled  (use when you know what you are doing, not in normal operation)";
         prefix = "FORCE_FAST_MATCH_ENA";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
         align = 8;
      };
      field {
         name = "DBG: Force Full Match only";
         description = "Forces RTU to use only Full Match for forwarding decisions (useful for debugging).\
                 0: Disabled [default]\
                 1: Enabled  (use when you know what you are doing, not in normal operation)";
         prefix = "FORCE_FULL_MATCH_ENA";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

   };
   reg {
      prefix = "RX_FF_MAC_R0";
      name = "RTU Extension: Fast Forward MAC bits [31:0] (validated on write to RX_FF_MAC_R1).";
      
      field {
         name = "Fast Forward MAC";
         prefix = "LO";
         type = SLV;
         size = 32;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };
   reg {
      prefix = "RX_FF_MAC_R1";
      name = "RTU Extension: Fast Forward MAC and control";
      description = "Double purpose on \
                 WRITE: low bigs: MAC bits [47:32]; high bits: MAC ID, single/range, valid,\
                 READ: low bits: max number of single entries (MAX ID), high bits: max number of range entries (MAX ID).";
      field {
         name = "Fast Forward MAC";
         prefix = "HI_ID";
         type = SLV;
         size = 16;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
      };
      
      field {
         name ="Fast Forward entry index (single/range)";
         description = "Depending on the Single/Range bit: \
                 0: Index of the Fast Forward MAC for single Fast Forward MAC\
                 1: Index of the Fast Forward MAC for the Fast Forward MAC range (low bit 0 indicates lower range, low bit 1 indicates upper range, inclusive) ";
         prefix = "ID";
         type = SLV;
         size = 8;
         align =8;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
      };

      field {
         name = "Fast Forward MAC single/range entry";
         description = "Indicates what kind of entry is written \
                 0: Single Fast Forward MAC,\
                 1: Range Fast Forward MAC (low bit of MAC ID equal to 0 indicates lower range, low bit of MAX ID equal to 1 indicates upper range, inclusive) ";
         prefix = "TYPE";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Fast Forward MAC valid";
         description = "The value of the bit (only validated entries are used):\
                 0: Invalidates the entry,\
                 1: Validates the entry.";
         prefix = "VALID";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
   };
   reg {
      prefix = "CPU_PORT";
      name = "RTU Extension: CPU port mask (Link-Limited Frames Fast Forward Mask)";
      field {
         name = " CPU/LL Mask";
         description = " It is only for debugging purposes. The ID of the CPU port is set in HW using generic which produces the CPU/LL Mask.\
             It is used for\
             * forwarding of the Link-Limited traffic to CPU (if enabled by config) \
             * enabling/disabling forwarding of HP traffic to CPU (HP_FW_CPU_ENA)\
             * enabling/disabling forwarding of unrecognized broadcast to CPU (UREC_FW_CPU_ENA).";
         prefix = "MASK";
         type = SLV;
         size = 32;
         access_bus = READ_ONLY;
         access_dev = WRITE_ONLY;
      };
   };
   reg {
      prefix = "RX_MP_R0";
      name = "RTU Extension: Mirroring Ports Control Register - select for the mask written using RX_MP_R1";
      field {
         name = "DST/SRC Mirror port";
         description = "Defines whether destination or source mask is written to RX_MP_R1:\
                 0: Mirror port(s) - destination of the mirrored traffic,\
                 1: Mirrored port(s) - source of the mirrored traffic";
         prefix = "DST_SRC";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "RX/TX mirror port source";
         description = "Defines whether transmission or reception source mask is written to RX_MP_R1 (used only when DST_SRC bit is 1):\
                 0: Reception traffic mirror source,\
                 1: Transmission traffic mirror source.";
         prefix = "RX_TX";
         type = BIT;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };
      field {
         name = "Mirrored Port MASK Index";
         description = "Index of the mirrored configuration (to be considered for implementation in future, curreantly only single config available)";
         prefix = "MASK_ID";
         type = SLV;
         size = 16;
         align = 16;
         access_bus = READ_WRITE;
         access_dev = READ_ONLY;
      };

   };
   reg {
      prefix = "RX_MP_R1";
      name = "RTU Extension: Mirroring Ports Control Register 1";
      field {
         name = "Mirror Port MASK";
         description = "MASK to define mirroring, depending on two lowets bit of select reg:\
         00: port(s) which output mirrored traffic from the mirrored port(s)- destination of the mirrored traffic (egress only, disabled for ingress traffic and traffic other then from mirrored, source, port(s))\
         10: port(s) whose ingress traffic is mirrored (reception source) - all the traffic received on this port(s) is forwarded to the mirror port(s)\
         11: port(s) whose egress traffic is mirrored (transmision source) - all the traffic forwareded to this port(s) is also forwarded to the mirror port(s).";
         prefix = "MASK";
         type = SLV;
         size = 32;
         access_bus = READ_WRITE;
         access_dev = READ_WRITE;
         load = LOAD_EXT;
      };
   };
	ram {
		 name = "Aging bitmap for main hashtable";
		 description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
                    0: entry wasn't matched\
                    1: entry was matched at least once.\
                    CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
		 prefix = "ARAM";

		 width = 32;
		 size = 8192 / 32; -- 8192 bits
		 access_dev = READ_WRITE;
		 access_bus = READ_WRITE;
		 
		 --[changed 6/10/2010] clock = "clk_match_i";
		 --clock = "clk_match_i"; --async?

	};

irq {
		 name = "UFIFO Not Empty IRQ";
		 description = "Interrupt active when there are some requests in UFIFO.";
		 prefix = "nempty";
		 trigger = LEVEL_0;
	};

};


