/*
  Register definitions for slave core: WR switch Time Aware Traffic Shaper controller

  * File           : tatsu-regs.h
  * Author         : auto-generated by wbgen2 from tatsu-regs.wb
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tatsu-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_TATSU
#define __WBGEN2_REGDEFS_TATSU

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif


#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: TATSU Control Register/Status */

/* definitions for field: Validate new settings, enable TATSU (if disabled) in reg: TATSU Control Register/Status */
#define TATSU_TCR_VALIDATE                    WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Stop TATSU in reg: TATSU Control Register/Status */
#define TATSU_TCR_DISABLE                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Drop no-HP at HP in reg: TATSU Control Register/Status */
#define TATSU_TCR_DROP_ENA                    WBGEN2_GEN_MASK(8, 1)

/* definitions for field: Min repeat value in reg: TATSU Control Register/Status */
#define TATSU_TCR_MIN_RPT_MASK                WBGEN2_GEN_MASK(16, 8)
#define TATSU_TCR_MIN_RPT_SHIFT               16
#define TATSU_TCR_MIN_RPT_W(value)            WBGEN2_GEN_WRITE(value, 16, 8)
#define TATSU_TCR_MIN_RPT_R(reg)              WBGEN2_GEN_READ(reg, 16, 8)

/* definitions for field: TATSU started in reg: TATSU Control Register/Status */
#define TATSU_TCR_STARTED                     WBGEN2_GEN_MASK(24, 1)

/* definitions for field: Delayed start in reg: TATSU Control Register/Status */
#define TATSU_TCR_DELAYED                     WBGEN2_GEN_MASK(25, 1)

/* definitions for field: Settings OK in reg: TATSU Control Register/Status */
#define TATSU_TCR_STG_OK                      WBGEN2_GEN_MASK(26, 1)

/* definitions for field: Settings Error in reg: TATSU Control Register/Status */
#define TATSU_TCR_STG_ERR                     WBGEN2_GEN_MASK(27, 1)

/* definitions for field: Settings Error: TAI value in reg: TATSU Control Register/Status */
#define TATSU_TCR_STG_ERR_TAI                 WBGEN2_GEN_MASK(28, 1)

/* definitions for field: Settings Error: cycle value in reg: TATSU Control Register/Status */
#define TATSU_TCR_STG_ERR_CYC                 WBGEN2_GEN_MASK(29, 1)

/* definitions for field: Settings Error: repeat value in reg: TATSU Control Register/Status */
#define TATSU_TCR_STG_ERR_RPT                 WBGEN2_GEN_MASK(30, 1)

/* definitions for field: Internal Time Sync Error in reg: TATSU Control Register/Status */
#define TATSU_TCR_STG_ERR_SNC                 WBGEN2_GEN_MASK(31, 1)

/* definitions for register: TATSU Settings Register 0 */

/* definitions for field: Quanta in reg: TATSU Settings Register 0 */
#define TATSU_TSR0_QNT_MASK                   WBGEN2_GEN_MASK(0, 16)
#define TATSU_TSR0_QNT_SHIFT                  0
#define TATSU_TSR0_QNT_W(value)               WBGEN2_GEN_WRITE(value, 0, 16)
#define TATSU_TSR0_QNT_R(reg)                 WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Window Priorit Mask in reg: TATSU Settings Register 0 */
#define TATSU_TSR0_PRIO_MASK                  WBGEN2_GEN_MASK(16, 8)
#define TATSU_TSR0_PRIO_SHIFT                 16
#define TATSU_TSR0_PRIO_W(value)              WBGEN2_GEN_WRITE(value, 16, 8)
#define TATSU_TSR0_PRIO_R(reg)                WBGEN2_GEN_READ(reg, 16, 8)

/* definitions for field: Start time (hi_TAI) in reg: TATSU Settings Register 0 */
#define TATSU_TSR0_HTAI_MASK                  WBGEN2_GEN_MASK(24, 8)
#define TATSU_TSR0_HTAI_SHIFT                 24
#define TATSU_TSR0_HTAI_W(value)              WBGEN2_GEN_WRITE(value, 24, 8)
#define TATSU_TSR0_HTAI_R(reg)                WBGEN2_GEN_READ(reg, 24, 8)

/* definitions for register: TATSU Settings Register 1 */

/* definitions for field: Start time (lo_TAI) in reg: TATSU Settings Register 1 */
#define TATSU_TSR1_LTAI_MASK                  WBGEN2_GEN_MASK(0, 32)
#define TATSU_TSR1_LTAI_SHIFT                 0
#define TATSU_TSR1_LTAI_W(value)              WBGEN2_GEN_WRITE(value, 0, 32)
#define TATSU_TSR1_LTAI_R(reg)                WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TATSU Settings Register 2 */

/* definitions for field: Start time (cycles) in reg: TATSU Settings Register 2 */
#define TATSU_TSR2_CYC_MASK                   WBGEN2_GEN_MASK(0, 28)
#define TATSU_TSR2_CYC_SHIFT                  0
#define TATSU_TSR2_CYC_W(value)               WBGEN2_GEN_WRITE(value, 0, 28)
#define TATSU_TSR2_CYC_R(reg)                 WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for register: TATSU Settings Register 3 */

/* definitions for field: Repeat time (cycle) in reg: TATSU Settings Register 3 */
#define TATSU_TSR3_CYC_MASK                   WBGEN2_GEN_MASK(0, 28)
#define TATSU_TSR3_CYC_SHIFT                  0
#define TATSU_TSR3_CYC_W(value)               WBGEN2_GEN_WRITE(value, 0, 28)
#define TATSU_TSR3_CYC_R(reg)                 WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for register: TATSU Settings Register 4 */

/* definitions for field: Ports mask in reg: TATSU Settings Register 4 */
#define TATSU_TSR4_PORTS_MASK                 WBGEN2_GEN_MASK(0, 32)
#define TATSU_TSR4_PORTS_SHIFT                0
#define TATSU_TSR4_PORTS_W(value)             WBGEN2_GEN_WRITE(value, 0, 32)
#define TATSU_TSR4_PORTS_R(reg)               WBGEN2_GEN_READ(reg, 0, 32)

PACKED struct TATSU_WB {
  /* [0x0]: REG TATSU Control Register/Status */
  uint32_t TCR;
  /* [0x4]: REG TATSU Settings Register 0 */
  uint32_t TSR0;
  /* [0x8]: REG TATSU Settings Register 1 */
  uint32_t TSR1;
  /* [0xc]: REG TATSU Settings Register 2 */
  uint32_t TSR2;
  /* [0x10]: REG TATSU Settings Register 3 */
  uint32_t TSR3;
  /* [0x14]: REG TATSU Settings Register 4 */
  uint32_t TSR4;
};

#endif
