/*
  Register definitions for slave core: Simple Pulse Width Modulation Controller

  * File           : spwm-regs.h
  * Author         : auto-generated by wbgen2 from simple_pwm_wb.wb
  * Created        : Mon Jan 21 14:31:18 2013
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE simple_pwm_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_SIMPLE_PWM_WB_WB
#define __WBGEN2_REGDEFS_SIMPLE_PWM_WB_WB

#include <inttypes.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Control Register */

/* definitions for field: Prescaler Ratio in reg: Control Register */
#define SPWM_CR_PRESC_MASK                    WBGEN2_GEN_MASK(0, 16)
#define SPWM_CR_PRESC_SHIFT                   0
#define SPWM_CR_PRESC_W(value)                WBGEN2_GEN_WRITE(value, 0, 16)
#define SPWM_CR_PRESC_R(reg)                  WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Period in reg: Control Register */
#define SPWM_CR_PERIOD_MASK                   WBGEN2_GEN_MASK(16, 16)
#define SPWM_CR_PERIOD_SHIFT                  16
#define SPWM_CR_PERIOD_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define SPWM_CR_PERIOD_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: Status Register */

/* definitions for field: Channel count in reg: Status Register */
#define SPWM_SR_N_CHANNELS_MASK               WBGEN2_GEN_MASK(0, 4)
#define SPWM_SR_N_CHANNELS_SHIFT              0
#define SPWM_SR_N_CHANNELS_W(value)           WBGEN2_GEN_WRITE(value, 0, 4)
#define SPWM_SR_N_CHANNELS_R(reg)             WBGEN2_GEN_READ(reg, 0, 4)

/* definitions for register: Channel 0 Drive Register */

/* definitions for register: Channel 1 Drive Register */

/* definitions for register: Channel 2 Drive Register */

/* definitions for register: Channel 3 Drive Register */

/* definitions for register: Channel 4 Drive Register */

/* definitions for register: Channel 5 Drive Register */

/* definitions for register: Channel 6 Drive Register */

/* definitions for register: Channel 7 Drive Register */

PACKED struct SPWM_WB {
  /* [0x0]: REG Control Register */
  uint32_t CR;
  /* [0x4]: REG Status Register */
  uint32_t SR;
  /* [0x8]: REG Channel 0 Drive Register */
  uint32_t DR0;
  /* [0xc]: REG Channel 1 Drive Register */
  uint32_t DR1;
  /* [0x10]: REG Channel 2 Drive Register */
  uint32_t DR2;
  /* [0x14]: REG Channel 3 Drive Register */
  uint32_t DR3;
  /* [0x18]: REG Channel 4 Drive Register */
  uint32_t DR4;
  /* [0x1c]: REG Channel 5 Drive Register */
  uint32_t DR5;
  /* [0x20]: REG Channel 6 Drive Register */
  uint32_t DR6;
  /* [0x24]: REG Channel 7 Drive Register */
  uint32_t DR7;
};

#endif
