/*
  Register definitions for slave core: WR Switch aux clock generation module

  * File           : gen10mhz-regs.h
  * Author         : auto-generated by wbgen2 from gen10mhz-regs.wb
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE gen10mhz-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_GEN10MHZ
#define __WBGEN2_REGDEFS_GEN10MHZ

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif


#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Period Register */

/* definitions for field: Half period width in reg: Period Register */
#define GEN10_PR_HP_WIDTH_MASK                WBGEN2_GEN_MASK(0, 16)
#define GEN10_PR_HP_WIDTH_SHIFT               0
#define GEN10_PR_HP_WIDTH_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define GEN10_PR_HP_WIDTH_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for register: Duty Cycle Register */

/* definitions for field: Low state width in reg: Duty Cycle Register */
#define GEN10_DCR_LOW_WIDTH_MASK              WBGEN2_GEN_MASK(0, 16)
#define GEN10_DCR_LOW_WIDTH_SHIFT             0
#define GEN10_DCR_LOW_WIDTH_W(value)          WBGEN2_GEN_WRITE(value, 0, 16)
#define GEN10_DCR_LOW_WIDTH_R(reg)            WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for register: Coarse Shift Register */

/* definitions for register: IODelay Register */

/* definitions for field: Required delay value in reg: IODelay Register */
#define GEN10_IOR_TAP_SET_MASK                WBGEN2_GEN_MASK(0, 5)
#define GEN10_IOR_TAP_SET_SHIFT               0
#define GEN10_IOR_TAP_SET_W(value)            WBGEN2_GEN_WRITE(value, 0, 5)
#define GEN10_IOR_TAP_SET_R(reg)              WBGEN2_GEN_READ(reg, 0, 5)

/* definitions for field: Current delay value read from IODelay in reg: IODelay Register */
#define GEN10_IOR_TAP_CUR_MASK                WBGEN2_GEN_MASK(8, 5)
#define GEN10_IOR_TAP_CUR_SHIFT               8
#define GEN10_IOR_TAP_CUR_W(value)            WBGEN2_GEN_WRITE(value, 8, 5)
#define GEN10_IOR_TAP_CUR_R(reg)              WBGEN2_GEN_READ(reg, 8, 5)

/* definitions for field: IOdelay locked in reg: IODelay Register */
#define GEN10_IOR_LCK                         WBGEN2_GEN_MASK(31, 1)

/* definitions for register: PPS IODelay Register */

/* definitions for field: Required delay value in reg: PPS IODelay Register */
#define GEN10_PPS_IOR_TAP_SET_MASK            WBGEN2_GEN_MASK(0, 5)
#define GEN10_PPS_IOR_TAP_SET_SHIFT           0
#define GEN10_PPS_IOR_TAP_SET_W(value)        WBGEN2_GEN_WRITE(value, 0, 5)
#define GEN10_PPS_IOR_TAP_SET_R(reg)          WBGEN2_GEN_READ(reg, 0, 5)

/* definitions for field: Current delay value read from IODelay in reg: PPS IODelay Register */
#define GEN10_PPS_IOR_TAP_CUR_MASK            WBGEN2_GEN_MASK(8, 5)
#define GEN10_PPS_IOR_TAP_CUR_SHIFT           8
#define GEN10_PPS_IOR_TAP_CUR_W(value)        WBGEN2_GEN_WRITE(value, 8, 5)
#define GEN10_PPS_IOR_TAP_CUR_R(reg)          WBGEN2_GEN_READ(reg, 8, 5)

PACKED struct GEN10_WB {
  /* [0x0]: REG Period Register */
  uint32_t PR;
  /* [0x4]: REG Duty Cycle Register */
  uint32_t DCR;
  /* [0x8]: REG Coarse Shift Register */
  uint32_t CSR;
  /* [0xc]: REG IODelay Register */
  uint32_t IOR;
  /* [0x10]: REG PPS IODelay Register */
  uint32_t PPS_IOR;
};

#endif
