/*
  Register definitions for slave core: White Rabbit Switch NIC's spec

  * File           : nic-regs.h
  * Author         : auto-generated by wbgen2 from nic-regs.wb
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE nic-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_NIC
#define __WBGEN2_REGDEFS_NIC

#include <linux/types.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: NIC Control Register */

/* definitions for field: Receive enable in reg: NIC Control Register */
#define NIC_CR_RX_EN                          WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Transmit enable in reg: NIC Control Register */
#define NIC_CR_TX_EN                          WBGEN2_GEN_MASK(1, 1)

/* definitions for register: NIC Status Register */

/* definitions for field: Buffer Not Available in reg: NIC Status Register */
#define NIC_SR_BNA                            WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Frame Received in reg: NIC Status Register */
#define NIC_SR_REC                            WBGEN2_GEN_MASK(1, 1)

/* definitions for register: SW_Reset */

/* definitions for register: TX Descriptor 1 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D1_TS_ID_SHIFT                16
#define NIC_TX1_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX1_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 1 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX1_D2_OFFSET_SHIFT               0
#define NIC_TX1_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX1_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D2_LEN_SHIFT                  16
#define NIC_TX1_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX1_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 1 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 1 register 3 */
#define NIC_TX1_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX1_D3_DPM_SHIFT                  0
#define NIC_TX1_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX1_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 2 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D1_TS_ID_SHIFT                16
#define NIC_TX2_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 2 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX2_D2_OFFSET_SHIFT               0
#define NIC_TX2_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX2_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D2_LEN_SHIFT                  16
#define NIC_TX2_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 2 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 2 register 3 */
#define NIC_TX2_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX2_D3_DPM_SHIFT                  0
#define NIC_TX2_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX2_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 3 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D1_TS_ID_SHIFT                16
#define NIC_TX3_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 3 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX3_D2_OFFSET_SHIFT               0
#define NIC_TX3_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX3_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D2_LEN_SHIFT                  16
#define NIC_TX3_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 3 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 3 register 3 */
#define NIC_TX3_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX3_D3_DPM_SHIFT                  0
#define NIC_TX3_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX3_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 4 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D1_TS_ID_SHIFT                16
#define NIC_TX4_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 4 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX4_D2_OFFSET_SHIFT               0
#define NIC_TX4_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX4_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D2_LEN_SHIFT                  16
#define NIC_TX4_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 4 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 4 register 3 */
#define NIC_TX4_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX4_D3_DPM_SHIFT                  0
#define NIC_TX4_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX4_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 5 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D1_TS_ID_SHIFT                16
#define NIC_TX5_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 5 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX5_D2_OFFSET_SHIFT               0
#define NIC_TX5_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX5_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D2_LEN_SHIFT                  16
#define NIC_TX5_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 5 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 5 register 3 */
#define NIC_TX5_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX5_D3_DPM_SHIFT                  0
#define NIC_TX5_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX5_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 6 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D1_TS_ID_SHIFT                16
#define NIC_TX6_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 6 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX6_D2_OFFSET_SHIFT               0
#define NIC_TX6_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX6_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D2_LEN_SHIFT                  16
#define NIC_TX6_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 6 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 6 register 3 */
#define NIC_TX6_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX6_D3_DPM_SHIFT                  0
#define NIC_TX6_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX6_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 7 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D1_TS_ID_SHIFT                16
#define NIC_TX7_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 7 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX7_D2_OFFSET_SHIFT               0
#define NIC_TX7_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX7_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D2_LEN_SHIFT                  16
#define NIC_TX7_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 7 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 7 register 3 */
#define NIC_TX7_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX7_D3_DPM_SHIFT                  0
#define NIC_TX7_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX7_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: TX Descriptor 8 register 1 */

/* definitions for field: Ready in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_READY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timestamp Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_E                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Pad Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_PAD_E                      WBGEN2_GEN_MASK(3, 1)

/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_ID_MASK                 WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D1_TS_ID_SHIFT                16
#define NIC_TX8_D1_TS_ID_W(value)             WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D1_TS_ID_R(reg)               WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 8 register 2 */

/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_TX8_D2_OFFSET_SHIFT               0
#define NIC_TX8_D2_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX8_D2_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D2_LEN_SHIFT                  16
#define NIC_TX8_D2_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D2_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: TX Descriptor 8 register 3 */

/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc.  0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 8 register 3 */
#define NIC_TX8_D3_DPM_MASK                   WBGEN2_GEN_MASK(0, 32)
#define NIC_TX8_D3_DPM_SHIFT                  0
#define NIC_TX8_D3_DPM_W(value)               WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX8_D3_DPM_R(reg)                 WBGEN2_GEN_READ(reg, 0, 32)

/* definitions for register: RX Descriptor 1 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX1_D1_PORT_SHIFT                 8
#define NIC_RX1_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX1_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 1 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 1 register 2 */
#define NIC_RX1_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX1_D2_TS_R_SHIFT                 0
#define NIC_RX1_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX1_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 1 register 2 */
#define NIC_RX1_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX1_D2_TS_F_SHIFT                 28
#define NIC_RX1_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX1_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 1 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 1 register 3 */
#define NIC_RX1_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX1_D3_OFFSET_SHIFT               0
#define NIC_RX1_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX1_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 1 register 3 */
#define NIC_RX1_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX1_D3_LEN_SHIFT                  16
#define NIC_RX1_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX1_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 2 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX2_D1_PORT_SHIFT                 8
#define NIC_RX2_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX2_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 2 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX2_D2_TS_R_SHIFT                 0
#define NIC_RX2_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX2_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX2_D2_TS_F_SHIFT                 28
#define NIC_RX2_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX2_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 2 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX2_D3_OFFSET_SHIFT               0
#define NIC_RX2_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX2_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX2_D3_LEN_SHIFT                  16
#define NIC_RX2_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX2_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 3 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX3_D1_PORT_SHIFT                 8
#define NIC_RX3_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX3_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 3 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX3_D2_TS_R_SHIFT                 0
#define NIC_RX3_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX3_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX3_D2_TS_F_SHIFT                 28
#define NIC_RX3_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX3_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 3 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX3_D3_OFFSET_SHIFT               0
#define NIC_RX3_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX3_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX3_D3_LEN_SHIFT                  16
#define NIC_RX3_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX3_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 4 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX4_D1_PORT_SHIFT                 8
#define NIC_RX4_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX4_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 4 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX4_D2_TS_R_SHIFT                 0
#define NIC_RX4_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX4_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX4_D2_TS_F_SHIFT                 28
#define NIC_RX4_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX4_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 4 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX4_D3_OFFSET_SHIFT               0
#define NIC_RX4_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX4_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX4_D3_LEN_SHIFT                  16
#define NIC_RX4_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX4_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 5 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX5_D1_PORT_SHIFT                 8
#define NIC_RX5_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX5_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 5 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX5_D2_TS_R_SHIFT                 0
#define NIC_RX5_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX5_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX5_D2_TS_F_SHIFT                 28
#define NIC_RX5_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX5_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 5 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX5_D3_OFFSET_SHIFT               0
#define NIC_RX5_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX5_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX5_D3_LEN_SHIFT                  16
#define NIC_RX5_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX5_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 6 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX6_D1_PORT_SHIFT                 8
#define NIC_RX6_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX6_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 6 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX6_D2_TS_R_SHIFT                 0
#define NIC_RX6_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX6_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX6_D2_TS_F_SHIFT                 28
#define NIC_RX6_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX6_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 6 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX6_D3_OFFSET_SHIFT               0
#define NIC_RX6_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX6_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX6_D3_LEN_SHIFT                  16
#define NIC_RX6_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX6_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 7 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX7_D1_PORT_SHIFT                 8
#define NIC_RX7_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX7_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 7 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX7_D2_TS_R_SHIFT                 0
#define NIC_RX7_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX7_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX7_D2_TS_F_SHIFT                 28
#define NIC_RX7_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX7_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 7 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX7_D3_OFFSET_SHIFT               0
#define NIC_RX7_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX7_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX7_D3_LEN_SHIFT                  16
#define NIC_RX7_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX7_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: RX Descriptor 8 register 1 */

/* definitions for field: Empty in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_EMPTY                      WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Error in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_ERROR                      WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_PORT_MASK                  WBGEN2_GEN_MASK(8, 6)
#define NIC_RX8_D1_PORT_SHIFT                 8
#define NIC_RX8_D1_PORT_W(value)              WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX8_D1_PORT_R(reg)                WBGEN2_GEN_READ(reg, 8, 6)

/* definitions for field: Got RX Timestamp in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_GOT_TS                     WBGEN2_GEN_MASK(14, 1)

/* definitions for register: RX Descriptor 8 register 2 */

/* definitions for field: RX_TS_R in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_R_MASK                  WBGEN2_GEN_MASK(0, 28)
#define NIC_RX8_D2_TS_R_SHIFT                 0
#define NIC_RX8_D2_TS_R_W(value)              WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX8_D2_TS_R_R(reg)                WBGEN2_GEN_READ(reg, 0, 28)

/* definitions for field: RX_TS_F in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_F_MASK                  WBGEN2_GEN_MASK(28, 4)
#define NIC_RX8_D2_TS_F_SHIFT                 28
#define NIC_RX8_D2_TS_F_W(value)              WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX8_D2_TS_F_R(reg)                WBGEN2_GEN_READ(reg, 28, 4)

/* definitions for register: RX Descriptor 8 register 3 */

/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_OFFSET_MASK                WBGEN2_GEN_MASK(0, 16)
#define NIC_RX8_D3_OFFSET_SHIFT               0
#define NIC_RX8_D3_OFFSET_W(value)            WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX8_D3_OFFSET_R(reg)              WBGEN2_GEN_READ(reg, 0, 16)

/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_LEN_MASK                   WBGEN2_GEN_MASK(16, 16)
#define NIC_RX8_D3_LEN_SHIFT                  16
#define NIC_RX8_D3_LEN_W(value)               WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX8_D3_LEN_R(reg)                 WBGEN2_GEN_READ(reg, 16, 16)

/* definitions for register: Interrupt disable register */

/* definitions for field: Receive Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_RCOMP                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Transmit Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_TCOMP                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Receive Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_RXERR                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Transmit Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_TXERR                     WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Interrupt enable register */

/* definitions for field: Receive Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_RCOMP                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Transmit Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_TCOMP                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Receive Error in reg: Interrupt enable register */
#define NIC_EIC_IER_RXERR                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Transmit Error in reg: Interrupt enable register */
#define NIC_EIC_IER_TXERR                     WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Interrupt mask register */

/* definitions for field: Receive Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_RCOMP                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Transmit Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_TCOMP                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Receive Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_RXERR                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Transmit Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_TXERR                     WBGEN2_GEN_MASK(3, 1)

/* definitions for register: Interrupt status register */

/* definitions for field: Receive Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_RCOMP                     WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Transmit Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_TCOMP                     WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Receive Error in reg: Interrupt status register */
#define NIC_EIC_ISR_RXERR                     WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Transmit Error in reg: Interrupt status register */
#define NIC_EIC_ISR_TXERR                     WBGEN2_GEN_MASK(3, 1)
/* definitions for RAM: TX/RX Buffers */
#define NIC_MEM_BYTES 0x00008000 /* size in bytes */                               
#define NIC_MEM_WORDS 0x00002000 /* size in 32-bit words, 32-bit aligned */        

PACKED struct NIC_WB {
  /* [0x0]: REG NIC Control Register */
  uint32_t CR;
  /* [0x4]: REG NIC Status Register */
  uint32_t SR;
  /* [0x8]: REG SW_Reset */
  uint32_t RESET;
  /* padding to: 4 words */
  uint32_t __padding_0[1];
  /* [0x10]: REG TX Descriptor 1 register 1 */
  uint32_t TX1_D1;
  /* [0x14]: REG TX Descriptor 1 register 2 */
  uint32_t TX1_D2;
  /* [0x18]: REG TX Descriptor 1 register 3 */
  uint32_t TX1_D3;
  /* padding to: 8 words */
  uint32_t __padding_1[1];
  /* [0x20]: REG TX Descriptor 2 register 1 */
  uint32_t TX2_D1;
  /* [0x24]: REG TX Descriptor 2 register 2 */
  uint32_t TX2_D2;
  /* [0x28]: REG TX Descriptor 2 register 3 */
  uint32_t TX2_D3;
  /* padding to: 12 words */
  uint32_t __padding_2[1];
  /* [0x30]: REG TX Descriptor 3 register 1 */
  uint32_t TX3_D1;
  /* [0x34]: REG TX Descriptor 3 register 2 */
  uint32_t TX3_D2;
  /* [0x38]: REG TX Descriptor 3 register 3 */
  uint32_t TX3_D3;
  /* padding to: 16 words */
  uint32_t __padding_3[1];
  /* [0x40]: REG TX Descriptor 4 register 1 */
  uint32_t TX4_D1;
  /* [0x44]: REG TX Descriptor 4 register 2 */
  uint32_t TX4_D2;
  /* [0x48]: REG TX Descriptor 4 register 3 */
  uint32_t TX4_D3;
  /* padding to: 20 words */
  uint32_t __padding_4[1];
  /* [0x50]: REG TX Descriptor 5 register 1 */
  uint32_t TX5_D1;
  /* [0x54]: REG TX Descriptor 5 register 2 */
  uint32_t TX5_D2;
  /* [0x58]: REG TX Descriptor 5 register 3 */
  uint32_t TX5_D3;
  /* padding to: 24 words */
  uint32_t __padding_5[1];
  /* [0x60]: REG TX Descriptor 6 register 1 */
  uint32_t TX6_D1;
  /* [0x64]: REG TX Descriptor 6 register 2 */
  uint32_t TX6_D2;
  /* [0x68]: REG TX Descriptor 6 register 3 */
  uint32_t TX6_D3;
  /* padding to: 28 words */
  uint32_t __padding_6[1];
  /* [0x70]: REG TX Descriptor 7 register 1 */
  uint32_t TX7_D1;
  /* [0x74]: REG TX Descriptor 7 register 2 */
  uint32_t TX7_D2;
  /* [0x78]: REG TX Descriptor 7 register 3 */
  uint32_t TX7_D3;
  /* padding to: 32 words */
  uint32_t __padding_7[1];
  /* [0x80]: REG TX Descriptor 8 register 1 */
  uint32_t TX8_D1;
  /* [0x84]: REG TX Descriptor 8 register 2 */
  uint32_t TX8_D2;
  /* [0x88]: REG TX Descriptor 8 register 3 */
  uint32_t TX8_D3;
  /* padding to: 36 words */
  uint32_t __padding_8[1];
  /* [0x90]: REG RX Descriptor 1 register 1 */
  uint32_t RX1_D1;
  /* [0x94]: REG RX Descriptor 1 register 2 */
  uint32_t RX1_D2;
  /* [0x98]: REG RX Descriptor 1 register 3 */
  uint32_t RX1_D3;
  /* padding to: 40 words */
  uint32_t __padding_9[1];
  /* [0xa0]: REG RX Descriptor 2 register 1 */
  uint32_t RX2_D1;
  /* [0xa4]: REG RX Descriptor 2 register 2 */
  uint32_t RX2_D2;
  /* [0xa8]: REG RX Descriptor 2 register 3 */
  uint32_t RX2_D3;
  /* padding to: 44 words */
  uint32_t __padding_10[1];
  /* [0xb0]: REG RX Descriptor 3 register 1 */
  uint32_t RX3_D1;
  /* [0xb4]: REG RX Descriptor 3 register 2 */
  uint32_t RX3_D2;
  /* [0xb8]: REG RX Descriptor 3 register 3 */
  uint32_t RX3_D3;
  /* padding to: 48 words */
  uint32_t __padding_11[1];
  /* [0xc0]: REG RX Descriptor 4 register 1 */
  uint32_t RX4_D1;
  /* [0xc4]: REG RX Descriptor 4 register 2 */
  uint32_t RX4_D2;
  /* [0xc8]: REG RX Descriptor 4 register 3 */
  uint32_t RX4_D3;
  /* padding to: 52 words */
  uint32_t __padding_12[1];
  /* [0xd0]: REG RX Descriptor 5 register 1 */
  uint32_t RX5_D1;
  /* [0xd4]: REG RX Descriptor 5 register 2 */
  uint32_t RX5_D2;
  /* [0xd8]: REG RX Descriptor 5 register 3 */
  uint32_t RX5_D3;
  /* padding to: 56 words */
  uint32_t __padding_13[1];
  /* [0xe0]: REG RX Descriptor 6 register 1 */
  uint32_t RX6_D1;
  /* [0xe4]: REG RX Descriptor 6 register 2 */
  uint32_t RX6_D2;
  /* [0xe8]: REG RX Descriptor 6 register 3 */
  uint32_t RX6_D3;
  /* padding to: 60 words */
  uint32_t __padding_14[1];
  /* [0xf0]: REG RX Descriptor 7 register 1 */
  uint32_t RX7_D1;
  /* [0xf4]: REG RX Descriptor 7 register 2 */
  uint32_t RX7_D2;
  /* [0xf8]: REG RX Descriptor 7 register 3 */
  uint32_t RX7_D3;
  /* padding to: 64 words */
  uint32_t __padding_15[1];
  /* [0x100]: REG RX Descriptor 8 register 1 */
  uint32_t RX8_D1;
  /* [0x104]: REG RX Descriptor 8 register 2 */
  uint32_t RX8_D2;
  /* [0x108]: REG RX Descriptor 8 register 3 */
  uint32_t RX8_D3;
  /* padding to: 72 words */
  uint32_t __padding_16[5];
  /* [0x120]: REG Interrupt disable register */
  uint32_t EIC_IDR;
  /* [0x124]: REG Interrupt enable register */
  uint32_t EIC_IER;
  /* [0x128]: REG Interrupt mask register */
  uint32_t EIC_IMR;
  /* [0x12c]: REG Interrupt status register */
  uint32_t EIC_ISR;
  /* padding to: 8192 words */
  uint32_t __padding_17[8116];
  /* [0x8000 - 0xffff]: RAM TX/RX Buffers, 8192 32-bit words, 32-bit aligned, word-addressable */
  uint32_t MEM [8192];
};

#endif
