/*
  Register definitions for slave core: WR Switch PPS generator and RTC

  * File           : pps_gen_regs.h
  * Author         : auto-generated by wbgen2 from pps_gen_wb.wb
  * Created        : Mon Apr 23 22:33:01 2012
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pps_gen_wb.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

*/

#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB

#include <stdint.h>

#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif

#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif


/* definitions for register: Control Register */

/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST                       WBGEN2_GEN_MASK(0, 1)

/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN                        WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ                       WBGEN2_GEN_MASK(2, 1)

/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET                       WBGEN2_GEN_MASK(3, 1)

/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK                   WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT                  4
#define PPSG_CR_PWIDTH_W(value)               WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg)                 WBGEN2_GEN_READ(reg, 4, 28)

/* definitions for register: Nanosecond counter register */

/* definitions for register: SEC Counter register (least-significant part) */

/* definitions for register: SEC Counter register (most-significant part) */

/* definitions for register: Nanosecond adjustment register */

/* definitions for register: SEC Adjustment register (least-significant part) */

/* definitions for register: SEC Adjustment register (most-significant part) */

/* definitions for register: External sync control register */

/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC                        WBGEN2_GEN_MASK(0, 1)

/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID                   WBGEN2_GEN_MASK(1, 1)

/* definitions for field: Timecode output(SEC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID                    WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
#define PPSG_REG_CNTR_NSEC 0x00000004
/* [0x8]: REG SEC Counter register (least-significant part) */
#define PPSG_REG_CNTR_SECLO 0x00000008
/* [0xc]: REG SEC Counter register (most-significant part) */
#define PPSG_REG_CNTR_SECHI 0x0000000c
/* [0x10]: REG Nanosecond adjustment register */
#define PPSG_REG_ADJ_NSEC 0x00000010
/* [0x14]: REG SEC Adjustment register (least-significant part) */
#define PPSG_REG_ADJ_SECLO 0x00000014
/* [0x18]: REG SEC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_SECHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
#endif
