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Last edited by Erik van der Bij
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White Rabbit Switch Hardware

Project description

White Rabbit Switch is an open hardware design of an 18-ports Ethernet switch licensed under CERN OHL 1.2. It is a central element of a White Rabbit network and was designed as a part of the White Rabbit project.
The WR Switch can be used with official firmware releases. As the design is open it can also be used as the hardware platform for other, non-White Rabbit projects.


Figure 1: WR Switch v3.4


Figure 2: WR Switch v3.4: Front view, FMC connectors


Figure 3: WR Switch v3.3 back view

WR Switch hardware consists of three elements:

  • WR Switch Box (fig. 1) - is a white metal 19'' 1U case with two cooling fans in the back
  • main PCB (fig. 4) - contains main electronics components, ARM processor, Xilinx FPGA chip, oscillators, memories, etc.
  • backplane PCB (fig. 4) - electrical connections to 18 SFP cages, debug USB-uart ports, LEDs, etc.


Figure 4: WR Switch v3.3 top view of PCBs

Main Features

  • Front Panel
    • 5 SMC connectors
      • 1-PPS input and output
      • 62.5 MHz output
      • 10 MHz output (software configurable)
      • 10 MHz input
    • 18 cages for Gigabit SFP transceivers (connected to Xilinx GTXs)
    • 10/100 Ethernet management port (connected to ARM CPU)
    • USB-uart management port (connected to ARM CPU)
    • Power and Status LEDs
    • Link and Act LEDs for each SFP cage
  • Back Panel
    • 2x USB-uart debugging port (connected to ARM CPU and FPGA I/O pins)
    • power button
    • 2x cooling fan
    • 2x microswitch
    • 1x grounding connector
  • Xilinx Virtex-6 FPGA (XC6VLX240T-1FFG1156C)
  • Clocking resources
    • 1x Low-Jitter Clock Generator (TI CDCM61002, used as DMTD offset clock in WR Switch HDL)
    • 1x 25MHz VCXO, FRETHE025 controlled by DAC with SPI interface (AD5662, used to drive CDCM61002 generator)
    • 1x 25MHz VCO controlled by DAC with SPI interface (AD5662, used to drive AD9516 generator)
    • 1x 25MHz XO oscillator FNETHE025 (main FPGA clock)
    • 14-Output Clock Generator with Integrated 1.6 GHz VCO (AD9516, clock signals for Xilinx GTXs, uTCA connectors)
    • 1x Internal Oscillator (VM53S3-25.000, tuned to follow WR master clock or followed in Free Running mode)
  • ARM Atmel AT91 SAM9G45 CPU
  • Memory:
    • 64MB DDR2
    • 256MB NAND
    • 8MB boot flash
  • Others:
    • 1x FPGA JTAG connector
    • 1x ARM JTAG connector
    • 2x I2C multiplexer (PCA9548A)
    • 1x I2C GPIO driver (PCA9554PW, driving Power and Status LEDs on the front panel)
    • 9x I2C GPIO driver (PCA9554PW, driving LEDs for each SFP cage)
  • Power supply 100-240VAC, 2.0A, 50-60Hz input, 12V DC, 6.66A, 80W output
  • Box dimensions 482.8 x 42.34 x 222 mm
  • Certification
    • IPC-610 Rev E Class 2
    • ISO-9001
    • ISO-14001
    • CE
    • RoHS

Project information

Releases

Contacts

Commercial producers

General question about project

Status

Date Event
31-03-2009 Review of Switch MCH card v1
01-04-2010 Switch MCH card v2 PCB ready
05-03-2012 CERN received 4 WR v3 switches
24-01-2013 White Rabbit switch V3.3 passes all CE marking tests (power, electrical safety, labels, EMI)
21-02-2013 GSI, Germany received the first production batch of v3.3 switches
25-04-2013 CERN, Switzerland received 10 v3.3 switches
15-05-2013 CERN installs one v3.3 WR Switch for CLIC Test Facility (CTF3)
25-04-2014 CERN received 4 WR v3.3 switches and will receive soon another four.
25-09-2014 Hardware release v3.4 with two programmable clock outputs is out
01-07-2015 Switch available from two different manufacturers.
13-12-2017 In total over 500 switches produced since start of project.
29-01-2020 Estimated over 1200 switches produced since start of project.
see also White Rabbit Applications and Enhancements

Grzegorz Daniluk, Erik van der Bij - 29 January 2020

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