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White Rabbit Switch - Hardware
Commit feb440ba authored by Benoit Rat's avatar Benoit Rat
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misc: clean-up old and unused files

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circuit_board/miniBackplane_v3/Connector_GTX.Harness deleted 100644 → 0
View file @ ce4bb7e7
WR_LINK_GTX=WR_LINK_RD_OUT_P,WR_LINK_RD_OUT_N,WR_LINK_TD_IN_P,WR_LINK_TD_IN_N
circuit_board/miniBackplane_v3/Connectors.Harness deleted 100644 → 0
View file @ ce4bb7e7
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_N,MGTTX112_0_P,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
circuit_board/miniBackplane_v3/Connectors_GPIOs.Harness deleted 100644 → 0
View file @ ce4bb7e7
I2C_GPIO=I2C_GPIO_INT2,I2C_GPIO_INT1,I2C_GPIO_INT0,I2C_SCL,I2C_SDA
I2C_WRL_IO=I2C_RESETZ,I2C_DL_SDA,I2C_DL_SCL,I2C_UL_IO_SCL,I2C_UL_IO_SDA
circuit_board/miniBackplane_v3/I2C_GPIO_Expansion.Harness deleted 100644 → 0
View file @ ce4bb7e7
I2C_GPIO=I2C_SDA,I2C_SCL,I2C_GPIO_INT0,I2C_GPIO_INT1,I2C_GPIO_INT2
circuit_board/miniBackplane_v3/I2C_Multiplexers.Harness deleted 100644 → 0
View file @ ce4bb7e7
I2C_WRL_IO=I2C_UL_IO_SDA,I2C_UL_IO_SCL,I2C_DL_SCL,I2C_DL_SDA,I2C_RESETZ
circuit_board/miniBackplane_v3/PHY.Harness deleted 100644 → 0
View file @ ce4bb7e7
PHY_Control=PHY_TX_DISABLE,PHY_LOS,PHY_RESET,PHY_MODDEF0,PHY_MODDEF1,PHY_MODDEF2
PHY_GTX=PHY_TD_IN_P,PHY_TD_IN_N,PHY_RD_OUT_P,PHY_RD_OUT_N
circuit_board/miniBackplane_v3/SFP.Harness deleted 100644 → 0
View file @ ce4bb7e7
SFP_Control=SFP_TX_DISABLE,SFP_LOS,SFP_DETECT,SFP_SCL,SFP_SDA,SFP_TX_FAULT
SFP_GTX=SFP_TD_IN_N,SFP_TD_IN_P,SFP_RD_OUT_N,SFP_RD_OUT_P
circuit_board/miniBackplane_v3/WR_LINK.Harness deleted 100644 → 0
View file @ ce4bb7e7
SFP_Control=SFP_TX_FAULT,SFP_SDA,SFP_SCL,SFP_DETECT,SFP_LOS,SFP_TX_DISABLE
SFP_GTX=SFP_RD_OUT_P,SFP_RD_OUT_N,SFP_TD_IN_P,SFP_TD_IN_N
WR_LINK_GTX=WR_LINK_TD_IN_N,WR_LINK_TD_IN_P,WR_LINK_RD_OUT_N,WR_LINK_RD_OUT_P
circuit_board/miniBackplane_v3/miniBackplane.PrjPCB deleted 100644 → 0
View file @ ce4bb7e7
This diff is collapsed.
circuit_board/wrs_v3/SCB/CPU_100M_Ethernet.Harness deleted 100644 → 0
View file @ ce4bb7e7
ETH_100MHz=SHIELD,TX_P,TX_N,RX_P,RX_N,LED_LINK,LED_ACT
circuit_board/wrs_v3/SCB/CPU_IO_Ports.Harness deleted 100644 → 0
View file @ ce4bb7e7
CPU_SSC=RF1,RK1,RD1,TD1,TK1,TF1
SPI0=SPI0_MISO,SPI0_MOSI,SPI0_SPCK,SPI0_NPCS0
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
circuit_board/wrs_v3/SCB/CPU_JTAG_Power_PLL.Harness deleted 100644 → 0
View file @ ce4bb7e7
CPU_JTAG=JNRST,JTDO,JRTCK,JTCK,JTMS,JTDI,JNTRST
circuit_board/wrs_v3/SCB/CPU_Memory.Harness deleted 100644 → 0
View file @ ce4bb7e7
SPI0=SPI0_NPCS0,SPI0_SPCK,SPI0_MOSI,SPI0_MISO
circuit_board/wrs_v3/SCB/Connectors.Harness deleted 100644 → 0
View file @ ce4bb7e7
CPU_JTAG=JNTRST,JTDI,JTMS,JTCK,JRTCK,JTDO,JNRST
CPU_SSC=TF1,TK1,TD1,RD1,RK1,RF1
ETH_100MHz=LED_ACT,LED_LINK,RX_N,RX_P,TX_N,TX_P,SHIELD
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_P,MGTTX112_0_N,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N
circuit_board/wrs_v3/SCB/External WatchDogs.Harness deleted 100644 → 0
View file @ ce4bb7e7
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
circuit_board/wrs_v3/SCB/FPGA_CLKs.Harness deleted 100644 → 0
View file @ ce4bb7e7
DAC_CONTROL=DAC_REF_SCLK,DAC_REF_SYNC,DAC_REF_DIN,DAC_DMTD_SCLK,DAC_DMTD_SYNC,DAC_DMTD_DIN
circuit_board/wrs_v3/SCB/FPGA_Configuration.Harness deleted 100644 → 0
View file @ ce4bb7e7
FPGA_JTAG=FPGA_TMS,FPGA_TCK,FPGA_TDI,FPGA_TDO
FPGA_WD=FPGA_WD_SCL,FPGA_WD_SDA,FPGA_WD_INT,FPGA_WD_PROGRAM
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
circuit_board/wrs_v3/SCB/FPGA_GTX.Harness deleted 100644 → 0
View file @ ce4bb7e7
MGTREFCLK=MGTREFCLK112_P,MGTREFCLK112_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK116_P,MGTREFCLK116_N
MGTRX112PN=MGTRX112_0_P,MGTRX112_0_N,MGTRX112_1_P,MGTRX112_1_N,MGTRX112_2_P,MGTRX112_2_N,MGTRX112_3_P,MGTRX112_3_N
MGTRX113PN=MGTRX113_0_P,MGTRX113_0_N,MGTRX113_1_P,MGTRX113_1_N,MGTRX113_2_P,MGTRX113_2_N,MGTRX113_3_P,MGTRX113_3_N
MGTRX114PN=MGTRX114_0_P,MGTRX114_0_N,MGTRX114_1_P,MGTRX114_1_N,MGTRX114_2_P,MGTRX114_2_N,MGTRX114_3_P,MGTRX114_3_N
MGTRX115PN=MGTRX115_0_P,MGTRX115_0_N,MGTRX115_1_P,MGTRX115_1_N,MGTRX115_2_P,MGTRX115_2_N,MGTRX115_3_P,MGTRX115_3_N
MGTRX116PN=MGTRX116_0_P,MGTRX116_0_N,MGTRX116_1_P,MGTRX116_1_N,MGTRX116_2_P,MGTRX116_2_N,MGTRX116_3_P,MGTRX116_3_N
MGTTX112PN=MGTTX112_0_P,MGTTX112_0_N,MGTTX112_1_P,MGTTX112_1_N,MGTTX112_2_P,MGTTX112_2_N,MGTTX112_3_P,MGTTX112_3_N
MGTTX113PN=MGTTX113_0_P,MGTTX113_0_N,MGTTX113_1_P,MGTTX113_1_N,MGTTX113_2_P,MGTTX113_2_N,MGTTX113_3_P,MGTTX113_3_N
MGTTX114PN=MGTTX114_0_P,MGTTX114_0_N,MGTTX114_1_P,MGTTX114_1_N,MGTTX114_2_P,MGTTX114_2_N,MGTTX114_3_P,MGTTX114_3_N
MGTTX115PN=MGTTX115_0_P,MGTTX115_0_N,MGTTX115_1_P,MGTTX115_1_N,MGTTX115_2_P,MGTTX115_2_N,MGTTX115_3_P,MGTTX115_3_N
MGTTX116PN=MGTTX116_0_P,MGTTX116_0_N,MGTTX116_1_P,MGTTX116_1_N,MGTTX116_2_P,MGTTX116_2_N,MGTTX116_3_P,MGTTX116_3_N
circuit_board/wrs_v3/SCB/FPGA_PLLs.Harness deleted 100644 → 0
View file @ ce4bb7e7
MGTREFCLK=MGTREFCLK116_P,MGTREFCLK116_N,MGTREFCLK115_P,MGTREFCLK115_N,MGTREFCLK114_P,MGTREFCLK114_N,MGTREFCLK113_P,MGTREFCLK113_N,MGTREFCLK112_P,MGTREFCLK112_N
PLL_CONTROL=PLL_SYNC,PLL_SDI,PLL_SDO,PLL_SCLK,PLL_REFSEL,PLL_RESET,PLL_LOCK,PLL_STAT,PLL_CS
QDRII_CLKS=QDRII_CLK_P,QDRII_CLK_N,QDRII_200CLK_P,QDRII_200CLK_N
uTCA_CLK=UTCA_TONGUE2_CLK1_P,UTCA_TONGUE2_CLK1_N,UTCA_TONGUE2_CLK2_P,UTCA_TONGUE2_CLK2_N
circuit_board/wrs_v3/SCB/FPGA_QDRII.Harness deleted 100644 → 0
View file @ ce4bb7e7
qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
circuit_board/wrs_v3/SCB/Peripherals_Control.Harness deleted 100644 → 0
View file @ ce4bb7e7
DAC_CONTROL=DAC_DMTD_DIN,DAC_DMTD_SYNC,DAC_DMTD_SCLK,DAC_REF_DIN,DAC_REF_SYNC,DAC_REF_SCLK
PLL_CONTROL=PLL_CS,PLL_STAT,PLL_LOCK,PLL_RESET,PLL_REFSEL,PLL_SCLK,PLL_SDO,PLL_SDI,PLL_SYNC
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG,+1V2_CPU_PG
SPI1=SPI1_MISO,SPI1_MOSI,SPI1_SPCK,SPI1_NPCS0
circuit_board/wrs_v3/SCB/Power_Supply.Harness deleted 100644 → 0
View file @ ce4bb7e7
Power-Good=+1V0_GTX_PG,+3V3_PLL_PG,+2V5_PLL_PG,+1V2_GTX_PG,+3V3_PG,+1V2_CPU_PG
circuit_board/wrs_v3/SCB/QDRII_mem.Harness deleted 100644 → 0
View file @ ce4bb7e7
qdr2_1_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
qdr2_2_bus=A[18..0],D[35..0],Q[35..0],B\W\S\[3..0],K,K\,CQ,C\Q\,D\O\F\F\,R\P\S\,W\P\S\
circuit_board/wrs_v3/SCB/RS232_and_USB_ports.Harness deleted 100644 → 0
View file @ ce4bb7e7
RS232_MNG=RS232_MNG_TXD,RS232_MNG_RXD,RS232_FPGA_TXD,RS232_FPGA_RXD
circuit_board/wrs_v3/SCB/SCB.PrjPCB deleted 100644 → 0
View file @ ce4bb7e7
This diff is collapsed.
circuit_board/wrs_v3/SCB/SCB.PrjPCBStructure deleted 100644 → 0
View file @ ce4bb7e7
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_Connectors|SchDesignator=U_Connectors|FileName=Connectors.SchDoc|SymbolType=Normal|RawFileName=Connectors.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_100M_Ethernet|SchDesignator=U_CPU_100M_Ethernet|FileName=CPU_100M_Ethernet.SchDoc|SymbolType=Normal|RawFileName=CPU_100M_Ethernet.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_IO_Ports|SchDesignator=U_CPU_IO_Ports|FileName=CPU_IO_Ports.SchDoc|SymbolType=Normal|RawFileName=CPU_IO_Ports.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_JTAG_Power_PLL|SchDesignator=U_CPU_JTAG_Power_PLL|FileName=CPU_JTAG_Power_PLL.SchDoc|SymbolType=Normal|RawFileName=CPU_JTAG_Power_PLL.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_CPU_memory|SchDesignator=U_CPU_memory|FileName=CPU_memory.SchDoc|SymbolType=Normal|RawFileName=CPU_memory.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_External WatchDogs|SchDesignator=U_External WatchDogs|FileName=External WatchDogs.SchDoc|SymbolType=Normal|RawFileName=External WatchDogs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_Configuration|SchDesignator=U_FPGA_Configuration|FileName=FPGA_Configuration.SchDoc|SymbolType=Normal|RawFileName=FPGA_Configuration.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_CPU_EBI1|SchDesignator=U_FPGA_CPU_EBI1|FileName=FPGA_CPU_EBI1.SchDoc|SymbolType=Normal|RawFileName=FPGA_CPU_EBI1.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_GPIOs|SchDesignator=U_FPGA_GPIOs|FileName=FPGA_GPIOs.SchDoc|SymbolType=Normal|RawFileName=FPGA_GPIOs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_GTX|SchDesignator=U_FPGA_GTX|FileName=FPGA_GTX.SchDoc|SymbolType=Normal|RawFileName=FPGA_GTX.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_POWER_DGND|SchDesignator=U_FPGA_POWER_DGND|FileName=FPGA_POWER_DGND.SchDoc|SymbolType=Normal|RawFileName=FPGA_POWER_DGND.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_QDRII|SchDesignator=U_FPGA_QDRII|FileName=FPGA_QDRII.SchDoc|SymbolType=Normal|RawFileName=FPGA_QDRII.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_FPGA_System_Monitor|SchDesignator=U_FPGA_System_Monitor|FileName=FPGA_System_Monitor.SchDoc|SymbolType=Normal|RawFileName=FPGA_System_Monitor.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_Peripherals_Control|SchDesignator=U_Peripherals_Control|FileName=FPGA_Peripherals_Control.SchDoc|SymbolType=Normal|RawFileName=FPGA_Peripherals_Control.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_Power_Supply|SchDesignator=U_Power_Supply|FileName=Power_Supply.SchDoc|SymbolType=Normal|RawFileName=Power_Supply.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_QDRII_mem|SchDesignator=U_QDRII_mem|FileName=QDRII_mem.SchDoc|SymbolType=Normal|RawFileName=QDRII_mem.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_RS232_and_USB_ports|SchDesignator=U_RS232_and_USB_ports|FileName=RS232_and_USB_ports.SchDoc|SymbolType=Normal|RawFileName=RS232_and_USB_ports.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_SCB_CLKs|SchDesignator=U_SCB_CLKs|FileName=SCB_CLKs.SchDoc|SymbolType=Normal|RawFileName=SCB_CLKs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_SCB_PLLs|SchDesignator=U_SCB_PLLs|FileName=SCB_PLLs.SchDoc|SymbolType=Normal|RawFileName=SCB_PLLs.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_SMI_Link_7-12|SchDesignator=U_SMI_Link_7-12|FileName=SMI_Link_7-12.SchDoc|SymbolType=Normal|RawFileName=SMI_Link_7-12.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=SCB_MAIN.SchDoc|Designator=U_uTCA_Tongue3|SchDesignator=U_uTCA_Tongue3|FileName=uTCA_Tongue3.SchDoc|SymbolType=Normal|RawFileName=uTCA_Tongue3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=QDRII_mem.SchDoc|Designator=U_QDRII_power|SchDesignator=U_QDRII_power|FileName=QDRII_power.SchDoc|SymbolType=Normal|RawFileName=QDRII_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=SCB_MAIN.SchDoc
Record=FPGA_COMPONENT|BaseComponentDesignator=IC33|DocumentName=SMI_Link_7-12.SchDoc|LibraryReference=XC6VLX130T-1FF1156C|SubProjectPath= |Configuration= |Description=Virtex-6 LXT Platform FPGA, 600 User I/Os, 20 GTXs, 1156-Ball FFBGA, Speed Grade 1, Commercial Grade|NexusDeviceId=XC6VLX130T-1FF1156C|SubPartUniqueId1=DBHSHCXH|SubPartDocPath1=SMI_Link_7-12.SchDoc|SubPartUniqueId2=XWVTVJHF|SubPartDocPath2=FPGA_GPIOs.SchDoc|SubPartUniqueId3=OWHUSTVJ|SubPartDocPath3=uTCA_Tongue3.SchDoc|SubPartUniqueId4=QYOYBDCA|SubPartDocPath4=FPGA_CPU_EBI1.SchDoc|SubPartUniqueId5=IBKYCOIH|SubPartDocPath5=FPGA_CPU_EBI1.SchDoc|SubPartUniqueId6=QBBXHNVQ|SubPartDocPath6=FPGA_QDRII.SchDoc|SubPartUniqueId7=NEDXCUQQ|SubPartDocPath7=FPGA_QDRII.SchDoc|SubPartUniqueId8=TUYNOGEW|SubPartDocPath8=FPGA_Configuration.SchDoc|SubPartUniqueId9=DPLMNTYE|SubPartDocPath9=FPGA_QDRII.SchDoc|SubPartUniqueId10=PCOYLJSV|SubPartDocPath10=FPGA_QDRII.SchDoc|SubPartUniqueId11=FIQUEJVO|SubPartDocPath11=FPGA_Peripherals_Control.SchDoc|SubPartUniqueId12=VBEILCCE|SubPartDocPath12=FPGA_QDRII.SchDoc|SubPartUniqueId13=JDCVHSNO|SubPartDocPath13=FPGA_Configuration.SchDoc|SubPartUniqueId14=QFWKVKVE|SubPartDocPath14=FPGA_System_Monitor.SchDoc|SubPartUniqueId15=MKFEUOAO|SubPartDocPath15=FPGA_QDRII.SchDoc|SubPartUniqueId16=MXNCEXNH|SubPartDocPath16=FPGA_Configuration.SchDoc|SubPartUniqueId17=DYWROEHW|SubPartDocPath17=FPGA_GTX.SchDoc|SubPartUniqueId18=XATTCHJI|SubPartDocPath18=FPGA_GTX.SchDoc|SubPartUniqueId19=LFLUSIYY|SubPartDocPath19=FPGA_POWER_DGND.SchDoc|SubPartUniqueId20=SYFNNXGN|SubPartDocPath20=FPGA_POWER_DGND.SchDoc
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