The main purpose of the Clocking FMC is to test/prototype the clocking circuit proposed in the WRS-4 main board (Hardware_Architecture), section 3.4 (page 25-28). Additionally, the FMC has an SFP cage and it can be used to enable WR on a host board, such as e.g. AFCZ, or ZCU102/ZCU106 eval board.
|Date||Design files||Issue label for comments||Comments||Status|
|1||2020-07||schematics (pdf rar)||clockingFMC-review-1||see issues||Completed|
|2||2020-09||schematics (pdf, zip), BOM||clockingFMC-review-2||see issues||Completed|
|3||2020-10||layout (zip), stack-up (zip), schematics (pdf)||clockingFMC-review-3||see issues||Completed|
|4||2020-10||layout (zip), stack-up (zip), schematics (pdf)||clockingFMC-review-4||no comments||Completed
going for production
WR Clocking FMC Final Performance and tests Report
- It is a prototype, so we focus on major issues and we will work on the "cosmetics" in the final WRS-4 schematics design.
- please report any feedback as issue, with the label indicated in the table
Description of the clocking circuit
Extract from WRS-4 main board (Hardware_Architecture) - this FMC is to prototype the described clocking circuit, the description/figure is not of the FMC directly.
The figure shows a detailed block diagram of the proposed solution. As can be seen in this figure, the main PLL is the HMC7044 that has the following features of interest for the new WRS-4:
- Possibility to have a mixed scenario (part of the design working with 62.5 MHz recovered clock and another part with 156.25 MHz recovered clock, for 1Gbps and 10Gbps links respectively).
- Deterministic phase alignment between all output channels, allowing to generate the 10 MHz output directly from the HMC7044 PLL with SYNC support.
- Plenty of clock outputs with configurable type (LVDS or LVPECL).
The main oscillator is the DOT050V that has a plastic cover to avoid known problems related to the airflow. For the helper clock, we propose to use the programmable and tunable oscillator Si549 that has already been tested in a WR node and is ideal to support different frequencies. The 1PPS and Abscal outputs will be latched with D-type FF (with 125MHz or 250MHz). The design will have the possibility to mount an oscillator board (a type of module expansion) to allow better oscillator OCXO and DDS for lpGBT.
The Grandmaster 10 MHz input clock is multiplied by deterministic LMX2594 PLL to create a 1-PPS aligned 62.5/125 MHz, thus the SoftPLL of the WR PTP implementation can align to it. As such, it is the safest solution in case of loss of the 10 MHz input reference. Another option for the Grandmaster can be to connect the RFU of the HMC7044 directly with the LMX2594 in order to clock the system directly with 10 MHz input clock (multiplied to 2.5 GHz) and without using the main oscillator DOT050V. The main problem of this last option occurs when the input reference is lost, since the system might freeze. The RFU lines of HMC7044 can also be connected to the expansion board.