Fiber_SFP: why LOS and TX_FAULT are shorted together?
HMC7044: I need both 125 MHz and 156.25 MHz on the FMC connector for
testing 1G-10G interoperation. Can the PLL be programmed to deliver such
two clocks (with additional constraint of using the SYNC pin to align
the feedback dividers)?
Put an independent (exclusive) i2c bus for each of the Si549s. These
need to be disciplined by the softpll and the I2C bandwidth might be a
limiting factor here (discovered during development of FMC-ADC, AFCZ,
etc...)
I2C helper bus doesn't have pullups (or I'm unable to find them.)
Add series 0R resistors in 0603 package or larger on the i2c pins for
helper oscillators as well as the SPI pins of the main DAC. The reason:
we might need to put LC filters to kill noise injected from the FPGA
(observed during ertm development)
IC10: OSCIN is DC-coupled. Should it be? (don't know the chip, just
asking)
drive the SYNC pins of both PLLs from a pin with ODELAY primitive in
the FPGA (not all pins are capable of them). Consider using a
differential pair + buffer next to the load.
I2C for the EEPROM is also missing pullups (or I'm unable to find them).
There are some symbols/footprints that don't come from the CERN
library. Just a few - ask the DEM for the symbols. They'll be useful for
the real switch.
the schematics should say Copyright CERN and state clearly the
license, as agreed.