Add gw project. Add SD boot files

ed72801a · Jorge Machado · 55180a00 · ed72801a · ed72801a · ed72801a
Commit ed72801a authored Jan 26, 2021 by Jorge Machado
38 changed files
--- a/FCWR_tests/SD_BOOT/BOOT.BIN
+++ b/FCWR_tests/SD_BOOT/BOOT.BIN
--- a/FCWR_tests/SD_BOOT/Image
+++ b/FCWR_tests/SD_BOOT/Image
--- a/FCWR_tests/SD_BOOT/image.ub
+++ b/FCWR_tests/SD_BOOT/image.ub
--- a/FCWR_tests/fmc_support_gw/syn/build.sh
+++ b/FCWR_tests/fmc_support_gw/syn/build.sh
+#! /bin/bash
+
+function echo_err() {
+	echo -e "\033[0;31m$1\033[0m"
+}
+
+function echo_ok() {
+	echo -e "\e[42m$1\033[0m"
+}
+
+function remove_old_prj() {
+	echo "Removing old existing project..."
+	rm -f vivado*
+	rm -f webtalk*
+	rm -f hs_err_pid*
+	rm -rf .Xil
+	rm -rf fmc_support
+}
+
+script_name=`basename $0`
+expected_folder="fmc_support"
+folder=${PWD##*/}
+current_dir=${PWD}
+
+prj=$1
+
+case $prj in
+    "fmc_support" )
+			echo "Building wrs fmc_support project"
+			# Create the Vivado project and the Block design
+			vivado -mode batch -source fmc_support-prj.tcl
+			# Lauch Vivado IDE
+			vivado fmc_support/fmc_support.xpr
+		;;
+
+    "clean")
+			echo "Removing z16 HA project..."
+			remove_old_prj
+		;;
+	"clean-full")
+		echo "Removing z16 HA project..."
+		remove_old_prj
+	;;
+    * )
+		echo "You must specify the options: [fmc_support/clean/clean-full]"
+		;;
+esac
--- a/FCWR_tests/fmc_support_gw/syn/constraints/fmc_support_constraints.xdc
+++ b/FCWR_tests/fmc_support_gw/syn/constraints/fmc_support_constraints.xdc
+#ONEWIRE
+set_property PACKAGE_PIN AC2 [get_ports onewire]
+set_property IOSTANDARD LVCMOS18 [get_ports onewire]
+
+#SFP
+set_property PACKAGE_PIN V2 [get_ports sfp_detect]
+set_property PACKAGE_PIN V1 [get_ports iic_sfp_scl_io]
+set_property PACKAGE_PIN Y2 [get_ports iic_sfp_sda_io]
+set_property PACKAGE_PIN W2 [get_ports {sfp_tx_disable[0]}]
+set_property PACKAGE_PIN Y1 [get_ports sfp_los_tx_fault]
+set_property PACKAGE_PIN AB3 [get_ports {sfp_led_activity[0]}]
+set_property PACKAGE_PIN AC1 [get_ports {sfp_led_link[0]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_detect]
+set_property IOSTANDARD LVCMOS18 [get_ports iic_sfp_scl_io]
+set_property IOSTANDARD LVCMOS18 [get_ports iic_sfp_sda_io]
+set_property IOSTANDARD LVCMOS18 [get_ports {sfp_tx_disable[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_tx_fault]
+set_property IOSTANDARD LVCMOS18 [get_ports {sfp_led_activity[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {sfp_led_link[0]}]
+
+#set_property PACKAGE_PIN H1 [get_ports sfp_rxn]
+#set_property IOSTANDARD LVDS [get_ports sfp_rxn]
+
+#OTHERS
+set_property PACKAGE_PIN V4 [get_ports pps_in]
+set_property PACKAGE_PIN T11 [get_ports {term_en[0]}]
+set_property PACKAGE_PIN U4 [get_ports pps_out]
+set_property PACKAGE_PIN W1 [get_ports aux_out]
+set_property PACKAGE_PIN W5 [get_ports iic_helper_scl_io]
+set_property PACKAGE_PIN V3 [get_ports iic_helper_sda_io]
+set_property PACKAGE_PIN U5 [get_ports iic_si549_aux_scl_io]
+set_property PACKAGE_PIN AC3 [get_ports iic_si549_aux_sda_io]
+set_property PACKAGE_PIN M15 [get_ports {dac_cs[0]}]
+set_property PACKAGE_PIN M14 [get_ports dac_din]
+set_property PACKAGE_PIN P12 [get_ports dac_sclk]
+
+set_property IOSTANDARD LVCMOS18 [get_ports pps_in]
+set_property IOSTANDARD LVCMOS18 [get_ports {term_en[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports pps_out]
+set_property IOSTANDARD LVCMOS18 [get_ports aux_out]
+set_property IOSTANDARD LVCMOS18 [get_ports iic_helper_scl_io]
+set_property IOSTANDARD LVCMOS18 [get_ports iic_helper_sda_io]
+set_property IOSTANDARD LVCMOS18 [get_ports iic_si549_aux_scl_io]
+set_property IOSTANDARD LVCMOS18 [get_ports iic_si549_aux_sda_io]
+set_property IOSTANDARD LVCMOS18 [get_ports {dac_cs[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports dac_din]
+set_property IOSTANDARD LVCMOS18 [get_ports dac_sclk]
+
+
+set_property PACKAGE_PIN L13 [get_ports {hmc_sync_p[0]}]
+set_property PACKAGE_PIN K13 [get_ports {hmc_sync_n[0]}]
+set_property PACKAGE_PIN AA12 [get_ports hmc_sdata]
+set_property PACKAGE_PIN V6 [get_ports hmc_slen]
+set_property PACKAGE_PIN V7 [get_ports hmc_sclk]
+set_property PACKAGE_PIN N13 [get_ports {hmc_reset[0]}]
+set_property PACKAGE_PIN Y10 [get_ports hmc_gpio1]
+set_property PACKAGE_PIN L16 [get_ports hmc_gpio2]
+set_property PACKAGE_PIN K16 [get_ports hmc_gpio3]
+set_property PACKAGE_PIN M13 [get_ports hmc_gpio4]
+
+set_property IOSTANDARD LVDS [get_ports {hmc_sync_p[0]}]
+set_property IOSTANDARD LVDS [get_ports {hmc_sync_n[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_sdata]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_slen]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_sclk]
+set_property IOSTANDARD LVCMOS18 [get_ports {hmc_reset[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_gpio1]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_gpio2]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_gpio3]
+set_property IOSTANDARD LVCMOS18 [get_ports hmc_gpio4]
+
+set_property PACKAGE_PIN AA7 [get_ports ref_clk_p]
+set_property PACKAGE_PIN AA6 [get_ports ref_clk_n]
+set_property PACKAGE_PIN T8 [get_ports wr_clk_p]
+set_property PACKAGE_PIN R8 [get_ports wr_clk_n]
+set_property PACKAGE_PIN L7 [get_ports mgt_clk2_n]
+set_property PACKAGE_PIN L8 [get_ports mgt_clk2_p]
+set_property PACKAGE_PIN G7 [get_ports mgt_clk1_n]
+set_property PACKAGE_PIN G8 [get_ports mgt_clk1_p]
+set_property PACKAGE_PIN AB6 [get_ports ext_gm_fpga_p]
+set_property PACKAGE_PIN AB5 [get_ports ext_gm_fpga_n]
+
+set_property IOSTANDARD LVDS [get_ports ref_clk_p]
+set_property IOSTANDARD LVDS [get_ports ref_clk_n]
+set_property IOSTANDARD LVDS [get_ports wr_clk_p]
+set_property IOSTANDARD LVDS [get_ports wr_clk_n]
+#set_property IOSTANDARD LVDS [get_ports mgt_clk2_p]
+#set_property IOSTANDARD LVDS [get_ports mgt_clk2_n]
+#set_property IOSTANDARD LVDS [get_ports mgt_clk1_p]
+#set_property IOSTANDARD LVDS [get_ports mgt_clk1_n]
+set_property IOSTANDARD LVDS [get_ports ext_gm_fpga_p]
+set_property IOSTANDARD LVDS [get_ports ext_gm_fpga_n]
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {fmc_support_i/util_ds_buf_4/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O}]
+
+
+set_property PACKAGE_PIN AC8 [get_ports {pll_gm_csb[0]}]
+set_property PACKAGE_PIN AC6 [get_ports pll_gm_sdi]
+set_property PACKAGE_PIN W4 [get_ports pll_gm_sck]
+set_property PACKAGE_PIN AA2 [get_ports {pll_gm_sync_p[0]}]
+set_property PACKAGE_PIN AA1 [get_ports {pll_gm_sync_n[0]}]
+set_property PACKAGE_PIN AB8 [get_ports {pll_gm_rampdir[0]}]
+set_property PACKAGE_PIN W6 [get_ports pll_gm_rampclk]
+set_property PACKAGE_PIN W7 [get_ports pll_gm_muxout]
+set_property PACKAGE_PIN AC7 [get_ports {pll_gm_sysrefreq[0]}]
+set_property PACKAGE_PIN P11 [get_ports lmx_gm_clk_p]
+set_property PACKAGE_PIN N11 [get_ports lmx_gm_clk_n]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {pll_gm_csb[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports pll_gm_sdi]
+set_property IOSTANDARD LVCMOS18 [get_ports pll_gm_sck]
+set_property IOSTANDARD LVDS [get_ports {pll_gm_sync_p[0]}]
+set_property IOSTANDARD LVDS [get_ports {pll_gm_sync_n[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {pll_gm_rampdir[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports pll_gm_rampclk]
+set_property IOSTANDARD LVCMOS18 [get_ports pll_gm_muxout]
+set_property IOSTANDARD LVCMOS18 [get_ports {pll_gm_sysrefreq[0]}]
+set_property IOSTANDARD LVDS [get_ports lmx_gm_clk_p]
+set_property IOSTANDARD LVDS [get_ports lmx_gm_clk_n]
+
+set_property PACKAGE_PIN G21 [get_ports clk_125_p]
+set_property PACKAGE_PIN F21 [get_ports clk_125_n]
+set_property IOSTANDARD LVDS_25 [get_ports clk_125_p]
+set_property IOSTANDARD LVDS_25 [get_ports clk_125_n]
+
+set_property PACKAGE_PIN AL8 [get_ports clk_300_p]
+set_property PACKAGE_PIN AL7 [get_ports clk_300_n]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_300_p]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports clk_300_n]
+
+set_property PACKAGE_PIN V11 [get_ports {enable[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {enable[0]}]
+
+set_property PACKAGE_PIN N9 [get_ports SI549_aux_p]
+set_property PACKAGE_PIN N8 [get_ports SI549_aux_n]
+set_property IOSTANDARD LVDS [get_ports SI549_aux_p]
+set_property IOSTANDARD LVDS [get_ports SI549_aux_n]
+
+set_property PACKAGE_PIN Y4 [get_ports helper_1_p]
+set_property PACKAGE_PIN Y3 [get_ports helper_1_n]
+set_property IOSTANDARD LVDS [get_ports helper_1_p]
+set_property IOSTANDARD LVDS [get_ports helper_1_n]
+
+set_property PACKAGE_PIN A20 [get_ports {PMOD0_0[0]}]
+set_property PACKAGE_PIN B20 [get_ports {PMOD0_1[0]}]
+set_property PACKAGE_PIN A22 [get_ports {PMOD0_2[0]}]
+set_property PACKAGE_PIN A21 [get_ports {PMOD0_3[0]}]
+set_property PACKAGE_PIN B21 [get_ports {PMOD0_4[0]}]
+set_property PACKAGE_PIN C21 [get_ports {PMOD0_5[0]}]
+set_property PACKAGE_PIN C22 [get_ports {PMOD0_6[0]}]
+set_property PACKAGE_PIN D21 [get_ports {PMOD0_7[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_0[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_1[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_2[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_3[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_4[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_5[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_6[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PMOD0_7[0]}]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {fmc_support_i/util_ds_buf_5/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O}]
\ No newline at end of file
--- a/FCWR_tests/fmc_support_gw/syn/fmc.tcl
+++ b/FCWR_tests/fmc_support_gw/syn/fmc.tcl
+#
+# Vivado (TM) v2017.3 (64-bit)
+#
+# z16-prj.tcl: Tcl script for re-creating project 'z16'
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (z16-prj.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    <none>
+#
+#*****************************************************************************************
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir [file dirname [info script]]
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/"]"
+
+# Create project
+create_project z16v4 $origin_dir/z16v4
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [get_projects z16v4]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "part" "xc7z035ffg900-2" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+set_property "ip_repo_paths" "$orig_proj_dir/../vivado_ip" $obj
+update_ip_catalog
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/xdc/z16v4.xdc"]"
+set file_added [add_files -norecurse -fileset $obj $file]
+set file "$origin_dir/xdc/z16v4.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property "file_type" "XDC" $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property "target_constrs_file" "[file normalize "$origin_dir/xdc/z16v4.xdc"]" $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+  create_run -name synth_1 -part xc7z035ffg900-2 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+
+set_property "steps.synth_design.tcl.pre" "[file normalize "$origin_dir/gen_date_gw_version.tcl"]" $obj
+
+set_property "constrset" "constrs_1" $obj
+set_property "part" "xc7z035ffg900-2" $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+  create_run -name impl_1 -part xc7z035ffg900-2 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -constrset constrs_2 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property "constrset" "constrs_1" $obj
+set_property "part" "xc7z035ffg900-2" $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:z16v4"
+
+# execute the BD script #$z16_board_ver
+source $origin_dir/z16v4_bd.tcl
+
+# create the HDL wrapper
+set design_name [get_bd_designs]
+make_wrapper -files [get_files $design_name.bd] -top -import
--- a/FCWR_tests/fmc_support_gw/syn/fmc_support-prj.tcl
+++ b/FCWR_tests/fmc_support_gw/syn/fmc_support-prj.tcl
+#
+# Vivado (TM) v2017.3 (64-bit)
+#
+# z16-prj.tcl: Tcl script for re-creating project 'z16'
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (z16-prj.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    <none>
+#
+#*****************************************************************************************
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir [file dirname [info script]]
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/"]"
+
+# Create project
+create_project fmc_support $origin_dir/fmc_support
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [get_projects fmc_support]
+set_property "default_lib" "xil_defaultlib" $obj
+set_property "part" "xczu9eg-ffvb1156-2-e" $obj
+set_property "simulator_language" "Mixed" $obj
+set_property "target_language" "VHDL" $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+set_property "ip_repo_paths" "$orig_proj_dir/../vivado_ip" $obj
+update_ip_catalog
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/constraints/fmc_support_constraints.xdc"]"
+set file_added [add_files -norecurse -fileset $obj $file]
+set file "$origin_dir/constraints/fmc_support_constraints.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property "file_type" "XDC" $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property "target_constrs_file" "[file normalize "$origin_dir/constraints/fmc_support_constraints.xdc"]" $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+  create_run -name synth_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+
+set_property "constrset" "constrs_1" $obj
+set_property "part" "xczu9eg-ffvb1156-2-e" $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+  create_run -name impl_1 -part xczu9eg-ffvb1156-2-e -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -constrset constrs_2 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property "constrset" "constrs_1" $obj
+set_property "part" "xczu9eg-ffvb1156-2-e" $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:fmc_support"
+
+# execute the BD script #$z16_board_ver
+source $origin_dir/fmc_support_bd.tcl
+
+# create the HDL wrapper
+set design_name [get_bd_designs]
+make_wrapper -files [get_files $design_name.bd] -top -import
--- a/FCWR_tests/fmc_support_gw/syn/fmc_support_bd.tcl
+++ b/FCWR_tests/fmc_support_gw/syn/fmc_support_bd.tcl
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/gui_handlers.wdf
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/gui_handlers.wdf
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6164647265706f7369746f7279696e666f6469616c6f675f6f6b:31:00:00
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--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/java_command_handlers.wdf
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/java_command_handlers.wdf
+version:1
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--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/project.wpc
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/project.wpc
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
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--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/webtalk_pa.xml
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.cache/wt/webtalk_pa.xml
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Thu Dec  3 12:46:09 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="dbdd5cf61b094ef6823f7724cd9bc268" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="AutoAssignAddress" value="1" type="JavaHandler"/>
+<property name="AutoConnectPort" value="2" type="JavaHandler"/>
+<property name="CloseProject" value="1" type="JavaHandler"/>
+<property name="CoreView" value="1" type="JavaHandler"/>
+<property name="CustomizeRSBBlock" value="4" type="JavaHandler"/>
+<property name="EditCopy" value="3" type="JavaHandler"/>
+<property name="EditPaste" value="3" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="1" type="JavaHandler"/>
+<property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
+<property name="NewProject" value="1" type="JavaHandler"/>
+<property name="OpenAddressEditor" value="1" type="JavaHandler"/>
+<property name="RegenerateRSBLayout" value="3" type="JavaHandler"/>
+<property name="SaveFileProxyHandler" value="3" type="JavaHandler"/>
+<property name="SaveRSBDesign" value="4" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="AddRepositoryInfoDialog_OK" value="1" type="GuiHandlerData"/>
+<property name="AddressTreeTablePanel_ADDRESS_TREE_TABLE" value="2" type="GuiHandlerData"/>
+<property name="BaseDialog_CANCEL" value="3" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="11" type="GuiHandlerData"/>
+<property name="BoardChooser_BOARD_TABLE" value="1" type="GuiHandlerData"/>
+<property name="CoreAndInterfacesBaseTreeTablePanel_ADD_REPOSITORY" value="1" type="GuiHandlerData"/>
+<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="1" type="GuiHandlerData"/>
+<property name="CreateRSBPortDialog_DIRECTION" value="5" type="GuiHandlerData"/>
+<property name="CreateRSBPortDialog_PORT_NAME" value="4" type="GuiHandlerData"/>
+<property name="CreateSrcFileDialog_FILE_NAME" value="2" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="10" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_REPORTS" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_WINDOW" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_ADDRESSEDITOR_WINDOW" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_AUTO_ASSIGN_ADDRESS" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_AUTO_CONNECT_PORTS" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_REGENERATE_LAYOUT" value="4" type="GuiHandlerData"/>
+<property name="PAViews_CODE" value="1" type="GuiHandlerData"/>
+<property name="PAViews_IP_CATALOG" value="1" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="4" type="GuiHandlerData"/>
+<property name="ParameterFacetTable_EDIT_PARAMETER" value="1" type="GuiHandlerData"/>
+<property name="ParameterFacetTable_PARAMETER_FACET_TABLE" value="6" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
+<property name="RSBApplyAutomationBar_RUN_CONNECTION_AUTOMATION" value="1" type="GuiHandlerData"/>
+<property name="RSBBlockPropPanels_NAME" value="2" type="GuiHandlerData"/>
+<property name="RSBExternalInterfacePropPanels_NAME" value="2" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_PACKAGE_IP" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_CREATE_FILE" value="2" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_MAKE_LOCAL_COPY_OF_THESE_FILES_INTO" value="1" type="GuiHandlerData"/>
+<property name="SystemBuilderView_EXPAND_COLLAPSE" value="2" type="GuiHandlerData"/>
+<property name="SystemBuilderView_PINNING" value="6" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="183" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="134" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.hw/dac_controller.lpr
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.hw/dac_controller.lpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/component.xml
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/component.xml
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/dac_controller.vhd
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/dac_controller.vhd
+-------------------------------------------------------------------------------
+-- Title      : Serial DAC interface
+-- Project    : White Rabbit Switch
+-------------------------------------------------------------------------------
+-- File       : serial_dac.vhd
+-- Author     : paas, slayer
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-02-25
+-- Last update: 2011-05-10
+-- Platform   : fpga-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Description: The dac unit provides an interface to a 16 bit serial Digita to Analogue converter (max5441, SPI?/QSPI?/MICROWIRE? compatible) 
+--
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+-------------------------------------------------------------------------------
+-- Revisions  :1
+-- Date        Version  Author  Description
+-- 2009-01-24  1.0      paas    Created
+-- 2010-02-25  1.1      slayer  Modified for rev 1.1 switch
+-------------------------------------------------------------------------------
+
+
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+entity wr_dac is
+
+  generic (
+    g_num_data_bits  : integer := 16;
+    g_num_extra_bits : integer := 8;
+    g_num_cs_select  : integer := 2
+    );
+
+  port (
+-- clock & reset
+    clk_i   : in std_logic;
+    rst_n_i : in std_logic;
+
+-- channel 1 value and value load strobe
+    value_i  : in std_logic_vector(g_num_data_bits-1 downto 0);
+    cs_sel_i : in std_logic_vector(g_num_cs_select-1 downto 0);
+    load_i   : in std_logic;
+
+-- SCLK divider: 000 = clk_i/8 ... 111 = clk_i/1024
+    sclk_divsel_i : in std_logic_vector(2 downto 0);
+
+-- DAC I/F
+    dac_cs_n_o  : out std_logic_vector(g_num_cs_select-1 downto 0);
+    dac_sclk_o  : out std_logic;
+    dac_sdata_o : out std_logic;
+
+    xdone_o : out std_logic
+    );
+end wr_dac;
+
+
+architecture syn of wr_dac is
+
+  signal divider        : unsigned(11 downto 0);
+  signal dataSh         : std_logic_vector(g_num_data_bits + g_num_extra_bits-1 downto 0);
+  signal bitCounter     : std_logic_vector(g_num_data_bits + g_num_extra_bits+1 downto 0);
+  signal endSendingData : std_logic;
+  signal sendingData    : std_logic;
+  signal iDacClk        : std_logic;
+  signal iValidValue    : std_logic;
+
+  signal divider_muxed : std_logic;
+
+  signal cs_sel_reg : std_logic_vector(g_num_cs_select-1 downto 0);
+  
+begin
+
+  select_divider : process (divider, sclk_divsel_i)
+  begin  -- process
+    case sclk_divsel_i is
+      when "000"  => divider_muxed <= divider(1);  -- sclk = clk_i/8
+      when "001"  => divider_muxed <= divider(2);  -- sclk = clk_i/16
+      when "010"  => divider_muxed <= divider(3);  -- sclk = clk_i/32
+      when "011"  => divider_muxed <= divider(4);  -- sclk = clk_i/64
+      when "100"  => divider_muxed <= divider(5);  -- sclk = clk_i/128
+      when "101"  => divider_muxed <= divider(6);  -- sclk = clk_i/256
+      when "110"  => divider_muxed <= divider(7);  -- sclk = clk_i/512
+      when "111"  => divider_muxed <= divider(8);  -- sclk = clk_i/1024
+      when others => null;
+    end case;
+  end process;
+
+
+  iValidValue <= load_i;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        sendingData <= '0';
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          sendingData <= '1';
+        elsif endSendingData = '1' then
+          sendingData <= '0';
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' then
+        divider <= (others => '0');
+      elsif sendingData = '1' then
+        if(divider_muxed = '1') then
+          divider <= (others => '0');
+        else
+          divider <= divider + 1;
+        end if;
+      elsif endSendingData = '1' then
+        divider <= (others => '0');
+      end if;
+    end if;
+  end process;
+
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        iDacClk <= '1';                 -- 0
+      else
+        if iValidValue = '1' then
+          iDacClk <= '1';               -- 0
+        elsif divider_muxed = '1' then
+          iDacClk <= not(iDacClk);
+        elsif endSendingData = '1' then
+          iDacClk <= '1';               -- 0
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i, rst_n_i)
+  begin
+    if rising_edge(clk_i) then
+      if rst_n_i = '0' then
+        dataSh <= (others => '0');
+      else
+        if iValidValue = '1' and sendingData = '0' then
+          cs_sel_reg <= cs_sel_i;
+          dataSh(g_num_data_bits-1 downto 0)     <= value_i;
+          dataSh(dataSh'left downto g_num_data_bits) <= (others => '0');
+        elsif sendingData = '1' and divider_muxed = '1' and iDacClk = '0' then
+          dataSh(0)                    <= dataSh(dataSh'left);
+          dataSh(dataSh'left downto 1) <= dataSh(dataSh'left - 1 downto 0);
+        end if;
+      end if;
+    end if;
+  end process;
+
+  process(clk_i)
+  begin
+    if rising_edge(clk_i) then
+      if iValidValue = '1' and sendingData = '0' then
+        bitCounter(0)                        <= '1';
+        bitCounter(bitCounter'left downto 1) <= (others => '0');
+      elsif sendingData = '1' and to_integer(divider) = 0 and iDacClk = '1' then
+        bitCounter(0)                        <= '0';
+        bitCounter(bitCounter'left downto 1) <= bitCounter(bitCounter'left - 1 downto 0);
+      end if;
+    end if;
+  end process;
+
+  endSendingData <= bitCounter(bitCounter'left);
+
+  xdone_o <= not SendingData;
+
+  dac_sdata_o <= dataSh(dataSh'left);
+
+  gen_cs_out : for i in 0 to g_num_cs_select-1 generate
+    dac_cs_n_o(i) <= not(sendingData) or (not cs_sel_reg(i));
+  end generate gen_cs_out;
+
+  dac_sclk_o <= iDacClk;
+
+
+end syn;
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/dac_controller_wrapper.vhd
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/dac_controller_wrapper.vhd
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/xgui/dac_controller_v1_0.tcl
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/xgui/dac_controller_v1_0.tcl
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "g_num_cs_select" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "g_num_data_bits" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "g_num_extra_bits" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.g_num_cs_select { PARAM_VALUE.g_num_cs_select } {
+	# Procedure called to update g_num_cs_select when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_num_cs_select { PARAM_VALUE.g_num_cs_select } {
+	# Procedure called to validate g_num_cs_select
+	return true
+}
+
+proc update_PARAM_VALUE.g_num_data_bits { PARAM_VALUE.g_num_data_bits } {
+	# Procedure called to update g_num_data_bits when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_num_data_bits { PARAM_VALUE.g_num_data_bits } {
+	# Procedure called to validate g_num_data_bits
+	return true
+}
+
+proc update_PARAM_VALUE.g_num_extra_bits { PARAM_VALUE.g_num_extra_bits } {
+	# Procedure called to update g_num_extra_bits when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_num_extra_bits { PARAM_VALUE.g_num_extra_bits } {
+	# Procedure called to validate g_num_extra_bits
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.g_num_data_bits { MODELPARAM_VALUE.g_num_data_bits PARAM_VALUE.g_num_data_bits } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_num_data_bits}] ${MODELPARAM_VALUE.g_num_data_bits}
+}
+
+proc update_MODELPARAM_VALUE.g_num_extra_bits { MODELPARAM_VALUE.g_num_extra_bits PARAM_VALUE.g_num_extra_bits } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_num_extra_bits}] ${MODELPARAM_VALUE.g_num_extra_bits}
+}
+
+proc update_MODELPARAM_VALUE.g_num_cs_select { MODELPARAM_VALUE.g_num_cs_select PARAM_VALUE.g_num_cs_select } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_num_cs_select}] ${MODELPARAM_VALUE.g_num_cs_select}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
+}
+
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/xgui/dac_controller_wrapper_v1_0.tcl
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.srcs/sources_1/new/xgui/dac_controller_wrapper_v1_0.tcl
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "C_S_AXI_ADDR_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "C_S_AXI_DATA_WIDTH" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "g_num_cs_select" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "g_num_data_bits" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "g_num_extra_bits" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to validate C_S_AXI_ADDR_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to validate C_S_AXI_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.g_num_cs_select { PARAM_VALUE.g_num_cs_select } {
+	# Procedure called to update g_num_cs_select when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_num_cs_select { PARAM_VALUE.g_num_cs_select } {
+	# Procedure called to validate g_num_cs_select
+	return true
+}
+
+proc update_PARAM_VALUE.g_num_data_bits { PARAM_VALUE.g_num_data_bits } {
+	# Procedure called to update g_num_data_bits when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_num_data_bits { PARAM_VALUE.g_num_data_bits } {
+	# Procedure called to validate g_num_data_bits
+	return true
+}
+
+proc update_PARAM_VALUE.g_num_extra_bits { PARAM_VALUE.g_num_extra_bits } {
+	# Procedure called to update g_num_extra_bits when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.g_num_extra_bits { PARAM_VALUE.g_num_extra_bits } {
+	# Procedure called to validate g_num_extra_bits
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.g_num_data_bits { MODELPARAM_VALUE.g_num_data_bits PARAM_VALUE.g_num_data_bits } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_num_data_bits}] ${MODELPARAM_VALUE.g_num_data_bits}
+}
+
+proc update_MODELPARAM_VALUE.g_num_extra_bits { MODELPARAM_VALUE.g_num_extra_bits PARAM_VALUE.g_num_extra_bits } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_num_extra_bits}] ${MODELPARAM_VALUE.g_num_extra_bits}
+}
+
+proc update_MODELPARAM_VALUE.g_num_cs_select { MODELPARAM_VALUE.g_num_cs_select PARAM_VALUE.g_num_cs_select } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.g_num_cs_select}] ${MODELPARAM_VALUE.g_num_cs_select}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
+}
+
--- a/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.xpr
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/dac_controller/dac_controller.xpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="39" Path="/home/jorge7s/workspace/WRS4_fmc/gw/fmc_support/ip_cores/dac_controller/dac_controller.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="b99108f02a3c423d818b3fb894ed48b4"/>
+    <Option Name="Part" Val="xczu9eg-ffvb1156-2-e"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="xilinx.com:zcu102:part0:3.2"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PSRCDIR/sources_1/new"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSABoardId" Val="zcu102"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/dac_controller.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/dac_controller_wrapper.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="dac_controller_wrapper"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="dac_controller_wrapper"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu9eg-ffvb1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu9eg-ffvb1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters/>
+  </BootPmcSettings>
+</Project>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/gui_handlers.wdf
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/gui_handlers.wdf
+version:1
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--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/java_command_handlers.wdf
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/java_command_handlers.wdf
+version:1
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--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/project.wpc
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/project.wpc
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/webtalk_pa.xml
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.cache/wt/webtalk_pa.xml
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Thu Dec  3 10:59:56 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="d3ae0b8c3c5b46c1aa67a1df006c6938" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="CloseProject" value="1" type="JavaHandler"/>
+<property name="CustomizeRSBBlock" value="7" type="JavaHandler"/>
+<property name="EditCopy" value="1" type="JavaHandler"/>
+<property name="EditDelete" value="3" type="JavaHandler"/>
+<property name="EditPaste" value="1" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="1" type="JavaHandler"/>
+<property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
+<property name="NewProject" value="1" type="JavaHandler"/>
+<property name="OpenBlockDesign" value="1" type="JavaHandler"/>
+<property name="SaveFileProxyHandler" value="3" type="JavaHandler"/>
+<property name="SaveRSBDesign" value="2" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_CANCEL" value="7" type="GuiHandlerData"/>
+<property name="BaseDialog_OK" value="15" type="GuiHandlerData"/>
+<property name="BoardChooser_BOARD_TABLE" value="2" type="GuiHandlerData"/>
+<property name="CreateRSBInterfaceDialog_INTERFACE_NAME" value="1" type="GuiHandlerData"/>
+<property name="CreateRSBPortDialog_DIRECTION" value="6" type="GuiHandlerData"/>
+<property name="CreateRSBPortDialog_PORT_NAME" value="8" type="GuiHandlerData"/>
+<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="6" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="1" type="GuiHandlerData"/>
+<property name="IdentificationContentPanel_DESCRIPTION" value="1" type="GuiHandlerData"/>
+<property name="IdentificationContentPanel_DISPLAY_NAME" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_OPEN_RECENT_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="PAViews_ADDRESS_EDITOR" value="1" type="GuiHandlerData"/>
+<property name="PAViews_PROJECT_SUMMARY" value="1" type="GuiHandlerData"/>
+<property name="PSSPanelClockingPage_TABBED_PANE" value="1" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_ADV_CLK_TREE" value="11" type="GuiHandlerData"/>
+<property name="PSSTreeTablePanelBuilder_CLK_TREE" value="3" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="6" type="GuiHandlerData"/>
+<property name="ParameterFacetTable_EDIT_PARAMETER" value="2" type="GuiHandlerData"/>
+<property name="ParameterFacetTable_PARAMETER_FACET_TABLE" value="4" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="1" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_PACKAGE_IP" value="1" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_CREATE_FILE" value="1" type="GuiHandlerData"/>
+<property name="SyntheticaGettingStartedView_RECENT_PROJECTS" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="183" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="134" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.hw/pps_gen.lpr
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.hw/pps_gen.lpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.srcs/sources_1/new/component.xml
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.srcs/sources_1/new/component.xml
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.srcs/sources_1/new/pps_gen.vhd
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.srcs/sources_1/new/pps_gen.vhd
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date: 12/03/2020 10:33:51 AM
+-- Design Name: 
+-- Module Name: pps_gen - Behavioral
+-- Project Name: 
+-- Target Devices: 
+-- Tool Versions: 
+-- Description: 
+-- 
+-- Dependencies: 
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+-- 
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity pps_gen is
+  Generic(
+    freq_hz : integer := 50000000;
+    pps_width : integer := 10000
+  );
+  Port ( 
+    clk_i : in std_logic;
+    rstn_i : in std_logic;
+    pps_o : out std_logic
+  );
+end pps_gen;
+
+architecture Behavioral of pps_gen is
+
+    signal second_counter : integer;
+    signal pps_counter : integer;
+    signal pps_internal_pulse : std_logic;
+    signal pps_internal : std_logic;
+
+begin
+
+ process(clk_i)
+ begin
+   if rising_edge(clk_i) then
+    if(rstn_i = '0') then
+      second_counter <= 0;
+      pps_internal_pulse <= '0';
+    else
+      if(second_counter = freq_hz - 1) then
+        pps_internal_pulse <= '1';
+        second_counter <= 0;
+      else
+        pps_internal_pulse <= '0';
+        second_counter <= second_counter + 1;
+      end if;
+    end if;
+   end if;
+ end process;
+ 
+ process(clk_i)
+ begin
+   if rising_edge(clk_i) then
+    if(rstn_i = '0') then
+      pps_counter <= 0;
+      pps_internal <= '0';    
+    else
+      if(pps_internal_pulse = '1') then
+        pps_counter <= pps_width + 1;
+        pps_internal <= '1'; 
+      elsif(pps_counter > 0) then
+        pps_counter <= pps_counter - 1;   
+        pps_internal <= '1';
+      else
+        pps_internal <= '0';
+      end if;
+    end if;
+   end if;
+ end process;
+
+pps_o <= pps_internal;
+
+end Behavioral;
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.srcs/sources_1/new/xgui/pps_gen_v1_0.tcl
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.srcs/sources_1/new/xgui/pps_gen_v1_0.tcl
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  ipgui::add_param $IPINST -name "freq_hz" -parent ${Page_0}
+  ipgui::add_param $IPINST -name "pps_width" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.freq_hz { PARAM_VALUE.freq_hz } {
+	# Procedure called to update freq_hz when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.freq_hz { PARAM_VALUE.freq_hz } {
+	# Procedure called to validate freq_hz
+	return true
+}
+
+proc update_PARAM_VALUE.pps_width { PARAM_VALUE.pps_width } {
+	# Procedure called to update pps_width when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.pps_width { PARAM_VALUE.pps_width } {
+	# Procedure called to validate pps_width
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.freq_hz { MODELPARAM_VALUE.freq_hz PARAM_VALUE.freq_hz } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.freq_hz}] ${MODELPARAM_VALUE.freq_hz}
+}
+
+proc update_MODELPARAM_VALUE.pps_width { MODELPARAM_VALUE.pps_width PARAM_VALUE.pps_width } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.pps_width}] ${MODELPARAM_VALUE.pps_width}
+}
+
--- a/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.xpr
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/pps_gen/pps_gen.xpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="39" Path="/home/jorge7s/workspace/WRS4_fmc/gw/fmc_support/ip_cores/pps_gen/pps_gen.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="34adb99838f341e5b5385d7b21e408b9"/>
+    <Option Name="Part" Val="xczu9eg-ffvb1156-2-e"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="xilinx.com:zcu102:part0:3.2"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PSRCDIR/sources_1/new"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSABoardId" Val="zcu102"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/pps_gen.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="pps_gen"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="pps_gen"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu9eg-ffvb1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu9eg-ffvb1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters/>
+  </BootPmcSettings>
+</Project>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/gui_handlers.wdf
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/gui_handlers.wdf
+version:1
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3131:00:00
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+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726576696577636f6e74656e7470616e656c5f7061636b6167655f6970:34:00:00
+70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:32:00:00
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+eof:4163418935
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/java_command_handlers.wdf
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/java_command_handlers.wdf
+version:1
+70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:31:00:00
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+eof:2270361395
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/project.wpc
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/project.wpc
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:1
+eof:
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/webtalk_pa.xml
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.cache/wt/webtalk_pa.xml
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Fri Dec  4 09:55:46 2020">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="6d932859aab647d49d922a8860ba44e6" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="CloseProject" value="1" type="JavaHandler"/>
+<property name="CustomizeRSBBlock" value="3" type="JavaHandler"/>
+<property name="EditCopy" value="1" type="JavaHandler"/>
+<property name="EditDelete" value="1" type="JavaHandler"/>
+<property name="EditPaste" value="1" type="JavaHandler"/>
+<property name="IPPackagerHandler" value="1" type="JavaHandler"/>
+<property name="IPPackagerWizardHandler" value="1" type="JavaHandler"/>
+<property name="NewProject" value="1" type="JavaHandler"/>
+<property name="ReportIPStatus" value="1" type="JavaHandler"/>
+<property name="SaveRSBDesign" value="2" type="JavaHandler"/>
+</item>
+<item name="Gui Handlers">
+<property name="BaseDialog_OK" value="11" type="GuiHandlerData"/>
+<property name="BaseReportTab_RERUN" value="5" type="GuiHandlerData"/>
+<property name="BoardChooser_BOARD_TABLE" value="1" type="GuiHandlerData"/>
+<property name="CoreTreeTablePanel_CORE_TREE_TABLE" value="6" type="GuiHandlerData"/>
+<property name="CreateRSBPortDialog_DIRECTION" value="2" type="GuiHandlerData"/>
+<property name="CreateRSBPortDialog_PORT_NAME" value="2" type="GuiHandlerData"/>
+<property name="CreateSrcFileDialog_FILE_NAME" value="1" type="GuiHandlerData"/>
+<property name="FileSetPanel_FILE_SET_PANEL_TREE" value="2" type="GuiHandlerData"/>
+<property name="FlowNavigatorTreePanel_FLOW_NAVIGATOR_TREE" value="3" type="GuiHandlerData"/>
+<property name="MainMenuMgr_EDIT" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FILE" value="8" type="GuiHandlerData"/>
+<property name="MainMenuMgr_FLOW" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_HELP" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_PROJECT" value="2" type="GuiHandlerData"/>
+<property name="MainMenuMgr_REPORTS" value="10" type="GuiHandlerData"/>
+<property name="MainMenuMgr_TOOLS" value="10" type="GuiHandlerData"/>
+<property name="MainMenuMgr_VIEW" value="4" type="GuiHandlerData"/>
+<property name="MainMenuMgr_WINDOW" value="8" type="GuiHandlerData"/>
+<property name="MainWinMenuMgr_LAYOUT" value="2" type="GuiHandlerData"/>
+<property name="PACommandNames_IP_PACKAGER_WIZARD" value="1" type="GuiHandlerData"/>
+<property name="PACommandNames_NEW_PROJECT" value="1" type="GuiHandlerData"/>
+<property name="PackagerStepsPanel_PACKAGER_STEPS_LIST" value="1" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_CHOOSE_PROJECT_LOCATION" value="2" type="GuiHandlerData"/>
+<property name="ProjectNameChooser_PROJECT_NAME" value="1" type="GuiHandlerData"/>
+<property name="ReviewContentPanel_PACKAGE_IP" value="4" type="GuiHandlerData"/>
+<property name="SrcChooserPanel_CREATE_FILE" value="2" type="GuiHandlerData"/>
+<property name="SystemTab_REPORT_IP_STATUS" value="1" type="GuiHandlerData"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="183" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="134" type="TclMode"/>
+</item>
+</section>
+</application>
+</document>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.hw/tri_state_ctrl.lpr
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.hw/tri_state_ctrl.lpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)                     -->
+<!--                                                              -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/component.xml
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/component.xml
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/tri_state_ctrl.vhd
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/tri_state_ctrl.vhd
+--=======================================================================
+--! @tri_state_ctrl.vhd
+--=======================================================================
+-------------------------------------------------------------------------
+--! @brief
+--! Control the activation of the tri state data line in the SPI 
+-------------------------------------------------------------------------
+--! @details
+--!
+-------------------------------------------------------------------------
+--! @version
+--! 0.1 | mc | 07.10.2020
+--!
+--! @author
+--! mc : Juan Fernandez, Seven Solutions SL
+-------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------
+-- ENTITY
+-------------------------------------------------------------------------
+entity ent_tri_state_ctrl is
+   port (
+    --------------------------------------------------------------------
+    -- Clocking ports
+    --------------------------------------------------------------------
+    clk_i : in  std_logic;
+    --------------------------------------------------------------------
+    -- Data ports
+    --------------------------------------------------------------------
+    cs_i      : in  std_logic;
+    sdata_i   : in  std_logic;
+    sdata_t_o : out std_logic
+  );
+  attribute keep_hierarchy : string;
+  attribute keep_hierarchy of ent_tri_state_ctrl : entity is "true";
+end ent_tri_state_ctrl;
+
+------------------------------------------------------------------------
+-- ARCHITECTURE
+------------------------------------------------------------------------
+architecture arch_tri_state_ctrl of ent_tri_state_ctrl is
+
+------------------------------------------------------------------------
+-- 1. COMPONENTS DECLARATION
+------------------------------------------------------------------------
+------------------------------------------------------------------------
+-- 2. CONSTANTS
+------------------------------------------------------------------------
+------------------------------------------------------------------------
+-- 3. TYPES
+------------------------------------------------------------------------
+ 
+
+------------------------------------------------------------------------
+-- 4. SIGNAL DECLARATION
+------------------------------------------------------------------------
+  signal s_count_cycles: integer := 0;
+  signal s_sdata_t     : std_logic := '0';
+  signal s_is_a_read   : std_logic := '0';
+------------------------------------------------------------------------
+-- 5. ATTRIBUTES
+------------------------------------------------------------------------
+ 
+------------------------------------------------------------------------
+-- BEGIN
+------------------------------------------------------------------------
+begin
+
+------------------------------------------------------------------------
+-- 1. COMPONENT INSTANTIATION
+------------------------------------------------------------------------
+------------------------------------------------------------------------
+-- 2. LOGIC
+------------------------------------------------------------------------
+sdata_t_o <= s_sdata_t;
+------------------------------------------------------------------------
+-- 3. PROCESS
+------------------------------------------------------------------------
+------------------------------------------------------------------------
+-- 
+------------------------------------------------------------------------
+p_count : process(clk_i, cs_i)
+begin
+  if cs_i = '1' then
+    s_count_cycles <=  0;
+    s_is_a_read    <= '0';
+  else
+    if rising_edge(clk_i) then
+      s_count_cycles <= s_count_cycles + 1;
+      -- at the first rising edge we check if it is a read operation
+      if s_count_cycles = 0 then
+        if sdata_i = '1' then
+          s_is_a_read <= '1';
+        else
+          s_is_a_read <= '0';
+        end if;
+      end if;
+    end if;
+  end if;
+end process;
+
+------------------------------------------------------------------------
+-- 
+------------------------------------------------------------------------
+p_tri_state : process(clk_i, cs_i)
+begin
+  if cs_i = '1' then
+    s_sdata_t      <= '0';
+  else
+    if falling_edge(clk_i) then
+      -- after 16 cycles if it was a read we rise the t signal to change the tristate buffer and
+      -- allow the input of data
+      if s_count_cycles = 16 and s_is_a_read = '1' then
+        s_sdata_t <= '1';
+      end if;
+    end if;
+  end if;
+end process;
+
+------------------------------------------------------------------------
+-- END ARCHITECTURE
+------------------------------------------------------------------------
+end;
\ No newline at end of file
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/xgui/ent_tri_state_ctrl_v1_0.tcl
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/xgui/ent_tri_state_ctrl_v1_0.tcl
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/xgui/tri_state_ctrl_v1_0.tcl
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.srcs/sources_1/new/xgui/tri_state_ctrl_v1_0.tcl
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+
--- a/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.xpr
+++ b/FCWR_tests/fmc_support_gw/vivado_ip/tri_state_ctrl/tri_state_ctrl.xpr
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2018.3 (64-bit)              -->
+<!--                                                         -->
+<!-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.   -->
+
+<Project Version="7" Minor="39" Path="/home/jorge7s/workspace/WRS4_fmc/gw/fmc_support/ip_cores/tri_state_ctrl/tri_state_ctrl.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="7592cbdcc9484a3aa83ebadf7ab14cbd"/>
+    <Option Name="Part" Val="xczu9eg-ffvb1156-2-e"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="TargetLanguage" Val="VHDL"/>
+    <Option Name="BoardPart" Val="xilinx.com:zcu102:part0:3.2"/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PSRCDIR/sources_1/new"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="DSAVendor" Val="xilinx"/>
+    <Option Name="DSABoardId" Val="zcu102"/>
+    <Option Name="DSANumComputeUnits" Val="60"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sources_1/new/tri_state_ctrl.vhd">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/component.xml">
+        <FileInfo SFType="IPXACT"/>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ent_tri_state_ctrl"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="ent_tri_state_ctrl"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="IES">
+      <Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="10">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xczu9eg-ffvb1156-2-e" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2018">
+          <Desc>Vivado Synthesis Defaults</Desc>
+        </StratHandle>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xczu9eg-ffvb1156-2-e" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2018">
+          <Desc>Default settings for Implementation.</Desc>
+        </StratHandle>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2018"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+    </Run>
+  </Runs>
+  <Board>
+    <Jumpers/>
+  </Board>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+  <BootPmcSettings Version="1" Minor="0">
+    <Parameters/>
+  </BootPmcSettings>
+</Project>