Commit b4786303 authored by Jorge Machado's avatar Jorge Machado

Allow access from PS to the wb memory space

parent 997e32e4
......@@ -659,7 +659,7 @@ proc create_root_design { parentCell } {
# Create instance: axi_interconnect_0, and set properties
set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ]
set_property -dict [ list \
CONFIG.NUM_MI {5} \
CONFIG.NUM_MI {6} \
] $axi_interconnect_0
# Create instance: clk_wiz_0, and set properties
......@@ -700,6 +700,9 @@ proc create_root_design { parentCell } {
# Create instance: rst_ps8, and set properties
set rst_ps8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8 ]
# Create instance: rst_ps9, and set properties
set rst_ps9 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps9 ]
# Create instance: sfp_axi_gpio, and set properties
set sfp_axi_gpio [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 sfp_axi_gpio ]
......@@ -2180,6 +2183,7 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net axi_interconnect_0_M02_AXI [get_bd_intf_pins axi_interconnect_0/M02_AXI] [get_bd_intf_pins pll_gm/S_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M03_AXI [get_bd_intf_pins axi_iic_si549/S_AXI] [get_bd_intf_pins axi_interconnect_0/M03_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M04_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins axi_interconnect_0/M04_AXI]
connect_bd_intf_net -intf_net axi_interconnect_0_M05_AXI [get_bd_intf_pins axi_interconnect_0/M05_AXI] [get_bd_intf_pins wrcore_1g_fmc_0/S_AXI_REGS]
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins axi_interconnect_0/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
# Create port connections
......@@ -2211,7 +2215,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net clk_125_p_1 [get_bd_ports clk_125_p] [get_bd_pins wrcore_1g_fmc_0/clk_125mhz_p_i]
connect_bd_net -net clk_300_n_1 [get_bd_ports clk_300_n] [get_bd_pins util_ds_buf_2/IBUF_DS_N]
connect_bd_net -net clk_300_p_1 [get_bd_ports clk_300_p] [get_bd_pins util_ds_buf_2/IBUF_DS_P]
connect_bd_net -net clk_wiz_0_clk_out2 [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins wrcore_1g_fmc_0/clk_sys_i]
connect_bd_net -net clk_wiz_0_clk_out2 [get_bd_pins axi_interconnect_0/M05_ACLK] [get_bd_pins clk_wiz_0/clk_out2] [get_bd_pins rst_ps9/slowest_sync_clk] [get_bd_pins wrcore_1g_fmc_0/clk_sys_i]
connect_bd_net -net dac_controller_1_dac_cs_n_o [get_bd_ports pll_gm_csb] [get_bd_pins pll_gm/pll_gm_csb]
connect_bd_net -net dac_controller_1_dac_sclk_o [get_bd_ports pll_gm_sck] [get_bd_pins pll_gm/pll_gm_sck]
connect_bd_net -net dac_controller_1_dac_sdata_o [get_bd_ports pll_gm_sdi] [get_bd_pins pll_gm/pll_gm_sdi]
......@@ -2238,6 +2242,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net reset_or_Res [get_bd_pins reset_or/Res] [get_bd_pins wrcore_1g_fmc_0/button_rst_i]
connect_bd_net -net rst_ps8_0_49M_peripheral_aresetn [get_bd_pins HMC/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_iic_si549/s_axi_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/M01_ARESETN] [get_bd_pins axi_interconnect_0/M02_ARESETN] [get_bd_pins axi_interconnect_0/M03_ARESETN] [get_bd_pins axi_interconnect_0/M04_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins pll_gm/S_AXI_ARESETN] [get_bd_pins rst_ps8/peripheral_aresetn] [get_bd_pins sfp_axi_gpio/s_axi_aresetn]
connect_bd_net -net rst_ps8_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins rst_ps8/interconnect_aresetn]
connect_bd_net -net rst_ps9_peripheral_aresetn [get_bd_pins axi_interconnect_0/M05_ARESETN] [get_bd_pins rst_ps9/peripheral_aresetn]
connect_bd_net -net sfp_axi_gpio_gpio_io_o [get_bd_pins HMC/Din] [get_bd_pins pll_gm/Din] [get_bd_pins sfp_axi_gpio/gpio_io_o] [get_bd_pins xlslice_0/Din] [get_bd_pins xlslice_3/Din]
connect_bd_net -net sfp_detect_1 [get_bd_ports sfp_detect] [get_bd_pins wrcore_1g_fmc_0/gtp0_mod_def0_b] [get_bd_pins xlconcat_0/In0]
connect_bd_net -net sfp_los_tx_fault_1 [get_bd_ports sfp_los_tx_fault] [get_bd_pins wrcore_1g_fmc_0/gtp0_tx_fault_i] [get_bd_pins xlconcat_0/In1]
......@@ -2271,7 +2276,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlslice_0_Dout [get_bd_ports sfp_tx_disable] [get_bd_pins xlslice_0/Dout]
connect_bd_net -net xlslice_3_Dout [get_bd_ports term_en] [get_bd_pins xlslice_3/Dout]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_ports PMOD0_3] [get_bd_pins HMC/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_iic_si549/s_axi_aclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/M01_ACLK] [get_bd_pins axi_interconnect_0/M02_ACLK] [get_bd_pins axi_interconnect_0/M03_ACLK] [get_bd_pins axi_interconnect_0/M04_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins pll_gm/S_AXI_ACLK] [get_bd_pins rst_ps8/slowest_sync_clk] [get_bd_pins sfp_axi_gpio/s_axi_aclk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8/ext_reset_in] [get_bd_pins rst_ps9/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
# Create address segments
create_bd_addr_seg -range 0x00001000 -offset 0xA0007000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg
......@@ -2279,6 +2284,7 @@ proc create_root_design { parentCell } {
create_bd_addr_seg -range 0x00010000 -offset 0xA0010000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs HMC/axi_quad_spi_0/AXI_LITE/Reg] SEG_axi_quad_spi_0_Reg
create_bd_addr_seg -range 0x00010000 -offset 0xA0020000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs pll_gm/axi_quad_spi_0/AXI_LITE/Reg] SEG_axi_quad_spi_0_Reg2
create_bd_addr_seg -range 0x00001000 -offset 0xA0003000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs sfp_axi_gpio/S_AXI/Reg] SEG_sfp_axi_gpio_Reg
create_bd_addr_seg -range 0x01000000 -offset 0xA1000000 [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs wrcore_1g_fmc_0/S_AXI_REGS/reg0] SEG_wrcore_1g_fmc_0_reg0
# Restore current instance
......
......@@ -4,6 +4,204 @@
<spirit:library>user</spirit:library>
<spirit:name>wrcore_1g_fmc</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>S_AXI_REGS</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
<spirit:slave>
<spirit:memoryMapRef spirit:memoryMapRef="S_AXI_REGS"/>
</spirit:slave>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_awaddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_awvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>AWREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_awready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_wdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WSTRB</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_wstrb</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_wlast</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_wvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_wready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_bresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_bvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>BREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_bready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARADDR</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_araddr</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_arvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>ARREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_arready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RDATA</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_rdata</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RRESP</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_rresp</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RLAST</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_rlast</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RVALID</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_rvalid</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RREADY</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>S_AXI_REGS_rready</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_sys_i</spirit:name>
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
<spirit:slave/>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_sys_i</spirit:name>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:parameters>
<spirit:parameter>
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
<spirit:value spirit:id="BUSIFPARAM_VALUE.CLK_SYS_I.ASSOCIATED_BUSIF">S_AXI_REGS</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:memoryMaps>
<spirit:memoryMap>
<spirit:name>S_AXI_REGS</spirit:name>
<spirit:addressBlock>
<spirit:name>reg0</spirit:name>
<spirit:baseAddress spirit:format="bitString" spirit:resolve="user" spirit:bitStringLength="32">0</spirit:baseAddress>
<spirit:range spirit:format="long" spirit:resolve="user" spirit:minimum="4096" spirit:rangeType="long">4294967296</spirit:range>
<spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
<spirit:usage>register</spirit:usage>
</spirit:addressBlock>
</spirit:memoryMap>
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
......@@ -21,7 +219,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c75d9562</spirit:value>
<spirit:value>f077c235</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -40,7 +238,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>viewChecksum</spirit:name>
<spirit:value>c75d9562</spirit:value>
<spirit:value>f077c235</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
......@@ -612,6 +810,71 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>len_conn_scl_b</spirit:name>
<spirit:wire>
<spirit:direction>inout</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>len_conn_sda_b</spirit:name>
<spirit:wire>
<spirit:direction>inout</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>debug0_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>debug1_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>debug3_o</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>led0_o</spirit:name>
<spirit:wire>
......@@ -664,6 +927,311 @@
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_arvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_awvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_bready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_rready</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_wlast</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="bitString" spirit:bitStringLength="1">0x1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_wvalid</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_araddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_awaddr</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_wdata</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_wstrb</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
<spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_arready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_awready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_bvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_rlast</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_rvalid</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_wready</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_bresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_rresp</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">1</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:name>S_AXI_REGS_rdata</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long">31</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_anylanguagesynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
</spirit:port>
</spirit:ports>
<spirit:modelParameters>
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
......@@ -745,27 +1313,31 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/disparity_gen_pkg.vhd</spirit:name>
<spirit:name>src/genram_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/genram_pkg.vhd</spirit:name>
<spirit:name>src/wishbone_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/gencores_pkg.vhd</spirit:name>
<spirit:name>src/axi4_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/dmtd_phase_meas.vhd</spirit:name>
<spirit:name>src/disparity_gen_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/dmtd_with_deglitcher.vhd</spirit:name>
<spirit:name>src/gencores_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wishbone_pkg.vhd</spirit:name>
<spirit:name>src/dmtd_phase_meas.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/dmtd_with_deglitcher.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
......@@ -1056,6 +1628,10 @@
<spirit:name>src/uart_baud_gen.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wb_axi4lite_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wb_onewire_master.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1068,6 +1644,14 @@
<spirit:name>src/wb_slave_adapter.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_eic.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_fifo_sync.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wrc_syscon_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1120,6 +1704,10 @@
<spirit:name>src/wrc_syscon_wb.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/xwb_axi4lite_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/xwb_crossbar.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1183,15 +1771,7 @@
<spirit:file>
<spirit:name>src/zcu102.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_eic.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_fifo_sync.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:userFileType>CHECKSUM_58cc5162</spirit:userFileType>
<spirit:userFileType>CHECKSUM_bae86fe3</spirit:userFileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
......@@ -1275,27 +1855,31 @@
<spirit:fileType>verilogSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/disparity_gen_pkg.vhd</spirit:name>
<spirit:name>src/genram_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/genram_pkg.vhd</spirit:name>
<spirit:name>src/wishbone_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/gencores_pkg.vhd</spirit:name>
<spirit:name>src/axi4_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/dmtd_phase_meas.vhd</spirit:name>
<spirit:name>src/disparity_gen_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/dmtd_with_deglitcher.vhd</spirit:name>
<spirit:name>src/gencores_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wishbone_pkg.vhd</spirit:name>
<spirit:name>src/dmtd_phase_meas.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/dmtd_with_deglitcher.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
......@@ -1586,6 +2170,10 @@
<spirit:name>src/uart_baud_gen.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wb_axi4lite_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wb_onewire_master.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1598,6 +2186,14 @@
<spirit:name>src/wb_slave_adapter.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_eic.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_fifo_sync.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wrc_syscon_pkg.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1650,6 +2246,10 @@
<spirit:name>src/wrc_syscon_wb.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/xwb_axi4lite_bridge.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/xwb_crossbar.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
......@@ -1714,14 +2314,6 @@
<spirit:name>src/zcu102.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_eic.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
<spirit:file>
<spirit:name>src/wbgen2_fifo_sync.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
</spirit:file>
</spirit:fileSet>
<spirit:fileSet>
<spirit:name>xilinx_anylanguagebehavioralsimulation_xilinx_com_ip_gtwizard_ultrascale_1_7__ref_view_fileset</spirit:name>
......@@ -1758,354 +2350,50 @@
<spirit:vendorExtensions>
<xilinx:coreExtensions>
<xilinx:supportedFamilies>
<xilinx:family xilinx:lifeCycle="Production">virtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qvirtex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qkintex7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qkintex7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">artix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">artix7l</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">aartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qartix7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">zynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">qzynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">azynq</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">spartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">aspartan7</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">virtexu</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">zynquplus</xilinx:family>
<xilinx:family xilinx:lifeCycle="Production">kintexu</xilinx:family>
</xilinx:supportedFamilies>
<xilinx:taxonomies>
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
</xilinx:taxonomies>
<xilinx:displayName>wrcore_1g_fmc</xilinx:displayName>
<xilinx:definitionSource>package_project</xilinx:definitionSource>
<xilinx:coreRevision>18</xilinx:coreRevision>
<xilinx:coreRevision>1</xilinx:coreRevision>
<xilinx:upgrades>
<xilinx:canUpgradeFrom>user.org:user:zcu102:1.0</xilinx:canUpgradeFrom>
</xilinx:upgrades>
<xilinx:coreCreationDateTime>2021-07-05T14:38:38Z</xilinx:coreCreationDateTime>
<xilinx:coreCreationDateTime>2021-08-24T11:48:33Z</xilinx:coreCreationDateTime>
<xilinx:tags>
<xilinx:tag xilinx:name="nopcore"/>
<xilinx:tag xilinx:name="ui.data.coregen.dd@77a60c71_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@28449771_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e5cc07d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66e00ba4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@77af47b5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@501dbf34_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5c892a4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@15d76a76_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@f3c4fe4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2e40d36_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@64610e83_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@294666d6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6468a2c0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@38e613a3_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5433a072_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@28417715_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@41099933_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@49d9c9aa_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@27d2812c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ad15d4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7bea0837_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@608d1f9f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@105e59af_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@244ea218_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4f1fc362_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@74d9ea29_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@aaf36a0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4fbf1119_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1c59068c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@57571135_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19223a36_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6dcf55f1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2c69081_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66cfd488_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e49fa6c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ac4bce4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7933e7e4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d6d6b78_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@307f45c1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@260d5710_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1d49933a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@334bb041_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@528d0811_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@146a5f00_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e1a1a6b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@72f8dd89_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@17503ef2_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@66622432_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@50d4fe16_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f1f7409_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4dda9212_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@e8d5f16_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@26fb7fb6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1a5881f7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6181da4f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@161dd8b1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e219fd9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3e2a628_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2bacda5c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e18e91a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6f0ff930_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@575bcd8f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@27bf5bd0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@43d5b56e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1bc7247a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d0a5699_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ad98a03_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5f280786_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5aa7e344_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@20e6028d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4c5be558_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@654d3b25_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ee09ead_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d1869ee_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3dbd6a4f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@641e6af9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19271cb9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@63d3997_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6c1c26ec_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3572bb64_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ec039d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5c27eb9c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@f29b83f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4a3747ce_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2b444b72_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7e3bd9d8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@578562a1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@25499a3a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2476ffa7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ccccaf0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d596999_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@520ba0fe_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@67e3fa68_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@78bf13bd_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@37c89cfd_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@14c7f30a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7053a089_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@57ae79c5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@36638637_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@23af6c75_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@50fbbe7b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@614c97c5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6d6aace7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@430fe85b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@29b0447_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@13b80a34_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4259f415_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2de3ab22_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5f2ea5f7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@727bf4b9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c455f31_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@226f0728_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@77126950_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5f23a2f5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3407e04e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5692934_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5acd7f84_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2aa5d4fd_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f73e07f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@37f067f8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@244cf93e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@536cde07_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@73357c0e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7cb09db4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6bfefa97_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5e6a056f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@21dbe78a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7bb3482a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4b74cc69_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1a76df88_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@864b6a2_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2ad5c91b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@27e69397_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@65032849_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3860bb4a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@210fe29d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c5eebe9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3f729831_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5ad7eedd_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@476eee5d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2e6a25a8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@10a02deb_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4f462373_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@156c7351_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@77694f8c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2306acbf_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@78384341_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@11905596_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4b29c7d6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@657bda49_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2ed2cb67_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1007cbfe_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@43d1c79e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@30025b2f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4554f300_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@759b5cb8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@53960906_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@47a14a13_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@605f4acb_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@8f70421_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19884ea6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@76666443_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3b6c9b28_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@383d1b28_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@924a760_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7cf5f96b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6f8e2ca_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@45fa4240_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@db19785_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2cf63af9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4410eb76_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7fedd4c8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@736b2670_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@347b65c5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@428dc5d7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@57269fe6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5e4c9645_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2d3a52c7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@68606236_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@23f043b3_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7afccd90_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4a51cf09_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@d9d655a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@281c0c64_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ba62a8a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ba12c9d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@278f47c1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ae17348_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@33abfefe_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ab98323_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@652ab8fc_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@46b45cb4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4e92d43_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5445fc61_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e72cbb0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6ae9fd39_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@10b66a3a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@386cbb80_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@10fbdb5b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@23464a64_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@289a6dad_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@59c8f9db_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@185ea63_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@213bb3a4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@458cd4fb_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@53bb7ee0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2fd20ecc_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6114e3bc_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5db82b6e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@170e5fa8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19fb3674_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6750942d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@8ae57f8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@74b109bf_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@29611030_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@363cf32f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@297c6687_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4ed7300a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1319bf93_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6f19403_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@42d16dc1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@23a529b3_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@25737f5c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4fd1228d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@333a7ba1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5a9fb8a5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5cc49001_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3228d01f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@eeeea1e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@31a1bbce_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5fbdbcf8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@552d581b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@31c0040b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e6aeab5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3d691617_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@290fe98f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7ffe479_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@32a3e819_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@19d46c10_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@727850ca_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@22300193_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@e74f767_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4d69e1b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@12d33efb_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@430523a5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3e38424b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@53266cc_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@669a7d75_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@75eca689_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@f0c6d6a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1c820254_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2ba0c8f0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@65c1532d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@527901a1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@406ecec6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6b3cc383_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4c16189c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5ec0c8e7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5c4eeaac_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@67de39ab_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@76dc7757_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@43f4cff1_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1d3fa1ea_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6e793926_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3c27594a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4227702e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@3ef4f58a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@9e57158_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@339a5f73_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7d579e57_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@549791d0_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5a81a094_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@333656ce_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@448ed5d2_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@e43a6f8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@58d07a02_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@d5d7672_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@372570d7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c8f9760_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@61bd2911_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@e80d2b6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4505fa01_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@50b17555_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@67ef3a48_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2f51af61_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@45e54790_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4f523788_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@13a55a6a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@bf28a60_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@295dde87_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@30242b1a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@61d23c4b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@af3eda5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1530a2b_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1113c8f5_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@76f3e821_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@6cad5aa_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2ac60bca_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@187aaf54_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@640705ea_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1aaade5c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@300b4f8f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@60f6c73_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@29fc808d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5bdb6a27_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7bd7aa05_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7c0b3ac4_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5012dab7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@aee3f8f_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@adf02a8_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@69b36f95_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw/fmc_support_1g_test/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@f1edde9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@4c557739_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7d09045e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@54c48f08_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5ee75c5d_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1fda1221_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@188ead7c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@2b4e5b11_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5850766c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@cc8790e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@7f1082d9_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@5d5acffe_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@303e866a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@36ef11bd_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@794b949_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@53132941_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@73e4d92e_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@425bcfa6_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@718aa246_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@300a736c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@113b8f5c_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1a27d5c7_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
<xilinx:tag xilinx:name="ui.data.coregen.dd@1e6a3e1a_ARCHIVE_LOCATION">/opt/workspace_opt/fmc_gw_mem_access/FCWR_tests/fmc_support_gw/vivado_ip/wrpc</xilinx:tag>
</xilinx:tags>
</xilinx:coreExtensions>
<xilinx:packagingInfo>
<xilinx:xilinxVersion>2018.3</xilinx:xilinxVersion>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5ebfd3a4"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="7f35c31b"/>
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="cc4e8748"/>
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="839552a9"/>
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="ed195b55"/>
<xilinx:checksum xilinx:scope="ports" xilinx:value="ad4eae5a"/>
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c66d56b3"/>
<xilinx:checksum xilinx:scope="parameters" xilinx:value="702472e0"/>
</xilinx:packagingInfo>
......
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge package
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : axi4_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.wishbone_pkg.all;
package axi4_pkg is
-- AXI4-Full interface, master output ports, 32 bits
type t_axi4_full_master_out_32 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARID : std_logic_vector (11 downto 0);
AWID : std_logic_vector (11 downto 0);
WID : std_logic_vector (11 downto 0);
ARBURST : std_logic_vector (1 downto 0);
ARLOCK : std_logic_vector (1 downto 0);
ARSIZE : std_logic_vector (2 downto 0);
AWBURST : std_logic_vector (1 downto 0);
AWLOCK : std_logic_vector (1 downto 0);
AWSIZE : std_logic_vector (2 downto 0);
ARPROT : std_logic_vector (2 downto 0);
AWPROT : std_logic_vector (2 downto 0);
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (31 downto 0);
ARCACHE : std_logic_vector (3 downto 0);
ARLEN : std_logic_vector (3 downto 0);
ARQOS : std_logic_vector (3 downto 0);
AWCACHE : std_logic_vector (3 downto 0);
AWLEN : std_logic_vector (3 downto 0);
AWQOS : std_logic_vector (3 downto 0);
WSTRB : std_logic_vector (3 downto 0);
end record;
-- AXI4-Full interface, master input ports, 32 bits
type t_axi4_full_master_in_32 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BID : std_logic_vector (11 downto 0);
RID : std_logic_vector (11 downto 0);
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (31 downto 0);
end record;
-- AXI4-Lite interface, master output ports, 32 bits
type t_axi4_lite_master_out_32 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (31 downto 0);
WSTRB : std_logic_vector (3 downto 0);
end record;
-- AXI4-Lite interface, master input ports, 32 bits
type t_axi4_lite_master_in_32 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (31 downto 0);
end record;
constant c_axi4_lite_default_master_in_32 : t_axi4_lite_master_in_32 :=
(
AWREADY => '0',
ARREADY => '0',
BVALID => '0',
RLAST => '0',
RVALID => '0',
WREADY => '0',
BRESP => "00",
RRESP => "00",
RDATA => (others => '0')
);
constant c_axi4_lite_default_master_out_32 : t_axi4_lite_master_out_32 :=
(
ARVALID => '0',
AWVALID => '0',
BREADY => '0',
RREADY => '0',
WLAST => '0',
WVALID => '0',
ARADDR => (others => '0'),
AWADDR => (others => '0'),
WDATA => (others => '0'),
WSTRB => (others => '0')
);
subtype t_axi4_lite_slave_in_32 is t_axi4_lite_master_out_32;
subtype t_axi4_lite_slave_out_32 is t_axi4_lite_master_in_32;
constant c_AXI4_RESP_OKAY : std_logic_vector(1 downto 0) := "00";
constant c_AXI4_RESP_EXOKAY : std_logic_vector(1 downto 0) := "01";
constant c_AXI4_RESP_SLVERR : std_logic_vector(1 downto 0) := "10";
constant c_AXI4_RESP_DECERR : std_logic_vector(1 downto 0) := "11";
function f_axi4_full_to_lite (
f : t_axi4_full_master_out_32
) return t_axi4_lite_master_out_32;
function f_axi4_lite_to_full (
l : t_axi4_lite_master_in_32
) return t_axi4_full_master_in_32;
component xwb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
axi4_slave_i : in t_axi4_lite_slave_in_32;
axi4_slave_o : out t_axi4_lite_slave_out_32;
wb_master_o : out t_wishbone_master_out;
wb_master_i : in t_wishbone_master_in);
end component xwb_axi4lite_bridge;
component wb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
ARVALID : in std_logic;
AWVALID : in std_logic;
BREADY : in std_logic;
RREADY : in std_logic;
WLAST : in std_logic;
WVALID : in std_logic;
ARADDR : in std_logic_vector (31 downto 0);
AWADDR : in std_logic_vector (31 downto 0);
WDATA : in std_logic_vector (31 downto 0);
WSTRB : in std_logic_vector (3 downto 0);
ARREADY : out std_logic;
AWREADY : out std_logic;
BVALID : out std_logic;
RLAST : out std_logic;
RVALID : out std_logic;
WREADY : out std_logic;
BRESP : out std_logic_vector (1 downto 0);
RRESP : out std_logic_vector (1 downto 0);
RDATA : out std_logic_vector (31 downto 0);
wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc : out std_logic;
wb_stb : out std_logic;
wb_we : out std_logic;
wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_err : in std_logic := '0';
wb_rty : in std_logic := '0';
wb_ack : in std_logic;
wb_stall : in std_logic
);
end component;
-- AXI4-Full interface, master output ports, 512 bits
type t_axi4_full_master_out_512 is record
ARVALID : std_logic;
AWVALID : std_logic;
BREADY : std_logic;
RREADY : std_logic;
WLAST : std_logic;
WVALID : std_logic;
ARID : std_logic_vector (11 downto 0);
AWID : std_logic_vector (11 downto 0);
ARBURST : std_logic_vector (1 downto 0);
ARLOCK : std_logic;
ARSIZE : std_logic_vector (2 downto 0);
AWBURST : std_logic_vector (1 downto 0);
AWLOCK : std_logic;
AWSIZE : std_logic_vector (2 downto 0);
ARPROT : std_logic_vector (2 downto 0);
AWPROT : std_logic_vector (2 downto 0);
ARADDR : std_logic_vector (31 downto 0);
AWADDR : std_logic_vector (31 downto 0);
WDATA : std_logic_vector (511 downto 0);
ARCACHE : std_logic_vector (3 downto 0);
ARLEN : std_logic_vector (7 downto 0);
ARQOS : std_logic_vector (3 downto 0);
AWCACHE : std_logic_vector (3 downto 0);
AWLEN : std_logic_vector (7 downto 0);
AWQOS : std_logic_vector (3 downto 0);
WSTRB : std_logic_vector (31 downto 0);
end record;
-- AXI4-Full interface, master input ports, 512 bits
type t_axi4_full_master_in_512 is record
ARREADY : std_logic;
AWREADY : std_logic;
BVALID : std_logic;
RLAST : std_logic;
RVALID : std_logic;
WREADY : std_logic;
BID : std_logic_vector (11 downto 0);
RID : std_logic_vector (11 downto 0);
BRESP : std_logic_vector (1 downto 0);
RRESP : std_logic_vector (1 downto 0);
RDATA : std_logic_vector (511 downto 0);
end record;
end package;
package body axi4_pkg is
function f_axi4_full_to_lite (
f : t_axi4_full_master_out_32
) return t_axi4_lite_master_out_32 is
variable l : t_axi4_lite_master_out_32;
begin
l.ARVALID := f.ARVALID;
l.AWVALID := f.AWVALID;
l.BREADY := f.BREADY;
l.RREADY := f.RREADY;
l.WLAST := f.WLAST;
l.WVALID := f.WVALID;
l.ARADDR := f.ARADDR;
l.AWADDR := f.AWADDR;
l.WDATA := f.WDATA;
l.WSTRB := f.WSTRB;
return l;
end f_axi4_full_to_lite;
function f_axi4_lite_to_full (
l : t_axi4_lite_master_in_32
) return t_axi4_full_master_in_32 is
variable f : t_axi4_full_master_in_32;
begin
f.ARREADY := l.ARREADY;
f.AWREADY := l.AWREADY;
f.BVALID := l.BVALID;
f.RLAST := l.RLAST;
f.RVALID := l.RVALID;
f.WREADY := l.WREADY;
f.BID := (others => '0');
f.RID := (others => '0');
f.BRESP := l.BRESP;
f.RRESP := l.RRESP;
f.RDATA := l.RDATA;
return f;
end f_axi4_lite_to_full;
end package body;
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : wb_axi4lite_bridge.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
use work.wishbone_pkg.all;
entity wb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
ARVALID : in std_logic;
AWVALID : in std_logic;
BREADY : in std_logic;
RREADY : in std_logic;
WLAST : in std_logic := '1';
WVALID : in std_logic;
ARADDR : in std_logic_vector (31 downto 0);
AWADDR : in std_logic_vector (31 downto 0);
WDATA : in std_logic_vector (31 downto 0);
WSTRB : in std_logic_vector (3 downto 0);
ARREADY : out std_logic;
AWREADY : out std_logic;
BVALID : out std_logic;
RLAST : out std_logic;
RVALID : out std_logic;
WREADY : out std_logic;
BRESP : out std_logic_vector (1 downto 0);
RRESP : out std_logic_vector (1 downto 0);
RDATA : out std_logic_vector (31 downto 0);
wb_adr : out std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_m2s : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc : out std_logic;
wb_stb : out std_logic;
wb_we : out std_logic;
wb_dat_s2m : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_err : in std_logic := '0';
wb_rty : in std_logic := '0';
wb_ack : in std_logic;
wb_stall : in std_logic
);
end wb_axi4lite_bridge;
architecture rtl of wb_axi4lite_bridge is
signal axi_in : t_axi4_lite_master_out_32;
signal axi_out : t_axi4_lite_master_in_32;
signal wb_in : t_wishbone_master_in;
signal wb_out : t_wishbone_master_out;
begin
axi_in.ARVALID <= ARVALID;
axi_in.AWVALID <= AWVALID;
axi_in.BREADY <= BREADY;
axi_in.RREADY <= RREADY;
axi_in.WLAST <= WLAST;
axi_in.WVALID <= WVALID;
axi_in.ARADDR <= ARADDR;
axi_in.AWADDR <= AWADDR;
axi_in.WDATA <= WDATA;
axi_in.WSTRB <= WSTRB;
ARREADY <= axi_out.ARREADY;
AWREADY <= axi_out.AWREADY;
BVALID <= axi_out.BVALID;
RLAST <= axi_out.RLAST;
RVALID <= axi_out.RVALID;
WREADY <= axi_out.WREADY;
BRESP <= axi_out.BRESP;
RRESP <= axi_out.RRESP;
RDATA <= axi_out.RDATA;
wb_adr <= wb_out.adr;
wb_dat_m2s <= wb_out.dat;
wb_stb <= wb_out.stb;
wb_sel <= wb_out.sel;
wb_cyc <= wb_out.cyc;
wb_we <= wb_out.we;
wb_in.err <= wb_err;
wb_in.rty <= wb_rty;
wb_in.ack <= wb_ack;
wb_in.stall <= wb_stall;
wb_in.dat <= wb_dat_s2m;
U_Wrapped_Bridge : xwb_axi4lite_bridge
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
axi4_slave_i => axi_in,
axi4_slave_o => axi_out,
wb_master_o => wb_out,
wb_master_i => wb_in);
end rtl;
-------------------------------------------------------------------------------
-- Title : AXI4Lite-to-WB bridge wrapper
-- Project : General Cores
-------------------------------------------------------------------------------
-- File : xwb_axi4lite_bridge.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Platform : FPGA-generics
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
--
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 0.51 (the "License") (which enables you, at your option,
-- to treat this file as licensed under the Apache License 2.0); you may not
-- use this file except in compliance with the License. You may obtain a copy
-- of the License at http://solderpad.org/licenses/SHL-0.51.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi4_pkg.all;
use work.wishbone_pkg.all;
entity xwb_axi4lite_bridge is
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
axi4_slave_i : in t_axi4_lite_slave_in_32;
axi4_slave_o : out t_axi4_lite_slave_out_32;
wb_master_o : out t_wishbone_master_out;
wb_master_i : in t_wishbone_master_in
);
end xwb_axi4lite_bridge;
architecture rtl of xwb_axi4lite_bridge is
constant c_timeout : integer := 256;
type t_state is
(IDLE, ISSUE_WRITE, ISSUE_READ, COMPLETE_WRITE, COMPLETE_READ, WAIT_ACK_READ, WAIT_ACK_WRITE, RESPONSE_READ, RESPONSE_WRITE);
signal state : t_state;
signal count : unsigned(10 downto 0);
begin
process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
axi4_slave_o <= c_axi4_lite_default_master_in_32;
wb_master_o.cyc <= '0';
state <= IDLE;
else
case state is
when IDLE =>
wb_master_o.cyc <= '0';
axi4_slave_o.ARREADY <= '1';
axi4_slave_o.AWREADY <= '1';
axi4_slave_o.WREADY <= '0';
axi4_slave_o.BVALID <= '0';
axi4_slave_o.BRESP <= (others => 'X');
axi4_slave_o.RDATA <= (others => 'X');
axi4_slave_o.RRESP <= (others => 'X');
axi4_slave_o.RVALID <= '0';
axi4_slave_o.RLAST <= '0';
if (axi4_slave_i.AWVALID = '1') then
state <= ISSUE_WRITE;
wb_master_o.adr <= axi4_slave_i.AWADDR;
elsif (axi4_slave_i.ARVALID = '1') then
state <= ISSUE_READ;
wb_master_o.adr <= axi4_slave_i.ARADDR;
end if;
when ISSUE_WRITE =>
wb_master_o.cyc <= '1';
wb_master_o.we <= '1';
axi4_slave_o.WREADY <= '1';
if (axi4_slave_i.WVALID = '1') then
wb_master_o.stb <= '1';
wb_master_o.sel <= axi4_slave_i.WSTRB;
wb_master_o.dat <= axi4_slave_i.WDATA;
state <= COMPLETE_WRITE;
end if;
when ISSUE_READ =>
wb_master_o.cyc <= '1';
wb_master_o.stb <= '1';
wb_master_o.we <= '0';
axi4_slave_o.RVALID <= '0';
axi4_slave_o.RLAST <= '0';
state <= COMPLETE_READ;
when COMPLETE_READ =>
if (wb_master_i.stall = '0') then
wb_master_o.stb <= '0';
if (wb_master_i.ack = '1') then
state <= IDLE;
axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
axi4_slave_o.RDATA <= wb_master_i.dat;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
wb_master_o.cyc <= '0';
else
state <= WAIT_ACK_READ;
count <= (others => '0');
end if;
end if;
when COMPLETE_WRITE =>
if (wb_master_i.stall = '0') then
wb_master_o.stb <= '0';
if (wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
wb_master_o.cyc <= '0';
else
state <= WAIT_ACK_WRITE;
count <= (others => '0');
end if;
end if;
when WAIT_ACK_WRITE =>
if (wb_master_i.ack = '1') then
state <= RESPONSE_WRITE;
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BRESP <= c_AXI4_RESP_OKAY;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= RESPONSE_WRITE;
axi4_slave_o.BVALID <= '1';
axi4_slave_o.BRESP <= c_AXI4_RESP_SLVERR;
wb_master_o.cyc <= '0';
end if;
count <= count + 1;
when WAIT_ACK_READ =>
if (wb_master_i.ack = '1') then
state <= RESPONSE_READ;
axi4_slave_o.RRESP <= c_AXI4_RESP_OKAY;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
axi4_slave_o.RDATA <= wb_master_i.dat;
wb_master_o.cyc <= '0';
elsif count = c_timeout then
state <= RESPONSE_READ;
axi4_slave_o.RRESP <= c_AXI4_RESP_SLVERR;
axi4_slave_o.RVALID <= '1';
axi4_slave_o.RLAST <= '1';
axi4_slave_o.RDATA <= (others => 'X');
wb_master_o.cyc <= '0';
end if;
count <= count + 1;
when RESPONSE_WRITE =>
if (axi4_slave_i.BREADY = '1') then
axi4_slave_o.BVALID <= '0';
state <= IDLE;
end if;
when RESPONSE_READ =>
if (axi4_slave_i.RREADY = '1') then
axi4_slave_o.RVALID <= '0';
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end rtl;
......@@ -16,6 +16,8 @@ use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
use work.axi4_pkg.all;
entity zcu102 is
generic
(
......@@ -119,7 +121,30 @@ entity zcu102 is
-- Voltage converter enabling pin
voltage_conv_en_o : out std_logic;
clk_125mhz_o : out std_logic
clk_125mhz_o : out std_logic;
-- System registers access (AXI4Lite-Slave)
S_AXI_REGS_arvalid : in std_logic;
S_AXI_REGS_awvalid : in std_logic;
S_AXI_REGS_bready : in std_logic;
S_AXI_REGS_rready : in std_logic;
S_AXI_REGS_wlast : in std_logic := '1';
S_AXI_REGS_wvalid : in std_logic;
S_AXI_REGS_araddr : in std_logic_vector (31 downto 0);
S_AXI_REGS_awaddr : in std_logic_vector (31 downto 0);
S_AXI_REGS_wdata : in std_logic_vector (31 downto 0);
S_AXI_REGS_wstrb : in std_logic_vector (3 downto 0);
S_AXI_REGS_arready : out std_logic;
S_AXI_REGS_awready : out std_logic;
S_AXI_REGS_bvalid : out std_logic;
S_AXI_REGS_rlast : out std_logic;
S_AXI_REGS_rvalid : out std_logic;
S_AXI_REGS_wready : out std_logic;
S_AXI_REGS_bresp : out std_logic_vector (1 downto 0);
S_AXI_REGS_rresp : out std_logic_vector (1 downto 0);
S_AXI_REGS_rdata : out std_logic_vector (31 downto 0)
);
end zcu102;
......@@ -162,6 +187,7 @@ component wr_gth_phy_kintex7ultrascale
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end component;
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
......@@ -282,8 +308,48 @@ component wr_gth_phy_kintex7ultrascale
signal s_sync : std_logic;
signal wb_master_in : t_wishbone_master_in;
signal wb_master_out : t_wishbone_master_out;
begin
U_axi4lite_bridge : wb_axi4lite_bridge
port map (
clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
ARVALID => S_AXI_REGS_arvalid,
AWVALID => S_AXI_REGS_awvalid,
BREADY => S_AXI_REGS_bready,
RREADY => S_AXI_REGS_rready,
WLAST => S_AXI_REGS_wlast,
WVALID => S_AXI_REGS_wvalid,
ARADDR => S_AXI_REGS_araddr,
AWADDR => S_AXI_REGS_awaddr,
WDATA => S_AXI_REGS_wdata,
WSTRB => S_AXI_REGS_wstrb,
ARREADY => S_AXI_REGS_arready,
AWREADY => S_AXI_REGS_awready,
BVALID => S_AXI_REGS_bvalid,
RLAST => S_AXI_REGS_rlast,
RVALID => S_AXI_REGS_rvalid,
WREADY => S_AXI_REGS_wready,
BRESP => S_AXI_REGS_bresp,
RRESP => S_AXI_REGS_rresp,
RDATA => S_AXI_REGS_rdata,
wb_adr => wb_master_out.adr,
wb_dat_m2s => wb_master_out.dat,
wb_sel => wb_master_out.sel,
wb_cyc => wb_master_out.cyc,
wb_stb => wb_master_out.stb,
wb_we => wb_master_out.we,
wb_dat_s2m => wb_master_in.dat,
wb_err => wb_master_in.err,
wb_rty => wb_master_in.rty,
wb_ack => wb_master_in.ack,
wb_stall => wb_master_in.stall
);
-- PLL stuff
pllout_clk_dmtd <= clk_25m_vcxo_bufg;
......@@ -436,7 +502,7 @@ begin
g_interface_mode => c_interface_mode,
g_address_granularity => c_address_granularity,
g_aux_sdb => c_wrc_periph3_sdb,
g_softpll_enable_debugger => false,
g_softpll_enable_debugger => true,
g_vuart_fifo_size => 1024)
port map (
clk_sys_i => clk_sys,
......@@ -498,8 +564,8 @@ begin
owr_pwren_o => open,
owr_en_o => owr_en,
owr_i => owr_i,
slave_i => cc_dummy_slave_in,
slave_o => open,
slave_i => wb_master_out,
slave_o => wb_master_in,
aux_master_o => open,
aux_master_i => cc_dummy_master_in,
wrf_src_o => open,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment