Commit 6e4a24d7 authored by Jorge Machado's avatar Jorge Machado

Update linux kernel

parent 1bc397a9
......@@ -23,6 +23,9 @@ tar xvf ${BUILDROOT}.tar.bz2
mv ${BUILDROOT} ${BASEDIR}/output
cd ${BASEDIR}
# Step 1.5: Add the custom patches (required for GCC 6.X)
cp ${BASEDIR}/patches/custom/7777-gcc-usban-file-compilation-error.patch ${BASEDIR}/output/${BUILDROOT}/package/gcc/6.3.0/
# Step 2: Configure buildroot
cp ${BASEDIR}/configs/buildroot/default.config ${BASEDIR}/output/${BUILDROOT}/.config
make -C ${BASEDIR}/output/${BUILDROOT} olddefconfig
......@@ -40,7 +43,7 @@ make -C ${BASEDIR}/output/${BUILDROOT} linux
export ARCH=arm64
export INSTALL_ROOTFS=${BASEDIR}/output/${BUILDROOT}/output/images/wr
export CROSS_COMPILE=${BASEDIR}/output/${BUILDROOT}/output/host/usr/bin/aarch64-buildroot-linux-gnu-
export LINUX=${BASEDIR}/output/${BUILDROOT}/output/build/linux-xilinx-v2017.3
export LINUX=${BASEDIR}/output/${BUILDROOT}/output/build/linux-xilinx-v2018.3
export INSTALL_MOD_PATH=${BASEDIR}/output/${BUILDROOT}/output/images/wr
make -C ${BASEDIR}/dts
make -C ${BASEDIR}/dts install
......
#! /bin/bash
# Variables
export BUILDROOT="buildroot-2017.02"
export BASEDIR=$(pwd)
# Step 6: Compile the devicetree and install it
export ARCH=arm64
export INSTALL_ROOTFS=${BASEDIR}/output/${BUILDROOT}/output/images/wr
export CROSS_COMPILE=${BASEDIR}/output/${BUILDROOT}/output/host/usr/bin/aarch64-buildroot-linux-gnu-
export LINUX=${BASEDIR}/output/${BUILDROOT}/output/build/linux-xilinx-v2018.3
export INSTALL_MOD_PATH=${BASEDIR}/output/${BUILDROOT}/output/images/wr
make -C ${BASEDIR}/dts
make -C ${BASEDIR}/dts install
# Step 7: Compile external drivers and install them
make -C ${BASEDIR}/drivers
make -C ${BASEDIR}/drivers install
# Step 8: Compile external tools and install them
make -C ${BASEDIR}/tools
make -C ${BASEDIR}/tools install
# Step 9: Copy external drivers and tools to skeleton
if [ -e ${BASEDIR}/output/${BUILDROOT}/output/target/wr ]; then
rm -r ${BASEDIR}/output/${BUILDROOT}/output/target/wr
fi
cp -r ${BASEDIR}/output/${BUILDROOT}/output/images/wr ${BASEDIR}/output/${BUILDROOT}/output/target/wr
# Step 10: Generate the rootfs (skeleton)
unset ARCH
unset INSTALL_ROOTFS
unset CROSS_COMPILE
unset LINUX
unset INSTALL_MOD_PATH
make -C ${BASEDIR}/output/${BUILDROOT}
if [ ! $? -eq 0 ] ; then
cd ${BASEDIR}/output/${BUILDROOT}
patch -p1 < ${BASEDIR}/patches/buildroot/0001-fix-automake.patch
cd ${BASEDIR}
make -C ${BASEDIR}/output/${BUILDROOT}
fi
# Step 11: Clean final images
if [ -e ${BASEDIR}/images ]; then
rm -r ${BASEDIR}/images
fi
# Step 12: Generate final images (install mkimage if not installed, in uboot-tools pkg)
mkdir -p ${BASEDIR}/images
cp ${BASEDIR}/create_fdt_image.its ${BASEDIR}/images
cp ${BASEDIR}/binaries/BOOT.bin ${BASEDIR}/images/BOOT.bin
cp ${BASEDIR}/output/${BUILDROOT}/output/images/wr/dts/devicetree-zcu102.dtb ${BASEDIR}/images/devicetree.dtb
cp ${BASEDIR}/output/${BUILDROOT}/output/images/Image ${BASEDIR}/images
cp ${BASEDIR}/output/${BUILDROOT}/output/images/rootfs.cpio ${BASEDIR}/images/uramdisk.cpio
cd ${BASEDIR}/images
mkimage -f ${BASEDIR}/images/create_fdt_image.its ${BASEDIR}/images/image.ub
cd ${BASEDIR}
# Finally the remaining vars
unset BUILDROOT
unset BASEDIR
......@@ -171,11 +171,11 @@ BR2_BINUTILS_EXTRA_CONFIG_OPTIONS=""
# GCC Options
#
# BR2_GCC_VERSION_4_9_X is not set
BR2_GCC_VERSION_5_X=y
# BR2_GCC_VERSION_6_X is not set
# BR2_GCC_VERSION_5_X is not set
BR2_GCC_VERSION_6_X=y
BR2_GCC_ARCH_HAS_CONFIGURABLE_DEFAULTS=y
BR2_GCC_SUPPORTS_FINEGRAINEDMTUNE=y
BR2_GCC_VERSION="5.4.0"
BR2_GCC_VERSION="6.3.0"
BR2_EXTRA_GCC_CONFIG_OPTIONS=""
BR2_TOOLCHAIN_BUILDROOT_CXX=y
# BR2_TOOLCHAIN_BUILDROOT_FORTRAN is not set
......@@ -245,7 +245,8 @@ BR2_TOOLCHAIN_GCC_AT_LEAST_4_7=y
BR2_TOOLCHAIN_GCC_AT_LEAST_4_8=y
BR2_TOOLCHAIN_GCC_AT_LEAST_4_9=y
BR2_TOOLCHAIN_GCC_AT_LEAST_5=y
BR2_TOOLCHAIN_GCC_AT_LEAST="5"
BR2_TOOLCHAIN_GCC_AT_LEAST_6=y
BR2_TOOLCHAIN_GCC_AT_LEAST="6"
BR2_TOOLCHAIN_HAS_SYNC_1=y
BR2_TOOLCHAIN_HAS_SYNC_2=y
BR2_TOOLCHAIN_HAS_SYNC_4=y
......@@ -318,9 +319,9 @@ BR2_LINUX_KERNEL_CUSTOM_GIT=y
# BR2_LINUX_KERNEL_CUSTOM_HG is not set
# BR2_LINUX_KERNEL_CUSTOM_SVN is not set
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="git://github.com/Xilinx/linux-xlnx.git"
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2017.3"
BR2_LINUX_KERNEL_VERSION="xilinx-v2017.3"
BR2_LINUX_KERNEL_PATCH="$(TOPDIR)/../../patches/linux/v4.9.x/"
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="xilinx-v2018.3"
BR2_LINUX_KERNEL_VERSION="xilinx-v2018.3"
BR2_LINUX_KERNEL_PATCH="$(TOPDIR)/../../patches/linux/v4.14.x/"
# BR2_LINUX_KERNEL_USE_DEFCONFIG is not set
# BR2_LINUX_KERNEL_USE_ARCH_DEFAULT_CONFIG is not set
BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
......@@ -2245,8 +2246,8 @@ BR2_TARGET_UBOOT_CUSTOM_GIT=y
# BR2_TARGET_UBOOT_CUSTOM_HG is not set
# BR2_TARGET_UBOOT_CUSTOM_SVN is not set
BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/Xilinx/u-boot-xlnx.git"
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="xilinx-v2017.3"
BR2_TARGET_UBOOT_VERSION="xilinx-v2017.3"
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="xilinx-v2018.3"
BR2_TARGET_UBOOT_VERSION="xilinx-v2018.3"
BR2_TARGET_UBOOT_PATCH="$(TOPDIR)/../../patches/u-boot"
# BR2_TARGET_UBOOT_NEEDS_DTC is not set
# BR2_TARGET_UBOOT_NEEDS_OPENSSL is not set
......
cmd_/home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.ko := /home/test/zcu102_buildroot_new_kernel/output/buildroot-2017.02/output/host/usr/bin/aarch64-buildroot-linux-gnu-ld -EL -r -maarch64linux -T ./scripts/module-common.lds --build-id -o /home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.ko /home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.o /home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.mod.o ; true
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/home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.ko
/home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.o
#include <linux/module.h>
#include <linux/vermagic.h>
#include <linux/compiler.h>
MODULE_INFO(vermagic, VERMAGIC_STRING);
MODULE_INFO(name, KBUILD_MODNAME);
__visible struct module __this_module
__attribute__((section(".gnu.linkonce.this_module"))) = {
.name = KBUILD_MODNAME,
.init = init_module,
#ifdef CONFIG_MODULE_UNLOAD
.exit = cleanup_module,
#endif
.arch = MODULE_ARCH_INIT,
};
static const char __module_depends[]
__used
__attribute__((section(".modinfo"))) =
"depends=";
MODULE_ALIAS("spi:hmc7044");
MODULE_ALIAS("spi:hmc7043");
kernel//home/test/zcu102_buildroot_new_kernel/drivers/hmc7044/hmc7044.ko
cmd_/home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.ko := /home/test/zcu102_buildroot_new_kernel/output/buildroot-2017.02/output/host/usr/bin/aarch64-buildroot-linux-gnu-ld -EL -r -maarch64linux -T ./scripts/module-common.lds --build-id -o /home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.ko /home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.o /home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.mod.o ; true
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/home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.ko
/home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.o
#include <linux/module.h>
#include <linux/vermagic.h>
#include <linux/compiler.h>
MODULE_INFO(vermagic, VERMAGIC_STRING);
MODULE_INFO(name, KBUILD_MODNAME);
__visible struct module __this_module
__attribute__((section(".gnu.linkonce.this_module"))) = {
.name = KBUILD_MODNAME,
.init = init_module,
#ifdef CONFIG_MODULE_UNLOAD
.exit = cleanup_module,
#endif
.arch = MODULE_ARCH_INIT,
};
static const char __module_depends[]
__used
__attribute__((section(".modinfo"))) =
"depends=";
MODULE_ALIAS("of:N*T*Csilabs,si549a");
MODULE_ALIAS("of:N*T*Csilabs,si549aC*");
MODULE_ALIAS("of:N*T*Csilabs,si549b");
MODULE_ALIAS("of:N*T*Csilabs,si549bC*");
MODULE_ALIAS("of:N*T*Csilabs,si549c");
MODULE_ALIAS("of:N*T*Csilabs,si549cC*");
MODULE_ALIAS("i2c:si549a");
MODULE_ALIAS("i2c:si549b");
MODULE_ALIAS("i2c:si549c");
kernel//home/test/zcu102_buildroot_new_kernel/drivers/si549/clk-si549.ko
INSTALL_ROOTFS ?= $(WRZ_OUTPUT_DIR)/images
INSTALL_TARGET_DTS = dts
devicetree-zcu102.dtb: system-zcu102.dts pl-zcu102.dtsi
@dtc -O dtb -o devicetree-zcu102.dtb system-zcu102.dts
devicetree-zcu102.dtb: system-top.dts pl.dtsi
@dtc -O dtb -o devicetree-zcu102.dtb system-top.dts
@echo "Compiling the ZCU-102 device tree..."
install: devicetree-zcu102.dtb
......
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/*
* CAUTION: This file is automatically generated by Xilinx.
* Version:
* Today is: Tue Jan 16 08:25:28 2018
* Version: XSCT 2018.3
* Today is: Tue Apr 6 09:22:55 2021
*/
&gic {
num_cpus = <2>;
num_interrupts = <96>;
};
&lpd_dma_chan1 {
status = "okay";
};
......@@ -32,10 +36,27 @@
&xilinx_ams {
status = "okay";
};
&perf_monitor_ocm {
xlnx,enable-32bit-filter-id = <0x1>;
xlnx,enable-advanced = <0x1>;
xlnx,enable-event-count = <0x1>;
xlnx,enable-event-log = <0x0>;
xlnx,enable-profile = <0x0>;
xlnx,enable-trace = <0x0>;
xlnx,fifo-axis-depth = <0x20>;
xlnx,fifo-axis-tdata-width = <0x38>;
xlnx,fifo-axis-tid-width = <0x1>;
xlnx,global-count-width = <0x20>;
xlnx,have-sampled-metric-cnt = <0x1>;
xlnx,metric-count-scale = <0x1>;
xlnx,metrics-sample-count-width = <0x20>;
xlnx,num-monitor-slots = <0x1>;
xlnx,num-of-counters = <0x3>;
};
&can1 {
status = "okay";
};
&xlnx_dp {
&zynqmp_dpsub {
phy-names = "dp-phy0";
phys = <&lane1 5 0 3 27000000>;
status = "okay";
......@@ -108,10 +129,18 @@
status = "okay";
};
&sata {
ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
status = "okay";
};
&sdhci1 {
clock-frequency = <187498000>;
clock-frequency = <187481262>;
status = "okay";
xlnx,mio_bank = <0x1>;
};
......@@ -132,35 +161,36 @@
};
&usb0 {
status = "okay";
xlnx,usb-reset = <0x2faf080>;
xlnx,usb-polarity = <0x0>;
xlnx,usb-reset-mode = <0x0>;
};
&dwc3_0 {
status = "okay";
};
&watchdog0 {
&lpd_watchdog {
status = "okay";
};
&ams_ps {
&watchdog0 {
status = "okay";
};
&ams_pl {
status = "okay";
&pss_ref_clk {
clock-frequency = <33330000>;
};
&xilinx_drm {
&ams_ps {
status = "okay";
};
&xlnx_dp_sub {
&ams_pl {
status = "okay";
};
&xlnx_dp_snd_pcm0 {
&zynqmp_dp_snd_pcm0 {
status = "okay";
};
&xlnx_dp_snd_pcm1 {
&zynqmp_dp_snd_pcm1 {
status = "okay";
};
&xlnx_dp_snd_card {
&zynqmp_dp_snd_card0 {
status = "okay";
};
&xlnx_dp_snd_codec0 {
&zynqmp_dp_snd_codec0 {
status = "okay";
};
......@@ -20,23 +20,6 @@
interrupts = <0 89 4>;
};
/* I2C helper */
axi_iic_1: i2c@00A0001000 {
compatible = "xlnx,xps-iic-2.00.a";
reg = <0x0 0x00A0001000 0x0 0x1000>;
clock-names = "clk_50";
clocks = <&clk_50>;
interrupt-parent = <&gic>;
interrupts = <0 90 4>;
helper: clock-controller@67 {
clock-output-names = "helper";
reg = <0x67>;
#clock-cells = <0>;
compatible = "silabs,si549a";
};
};
/* I2C si549 */
axi_iic_2: i2c@00A0002000 {
compatible = "xlnx,xps-iic-2.00.a";
......@@ -113,7 +96,7 @@
hmc7044_c5: channel@5 {
reg = <5>;
adi,extended-name = "10mhz_clk";
adi,divider = <300>;
adi,divider = <48>;
adi,driver-mode = <3>;
};
......@@ -154,7 +137,7 @@
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "MGT_CLK1";
adi,divider = <48>;
adi,divider = <24>;
adi,driver-mode = <2>;
};
};
......
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version:
* Today is: Tue Sep 8 08:35:15 2020
*/
/ {
amba_pl: amba_pl@0 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges ;
axi_iic_0: i2c@00A0000000 {
compatible = "xlnx,xps-iic-2.00.a";
reg = <0x0 0x00A0000000 0x0 0x1000>;
clock-names = "clk_50";
clocks = <&clk_50>;
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
};
/* I2C si549 */
axi_iic_2: i2c@00A0002000 {
compatible = "xlnx,xps-iic-2.00.a";
reg = <0x0 0x00A0002000 0x0 0x1000>;
clock-names = "clk_50";
clocks = <&clk_50>;
interrupt-parent = <&gic>;
interrupts = <0 91 4>;
si549: clock-controller@67 {
clock-output-names = "aux";
reg = <0x67>;
#clock-cells = <0>;
compatible = "silabs,si549a";
};
};
HMC_axi_quad_spi_0: axi_quad_spi@a0010000 {
bits-per-word = <8>;
clock-names = "clk_50";
clocks = <&clk_50>;
compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a";
fifo-size = <16>;
interrupt-parent = <&gic>;
interrupts = <0 92 1>;
num-cs = <0x1>;
reg = <0x0 0xa0010000 0x0 0x10000>;
xlnx,num-ss-bits = <0x1>;
xlnx,spi-mode = <0>;
hmc7044: hmc7044@0 {
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <10000000>;
adi,pll1-clkin-frequencies = <0 62500000 0 0>;
adi,pll1-loop-bandwidth = <200>;
adi,vcxo-frequency = <10000000>;
adi,pll2-output-frequency = <3000000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x0>;
adi,oscin-buffer-mode = <0x3>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;
clock-output-names = "hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c0: channel@0 {
reg = <0>;
adi,extended-name = "REF_CLK";
adi,divider = <30>;
adi,driver-mode = <2>;
};
hmc7044_c1: channel@1 {
reg = <1>;
adi,extended-name = "WR_CLK";
adi,divider = <48>;
adi,driver-mode = <2>;
};
hmc7044_c5: channel@5 {
reg = <5>;
adi,extended-name = "10mhz_clk";
adi,divider = <300>;
adi,driver-mode = <3>;
};
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DAC_CLK";
adi,divider = <1>;
adi,driver-mode = <1>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DAC_SYSREF";
adi,divider = <512>;
adi,driver-mode = <1>;
};
hmc7044_c7: channel@7 {
reg = <7>;
adi,extended-name = "SYNC1_CLK";
adi,divider = <60>;
adi,driver-mode = <0>;
};
hmc7044_c11: channel@11 {
reg = <11>;
adi,extended-name = "MGT_CLK2";
adi,divider = <48>;
adi,driver-mode = <2>;
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_CLK";
adi,divider = <8>;
adi,driver-mode = <2>;
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "MGT_CLK1";
adi,divider = <24>;
adi,driver-mode = <2>;
};
};
};
};
};
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version: XSCT 2018.3
* Today is: Tue Apr 6 09:22:55 2021
*/
/dts-v1/;
/include/ "zynqmp.dtsi"
/include/ "zynqmp-clk-ccf.dtsi"
/include/ "pl.dtsi"
/include/ "pcw.dtsi"
/ {
chosen {
bootargs = "earlycon clk_ignore_unused";
stdout-path = "serial0:115200n8";
};
aliases {
ethernet0 = &gem3;
i2c0 = &axi_iic_0;
i2c1 = &axi_iic_2;
i2c2 = &i2c0;
i2c3 = &i2c1;
serial0 = &uart0;
serial1 = &uart1;
spi0 = &qspi;
spi1 = &HMC_axi_quad_spi_0;
};
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x7ff00000>, <0x00000008 0x00000000 0x0 0x80000000>;
};
};
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version: XSCT 2018.3
* Today is: Tue Apr 6 09:22:55 2021
*/
&gem3 {
local-mac-address = [00 0a 35 00 00 00];
};
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--- A/output/host/usr/bin/automake 2021-01-27 10:58:39.326087189 +0100
+++ B/output/host/usr/bin/automake 2021-01-27 10:45:32.772894797 +0100
@@ -3933,7 +3933,7 @@
sub substitute_ac_subst_variables
{
my ($text) = @_;
- $text =~ s/\${([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
+ $text =~ s/\$\{([^ \t=:+{}]+)}/substitute_ac_subst_variables_worker ($1)/ge;
return $text;
}
commit 509aa198dac3fe2abb6bf949f2d41c4a796794b7
Author: Adrian Fiergolski <adrian.fiergolski@cern.ch>
Date: Wed Aug 30 21:30:04 2017 +0200
Fix power managment in spi-xilinx.c
Power managment for qspi->dev is never enabled. Thus xspi_setup always fails. In fact, spi_master takes care of its power managment and ignores its childs.
It is enough to provide power managment at platform_device (pdev->dev) level.
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@cern.ch>
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index 8df73ed535d0..f435ec90e487 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -380,12 +380,7 @@ static int xspi_setup(struct spi_device *qspi)
if (qspi->master->busy)
return -EBUSY;
- ret = pm_runtime_get_sync(&qspi->dev);
- if (ret < 0)
- return ret;
-
ret = xspi_setup_transfer(qspi, NULL);
- pm_runtime_put_sync(&qspi->dev);
return ret;
}
@@ -456,10 +451,6 @@ static int xspi_prepare_transfer_hardware(struct spi_master *master)
u32 cr;
int ret;
- ret = pm_runtime_get_sync(&master->dev);
- if (ret < 0)
- return ret;
-
cr = xqspi->read_fn(xqspi->regs + XSPI_CR_OFFSET);
cr |= XSPI_CR_ENABLE;
xqspi->write_fn(cr, xqspi->regs + XSPI_CR_OFFSET);
@@ -485,7 +476,6 @@ static int xspi_unprepare_transfer_hardware(struct spi_master *master)
cr &= ~XSPI_CR_ENABLE;
xqspi->write_fn(cr, xqspi->regs + XSPI_CR_OFFSET);
- pm_runtime_put_sync(&master->dev);
return 0;
}
@@ -800,11 +790,15 @@ static int xilinx_spi_probe(struct platform_device *pdev)
goto clk_unprepare_all;
}
xspi->cs_inactive = 0xffffffff;
+ ret = pm_runtime_get_sync(&pdev->dev);
+ if (ret < 0)
+ goto clk_unprepare_all;
ret = spi_register_master(master);
if (ret) {
dev_err(&pdev->dev, "spi_register_master failed\n");
goto clk_unprepare_all;
}
+ pm_runtime_put(&pdev->dev);
return ret;
From 457355fb309ecb3906fe26f1757a50c0a81fbd22 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Emilio=20Mar=C3=ADn=20L=C3=B3pez?= <emilio@sevensols.com>
Date: Mon, 27 Nov 2017 18:30:51 +0100
Subject: [PATCH 1/2] u-boot loads an image.ub file instead Image, uramdisk &
dt
---
include/configs/xilinx_zynqmp.h | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 5e4aedd489..e5989d8aad 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -219,10 +219,9 @@
"echo Running uenvcmd ...; " \
"run uenvcmd; " \
"fi\0" \
- "sdboot=mmc dev $sdbootdev && mmcinfo && run uenvboot || run sdroot$sdbootdev; " \
- "load mmc $sdbootdev:$partid $fdt_addr system.dtb && " \
- "load mmc $sdbootdev:$partid $kernel_addr Image && " \
- "booti $kernel_addr - $fdt_addr\0" \
+ "sdboot=echo Copying Linux from SD to RAM...;" \
+ "fatload mmc 0 0x3000000 image.ub;" \
+ "bootm 0x3000000\0" \
"emmcboot=run sdboot\0" \
"nandboot=nand info && nand read $fdt_addr $fdt_offset $fdt_size && " \
"nand read $kernel_addr $kernel_offset $kernel_size && " \
--
2.25.1
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