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White Rabbit Switch - Hardware V4
Commit 3200e1c4 authored by Jorge Machado's avatar Jorge Machado
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Modify devicetree and hmc7044 driver to perform SYNC operation

parent 997e32e4
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Showing with 180 additions and 11 deletions
FCWR_tests/sw/drivers/hmc7044/hmc7044.c
View file @ 3200e1c4
......@@ -336,6 +336,7 @@ static int hmc7044_write(struct iio_dev *indio_dev,
unsigned int reg,
unsigned int val)
{
printk("writing reg 0x%08x with value 0x%08x", reg, val);
struct hmc7044 *hmc = iio_priv(indio_dev);
unsigned char buf[3];
u16 cmd;
......@@ -365,6 +366,8 @@ static int hmc7044_read(struct iio_dev *indio_dev,
*val = buf[2];
printk("reading reg 0x%08x with value 0x%08x", reg, *val);
return ret;
}
......@@ -501,6 +504,84 @@ out:
return ret ? ret : len;
}
static ssize_t hmc7044_store_ch13(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct hmc7044 *hmc = iio_priv(indio_dev);
bool state;
int ret;
u32 val, write_val;
ret = strtobool(buf, &state);
if (ret < 0)
return ret;
mutex_lock(&hmc->lock);
ret = hmc7044_read(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(13), &val);
if (ret < 0)
goto out;
if (state)
write_val = val | (u32)this_attr->address;
else
write_val = val & ~((u32)this_attr->address);
ret = hmc7044_write(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(13), write_val);
//switch ((u32)this_attr->address) {
//case HMC7044_SYNC_EN:
//case HMC7044_PULSE_GEN_REQ:
//case HMC7044_RESTART_DIV_FSM:
//}
out:
mutex_unlock(&hmc->lock);
return ret ? ret : len;
}
static ssize_t hmc7044_store_ch1(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct hmc7044 *hmc = iio_priv(indio_dev);
bool state;
int ret;
u32 val, write_val;
ret = strtobool(buf, &state);
if (ret < 0)
return ret;
mutex_lock(&hmc->lock);
ret = hmc7044_read(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(1), &val);
if (ret < 0)
goto out;
if (state)
write_val = val | (u32)this_attr->address;
else
write_val = val & ~((u32)this_attr->address);
ret = hmc7044_write(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(1), write_val);
//switch ((u32)this_attr->address) {
//case HMC7044_SYNC_EN:
//case HMC7044_PULSE_GEN_REQ:
//case HMC7044_RESTART_DIV_FSM:
//}
out:
mutex_unlock(&hmc->lock);
return ret ? ret : len;
}
static ssize_t hmc7044_show(struct device *dev,
struct device_attribute *attr,
char *buf)
......@@ -521,6 +602,46 @@ static ssize_t hmc7044_show(struct device *dev,
return ret;
}
static ssize_t hmc7044_show_ch13(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct hmc7044 *hmc = iio_priv(indio_dev);
int ret;
u32 val;
mutex_lock(&hmc->lock);
ret = hmc7044_read(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(13), &val);
if (ret >= 0)
ret = sprintf(buf, "%d\n", !!(val & (u32)this_attr->address));
mutex_unlock(&hmc->lock);
return ret;
}
static ssize_t hmc7044_show_ch1(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *indio_dev = dev_to_iio_dev(dev);
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct hmc7044 *hmc = iio_priv(indio_dev);
int ret;
u32 val;
mutex_lock(&hmc->lock);
ret = hmc7044_read(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(1), &val);
if (ret >= 0)
ret = sprintf(buf, "%d\n", !!(val & (u32)this_attr->address));
mutex_unlock(&hmc->lock);
return ret;
}
static int hmc7044_sync_pin_set(struct iio_dev *indio_dev, unsigned mode)
{
u32 val;
......@@ -614,6 +735,15 @@ static IIO_DEVICE_ATTR(sync_pin_mode, S_IRUGO | S_IWUSR,
static IIO_CONST_ATTR(sync_pin_mode_available,
"disable sync sysref sync_else_sysref");
static IIO_DEVICE_ATTR(sync_pin_enable_ch13, S_IRUGO | S_IWUSR,
hmc7044_show_ch13, hmc7044_store_ch13,
HMC7044_SYNC_EN);
static IIO_DEVICE_ATTR(sync_pin_enable_ch1, S_IRUGO | S_IWUSR,
hmc7044_show_ch1, hmc7044_store_ch1,
HMC7044_SYNC_EN);
static struct attribute *hmc7044_attributes[] = {
&iio_dev_attr_reseed_request.dev_attr.attr,
&iio_dev_attr_mute_request.dev_attr.attr,
......@@ -622,6 +752,8 @@ static struct attribute *hmc7044_attributes[] = {
&iio_dev_attr_sleep_request.dev_attr.attr,
&iio_dev_attr_sync_pin_mode.dev_attr.attr,
&iio_const_attr_sync_pin_mode_available.dev_attr.attr,
&iio_dev_attr_sync_pin_enable_ch13.dev_attr.attr,
&iio_dev_attr_sync_pin_enable_ch1.dev_attr.attr,
NULL,
};
......@@ -918,6 +1050,7 @@ static int hmc7044_setup(struct iio_dev *indio_dev)
/* Select the VCO range */
if (hmc->clkin1_vcoin_en) {
printk("clkin1_vcoin_en true\n");
hmc->pll2_freq = hmc->clkin_freq_ccf[1] ?
hmc->clkin_freq_ccf[1] : hmc->clkin_freq[1];
......@@ -932,6 +1065,7 @@ static int hmc7044_setup(struct iio_dev *indio_dev)
hmc7044_write(indio_dev, HMC7044_REG_SYNC, HMC7044_SYNC_RETIME);
} else {
printk("clkin1_vcoin_en false\n");
hmc7044_write(indio_dev, HMC7044_REG_EN_CTRL_0,
(hmc->rf_reseeder_en ? HMC7044_RF_RESEEDER_EN : 0) |
HMC7044_VCO_SEL(high_vco_en ?
......@@ -939,6 +1073,8 @@ static int hmc7044_setup(struct iio_dev *indio_dev)
HMC7044_VCO_LOW) |
HMC7044_SYSREF_TIMER_EN | HMC7044_PLL2_EN |
HMC7044_PLL1_EN);
//hmc7044_write(indio_dev, HMC7044_REG_SYNC, HMC7044_SYNC_THROUGH_PLL2);
}
if (hmc->pll2_cap_bank_sel != ~0)
......@@ -1060,13 +1196,27 @@ static int hmc7044_setup(struct iio_dev *indio_dev)
hmc7044_write(indio_dev, HMC7044_REG_CH_OUT_CRTL_7(chan->num),
chan->out_mux_mode & 0x3);
hmc7044_write(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
(chan->start_up_mode_dynamic_enable ?
HMC7044_START_UP_MODE_DYN_EN : 0) |
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
(chan->high_performance_mode_dis ?
0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN |
HMC7044_CH_EN);
if(chan->num == 5 || chan->num == 7 || chan->num == 12)
{
hmc7044_write(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
(chan->start_up_mode_dynamic_enable ?
HMC7044_START_UP_MODE_DYN_EN : 0) |
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
(chan->high_performance_mode_dis ?
0 : HMC7044_HI_PERF_MODE) | HMC7044_SYNC_EN |
HMC7044_CH_EN);
}
else
{
hmc7044_write(indio_dev, HMC7044_REG_CH_OUT_CRTL_0(chan->num),
(chan->start_up_mode_dynamic_enable ?
HMC7044_START_UP_MODE_DYN_EN : 0) |
(chan->output_control0_rb4_enable ? BIT(4) : 0) |
(chan->high_performance_mode_dis ?
0 : HMC7044_HI_PERF_MODE) |
HMC7044_CH_EN);
}
hmc->iio_channels[i].type = IIO_ALTVOLTAGE;
hmc->iio_channels[i].output = 1;
......
FCWR_tests/sw/dts/pl.dtsi
View file @ 3200e1c4
......@@ -55,7 +55,7 @@
adi,pll2-output-frequency = <3000000000>;
adi,sysref-timer-divider = <1024>;
adi,sysref-timer-divider = <1200>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x0>;
......@@ -64,6 +64,8 @@
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x1f 0x2b 0x00 0x00>;
//adi,sync-pin-mode = <0x0>;
clock-output-names = "hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
......@@ -89,6 +91,7 @@
reg = <5>;
adi,extended-name = "10mhz_clk";
adi,divider = <300>;
//adi,divider = <48>;
adi,driver-mode = <3>;
};
......@@ -102,7 +105,7 @@
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DAC_SYSREF";
adi,divider = <512>;
adi,divider = <300>;
adi,driver-mode = <1>;
};
......@@ -110,7 +113,7 @@
hmc7044_c7: channel@7 {
reg = <7>;
adi,extended-name = "SYNC1_CLK";
adi,divider = <60>;
adi,divider = <48>;
adi,driver-mode = <0>;
};
......@@ -123,7 +126,7 @@
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_CLK";
adi,divider = <8>;
adi,divider = <300>;
adi,driver-mode = <2>;
};
hmc7044_c13: channel@13 {
......
FCWR_tests/sw/tools/scripts/fmc_conf.sh
View file @ 3200e1c4
......@@ -15,5 +15,21 @@ cd
/wr/bin/lmx2594_programmer
#Reset LM32
devmem 0x00A0007000 w 0x1
echo "1" > /sys/bus/iio/devices/iio:device1/sync_pin_enable_ch1
cat /sys/bus/iio/devices/iio:device1/sync_pin_enable_ch1
echo "1" > /sys/bus/iio/devices/iio:device1/reset_dividers_request
echo "0" > /sys/bus/iio/devices/iio:device1/reset_dividers_request
echo "1" > /sys/bus/iio/devices/iio:device1/reseed_request
cat /sys/bus/iio/devices/iio:device1/reseed_request
echo "0" > /sys/bus/iio/devices/iio:device1/reseed_request
cat /sys/bus/iio/devices/iio:device1/reseed_request
echo "0" > /sys/bus/iio/devices/iio:device1/sync_pin_enable_ch1
cat /sys/bus/iio/devices/iio:device1/sync_pin_enable_ch1
sleep 1
devmem 0x00A0007000 w 0x0
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