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White Rabbit Switch - Hardware V4
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White Rabbit Switch - Hardware V4
Commits
0cd5cded
Commit
0cd5cded
authored
Feb 09, 2022
by
Jorge Machado
Browse files
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Plain Diff
Include gw support for HMC7044 SYNC
parent
3200e1c4
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6 changed files
with
754 additions
and
362 deletions
+754
-362
fmc_support_bd.tcl
FCWR_tests/fmc_support_gw/syn/fmc_support_bd.tcl
+15
-4
component.xml
...ts/fmc_support_gw/vivado_ip/sync_controller/component.xml
+378
-0
sync_controller.vhd
...port_gw/vivado_ip/sync_controller/src/sync_controller.vhd
+172
-0
sync_controller_v1_0.tcl
...w/vivado_ip/sync_controller/xgui/sync_controller_v1_0.tcl
+40
-0
component.xml
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/component.xml
+141
-355
zcu102.vhd
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/zcu102.vhd
+8
-3
No files found.
FCWR_tests/fmc_support_gw/syn/fmc_support_bd.tcl
View file @
0cd5cded
...
...
@@ -126,8 +126,9 @@ if { $bCheckIPs == 1 } {
xilinx.com:ip:axi_gpio:2.0
\
xilinx.com:ip:axi_iic:2.0
\
xilinx.com:ip:clk_wiz:6.0
\
xilinx.com:ip:util_vector_logic:2.0
\
xilinx.com:ip:proc_sys_reset:5.0
\
xilinx.com:ip:util_vector_logic:2.0
\
user.org:user:sync_controller:1.0
\
xilinx.com:ip:util_ds_buf:2.1
\
user.org:user:wrcore_1g_fmc:1.0
\
xilinx.com:ip:xlconcat:2.1
\
...
...
@@ -324,6 +325,7 @@ proc create_hier_cell_HMC { parentCell nameHier } {
create_bd_pin -dir O -type intr ip2intc_irpt
create_bd_pin -dir I -type clk s_axi_aclk
create_bd_pin -dir I -type rst s_axi_aresetn
create_bd_pin -dir I -from 0 -to 0 -type clk sync_in
# Create instance: axi_quad_spi_0, and set properties
set axi_quad_spi_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.2 axi_quad_spi_0
]
...
...
@@ -463,6 +465,7 @@ proc create_hier_cell_HMC { parentCell nameHier } {
connect_bd_net -net Net4
[
get_bd_pins hmc_gpio2
]
[
get_bd_pins util_ds_buf_5/IOBUF_IO_IO
]
connect_bd_net -net Net5
[
get_bd_pins hmc_gpio3
]
[
get_bd_pins util_ds_buf_6/IOBUF_IO_IO
]
connect_bd_net -net Net6
[
get_bd_pins hmc_gpio4
]
[
get_bd_pins util_ds_buf_7/IOBUF_IO_IO
]
connect_bd_net -net OBUF_IN_1
[
get_bd_pins sync_in
]
[
get_bd_pins util_ds_buf_0/OBUF_IN
]
connect_bd_net -net axi_quad_spi_0_io0_o
[
get_bd_pins axi_quad_spi_0/io0_o
]
[
get_bd_pins tri_state_ctrl_0/sdata_i
]
[
get_bd_pins util_ds_buf_2/IOBUF_IO_I
]
connect_bd_net -net axi_quad_spi_0_ip2intc_irpt
[
get_bd_pins ip2intc_irpt
]
[
get_bd_pins axi_quad_spi_0/ip2intc_irpt
]
connect_bd_net -net axi_quad_spi_0_sck_o
[
get_bd_pins axi_quad_spi_0/sck_o
]
[
get_bd_pins tri_state_ctrl_0/clk_i
]
[
get_bd_pins util_ds_buf_3/IOBUF_IO_I
]
...
...
@@ -485,7 +488,6 @@ proc create_hier_cell_HMC { parentCell nameHier } {
connect_bd_net -net xlslice_11_Dout
[
get_bd_pins util_ds_buf_6/IOBUF_IO_T
]
[
get_bd_pins xlslice_11/Dout
]
connect_bd_net -net xlslice_12_Dout
[
get_bd_pins util_ds_buf_7/IOBUF_IO_I
]
[
get_bd_pins xlslice_12/Dout
]
connect_bd_net -net xlslice_13_Dout
[
get_bd_pins util_ds_buf_7/IOBUF_IO_T
]
[
get_bd_pins xlslice_13/Dout
]
connect_bd_net -net xlslice_4_Dout
[
get_bd_pins util_ds_buf_0/OBUF_IN
]
[
get_bd_pins xlslice_4/Dout
]
connect_bd_net -net xlslice_5_Dout
[
get_bd_pins hmc_reset
]
[
get_bd_pins xlslice_5/Dout
]
connect_bd_net -net xlslice_6_Dout
[
get_bd_pins util_ds_buf_4/IOBUF_IO_I
]
[
get_bd_pins xlslice_6/Dout
]
connect_bd_net -net xlslice_7_Dout
[
get_bd_pins util_ds_buf_4/IOBUF_IO_T
]
[
get_bd_pins xlslice_7/Dout
]
...
...
@@ -689,6 +691,9 @@ proc create_root_design { parentCell } {
# Create instance: pll_gm
create_hier_cell_pll_gm
[
current_bd_instance .
]
pll_gm
# Create instance: proc_sys_reset_0, and set properties
set proc_sys_reset_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0
]
# Create instance: reset_or, and set properties
set reset_or
[
create_bd_cell -type ip -vlnv xilinx.com:ip:util_vector_logic:2.0 reset_or
]
set_property -dict
[
list
\
...
...
@@ -703,6 +708,9 @@ proc create_root_design { parentCell } {
# Create instance: sfp_axi_gpio, and set properties
set sfp_axi_gpio
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 sfp_axi_gpio
]
# Create instance: sync_controller_0, and set properties
set sync_controller_0
[
create_bd_cell -type ip -vlnv user.org:user:sync_controller:1.0 sync_controller_0
]
# Create instance: util_ds_buf_0, and set properties
set util_ds_buf_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:util_ds_buf:2.1 util_ds_buf_0
]
set_property -dict
[
list
\
...
...
@@ -2201,6 +2209,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net Net9
[
get_bd_ports onewire
]
[
get_bd_pins wrcore_1g_fmc_0/thermo_id
]
connect_bd_net -net Net10
[
get_bd_ports iic_sfp_scl_io
]
[
get_bd_pins wrcore_1g_fmc_0/gtp0_mod_def1_b
]
connect_bd_net -net Net11
[
get_bd_ports iic_sfp_sda_io
]
[
get_bd_pins wrcore_1g_fmc_0/gtp0_mod_def2_b
]
connect_bd_net -net Net12
[
get_bd_pins proc_sys_reset_0/slowest_sync_clk
]
[
get_bd_pins sync_controller_0/clk_ref_i
]
[
get_bd_pins wrcore_1g_fmc_0/clk_ref_o
]
connect_bd_net -net SI549_aux_n_1
[
get_bd_ports SI549_aux_n
]
[
get_bd_pins util_ds_buf_5/IBUF_DS_N
]
connect_bd_net -net SI549_aux_p_1
[
get_bd_ports SI549_aux_p
]
[
get_bd_pins util_ds_buf_5/IBUF_DS_P
]
connect_bd_net -net axi_gpio_0_gpio_io_o
[
get_bd_pins axi_gpio_0/gpio_io_o
]
[
get_bd_pins reset_or/Op1
]
...
...
@@ -2231,8 +2240,9 @@ proc create_root_design { parentCell } {
connect_bd_net -net pll_gm_muxout_1
[
get_bd_ports pll_gm_muxout
]
[
get_bd_pins pll_gm/pll_gm_muxout
]
connect_bd_net -net pll_gm_pll_gm_rampdir
[
get_bd_ports pll_gm_rampdir
]
[
get_bd_pins pll_gm/pll_gm_rampdir
]
connect_bd_net -net pll_gm_pll_gm_sysrefreq
[
get_bd_ports pll_gm_sysrefreq
]
[
get_bd_pins pll_gm/pll_gm_sysrefreq
]
connect_bd_net -net pps_gen_1_pps_o
[
get_bd_ports aux_out
]
[
get_bd_ports pps_out
]
[
get_bd_pins wrcore_1g_fmc_0/pps_out_o
]
connect_bd_net -net pps_gen_1_pps_o
[
get_bd_ports aux_out
]
[
get_bd_ports pps_out
]
[
get_bd_pins
sync_controller_0/pps_i
]
[
get_bd_pins
wrcore_1g_fmc_0/pps_out_o
]
connect_bd_net -net pps_in_1
[
get_bd_ports pps_in
]
[
get_bd_pins wrcore_1g_fmc_0/pps_i
]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn
[
get_bd_pins proc_sys_reset_0/peripheral_aresetn
]
[
get_bd_pins sync_controller_0/rst_n_i
]
connect_bd_net -net ref_clk_n_1
[
get_bd_ports ref_clk_n
]
[
get_bd_pins util_ds_buf_9/IBUF_DS_N
]
connect_bd_net -net ref_clk_p_1
[
get_bd_ports ref_clk_p
]
[
get_bd_pins util_ds_buf_9/IBUF_DS_P
]
connect_bd_net -net reset_or_Res
[
get_bd_pins reset_or/Res
]
[
get_bd_pins wrcore_1g_fmc_0/button_rst_i
]
...
...
@@ -2241,6 +2251,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net sfp_axi_gpio_gpio_io_o
[
get_bd_pins HMC/Din
]
[
get_bd_pins pll_gm/Din
]
[
get_bd_pins sfp_axi_gpio/gpio_io_o
]
[
get_bd_pins xlslice_0/Din
]
[
get_bd_pins xlslice_3/Din
]
connect_bd_net -net sfp_detect_1
[
get_bd_ports sfp_detect
]
[
get_bd_pins wrcore_1g_fmc_0/gtp0_mod_def0_b
]
[
get_bd_pins xlconcat_0/In0
]
connect_bd_net -net sfp_los_tx_fault_1
[
get_bd_ports sfp_los_tx_fault
]
[
get_bd_pins wrcore_1g_fmc_0/gtp0_tx_fault_i
]
[
get_bd_pins xlconcat_0/In1
]
connect_bd_net -net sync_controller_0_sync_o
[
get_bd_pins HMC/sync_in
]
[
get_bd_pins sync_controller_0/sync_o
]
connect_bd_net -net uart_cts_i_1
[
get_bd_ports uart_cts_i
]
[
get_bd_pins wrcore_1g_fmc_0/uart_cts_i
]
connect_bd_net -net uart_rxd_i_1
[
get_bd_ports uart_rxd_i
]
[
get_bd_pins wrcore_1g_fmc_0/uart_rxd_i
]
connect_bd_net -net util_ds_buf_0_IBUF_DS_ODIV2
[
get_bd_pins util_ds_buf_0/IBUF_DS_ODIV2
]
[
get_bd_pins util_ds_buf_1/BUFG_GT_I
]
...
...
@@ -2271,7 +2282,7 @@ proc create_root_design { parentCell } {
connect_bd_net -net xlslice_0_Dout
[
get_bd_ports sfp_tx_disable
]
[
get_bd_pins xlslice_0/Dout
]
connect_bd_net -net xlslice_3_Dout
[
get_bd_ports term_en
]
[
get_bd_pins xlslice_3/Dout
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0
[
get_bd_ports PMOD0_3
]
[
get_bd_pins HMC/s_axi_aclk
]
[
get_bd_pins axi_gpio_0/s_axi_aclk
]
[
get_bd_pins axi_iic_si549/s_axi_aclk
]
[
get_bd_pins axi_interconnect_0/ACLK
]
[
get_bd_pins axi_interconnect_0/M00_ACLK
]
[
get_bd_pins axi_interconnect_0/M01_ACLK
]
[
get_bd_pins axi_interconnect_0/M02_ACLK
]
[
get_bd_pins axi_interconnect_0/M03_ACLK
]
[
get_bd_pins axi_interconnect_0/M04_ACLK
]
[
get_bd_pins axi_interconnect_0/S00_ACLK
]
[
get_bd_pins clk_wiz_0/clk_out1
]
[
get_bd_pins pll_gm/S_AXI_ACLK
]
[
get_bd_pins rst_ps8/slowest_sync_clk
]
[
get_bd_pins sfp_axi_gpio/s_axi_aclk
]
[
get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0
[
get_bd_pins rst_ps8/ext_reset_in
]
[
get_bd_pins zynq_ultra_ps_e_0/pl_resetn0
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0
[
get_bd_pins
proc_sys_reset_0/ext_reset_in
]
[
get_bd_pins
rst_ps8/ext_reset_in
]
[
get_bd_pins zynq_ultra_ps_e_0/pl_resetn0
]
# Create address segments
create_bd_addr_seg -range 0x00001000 -offset 0xA0007000
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs axi_gpio_0/S_AXI/Reg
]
SEG_axi_gpio_0_Reg
...
...
FCWR_tests/fmc_support_gw/vivado_ip/sync_controller/component.xml
0 → 100644
View file @
0cd5cded
This diff is collapsed.
Click to expand it.
FCWR_tests/fmc_support_gw/vivado_ip/sync_controller/src/sync_controller.vhd
0 → 100644
View file @
0cd5cded
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11/24/2021 11:15:08 AM
-- Design Name:
-- Module Name: sync_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity
sync_controller
is
generic
(
c_number_of_pps_per_sync
:
integer
:
=
10
;
c_pps_length
:
integer
:
=
10
);
port
(
clk_ref_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
pps_i
:
in
std_logic
;
sync_o
:
out
std_logic
);
end
sync_controller
;
architecture
Behavioral
of
sync_controller
is
signal
s_pps_counter
:
integer
;
signal
s_pps_r0
:
std_logic
;
signal
s_pps_r1
:
std_logic
;
signal
s_pps_r2
:
std_logic
;
signal
s_pps_r3
:
std_logic
;
signal
s_pps_edge
:
std_logic
;
signal
s_pps_length_counter
:
integer
;
signal
s_pps_delay_counter
:
integer
;
signal
s_sync_internal
:
std_logic
;
signal
s_sync_internal_r0
:
std_logic
;
signal
s_sync_internal_r1
:
std_logic
;
signal
s_sync_internal_edge
:
std_logic
;
signal
s_sync_extend
:
std_logic
;
signal
s_pps_delay
:
integer
:
=
2
;
attribute
MARK_DEBUG
:
string
;
type
state
is
(
waiting_for_trigger
,
delay
,
extend_sync
);
signal
fsm_state
:
state
;
attribute
MARK_DEBUG
of
pps_i
:
signal
is
"TRUE"
;
attribute
MARK_DEBUG
of
sync_o
:
signal
is
"TRUE"
;
attribute
MARK_DEBUG
of
s_pps_counter
:
signal
is
"TRUE"
;
attribute
MARK_DEBUG
of
s_pps_length_counter
:
signal
is
"TRUE"
;
attribute
MARK_DEBUG
of
s_pps_delay_counter
:
signal
is
"TRUE"
;
attribute
MARK_DEBUG
of
s_pps_delay
:
signal
is
"TRUE"
;
attribute
MARK_DEBUG
of
fsm_state
:
signal
is
"TRUE"
;
begin
s_pps_edge
<=
'1'
when
s_pps_r0
=
'1'
and
s_pps_r1
=
'0'
else
'0'
;
--Process to generate the sync signal every c_number_of_pps_per_sync pps
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
(
rst_n_i
=
'0'
)
then
s_sync_internal
<=
'0'
;
s_pps_counter
<=
0
;
s_pps_r0
<=
'0'
;
s_pps_r1
<=
'0'
;
s_pps_r2
<=
'0'
;
s_pps_r3
<=
'0'
;
else
s_pps_r0
<=
pps_i
;
s_pps_r1
<=
s_pps_r0
;
s_pps_r2
<=
s_pps_r1
;
s_pps_r3
<=
s_pps_r2
;
if
(
s_pps_edge
=
'1'
)
then
if
(
s_pps_counter
=
c_number_of_pps_per_sync
-1
)
then
s_pps_counter
<=
0
;
s_sync_internal
<=
'1'
;
else
s_pps_counter
<=
s_pps_counter
+
1
;
s_sync_internal
<=
'0'
;
end
if
;
else
s_sync_internal
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
process
;
s_sync_internal_edge
<=
'1'
when
s_sync_internal_r0
=
'1'
and
s_sync_internal_r1
=
'0'
else
'0'
;
process
(
clk_ref_i
)
begin
if
rising_edge
(
clk_ref_i
)
then
if
(
rst_n_i
=
'0'
)
then
s_pps_delay
<=
2
;
s_pps_length_counter
<=
0
;
s_sync_extend
<=
'0'
;
s_pps_delay_counter
<=
0
;
fsm_state
<=
waiting_for_trigger
;
else
s_sync_internal_r0
<=
s_sync_internal
;
s_sync_internal_r1
<=
s_sync_internal_r0
;
case
fsm_state
is
when
waiting_for_trigger
=>
if
(
s_sync_internal_edge
=
'1'
)
then
fsm_state
<=
delay
;
s_pps_delay_counter
<=
s_pps_delay_counter
+
1
;
end
if
;
when
delay
=>
if
(
s_pps_delay_counter
=
s_pps_delay
)
then
fsm_state
<=
extend_sync
;
s_pps_delay_counter
<=
0
;
s_sync_extend
<=
'1'
;
s_pps_length_counter
<=
s_pps_length_counter
+
1
;
--if(s_pps_delay = 2) then
-- s_pps_delay <= 4;
--else
-- s_pps_delay <= 2;
--end if;
else
s_pps_delay_counter
<=
s_pps_delay_counter
+
1
;
end
if
;
when
extend_sync
=>
if
(
s_pps_length_counter
=
c_pps_length
)
then
s_pps_length_counter
<=
0
;
s_sync_extend
<=
'0'
;
fsm_state
<=
waiting_for_trigger
;
else
s_pps_length_counter
<=
s_pps_length_counter
+
1
;
s_sync_extend
<=
'1'
;
end
if
;
end
case
;
end
if
;
end
if
;
end
process
;
sync_o
<=
s_sync_extend
;
end
Behavioral
;
FCWR_tests/fmc_support_gw/vivado_ip/sync_controller/xgui/sync_controller_v1_0.tcl
0 → 100644
View file @
0cd5cded
# Definitional proc to organize widgets for parameters.
proc
init_gui
{
IPINST
}
{
ipgui::add_param $IPINST -name
"Component_Name"
#Adding Page
ipgui::add_page $IPINST -name
"Page 0"
ipgui::add_param $IPINST -name
"c_pps_length"
ipgui::add_param $IPINST -name
"c_number_of_pps_per_sync"
}
proc
update_PARAM_VALUE.c_number_of_pps_per_sync
{
PARAM_VALUE.c_number_of_pps_per_sync
}
{
# Procedure called to update c_number_of_pps_per_sync when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.c_number_of_pps_per_sync
{
PARAM_VALUE.c_number_of_pps_per_sync
}
{
# Procedure called to validate c_number_of_pps_per_sync
return true
}
proc
update_PARAM_VALUE.c_pps_length
{
PARAM_VALUE.c_pps_length
}
{
# Procedure called to update c_pps_length when any of the dependent parameters in the arguments change
}
proc
validate_PARAM_VALUE.c_pps_length
{
PARAM_VALUE.c_pps_length
}
{
# Procedure called to validate c_pps_length
return true
}
proc
update_MODELPARAM_VALUE.c_number_of_pps_per_sync
{
MODELPARAM_VALUE.c_number_of_pps_per_sync PARAM_VALUE.c_number_of_pps_per_sync
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.c_number_of_pps_per_sync}
]
${MODELPARAM_VALUE.c_number_of_pps_per_sync}
}
proc
update_MODELPARAM_VALUE.c_pps_length
{
MODELPARAM_VALUE.c_pps_length PARAM_VALUE.c_pps_length
}
{
# Procedure called to set VHDL generic/Verilog parameter value
(
s
)
based on TCL parameter value
set_property value
[
get_property value
${PARAM_VALUE.c_pps_length}
]
${MODELPARAM_VALUE.c_pps_length}
}
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/component.xml
View file @
0cd5cded
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Click to expand it.
FCWR_tests/fmc_support_gw/vivado_ip/wrpc/src/zcu102.vhd
View file @
0cd5cded
...
...
@@ -119,11 +119,13 @@ entity zcu102 is
-- Voltage converter enabling pin
voltage_conv_en_o
:
out
std_logic
;
clk_125mhz_o
:
out
std_logic
clk_125mhz_o
:
out
std_logic
;
clk_ref_o
:
out
std_logic
;
clk_sec_o
:
out
std_logic
);
end
zcu102
;
architecture
rtl
of
zcu102
is
component
reset_gen
...
...
@@ -334,6 +336,7 @@ begin
debug0_o
<=
wr_ref_clk
;
debug1_o
<=
pps_out
;
--debug3_o <= ;
clk_ref_o
<=
wr_ref_clk
;
pps_out_o
<=
pps_out
;
...
...
@@ -372,6 +375,8 @@ begin
O
=>
s_sec_ref_clkg
,
I
=>
s_sec_ref_clk
);
clk_sec_o
<=
s_sec_ref_clkg
;
------------------------------------------------------------------------------
-- External MHz clock
------------------------------------------------------------------------------
...
...
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