For Developers
Here is some information for people who want to contribute to the development of switch's HDL. Note that we use HDLmake tool to make our life easier. An unfinished drawing of the architecture of switch HDL is here. Note that the switch is under development and some details of the drawing might be out of date, the general picture remains.
HDLmake
- Tool for generating multi-purpose makefiles for FPGA projects that is used to simulate and synthesize switch HDL
- The below explanation of the switch HDL simulation/synthesis assumes that you are familiar with HDLmake and use it
- The website of the HDLmake project is here
- Handful information about using HDLmake can be found in Chapter 3.4.2 of the Getting Started with the SPEC tutorial that is part of Getting Started with SPEC project
- Beware: we are currently using ISYP branch of the HDLmake
HDL directory structure
ip_cores - contains external cores used by the project (included in the
git repo as submodules)
modules - include switch-specific and FPGA-independent VHDL modules
platform - contains FPGA-dependent VHDL code
sim - contains SystemVerilog modeles, drivers and register layouts used
by testbenches
syn - contains ISE project files for sythesis (e.g. if you want to
synthesize for 18-port switch, you should go into syn/scb_18ports)
testbench - contains testbenches for top-level of the switch and
separate modules, also for a network of switches
top - contains top-levels and constraint (UCF) files
The top/bare_top/ contains scb_top_bare.vhd which is a configurable top level entity of the switch. This entity is used by both, sythesis top levels and testbench of the switch. In other words, this is a configurable IP which needs some more VHDL to simulate or synthesize.
Switch Testbench
The testbench of the switch is written in SystemVerilog and contained in testbench/scb_top/main.sv. It uses top/bare_top/scb_top_bare.vhd indirectly:
- scb_top_bare.vhd is instantiated in top/bare_top/scb_top_sim.vhd
- scb_top_sim.vhd is wrapped by testbench/scb_top/scb_top_sim_svwrap.svh
- scb_top_sim_svwrap.svh is used in the main testbench: testbench/scb_top/main.sv
Switch Synthesis
ISE projects for switch synthesis are defined for different number of ports (i.e. 8, 15, and 18) in the syn directory (e.g.: syn/scb_18ports for 18-switch synthesis). This is done to speed up development process: synthesis for 18 ports takes 4h, for 8 ports 1h, so we develop synthesizing for 8 ports.
The ISE project in syn/scb_18ports relates to the top entity and UCF
file in top/scb_18ports directory, i.e. scb_top_synthesis.vhd and
scb_top_sythesis.ucf.
The scb_top_sythesis.vhd instantiates top/bare_top/scb_top_bare.vhd
with proper parameters.
Steps to run switch simulation
(this assumes you use Linux and have HDLmake in place, otherwise good luck)
Version of HDL compatible with v3.3 software, tag: wr-switch-sw-v3.3
The following steps are needed to simulate the switch
- Clone the repo with submodules
git clone --recursive git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git - Checkout tag that is compatible with v3.3 software
(wr-switch-sw-v3.3) and updates submodules
git checkout wr-switch-sw-v3.3
git submodules update - Add symbolic link in sim to wr-cores simulation drivers:
cd sim
ln -s ../ip_cores/wr-cores/sim wr-hdl - Enter testbench/scb_top and generate makefiles using HDLmake
cd testbench/scb_top
hdlmake --make-sim - This should result in generation of proper Makefile, now you can
simulate by running run.do script
do run.do - This will probably not finish successfully since the repo does not contain wave.do file
- The switch does not allow traffic through due to some bugs in simulation, corrected in V4
Version of HDL compatible with v4 software (currently master, once released will be wr-switch-sw-v4)
The following steps are needed to simulate the switch
- Clone the repo with submodules
git clone --recursive git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git - Add symbolic link in sim to wr-cores simulation drivers:
cd sim
ln -s ../ip_cores/wr-cores/sim wr-hdl - Enter testbench/scb_top and generate makefiles using HDLmake
cd testbench/scb_top
hdlmake --make-sim - This should result in generation of proper Makefile, now you can
simulate by running run.do script
do run.do - This will probably not finish successfully since the repo does not contain wave.do file
Steps to sythesize switch HDL
The following steps are needed to sythesize the switch for 18 ports
- Clone the repo with submodules
git clone --recursive git:https://www.ohwr.org/white-rabbit/wr-switch-hdl.git - Enter syn/scb_18ports and generate makefiles using HDLmake
cd syn/scb_18ports
hdlmake --make-syn - Run sythesis:
make - Go home, it should be ready in 4h...