Improve multiport Linked List inside the Switching Core
In some situations the multiport linked list (MLL) module is a
performance bottleneck of the Switching Core. This happens especially
when Switching Core has to handle high priority (HP) frames. In this
case, since our switch is cut-through, we have a race condition between
the Input Block (IB) requesting memory pages to receive a frame and
Output Block (OB) reading validated pages and sending data to the
If MLL is not able to provide quickly new memory page to IB, the sending FSM in OB will stall waiting for next page being completely written (or with end-of-frame bit set). If OB stalls, Tx PCS in the Endpoint can underrun and the frame is cut (as a consequence, only a fragment with incorrect CRC is received on the other side of the link).
Multiport Linked List should be re-written to be able to serve requests from all 18 ports of the switch more efficiently.