Commits · wrs-lj-ext-ho-WRITE · Projects / White Rabbit Switch - Gateware · Open Hardware Repository

29 Jul, 2020 2 commits
- Fixed accidental old code from latest merge · 73e3e5c6
  José López Jiménez authored Jul 29, 2020
  
  73e3e5c6
- Updated wr-cores submodule with softpll regs for holdover exp board support · 2e3dce58
  José López Jiménez authored Jul 29, 2020
  
  2e3dce58
07 Jul, 2020 1 commit
- Support for UART in holdover exp board · 7ec1f1a1
  José López Jiménez authored Jul 07, 2020
```
Also, doubled size of U_DPRAM
```
  7ec1f1a1
02 Jul, 2020 1 commit
- Enable use of Main VCO power switch from GPIO controller · cd61fa8a
  José López Jiménez authored Jul 02, 2020
  
  cd61fa8a
30 Jun, 2020 1 commit
- Added capabilities for another DAC in SoftPLL and its associated regs · a4ce5847
  José López Jiménez authored May 29, 2020
  
  a4ce5847
27 May, 2020 3 commits
- Created another DAC controller for the ho exp board · b86f3d0f
  José López Jiménez authored May 27, 2020
```
Until further development, this DAC only mirrors the actuation that is commanded for the Main DAC loop.
```
  b86f3d0f
- DAC signals from scb_bare top to the output ports · e65bed74
  José López Jiménez authored May 27, 2020
```
Also, renamed the signals to align with the existing naming convention of the Helper and Main DAC ports.
```
  e65bed74
- Removed vestigial ext dac port · fc9c221d
  José López Jiménez authored May 27, 2020
  
  fc9c221d
20 Dec, 2019 2 commits
- Merge branch 'joselj-ljwrs-dev' of bitbucket.org:sevensols/wr-switch-hdl into joselj-ljwrs-dev · 4ccde3e6
  José López Jiménez authored Dec 20, 2019
  
  4ccde3e6
- Integrated new I2C sensor and defined interface with expansion board · a92609d3
  José López Jiménez authored Dec 20, 2019
  
  a92609d3
19 Dec, 2019 1 commit
- The FPGA REF CLK is now connected to the output 5 of the AD9516 (instead of 8) · 76196c22
  Mario Lizana authored Dec 19, 2019
  
  76196c22
03 Sep, 2019 1 commit
- Fixes on the timing scheme of the 18 port low jitter version · 0e9ae9d4
  José López Jiménez authored Sep 03, 2019
```
Also mended some typos.
```
  0e9ae9d4
12 Jun, 2019 1 commit
- Cleaned and adapted code for wr switch lj components · 3681f28d
  José López Jiménez authored Jun 12, 2019
  
  3681f28d
28 May, 2019 1 commit
- Added holdover expansion pins and changed GM PLL pinout · e278e934
  Jose Lopez authored May 28, 2019
  
  e278e934
27 May, 2019 1 commit
- Pinout changes for low jitter clocking · 5270dde2
  Jose Lopez authored May 27, 2019
  
  5270dde2
14 May, 2019 2 commits
- Solved typo in 8-port constraints file and reverted to older hdlmake · 9228ccd6
  Jose Lopez authored May 14, 2019
  
  9228ccd6
- Changed submodule path post-migration · 67879dad
  Jose Lopez authored May 14, 2019
  
  67879dad
20 Dec, 2016 8 commits
- Modified synthesis configuration for 18ports build · d5d48576
  Mattia Rizzi authored Dec 20, 2016
  
  d5d48576
- Updated wr-cores for external board · b8917f9d
  Mattia Rizzi authored Dec 20, 2016
  
  b8917f9d
- Modified contrains for 8 ports · ab7c802d
  Mattia Rizzi authored Dec 20, 2016
  
  ab7c802d
- Modifed Manifests to build correctly the project file · 40afecdc
  Mattia Rizzi authored Dec 20, 2016
  
  40afecdc
- Added support for the external board · 796d4eb7
  Mattia Rizzi authored Dec 20, 2016
  
  796d4eb7
- Added a powerdown line to shutdown the noisy MMCMs when external PLL is detected · f9bdf7b3
  Mattia Rizzi authored Dec 20, 2016
  
  f9bdf7b3
- Modifed constrains for WRS low jitter daughterboard · d849cd87
  Mattia Rizzi authored Dec 20, 2016
  
  d849cd87
- Added module to check the presence of the external board · db8d013c
  Mattia Rizzi authored Dec 20, 2016
  
  db8d013c
28 Nov, 2016 1 commit
- Modified contrain file for 8 ports · f5543a85
  Mattia Rizzi authored Nov 28, 2016
  
  f5543a85
25 Nov, 2016 1 commit
- update general-cores and wr-cores since sdb crossbar is now fixed for metadata · 1d500455
  Grzegorz Daniluk authored Nov 25, 2016
  
  1d500455
23 Nov, 2016 1 commit
- update simulation manifests to use new hdlmake · aef7d8ab
  Grzegorz Daniluk authored Nov 23, 2016
  
  aef7d8ab
22 Nov, 2016 3 commits
- update reported GW version to v5.0 · 388f812d
  Grzegorz Daniluk authored Nov 22, 2016
  
  388f812d
- update wr-cores for new release · 99170f6d
  Grzegorz Daniluk authored Nov 22, 2016
  
  99170f6d
- update general-cores to HEAD of master · 03b27a71
  Grzegorz Daniluk authored Nov 22, 2016
  
  03b27a71
21 Nov, 2016 2 commits
- update synthesis Manifests to use new hdlmake · 15b94c3a
  Grzegorz Daniluk authored Nov 21, 2016
  
  15b94c3a
- Merge branch 'greg-swcore' into proposed_master · 0f1a7547
  Grzegorz Daniluk authored Nov 21, 2016
  
  0f1a7547
18 Nov, 2016 7 commits
- swcore: fix output block frame dropping on HP (still not perfect) · 1a662f42
  Grzegorz Daniluk authored Nov 18, 2016
  
  1a662f42
- swcore: multiport LL, fix write ports split · 7a1b9191
  Grzegorz Daniluk authored Nov 18, 2016
  
  7a1b9191
- swcore: add wishbone register to enable dropping traffic in OB if HP frames are queued · a72c35b0
  Grzegorz Daniluk authored Sep 13, 2016
  
  a72c35b0
- swcore: use record-based interfaces for multiport linked list · e94dffe1
  Grzegorz Daniluk authored Sep 13, 2016
  
  e94dffe1
- swcore: multiport LL, use 3 write ports · babcf5c0
  Grzegorz Daniluk authored Sep 12, 2016
  
  babcf5c0
- swcore: multiport LL configurable number of write ports to MPRAM · ce4988d9
  Grzegorz Daniluk authored Sep 12, 2016
  
  ce4988d9
- swcore: multiport LL rewritten to use multiport RAM with 2 write ports · 8452ca3a
  Grzegorz Daniluk authored Sep 03, 2016
  
  8452ca3a