swcore: added xswc_input block (pWB), debugging stuff, there are bugs in xswc_output (missing some words when stab/stall strange combinations

swcore[v2->v3 port]: a simple simulation for the wishbonized and wrapped (multiple times) swcore is working ... : sending/receiving few frames

swcore[v2->v3 port] wrappers for the wishbonized (xswc_core) swcore written, they enable the pWB emulators to talk to xswc_core (two wrappers needed). added simulation (xswc_core.sv) which instanciates 7 ports and wrapped xswc_core)

swcore[v2->v3 port]: added Tom's pWB<->WRF adapters into the wrapper, so we have a swcore which has pWB I/F, next step: change the simulation to test how it works

swcore[v2->v3 port]: simulation working for altera ip/genrams but cannot make it work for xilinx, leaving simulation with xilinx for later

swcore[v2->v3 port] the old simulation works (depending on some old code, e.g.: platform/genrams) that is not commited..

swcore[v2->v3 port]: changed generic_ssram_dualport_singleclock to generic_dpram in packet_mem and linked_list