swcore[new mpm]: bugfix in the MPM: empty HIGH at the very last word caused the Rx Path to go nuts, fixed by ANDing d_last_int with counter_equals

swcore[new mpm]: corrected the way the first page is cleared and how we make sure that it is cleared at the end of the first page receptipn

swcore[new mpm]: more debugging and corrections of input block, changing simulatioon to test 16 ports

RTU: added optional hack (can be turned on with generics) which was introduce to prevent Endpoint from pushing new requests to RTU while the current one is currently handled. This might cause errors in forwaring packets (RTU handling requets of packets which were dropped by Endpint because the buffer has become full waiting for decisions of RTU of the previous packets. Everythig because RTU is to slow .... (testing throwing bursts of frames at 14 ports simultaneusly). Also: added missing prioriy connection in the wrapper

RTU: modified the WB interface of RTU to extend the number of ports supported by rtu (it was up to 10). Now, WB-wise RTU supports 20 ports (however, there are other limitations which make the current max number of ports = 16)

swcore[new mpm]: input/output blocks debugged (output block still needs few more features and performance boost

swcore[new mpm]: revised input block. I reanalized the FSMs (we have 4 there) and improved the synchronization between them, cleaned the code, etc. Needs more debugging. At this stage, code passes simple test

swcore[new mpm]: modified reading path to prevent reading process overtake writing (added some waiting at the beginning of pck and at the end of each page if new page not read)

swcore[new mpm]: debugged input and output (first version which does not loose pages during the basic tests !!!)

swcore[new mpm]: added FSM to manage Linked List writes, it enables for some performance optimizatio,prevents STALLing, loosing pages

swcore[new mpm]: modified linked list to enable clearing pckstart_addr with the last page of the previous pck

swcore[new mpm]: bugfix in asynchronous MPM (the LL address mux-ed in p_ll_mux_addr was not synch-ed with delayed grand and data registering in mpm_rpath_io_block

swcore[new mpm]: freeing module adapted to new usecnt handling (the usecnt of pck stored only with the first page). This is the first swcore version working fully with the new MPM, however, it is still buggy and needs tests

swcore[new mpm]: testbenches and wrappers changed to include new (for new mpm, i/o blocks) parameters

swcore[new mpm]: page allocator (both old and new) modified to enable a new way of page usecnt handling: we store the usecnt only in the first page of the pck, the non-first pages have usecnt=1. When pck is sent on the output port, only the usecnt of the first page is decremented unless the usecnt==1, then we free all the pages allocated to the pck, so the page allocator needs to indicate if the usecnt is 1

swcore[new mpm]: bugfix in asynchronous MPM (dreq=LOW on the one but last word caused readout problem and dlast to be HIGH when dvalid=LOW while not yet the last word)

swcore[new_mpm + cut-through]: modified LinkedList for the needs of the new_mpm (direct access with core_clock) and enabled cut-through (validation of page entry, and waiting on non-validated entry. Additionally, the write access has been speeded up (two writes, one for valid entry, second for the next non-valid entry), and the Round Robin arbitration has been speeded up

swcore[new mpm]: modified (thoroughly) input_block (+ other necessary changes) to work with the new mpm (asynch by Tom)

swcore[generic-ing]: generic-azed hard-coded values (connected with rr_arbiter usage), identified limitation (in prio_encoder,TODO), added some description, tested with different port number values

swcore[generic-azing]: generic simulation (for any number of ports) works, cleaned up, added README to testbenches, changed names to add clarity to the naming