Commits · ML-tmp-btrain-debug-v6 · Projects / White Rabbit Switch

08 Jan, 2021 5 commits
- hack wr-cores to make sim work · cedf5726
  Maciej Lipinski authored Jan 08, 2021
  
  cedf5726
- bug caught in RX PCS · a05ee6da
  Maciej Lipinski authored Jan 08, 2021
  
  a05ee6da
- remove unused code... · 05089204
  Maciej Lipinski authored Jan 08, 2021
  
  05089204
- working check of link-down at different moments of frame rx · 7ff88d15
  Maciej Lipinski authored Jan 08, 2021
  
  7ff88d15
- [SIM] make the top simulation work again · 39cccfb9
  Maciej Lipinski authored Jan 08, 2021
  
  39cccfb9
06 Apr, 2020 1 commit
- update gateware version to v6.0 · d315bf7b
  Grzegorz Daniluk authored Apr 03, 2020
  
  d315bf7b
03 Apr, 2020 1 commit
- lpdc: allow WRS shutting down the interface without breaking Tx LPDC · 8b7d73e6
  Grzegorz Daniluk authored Apr 03, 2020
  
  8b7d73e6
20 Jan, 2020 1 commit
- update wr-cores to fix another LPDC bug · 149742fa
  Grzegorz Daniluk authored Jan 20, 2020
  
  149742fa
07 Jan, 2020 1 commit
- pstats: more registers to improve timing · 0f9aee8f
  Grzegorz Daniluk authored Jan 07, 2020
  
  0f9aee8f
17 Dec, 2019 2 commits
- add project file for release · 350789e8
  Grzegorz Daniluk authored Dec 17, 2019
  
  350789e8
- pstats: add registers to improve timing · 982b8362
  Grzegorz Daniluk authored Dec 17, 2019
  
  982b8362
09 Dec, 2019 1 commit
- lpd: update wr-cores for chicken-bits and rx synchronizer · 3cc77ba7
  Grzegorz Daniluk authored Dec 09, 2019
  
  3cc77ba7
30 Aug, 2019 13 commits
- Merge branch 'greg-lpd-rebased' into proposed_master · 5d5f1a74
  Grzegorz Daniluk authored Aug 30, 2019
  
  5d5f1a74
- fix low-jitter constraints after rebase · 868072d9
  Grzegorz Daniluk authored Aug 30, 2019
  
  868072d9
- low phase drift calibration: cleanup 8-port version · 8c21725c
  Grzegorz Daniluk authored Jul 14, 2019
  
  8c21725c
- cleanup low phase drift calibration interface · fe0ba167
  Grzegorz Daniluk authored Jul 12, 2019
  
  fe0ba167
- rt_subsystem: add external samplers for port that are not calibrated for low phase drift · 095c800f
  Grzegorz Daniluk authored Jul 10, 2019
  
  095c800f
- low phase drift calibration only for 12 ports · 1b4724a5
  Grzegorz Daniluk authored Jul 10, 2019
```
Possible through the combination of global and regional clocks. Cannot
have it for all ports because we don't have enough global/regional clock
nets in virtex-6.
```
  1b4724a5
- top: manual control of TX/RX clock buffers for PHYs through generics · 640c7bb4
  Tomasz Wlostowski authored Jul 03, 2019
  
  640c7bb4
- constraining tx_out clock produced by GTX_LP · 0f99e5cf
  Grzegorz Daniluk authored Jun 19, 2019
  
  0f99e5cf
- phy determinism for 18-port version · d49e5993
  Grzegorz Daniluk authored Jun 19, 2019
  
  d49e5993
- Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of… · 5eb9d456
  Tomasz Wlostowski authored Nov 14, 2018
```
Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...
```
  5eb9d456
- top/scb_8ports: 8-port PoC firmware with deterministic V6 transceiver config · bbe909f5
  Tomasz Wlostowski authored Jun 19, 2018
  
  bbe909f5
- top/bare_top: move DDMTD samplers to the PHY module, g_without_network… · 93a74f10
  Tomasz Wlostowski authored Jun 19, 2018
```
top/bare_top: move DDMTD samplers to the PHY module, g_without_network instantiates the endpoints but no RTU/Swcore
```
  93a74f10
- wrsw_rt_subsystem: allow externally sampled RX clocks (DDMTD inside the PHY module) · 6b3c0e71
  Tomasz Wlostowski authored Jun 19, 2018
  
  6b3c0e71
20 Aug, 2019 2 commits
- update wr-cores: low-jitter support merged to proposed_master · 205a4500
  Grzegorz Daniluk authored Aug 20, 2019
  
  205a4500
- Merge branch 'greg-low-jitter' into proposed_master · ebe9d4c9
  Grzegorz Daniluk authored Aug 20, 2019
  
  ebe9d4c9
19 Aug, 2019 1 commit
- ljd: use ad9516 lock signal and reset it with ext_pll_reset bit · 76eaac7d
  Grzegorz Daniluk authored Aug 19, 2019
  
  76eaac7d
15 Aug, 2019 2 commits
- add _ljd_ prefix to everything Low-Jitter Daughterboard related · 90536db3
  Grzegorz Daniluk authored Aug 15, 2019
  
  90536db3
- ljd: move daughterboard detection inside rt subsystem · f8127017
  Grzegorz Daniluk authored Aug 15, 2019
```
Less code duplication in scb_8ports and scb_18ports top hdl.
```
  f8127017
14 Aug, 2019 1 commit
- wrs_ljd: use bufr for 8port like to 18port · 0e2e8d7c
  Grzegorz Daniluk authored Aug 14, 2019
  
  0e2e8d7c
13 Aug, 2019 1 commit
- softpll: use generic to define number of ext channels · 8d17a35c
  Grzegorz Daniluk authored Aug 13, 2019
  
  8d17a35c
12 Aug, 2019 1 commit
- rename ext_board_check to wrsw_ext_board_check · 1a8c42fa
  Grzegorz Daniluk authored Aug 12, 2019
  
  1a8c42fa
09 Aug, 2019 7 commits
- remove unused I/Os and assign default values · 5e7d55d6
  Grzegorz Daniluk authored Aug 09, 2019
  
  5e7d55d6
- wrsw_ext_board: synchronous reset for FSM · 1c33a80f
  Grzegorz Daniluk authored Aug 09, 2019
  
  1c33a80f
- wrsw_ext_board: fix formatting, no technical change · 78d3f242
  Grzegorz Daniluk authored Aug 09, 2019
  
  78d3f242
- rt_subsystem: add generic for low jitter daughterboard support · a8d8867f
  Grzegorz Daniluk authored Aug 08, 2019
  
  a8d8867f
- Modified synthesis configuration for 18ports build · b5489272
  Mattia Rizzi authored Dec 20, 2016
  
  b5489272
- Modified constraints for low-jitter daughterboard · 7d9971a2
  Mattia Rizzi authored Aug 09, 2019
  
  7d9971a2
- Updated wr-cores for external board · 31d7252e
  Mattia Rizzi authored Dec 20, 2016
  
  31d7252e