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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
fe0ba167
Commit
fe0ba167
authored
Jul 12, 2019
by
Grzegorz Daniluk
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cleanup low phase drift calibration interface
parent
095c800f
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5 changed files
with
11 additions
and
10 deletions
+11
-10
general-cores
ip_cores/general-cores
+1
-1
wr-cores
ip_cores/wr-cores
+1
-1
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+4
-3
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+2
-2
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+3
-3
No files found.
general-cores
@
dcc7cc33
Subproject commit
17d08e592c482848bf1ce9401f39a2a8749d04f4
Subproject commit
dcc7cc33ffa3bce1a9a3da9ea317e3c768830398
wr-cores
@
25deb517
Subproject commit
b23b87769f895a8f75402ac47b401bf02bff6a57
Subproject commit
25deb51759cf467df4fdeeca3bd10e4e793f71ca
top/bare_top/scb_top_bare.vhd
View file @
fe0ba167
...
...
@@ -794,7 +794,8 @@ begin
g_use_new_rxcrc
=>
true
,
g_use_new_txcrc
=>
false
,
g_with_stop_traffic
=>
g_with_watchdog
,
g_ep_idx
=>
i
)
g_phy_lpcalib
=>
g_phy_lpcalib
(
i
),
g_ep_idx
=>
i
)
port
map
(
clk_ref_i
=>
clk_ref_i
,
clk_sys_i
=>
clk_sys
,
...
...
@@ -811,8 +812,8 @@ begin
phy_rst_o
=>
phys_o
(
i
)
.
rst
,
phy_loopen_o
=>
phys_o
(
i
)
.
loopen
,
phy_
debug_i
=>
phys_i
(
i
)
.
debug
,
phy_
debug_o
=>
phys_o
(
i
)
.
debug
,
phy_
lpc_stat_i
=>
phys_i
(
i
)
.
lpc_stat
,
phy_
lpc_ctrl_o
=>
phys_o
(
i
)
.
lpc_ctrl
,
phy_rdy_i
=>
phys_i
(
i
)
.
rdy
,
phy_ref_clk_i
=>
phys_i
(
i
)
.
ref_clk
,
phy_tx_data_o
=>
ep_dbg_data_array
(
i
),
-- phys_o(i).tx_data, --
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
fe0ba167
...
...
@@ -51,7 +51,7 @@ package wrsw_top_pkg is
syncen
:
std_logic
;
tx_data
:
std_logic_vector
(
15
downto
0
);
tx_k
:
std_logic_vector
(
1
downto
0
);
debug
:
std_logic_vector
(
15
downto
0
);
lpc_ctrl
:
std_logic_vector
(
15
downto
0
);
end
record
;
...
...
@@ -66,7 +66,7 @@ package wrsw_top_pkg is
rx_enc_err
:
std_logic
;
rx_bitslide
:
std_logic_vector
(
4
downto
0
);
rdy
:
std_logic
;
debug
:
std_logic_vector
(
15
downto
0
);
lpc_stat
:
std_logic_vector
(
15
downto
0
);
end
record
;
type
t_phyif_output_array
is
array
(
integer
range
<>
)
of
t_phyif_output
;
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
fe0ba167
...
...
@@ -792,8 +792,8 @@ begin
rx_enc_err_o
=>
from_phys
(
i
)
.
rx_enc_err
,
rx_bitslide_o
=>
from_phys
(
i
)
.
rx_bitslide
,
rst_i
=>
to_phys
(
i
)
.
rst
,
debug_o
=>
from_phys
(
i
)
.
debug
,
debug_i
=>
to_phys
(
i
)
.
debug
,
lpc_stat_o
=>
from_phys
(
i
)
.
lpc_stat
,
lpc_ctrl_i
=>
to_phys
(
i
)
.
lpc_ctrl
,
loopen_i
=>
to_phys
(
i
)
.
loopen
,
pad_txn_o
=>
gtx_txn_o
(
i
),
pad_txp_o
=>
gtx_txp_o
(
i
),
...
...
@@ -830,7 +830,7 @@ begin
rdy_o
=>
from_phys
(
i
)
.
rdy
);
from_phys
(
i
)
.
rx_sampled_clk
<=
'0'
;
from_phys
(
i
)
.
debug
<=
(
others
=>
'0'
);
from_phys
(
i
)
.
lpc_stat
<=
(
others
=>
'0'
);
end
generate
gen_no_lp
;
from_phys
(
i
)
.
ref_clk
<=
clk_ref
;
...
...
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