Commit f31bf3a0 authored by Maciej Lipinski's avatar Maciej Lipinski

CI: Add execution of script to generate files with repo versions, change to 18p.

parent 5187d38a
Pipeline #4999 failed with stage
in 162 minutes and 36 seconds
......@@ -16,6 +16,8 @@ stages:
# - apt-get install -y python
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - cd ../../modules/wrsw_hwiu
# - python gen_ver.py
# - cd ../../
# - cd sim
# - ln -s ../ip_cores/wr-cores/sim wr-hdl
......@@ -25,50 +27,56 @@ stages:
# - make
# - vsim -c -do run.do
job_scb_top_8p_syn:
stage: syn
tags:
- xilinx_ISE_14.7
script:
- /entrypoint.sh
- source ~/setup_ise147.sh
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- cd top/bare_top
- python gen_sdbsyn.py --project wr_switch
- cat synthesis_descriptor.vhd
- cd ../../syn/scb_8ports
- hdlmake makefile
- make
artifacts:
name: SCB_TOP_8P_CI_$CI_JOB_ID
paths:
- syn/scb_8ports/*.syr
- syn/scb_8ports/*.mrp
- syn/scb_8ports/*.bit
- syn/scb_8ports/*.bin
- syn/scb_8ports/*.par
- syn/scb_8ports/*.twr
#job_scb_top_8p_syn:
#stage: syn
#tags:
#- xilinx_ISE_14.7
#script:
#- /entrypoint.sh
#- source ~/setup_ise147.sh
#- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
#- cd top/bare_top
#- python gen_sdbsyn.py --project wr_switch
#- cat synthesis_descriptor.vhd
#- cd ../../modules/wrsw_hwiu
#- python gen_ver.py
#- cat gw_ver_pkg.vhd
#- cd ../../syn/scb_8ports
#- hdlmake makefile
#- make
#artifacts:
#name: SCB_TOP_8P_CI_$CI_JOB_ID
#paths:
#- syn/scb_8ports/*.syr
#- syn/scb_8ports/*.mrp
#- syn/scb_8ports/*.bit
#- syn/scb_8ports/*.bin
#- syn/scb_8ports/*.par
#- syn/scb_8ports/*.twr
#job_scb_top_18p_syn:
# stage: syn
# tags:
# - xilinx_ISE_14.7
# script:
# - /entrypoint.sh
# - source ~/setup_ise147.sh
# - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - cat synthesis_descriptor.vhd
# - cd ../../syn/scb_18ports
# - hdlmake makefile
# - make
# artifacts:
# name: SCB_TOP_8P_CI_$CI_JOB_ID
# paths:
# - syn/scb_18ports/*.syr
# - syn/scb_18ports/*.mrp
# - syn/scb_18ports/*.bit
# - syn/scb_18ports/*.bin
# - syn/scb_18ports/*.par
# - syn/scb_18ports/*.twr
job_scb_top_18p_syn:
stage: syn
tags:
- xilinx_ISE_14.7
script:
- /entrypoint.sh
- source ~/setup_ise147.sh
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- cd top/bare_top
- python gen_sdbsyn.py --project wr_switch
- cat synthesis_descriptor.vhd
- cd ../../modules/wrsw_hwiu
- python gen_ver.py
- cat gw_ver_pkg.vhd
- cd ../../syn/scb_18ports
- hdlmake makefile
- make
artifacts:
name: SCB_TOP_8P_CI_$CI_JOB_ID
paths:
- syn/scb_18ports/*.syr
- syn/scb_18ports/*.mrp
- syn/scb_18ports/*.bit
- syn/scb_18ports/*.bin
- syn/scb_18ports/*.par
- syn/scb_18ports/*.twr
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment