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White Rabbit Switch - Gateware
Commit c9ea0477 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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[debug]: more debug signals for swcore

parent 6dfd8eb4
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Showing with 351 additions and 35 deletions
modules/wrsw_swcore/mpm/mpm_read_path.vhd
View file @ c9ea0477
......@@ -492,6 +492,6 @@ begin -- rtl
core(i).pf_pg_lines <= core(i).pf_q(c_fbm_addr_width + c_line_size_width-1 downto c_fbm_addr_width);
end generate gen_io_core_blocks;
nice_dbg_o.ll_adr <= ll_addr_out;
nice_dbg_o.ll_adr(g_page_addr_width-1 downto 0) <= ll_addr_out;
end rtl;
modules/wrsw_swcore/mpm/mpm_rpath_io_block.vhd
View file @ c9ea0477
......@@ -531,8 +531,8 @@ begin -- behavioral
nice_dbg_o.ll_req <= ll_req_out;
nice_dbg_o.ll_grant <= ll_grant_i;
nice_dbg_o.ll_adr <= ll_addr_out;
nice_dbg_o.ll_next_page <= cur_ll.next_page;
nice_dbg_o.ll_adr(g_page_addr_width-1 downto 0) <= ll_addr_out;
nice_dbg_o.ll_next_page(g_page_addr_width-1 downto 0) <= cur_ll.next_page;
nice_dbg_o.ll_eof <= cur_ll.eof;
nice_dbg_o.ll_valid <= cur_ll.valid;
nice_dbg_o.page_fsm <= "000" when (page_state = FIRST_PAGE) else
......@@ -556,7 +556,7 @@ begin -- behavioral
nice_dbg_o.fetch_pg_words(6 downto 0) <= std_logic_vector(fetch_pg_words(6 downto 0));
nice_dbg_o.data <= df_d_i;
nice_dbg_o.data_rd <= df_rd_int;
nice_dbg_o.cur_page <= cur_page;
nice_dbg_o.cur_page(g_page_addr_width-1 downto 0) <= cur_page;
nice_dbg_o.df_empty <= df_empty_i;
nice_dbg_o.pf_we <= pf_we_int;
nice_dbg_o.pf_full <= pf_full_i;
......@@ -567,5 +567,7 @@ begin -- behavioral
nice_dbg_o.supress_pre_fetch <= supress_pre_fetch;
nice_dbg_o.fetch_pg_words_new <= fetch_pg_words_new;
nice_dbg_o.fetch_pg_words_used <= fetch_pg_words_used;
nice_dbg_o.wait_first_fetched <= wait_first_fetched;
nice_dbg_o.wait_next_valid_ll_read <= wait_next_valid_ll_read;
end behavioral;
modules/wrsw_swcore/optimized_new_allocator/swc_page_alloc_ram_bug.vhd
View file @ c9ea0477
......@@ -661,15 +661,15 @@ begin -- syn
res_almost_full_o <= res_almost_full;
end generate;
nice_dbg_o.free_pages <= std_logic_vector(free_pages);
nice_dbg_o.free_pages(g_page_addr_width downto 0) <= std_logic_vector(free_pages);
nice_dbg_o.res_almost_full <= or_reduce(res_almost_full);
nice_dbg_o.res_full <= or_reduce(res_full);
nice_dbg_o.q_write <= q_write_p1;
nice_dbg_o.q_read <= q_read_p0;
nice_dbg_o.rd_ptr <= std_logic_vector(rd_ptr_p0);
nice_dbg_o.wr_ptr <= std_logic_vector(wr_ptr_p1);
nice_dbg_o.in_pg <= q_input_addr_p1;
nice_dbg_o.out_pg <= q_output_addr_p1;
nice_dbg_o.rd_ptr(g_page_addr_width-1 downto 0) <= std_logic_vector(rd_ptr_p0);
nice_dbg_o.wr_ptr(g_page_addr_width-1 downto 0) <= std_logic_vector(wr_ptr_p1);
nice_dbg_o.in_pg(g_page_addr_width-1 downto 0) <= q_input_addr_p1;
nice_dbg_o.out_pg(g_page_addr_width-1 downto 0) <= q_output_addr_p1;
nice_dbg_o.grant_port_msk(g_num_ports-1 downto 0) <= alloc_req_d1.grant_vec;
nice_dbg_o.out_nomem_d1 <= out_nomem_d1;
nice_dbg_o.alloc_done <= done_p1;
......
modules/wrsw_swcore/swc_pck_pg_free_module.vhd
View file @ c9ea0477
......@@ -431,16 +431,16 @@ fsm_force_free : process(clk_i, rst_n_i)
-- GD Nice Debug
nice_dbg_o.free <= mmu_free;
nice_dbg_o.free_done <= mmu_free_done_i;
nice_dbg_o.pgadr <= current_page;
nice_dbg_o.pgadr(g_page_addr_width-1 downto 0) <= current_page;
nice_dbg_o.ffree <= mmu_force_free;
nice_dbg_o.ffree_done<= mmu_force_free_done_i;
nice_dbg_o.fsm <= free_FSM(2 downto 0);
nice_dbg_o.last_ucnt <= mmu_free_last_usecnt_i;
nice_dbg_o.ib_ffree <= ib_force_free_i;
nice_dbg_o.ib_ffree_done <= ib_force_free_done;
nice_dbg_o.ib_pgadr <= ib_force_free_pgaddr_i;
nice_dbg_o.ib_pgadr(g_page_addr_width-1 downto 0) <= ib_force_free_pgaddr_i;
nice_dbg_o.ob_free <= ob_free_i;
nice_dbg_o.ob_free_done <= ob_free_done;
nice_dbg_o.ob_pgadr <= ob_free_pgaddr_i;
nice_dbg_o.ob_pgadr(g_page_addr_width-1 downto 0) <= ob_free_pgaddr_i;
end syn;
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ c9ea0477
......@@ -554,7 +554,8 @@ package swc_swcore_pkg is
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
g_wb_ob_ignore_ack : boolean := true;
g_drop_outqueue_head_on_full : boolean := true
g_drop_outqueue_head_on_full : boolean := true;
g_port_number : integer
);
port (
clk_i : in std_logic;
......@@ -583,6 +584,7 @@ package swc_swcore_pkg is
src_o : out t_wrf_source_out;
wdog_o : out t_swc_fsms;
tap_out_o : out std_logic_vector(15 downto 0);
hp_count_o : out unsigned(63 downto 0);
nice_dbg_o : out t_dbg_swc_ob);
end component;
......
modules/wrsw_swcore/swc_wbgen2_pkg.vhd
View file @ c9ea0477
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : swc_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wrsw_swcore.wb
-- Created : Tue Sep 13 14:08:37 2016
-- Created : Fri Sep 23 11:31:56 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_swcore.wb
......@@ -26,6 +26,8 @@ package swc_wbgen2_pkg is
stat_max_fpg_i : std_logic_vector(15 downto 0);
cur_fpg_i : std_logic_vector(31 downto 0);
afull_thr_i : std_logic_vector(31 downto 0);
hpc_lo_i : std_logic_vector(31 downto 0);
hpc_hi_i : std_logic_vector(31 downto 0);
end record;
constant c_swc_in_registers_init_value: t_swc_in_registers := (
......@@ -34,7 +36,9 @@ package swc_wbgen2_pkg is
stat_min_fpg_i => (others => '0'),
stat_max_fpg_i => (others => '0'),
cur_fpg_i => (others => '0'),
afull_thr_i => (others => '0')
afull_thr_i => (others => '0'),
hpc_lo_i => (others => '0'),
hpc_hi_i => (others => '0')
);
-- Output registers (WB slave -> user design)
......@@ -87,6 +91,8 @@ tmp.stat_min_fpg_i := f_x_to_zero(left.stat_min_fpg_i) or f_x_to_zero(right.stat
tmp.stat_max_fpg_i := f_x_to_zero(left.stat_max_fpg_i) or f_x_to_zero(right.stat_max_fpg_i);
tmp.cur_fpg_i := f_x_to_zero(left.cur_fpg_i) or f_x_to_zero(right.cur_fpg_i);
tmp.afull_thr_i := f_x_to_zero(left.afull_thr_i) or f_x_to_zero(right.afull_thr_i);
tmp.hpc_lo_i := f_x_to_zero(left.hpc_lo_i) or f_x_to_zero(right.hpc_lo_i);
tmp.hpc_hi_i := f_x_to_zero(left.hpc_hi_i) or f_x_to_zero(right.hpc_hi_i);
return tmp;
end function;
end package body;
modules/wrsw_swcore/swc_wishbone_slave.vhd
View file @ c9ea0477
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : swc_wishbone_slave.vhd
-- Author : auto-generated by wbgen2 from wrsw_swcore.wb
-- Created : Tue Sep 13 14:08:37 2016
-- Created : Fri Sep 23 11:31:56 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_swcore.wb
......@@ -163,6 +163,18 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.hpc_lo_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.hpc_hi_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -198,6 +210,8 @@ begin
regs_o.afull_thr_o <= wrdata_reg(31 downto 0);
-- Port mask
regs_o.hp_ob_drop_mask_o <= swc_hp_ob_drop_mask_int;
-- cnt low
-- cnt high
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wrsw_swcore/wrsw_swcore.wb
View file @ c9ea0477
......@@ -120,4 +120,30 @@ peripheral {
};
};
reg {
name = "OB count register";
description = "Enables dropping regular traffic at the output of swcore ports when HP traffic is queued.";
prefix = "HPC_LO";
field {
name = "cnt low";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "OB count register";
description = "Enables dropping regular traffic at the output of swcore ports when HP traffic is queued.";
prefix = "HPC_HI";
field {
name = "cnt high";
size = 32;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
modules/wrsw_swcore/xswc_core.vhd
View file @ c9ea0477
......@@ -378,6 +378,10 @@ architecture rtl of xswc_core is
signal mmu_pmin, mmu_pmin_prev : unsigned(c_mpm_page_addr_width downto 0);
signal mmu_pmax, mmu_pmax_prev : unsigned(c_mpm_page_addr_width downto 0);
signal mmu_was_full, mmu_was_afull : std_logic;
-- dbg
type t_hpcount_array is array(0 to g_num_ports-1) of unsigned(63 downto 0);
signal hp_count : t_hpcount_array;
begin --rtl
......@@ -639,7 +643,8 @@ architecture rtl of xswc_core is
g_wb_addr_width => g_wb_addr_width,
g_wb_sel_width => g_wb_sel_width,
g_wb_ob_ignore_ack => g_wb_ob_ignore_ack,
g_drop_outqueue_head_on_full => g_drop_outqueue_head_on_full
g_drop_outqueue_head_on_full => g_drop_outqueue_head_on_full,
g_port_number => i
)
port map (
clk_i => clk_i,
......@@ -690,6 +695,7 @@ architecture rtl of xswc_core is
wdog_o => wdog_ob(i),
tap_out_o => tap_ob(i),
hp_count_o => hp_count(i),
nice_dbg_o => nice_dbg_o.ob(i)
);
......@@ -931,4 +937,9 @@ architecture rtl of xswc_core is
wdog_o(I)(c_FREE_FSM_IDX) <= wdog_free(I)(c_FREE_FSM_IDX);
end generate;
-- dbg
regs_towb.hpc_lo_i <= std_logic_vector(hp_count(1)(31 downto 0));
regs_towb.hpc_hi_i <= std_logic_vector(hp_count(1)(63 downto 32));
end rtl;
modules/wrsw_swcore/xswc_input_block.vhd
View file @ c9ea0477
......@@ -2764,26 +2764,26 @@ dbg_pckinter_pageaddr_o <= pckinter_pageaddr;
nice_dbg_o.finish_rcv <= finish_rcv_pck;
nice_dbg_o.force_free <= mmu_force_free_req;
nice_dbg_o.force_free_done <= mmu_force_free_done_i;
nice_dbg_o.force_free_adr <= mmu_force_free_addr;
nice_dbg_o.force_free_adr(g_page_addr_width-1 downto 0) <= mmu_force_free_addr;
nice_dbg_o.pckstart_in_adv <= pckstart_page_in_advance;
nice_dbg_o.pckinter_in_adv <= pckinter_page_in_advance;
nice_dbg_o.ll_wr <= ll_wr_req;
nice_dbg_o.ll_wr_done <= ll_wr_done_i;
nice_dbg_o.ll_page <= ll_entry.addr;
nice_dbg_o.ll_next_page <= ll_entry.next_page;
nice_dbg_o.ll_page(g_page_addr_width-1 downto 0) <= ll_entry.addr;
nice_dbg_o.ll_next_page(g_page_addr_width-1 downto 0) <= ll_entry.next_page;
nice_dbg_o.ll_page_valid <= ll_entry.valid;
nice_dbg_o.ll_eof <= ll_entry.eof;
nice_dbg_o.ll_size <= ll_entry.size;
nice_dbg_o.alloc_req <= pckinter_page_alloc_req or
pckstart_page_alloc_req;
nice_dbg_o.alloc_done <= mmu_page_alloc_done_i;
nice_dbg_o.alloc_page <= mmu_pageaddr_i;
nice_dbg_o.page_start <= pckstart_pageaddr;
nice_dbg_o.page_inter <= pckinter_pageaddr;
nice_dbg_o.cur_pckstart <= current_pckstart_pageaddr;
nice_dbg_o.alloc_page(g_page_addr_width-1 downto 0) <= mmu_pageaddr_i;
nice_dbg_o.page_start(g_page_addr_width-1 downto 0) <= pckstart_pageaddr;
nice_dbg_o.page_inter(g_page_addr_width-1 downto 0) <= pckinter_pageaddr;
nice_dbg_o.cur_pckstart(g_page_addr_width-1 downto 0) <= current_pckstart_pageaddr;
nice_dbg_o.pta_pgadr <= pta_pageaddr;
nice_dbg_o.pta_pgadr(g_page_addr_width-1 downto 0) <= pta_pageaddr;
nice_dbg_o.pta_transfer <= pta_transfer_pck;
nice_dbg_o.pta_mask <= pta_mask(7 downto 0);
nice_dbg_o.pta_transfer_ack <= pta_transfer_ack_i;
......@@ -2796,7 +2796,7 @@ dbg_pckinter_pageaddr_o <= pckinter_pageaddr;
nice_dbg_o.stall <= snk_stall_int;
nice_dbg_o.mpm_dlast_d0 <= mpm_dlast_reg;
nice_dbg_o.mpm_pg_req_d0 <= mpm_pg_req_d0;
nice_dbg_o.mpm_pg_adr <= mpm_pg_addr;
nice_dbg_o.mpm_pg_adr(g_page_addr_width-1 downto 0) <= mpm_pg_addr;
nice_dbg_o.ll_pckstart_stored <= ll_stored_eof;
nice_dbg_o.ffree_mask <= ffree_mask;
nice_dbg_o.new_pck_first_page <= new_pck_first_page;
......
modules/wrsw_swcore/xswc_output_block_new.vhd
View file @ c9ea0477
......@@ -80,7 +80,8 @@ entity xswc_output_block_new is
g_wb_addr_width : integer;
g_wb_sel_width : integer;
g_wb_ob_ignore_ack : boolean := true;
g_drop_outqueue_head_on_full : boolean := true
g_drop_outqueue_head_on_full : boolean := true;
g_port_number : integer
);
port (
clk_i : in std_logic;
......@@ -137,6 +138,7 @@ entity xswc_output_block_new is
-------------------------------------------------------------------------------
wdog_o : out t_swc_fsms;
tap_out_o : out std_logic_vector(15 downto 0);
hp_count_o : out unsigned(63 downto 0);
nice_dbg_o : out t_dbg_swc_ob
);
......@@ -329,6 +331,21 @@ architecture behavoural of xswc_output_block_new is
-- if FALSE, when a retry requsts comes from EP, it will be handled only if output queues are free
constant c_always_drop_at_retry : boolean := true;
-- dbg
signal dbg_byte_cnt : unsigned(10 downto 0);
type t_smac_array is array(0 to 5) of std_logic_vector(7 downto 0);
signal smac : t_smac_array;
signal smac_vec : std_logic_vector(47 downto 0);
signal we_drop_hp : std_logic;
signal hp_count : unsigned(63 downto 0);
signal hp_fifo_wr, hp_fifo_rd, hp_fifo_full, hp_fifo_empty : std_logic;
signal hp_fifo_q : std_logic_vector(g_mpm_page_addr_width-1 downto 0);
signal hp_fifo_error : std_logic;
type t_dbg_fsm is (WAIT_FIFO, READ_FIFO, WAIT_CYC_0, WAIT_CYC_1, ABORT_OR_OK);
signal dbg_state : t_dbg_fsm;
begin -- behavoural
wrf_status_err.is_hp <= '0';
......@@ -579,6 +596,7 @@ begin -- behavoural
new_tx_prio <= (others => '0');
else
if(rd_valid = '1') then
--new_tx_prio <= read_array;
new_tx_prio <= rd_array;
elsif((s_send_pck = S_EOF) and (s_prep_to_send = S_IDLE)) then
new_tx_prio <= (others => '0');
......@@ -1071,18 +1089,166 @@ begin -- behavoural
nice_dbg_o.prep_fsm <= prep_FSM;
nice_dbg_o.free <= ppfm_free;
nice_dbg_o.free_done <= ppfm_free_done_i;
nice_dbg_o.free_adr <= ppfm_free_pgaddr;
nice_dbg_o.free_adr(g_mpm_page_addr_width-1 downto 0) <= ppfm_free_pgaddr;
nice_dbg_o.cycle_frozen <= cycle_frozen;
nice_dbg_o.mpm_pgreq <= mpm_pg_req_i;
nice_dbg_o.pta_transfer_valid <= pta_transfer_data_valid_i;
nice_dbg_o.pta_pgadr <= pta_pageaddr_i;
nice_dbg_o.pta_pgadr(g_mpm_page_addr_width-1 downto 0) <= pta_pageaddr_i;
nice_dbg_o.pta_ack <= pta_transfer_data_ack;
nice_dbg_o.obq_full <= not (or_reduce(not_full_array));
nice_dbg_o.data_error <= out_dat_err;
nice_dbg_o.mpm_dlast <= mpm_dlast_i;
nice_dbg_o.mpm_pgadr <= mpm_pg_addr;
nice_dbg_o.mpm_pgadr(g_mpm_page_addr_width-1 downto 0) <= mpm_pg_addr;
nice_dbg_o.mpm_adr_int <= mpm2wb_adr_int;
nice_dbg_o.mpm_dat_int <= mpm2wb_dat_int;
nice_dbg_o.mpm_dvalid <= mpm_dvalid_i;
nice_dbg_o.cyc <= src_out_int.cyc;
nice_dbg_o.stb <= src_out_int.stb;
--nice_dbg_o.adr <= src_out_int.adr;
nice_dbg_o.dat <= src_out_int.dat;
nice_dbg_o.ack <= src_i.ack;
nice_dbg_o.stall <= src_i.stall;
nice_dbg_o.pta_hp <= pta_hp_i;
nice_dbg_o.abord_tx_at_hp <= abord_tx_at_hp;
nice_dbg_o.hp_in_queuing <= hp_in_queuing;
nice_dbg_o.non_hp_txing <= non_hp_txing;
nice_dbg_o.rd_valid <= rd_valid;
nice_dbg_o.not_empty_array <= not_empty_array;
nice_dbg_o.current_tx_prio <= current_tx_prio;
nice_dbg_o.new_tx_prio <= new_tx_prio;
nice_dbg_o.read_array <= read_array;
nice_dbg_o.rd_array <= rd_array;
nice_dbg_o.mpm_pg_valid <= mpm_pg_valid;
nice_dbg_o.mpm_abort <= mpm_abort;
nice_dbg_o.allow_next_newpck_set <= allow_next_newpck_set;
nice_dbg_o.pta_pgadr <= pta_pageaddr_i;
nice_dbg_o.mpm_pgadr <= mpm_pg_addr;
nice_dbg_o.we_drop_hp <= we_drop_hp;
smac_vec <= smac(0) & smac(1) & smac(2) & smac(3) & smac(4) & smac(5);
process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i='0' or src_out_int.cyc='0') then
dbg_byte_cnt <= (others=>'0');
we_drop_hp <= '0';
elsif (src_out_int.cyc='1' and src_out_int.stb='1') then
dbg_byte_cnt <= dbg_byte_cnt + 1;
if(dbg_byte_cnt=4) then
smac(0) <= src_out_int.dat(15 downto 8);
smac(1) <= src_out_int.dat(7 downto 0);
elsif(dbg_byte_cnt=5) then
smac(2) <= src_out_int.dat(15 downto 8);
smac(3) <= src_out_int.dat(7 downto 0);
elsif(dbg_byte_cnt=6) then
smac(4) <= src_out_int.dat(15 downto 8);
smac(5) <= src_out_int.dat(7 downto 0);
end if;
if(dbg_byte_cnt>6 and (smac_vec=x"3c470e040506" or smac_vec=x"3c470e141516") and abord_tx_at_hp='1') then
we_drop_hp <= '1';
end if;
end if;
end if;
end process;
GEN_DBG_HP_PAGES: if g_port_number=1 generate
nice_dbg_o.dbg_state <= "000" when(dbg_state = WAIT_FIFO) else
"001" when(dbg_state = READ_FIFO) else
"010" when(dbg_state = WAIT_CYC_0) else
"011" when(dbg_state = WAIT_CYC_1) else
"100" when(dbg_state = ABORT_OR_OK) else
"111";
nice_dbg_o.hp_fifo_full <= hp_fifo_full;
nice_dbg_o.hp_fifo_empty <= hp_fifo_empty;
nice_dbg_o.hp_fifo_error <= hp_fifo_error;
nice_dbg_o.hp_fifo_q <= hp_fifo_q;
nice_dbg_o.hp_fifo_wr <= hp_fifo_wr;
nice_dbg_o.hp_fifo_rd <= hp_fifo_rd;
--GEN_DBG_HP_PAGES: if g_port_number=2 generate
HP_FIFO: generic_sync_fifo
generic map (
g_data_width => g_mpm_page_addr_width,
g_size => 10,
g_show_ahead => false,
g_with_empty => true,
g_with_full => true)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => pta_pageaddr_i,
we_i => hp_fifo_wr,
q_o => hp_fifo_q,
rd_i => hp_fifo_rd,
empty_o => hp_fifo_empty,
full_o => hp_fifo_full);
end generate;
hp_fifo_wr <= pta_transfer_data_valid_i and pta_hp_i;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
dbg_state <= WAIT_FIFO;
hp_fifo_rd <= '0';
hp_fifo_error <= '0';
else
case dbg_state is
when WAIT_FIFO =>
hp_fifo_error <= '0';
if (hp_fifo_empty = '0' or hp_fifo_wr = '1') then
hp_fifo_rd <= '1';
dbg_state <= READ_FIFO;
end if;
when READ_FIFO =>
hp_fifo_rd <= '0';
if(mpm_pg_addr=hp_fifo_q and src_out_int.cyc='0') then
dbg_state <= WAIT_CYC_1;
elsif(mpm_pg_addr=hp_fifo_q and src_out_int.cyc='1') then
dbg_state <= WAIT_CYC_0;
end if;
when WAIT_CYC_0 =>
if(src_out_int.cyc='0') then
dbg_state <= WAIT_CYC_1;
end if;
when WAIT_CYC_1 =>
if(src_out_int.cyc='1') then
dbg_state <= ABORT_OR_OK;
end if;
when ABORT_OR_OK =>
if(abord_tx_at_hp='1') then
hp_fifo_error <= '1';
dbg_state <= WAIT_FIFO;
elsif(src_out_int.cyc='0') then
hp_fifo_error <= '0';
dbg_state <= WAIT_FIFO;
end if;
end case;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
hp_count <= (others=>'0');
elsif(hp_fifo_wr = '1') then
hp_count <= hp_count + 1;
end if;
end if;
end process;
hp_count_o <= hp_count;
end behavoural;
top/bare_top/scb_top_bare.vhd
View file @ c9ea0477
......@@ -1320,6 +1320,44 @@ begin
end process;
end generate;
--------------------------------------------------------
-- OB drop frames on HP debugging
--------------------------------------------------------
--TRIG0(0)(0) <= swc_dbg.ob(1).cyc;
--TRIG0(0)(1) <= swc_dbg.ob(1).stb;
--TRIG0(0)(2) <= swc_dbg.ob(1).ack;
--TRIG0(0)(3) <= swc_dbg.ob(1).stall;
--TRIG0(0)(19 downto 4) <= swc_dbg.ob(1).dat;
--TRIG0(0)(20) <= swc_dbg.ob(1).pta_transfer_valid;
--TRIG0(0)(21) <= swc_dbg.ob(1).pta_hp;
--TRIG0(0)(22) <= swc_dbg.ob(1).abord_tx_at_hp;
--TRIG0(0)(23) <= swc_dbg.ob(1).hp_in_queuing;
--TRIG0(0)(24) <= swc_dbg.ob(1).non_hp_txing;
--TRIG0(0)(25) <= swc_dbg.ob(1).rd_valid;
--TRIG0(0)(26) <= swc_dbg.ob(1).mpm_pg_valid;
--TRIG0(0)(27) <= swc_dbg.ob(1).mpm_abort;
--TRIG0(0)(28) <= swc_dbg.ob(1).mpm_dvalid;
--TRIG0(0)(29) <= swc_dbg.ob(1).allow_next_newpck_set;
--TRIG0(0)(30) <= swc_dbg.ob(1).mpm_pgreq;
--TRIG0(0)(31) <= swc_dbg.ob(1).we_drop_hp;
--TRIG1(0)( 7 downto 0) <= swc_dbg.ob(1).not_empty_array;
--TRIG1(0)(15 downto 8) <= swc_dbg.ob(1).current_tx_prio;
--TRIG1(0)(23 downto 16) <= swc_dbg.ob(1).new_tx_prio;
--TRIG1(0)(31 downto 24) <= swc_dbg.ob(1).read_array;
--TRIG2(0)( 7 downto 0) <= swc_dbg.ob(1).rd_array;
--TRIG2(0)(17 downto 8) <= swc_dbg.ob(1).pta_pgadr;
--TRIG2(0)(27 downto 18) <= swc_dbg.ob(1).mpm_pgadr;
--TRIG3(0)(2 downto 0) <= swc_dbg.ob(1).dbg_state;
--TRIG3(0)(3) <= swc_dbg.ob(1).hp_fifo_full;
--TRIG3(0)(4) <= swc_dbg.ob(1).hp_fifo_empty;
--TRIG3(0)(5) <= swc_dbg.ob(1).hp_fifo_error;
--TRIG3(0)(6) <= swc_dbg.ob(1).hp_fifo_wr;
--TRIG3(0)(7) <= swc_dbg.ob(1).hp_fifo_rd;
--TRIG3(0)(17 downto 8) <= swc_dbg.ob(1).hp_fifo_q;
-------------------------------------------------------------------
-------------------------------------------------------------------
......
top/bare_top/wrs_dbg_pkg.vhd
View file @ c9ea0477
......@@ -87,17 +87,46 @@ package wrs_dbg_pkg is
free_done : std_logic;
free_adr : std_logic_vector(9 downto 0);
cycle_frozen : std_logic;
mpm_pgreq : std_logic;
pta_transfer_valid : std_logic;
pta_pgadr : std_logic_vector(9 downto 0);
pta_ack : std_logic;
obq_full : std_logic;
data_error : std_logic;
mpm_dlast : std_logic;
mpm_pgadr : std_logic_vector(9 downto 0);
mpm_adr_int : std_logic_vector(1 downto 0);
mpm_dat_int : std_logic_vector(15 downto 0);
mpm_dvalid : std_logic;
cyc : std_logic;
stb : std_logic;
--adr : std_logic_vector(1 downto 0);
dat : std_logic_vector(15 downto 0);
ack : std_logic;
stall : std_logic;
pta_transfer_valid : std_logic;
pta_hp : std_logic;
abord_tx_at_hp : std_logic;
hp_in_queuing : std_logic;
non_hp_txing : std_logic;
rd_valid : std_logic;
not_empty_array: std_logic_vector(7 downto 0);
current_tx_prio: std_logic_vector(7 downto 0);
new_tx_prio : std_logic_vector(7 downto 0);
read_array : std_logic_vector(7 downto 0);
rd_array : std_logic_vector(7 downto 0);
mpm_pg_valid : std_logic;
mpm_abort : std_logic;
mpm_dvalid : std_logic;
allow_next_newpck_set : std_logic;
pta_pgadr : std_logic_vector(9 downto 0);
mpm_pgadr : std_logic_vector(9 downto 0);
mpm_pgreq : std_logic;
we_drop_hp : std_logic;
dbg_state : std_logic_vector(2 downto 0);
hp_fifo_full : std_logic;
hp_fifo_empty : std_logic;
hp_fifo_error : std_logic;
hp_fifo_q : std_logic_vector(9 downto 0);
hp_fifo_wr : std_logic;
hp_fifo_rd : std_logic;
end record;
type t_dbg_swc_ob_array is array (natural range <>) of t_dbg_swc_ob;
......@@ -162,12 +191,32 @@ package wrs_dbg_pkg is
rd_valid : std_logic;
req_o : std_logic;
rd_adr : std_logic_vector(9 downto 0);
rd_data : std_logic_vector(15 downto 0);
rd_data_valid : std_logic;
rd_data_ready : std_logic;
wr_adr0 : std_logic_vector(9 downto 0);
wr_dat0 : std_logic_vector(15 downto 0);
wr_ready0 : std_logic;
wr_adr1 : std_logic_vector(9 downto 0);
wr_dat1 : std_logic_vector(15 downto 0);
wr_ready1 : std_logic;
read_data_o : std_logic_vector(14 downto 0);
end record;
type t_dbg_swc_mll_rv_array is array (natural range<>) of t_dbg_swc_mll_rv;
type t_dbg_swc_mll is record
rv : t_dbg_swc_mll_rv_array(18 downto 0);
fpck_grant_d1 : std_logic_vector(18 downto 0);
write_in : std_logic_vector(18 downto 0);
write_done : std_logic_vector(18 downto 0);
write_next_valid : std_logic_vector(18 downto 0);
mpram_write : std_logic_vector(2 downto 0);
xmpram_wadr_d0_0 : std_logic_vector(9 downto 0);
xmpram_wadr_d0_1 : std_logic_vector(9 downto 0);
xmpram_wdat_d0_0 : std_logic_vector(14 downto 0);
xmpram_wdat_d0_1 : std_logic_vector(14 downto 0);
write_idx0 : std_logic_vector(4 downto 0);
write_idx1 : std_logic_vector(4 downto 0);
end record;
-- MPM types
......@@ -206,6 +255,8 @@ package wrs_dbg_pkg is
supress_pre_fetch: std_logic;
fetch_pg_words_new : std_logic;
fetch_pg_words_used : std_logic;
wait_first_fetched : std_logic;
wait_next_valid_ll_read : std_logic;
end record;
type t_dbg_mpm_read_io_array is array (natural range<>) of t_dbg_mpm_read_io;
......
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