Commit c2eb4734 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

10mhz_out: pushing forgotten simulations

parent d315bf7b
`timescale 1ns/1ps
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
import wishbone_pkg::*;
`define WIRE_WRF_SRC(dst, src) \
assign dst``_o.cyc = src.cyc; \
assign dst``_o.stb = src.stb; \
assign dst``_o.adr = src.adr; \
assign dst``_o.dat = src.dat_o; \
assign dst``_o.sel = src.sel; \
assign dst``_o.we = src.we; \
assign src.ack = dst``_i.ack; \
assign src.dat_i = dst``_i.dat; \
assign src.err = dst``_i.err; \
assign src.stall = dst``_i.stall;
module main;
reg clk_ref = 1'b0;
reg rst_n = 1'b0;
reg pps = 1'b0;
reg pps_valid = 1'b0;
IWishboneMaster #(32,32) sv_wbm (clk_ref, rst_n);
t_wishbone_master_out wbm_o;
t_wishbone_master_in wbm_i;
`WIRE_WRF_SRC(wbm, sv_wbm);
always #8ns clk_ref <= ~clk_ref;
initial begin
repeat(3) @(posedge clk_ref);
rst_n <= 1'b1;
//#90us
//rst_n <= 1'b0;
//repeat(3) @(posedge clk_ref);
//rst_n <= 1'b1;
end
initial begin
pps_valid <= 1'b0;
#20us
pps_valid <= 1'b1;
end
always begin
#39us;
#984ns;
pps <= 1'b1;
#16ns;
pps <= 1'b0;
end
xwrsw_gen_10mhz DUT
(
.rst_n_i(rst_n),
.clk_i(clk_ref),
.pps_i(pps),
.pps_valid_i(pps_valid),
.slave_i(wbm_o),
.slave_o(wbm_i)
);
initial begin
CWishboneAccessor acc;
acc = sv_wbm.get_accessor();
acc.set_mode(PIPELINED);
#50us;
acc.write('h0, 20);
#10us;
acc.write('h4, 30);
#10us;
acc.write('h8, 5);
#30us;
acc.write('hc, 'h0a);
#100us;
acc.write('hc, 'h1f);
end
endmodule
vcom -mixedsvvh l ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
vcom -mixedsvvh l ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
vcom -mixedsvvh l ../../modules/wrsw_rt_subsystem/xwrsw_gen_10mhz.vhd
vlog -sv main.sv +incdir+"." +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim
make -f Makefile
vsim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 300us
wave zoomfull
radix -hexadecimal
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/pps_i
add wave -noupdate /main/DUT/pps_valid_i
add wave -noupdate /main/DUT/pps_valid_d
add wave -noupdate /main/DUT/clk_realign
add wave -noupdate /main/DUT/serdes_rst
add wave -noupdate /main/DUT/clk_i
add wave -noupdate /main/DUT/clk_aux_p_o
add wave -noupdate /main/DUT/clk_aux_n_o
add wave -noupdate /main/DUT/clk_500
add wave -noupdate /main/DUT/U_PLL_500/LOCKED
add wave -noupdate /main/DUT/clk_fb
add wave -noupdate -radix binary /main/DUT/sd_data
add wave -noupdate /main/DUT/rst
add wave -noupdate /main/DUT/sd_out_p(0)
add wave -noupdate /main/DUT/sd_out_n(0)
add wave -noupdate -radix unsigned /main/DUT/aux_half_high
add wave -noupdate -radix unsigned /main/DUT/aux_half_low
add wave -noupdate /main/DUT/aux_shift
add wave -noupdate /main/DUT/new_freq
add wave -noupdate /main/DUT/U_10MHZ_SERDES/DELAY_RESET
add wave -noupdate /main/DUT/U_10MHZ_SERDES/DELAY_TAP_IN
add wave -noupdate /main/DUT/U_10MHZ_SERDES/DELAY_TAP_OUT
add wave -noupdate -divider {New Divider}
add wave -noupdate -expand /main/DUT/slave_i
add wave -noupdate -expand /main/DUT/slave_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {40007836140 fs} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {315 us}
`timescale 1ns/1ps
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
import wishbone_pkg::*;
`define WIRE_WRF_SRC(dst, src) \
assign dst``_o.cyc = src.cyc; \
assign dst``_o.stb = src.stb; \
assign dst``_o.adr = src.adr; \
assign dst``_o.dat = src.dat_o; \
assign dst``_o.sel = src.sel; \
assign dst``_o.we = src.we; \
assign src.ack = dst``_i.ack; \
assign src.dat_i = dst``_i.dat; \
assign src.err = dst``_i.err; \
assign src.stall = dst``_i.stall;
module main;
reg clk_ref = 1'b0;
reg rst_n = 1'b0;
reg rst_naux= 1'b1;
reg pps = 1'b0;
reg pps_valid = 1'b0;
IWishboneMaster #(32,32) sv_wbm (clk_ref, rst_n);
t_wishbone_master_out wbm_o;
t_wishbone_master_in wbm_i;
`WIRE_WRF_SRC(wbm, sv_wbm);
always #8ns clk_ref <= ~clk_ref;
initial begin
repeat(3) @(posedge clk_ref);
rst_n <= 1'b1;
//#90us
//rst_n <= 1'b0;
//repeat(3) @(posedge clk_ref);
//rst_n <= 1'b1;
end
//always begin
// #90us
// rst_naux <= 1'b0;
// repeat(3) @(posedge clk_ref);
// rst_naux <= 1'b1;
//end
initial begin
pps_valid <= 1'b0;
#20us
pps_valid <= 1'b1;
end
always begin
#39us;
#984ns;
pps <= 1'b1;
#16ns;
pps <= 1'b0;
end
wrsw_rt_subsystem
#(
.g_num_rx_clocks(1),
.g_simulation(1)) DUT
(
.clk_ref_i(clk_ref),
.clk_sys_i(clk_ref),
.clk_dmtd_i(clk_ref),
.clk_rx_i(1'b0),
.clk_ext_i(1'b0),
.clk_ext_mul_i(1'b0),
.rst_n_i(rst_n),
.wb_i(wbm_o),
.wb_o(wbm_i),
.uart_rxd_i(1'b0),
.pps_ext_i(1'b0),
.pll_status_i(1'b0),
.pll_miso_i(1'b0)
);
initial begin
CWishboneAccessor acc;
uint64_t dat;
acc = sv_wbm.get_accessor();
acc.set_mode(PIPELINED);
#1us;
//no more reset for ppsgen
acc.write('h10304*4, 'h8);
acc.write('h10500*4, 'h2);
acc.write('h1051c*4, 'h2);
#100us;
acc.write('h10520*4, 'h04);
acc.read('h10520*4, dat);
end
endmodule
#vcom -mixedsvvh l ../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
#vcom -mixedsvvh l ../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
#vcom -mixedsvvh l ../../modules/wrsw_rt_subsystem/gen_10mhz.vhd
vlog -sv main.sv +incdir+"." +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim
make -f Makefile
vsim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 300us
wave zoomfull
radix -hexadecimal
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate -expand /main/DUT/wb_i
add wave -noupdate /main/DUT/wb_o
add wave -noupdate -expand -group PPSG /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/rst_n_i
add wave -noupdate -expand -group PPSG -expand /main/DUT/U_PPS_Gen/slave_i
add wave -noupdate -expand -group PPSG -expand /main/DUT/U_PPS_Gen/slave_o
add wave -noupdate /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/ppsdel_tap
add wave -noupdate /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/ppsdel_tap_cur
add wave -noupdate /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/ppsdel_load
add wave -noupdate -radix unsigned /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/cntr_nsec
add wave -noupdate -radix unsigned /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/cntr_utc
add wave -noupdate -expand -group out /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/pps_out_predelay
add wave -noupdate -expand -group out /main/DUT/U_PPS_Gen/WRAPPED_PPSGEN/pps_out_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {0 fs} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {319108695650 fs}
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