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White Rabbit Switch - Gateware
Commit b1dcf5f8 authored by Maciej Lipinski's avatar Maciej Lipinski
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chipscope v6

parent da5737af
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Showing with 101 additions and 33 deletions
top/bare_top/scb_top_bare.vhd
View file @ b1dcf5f8
......@@ -355,7 +355,7 @@ architecture rtl of scb_top_bare is
type t_trig is array(integer range <>) of std_logic_vector(31 downto 0);
signal control0 : std_logic_vector(35 downto 0);
signal trig0, trig1, trig2, trig3 : t_trig(7 downto 0);--std_logic_vector(31 downto 0);
signal trig0, trig1, trig2, trig3 : std_logic_vector(31 downto 0);
signal t0, t1, t2, t3 : std_logic_vector(31 downto 0);
signal rst_n_periph : std_logic;
signal link_kill : std_logic_vector(c_NUM_PORTS-1 downto 0);
......@@ -471,22 +471,88 @@ architecture rtl of scb_top_bare is
signal dac_main_sclk : std_logic;
signal dac_main_data : std_logic;
type t_dbg_ep_array is array(integer range <>) of t_dbg_ep;
signal dbg_ep : t_dbg_ep_array(g_num_ports-1 downto 0);
begin
--CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
--CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys,
-- TRIG0 => TRIG0,
-- TRIG1 => TRIG1,
-- TRIG2 => TRIG2,
-- TRIG3 => TRIG3);
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => phys_i(2).rx_clk, --clk_sys,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
TRIG0( 15 downto 0) <= endpoint_src_out(2).dat;
TRIG0( 17 downto 16) <= endpoint_src_out(2).adr;
TRIG0( 18) <= endpoint_src_out(2).cyc;
TRIG0( 19) <= endpoint_src_out(2).stb;
TRIG0( 20) <= endpoint_src_out(2).we;
TRIG0( 21) <= std_logic(endpoint_src_out(2).sel(0) xor endpoint_src_out(2).sel(1));
TRIG0( 22) <= endpoint_src_in(2).ack;
TRIG0( 23) <= endpoint_src_in(2).stall;
TRIG0( 24) <= endpoint_src_in(2).err;
TRIG0( 25) <= endpoint_src_in(2).rty;
TRIG0( 26) <= phys_i(2).tx_disparity;
TRIG0( 27) <= phys_i(2).rx_enc_err;
TRIG0( 29 downto 28) <= phys_i(2).rx_k;
TRIG0( 31 downto 30) <= phys_i(2).rx_data(15 downto 14);
TRIG1( 2 downto 0) <= dbg_ep(2).pcs.rx.fsm;
TRIG1( 3) <= dbg_ep(2).rxpath.fab_pipe(0).dvalid;
TRIG1( 4) <= dbg_ep(2).rxpath.fab_pipe(0).sof;
TRIG1( 5) <= dbg_ep(2).rxpath.fab_pipe(0).eof;
TRIG1( 6) <= dbg_ep(2).rxpath.fab_pipe(0).error;
TRIG1( 8 downto 7) <= dbg_ep(2).rxpath.fab_pipe(0).addr;
TRIG1( 9) <= dbg_ep(2).rxpath.fab_pipe(1).dvalid;
TRIG1( 10) <= dbg_ep(2).rxpath.fab_pipe(1).sof;
TRIG1( 11) <= dbg_ep(2).rxpath.fab_pipe(1).eof;
TRIG1( 12) <= dbg_ep(2).rxpath.fab_pipe(1).error;
TRIG1( 14 downto 13) <= dbg_ep(2).rxpath.fab_pipe(1).addr;
TRIG1( 15) <= dbg_ep(2).rxpath.fab_pipe(0).data(1); -- error in status
TRIG1( 16) <= dbg_ep(2).rxpath.fab_pipe(1).data(1); -- error in status
TRIG1( 20) <= dbg_ep(2).rxpath.dreq_pipe(0);
TRIG1( 21) <= dbg_ep(2).rxpath.dreq_pipe(1);
TRIG1( 22) <= dbg_ep(2).rxpath.pcs_fifo_afull;
TRIG1( 23) <= dbg_ep(2).rxpath.pcs_fifo_empty;
TRIG1( 24) <= dbg_ep(2).rxpath.pcs_fifo_full;
TRIG1( 25) <= dbg_ep(2).rxpath.rxbuf_full;
TRIG1( 31 downto 26) <= phys_i(2).rx_data(5 downto 0);
TRIG2( 3 downto 0) <= swc_wdog_out(2)(c_ALLOC_FSM_IDX);
TRIG2( 7 downto 4) <= swc_wdog_out(2)(c_TRANS_FSM_IDX);
TRIG2( 11 downto 8) <= swc_wdog_out(2)(c_RCV_FSM_IDX);
TRIG2( 15 downto 12) <= swc_wdog_out(2)(c_LL_FSM_IDX);
TRIG2( 19 downto 16) <= swc_wdog_out(2)(c_PREP_FSM_IDX);
TRIG2( 20) <= dbg_ep(2).rxpath.fab_pipe(9).dvalid;
TRIG2( 21) <= dbg_ep(2).rxpath.fab_pipe(9).sof;
TRIG2( 22) <= dbg_ep(2).rxpath.fab_pipe(9).eof;
TRIG2( 23) <= dbg_ep(2).rxpath.fab_pipe(9).error;
TRIG2( 25 downto 24) <= dbg_ep(2).rxpath.fab_pipe(9).addr;
TRIG2( 26) <= dbg_ep(2).rxpath.fab_pipe(9).data(1);
TRIG2( 27) <= phys_i(2).rdy;
TRIG2( 31 downto 28) <= phys_i(2).rx_data(9 downto 6);
TRIG3( 3 downto 0) <= swc_wdog_out(3)(c_ALLOC_FSM_IDX);
TRIG3( 7 downto 4) <= swc_wdog_out(3)(c_TRANS_FSM_IDX);
TRIG3( 11 downto 8) <= swc_wdog_out(3)(c_RCV_FSM_IDX);
TRIG3( 15 downto 12) <= swc_wdog_out(3)(c_LL_FSM_IDX);
TRIG3( 19 downto 16) <= swc_wdog_out(3)(c_PREP_FSM_IDX);
TRIG3( 23 downto 20) <= swc_wdog_out(3)(c_SEND_FSM_IDX);
TRIG3( 27 downto 24) <= swc_wdog_out(3)(c_FREE_FSM_IDX);
TRIG3( 31 downto 28) <= phys_i(2).rx_data(13 downto 10);
cnx_slave_in(0) <= cpu_wb_i;
......@@ -869,7 +935,9 @@ begin
----------------------------
link_up_o => ep_links_up(i),
rmon_events_o => ep_events((i+1)*c_epevents_sz-1 downto i*c_epevents_sz),
--- debug:
nice_dbg_o => dbg_ep(i),
----------
led_link_o => led_link_o(i),
led_act_o => led_act_o(i),
stop_traffic_i => ep_stop_traffic
......@@ -1309,25 +1377,25 @@ begin
wrfreg_src_in <= swc_snk_out;
swc_snk_in <= wrfreg_src_out;
end generate;
gen_muxed_CS: if g_with_muxed_CS = true generate
CS_ICON : chipscope_icon
port map (
CONTROL0 => CONTROL0);
CS_ILA : chipscope_ila
port map (
CONTROL => CONTROL0,
CLK => clk_sys, --phys_i(0).rx_clk,
TRIG0 => T0,
TRIG1 => T1,
TRIG2 => T2,
TRIG3 => T3);
T0 <= TRIG0(to_integer(unsigned(dbg_chps_id)));
T1 <= TRIG1(to_integer(unsigned(dbg_chps_id)));
T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
end generate;
--
-- gen_muxed_CS: if g_with_muxed_CS = true generate
-- CS_ICON : chipscope_icon
-- port map (
-- CONTROL0 => CONTROL0);
-- CS_ILA : chipscope_ila
-- port map (
-- CONTROL => CONTROL0,
-- CLK => clk_sys, --phys_i(0).rx_clk,
-- TRIG0 => T0,
-- TRIG1 => T1,
-- TRIG2 => T2,
-- TRIG3 => T3);
--
-- T0 <= TRIG0(to_integer(unsigned(dbg_chps_id)));
-- T1 <= TRIG1(to_integer(unsigned(dbg_chps_id)));
-- T2 <= TRIG2(to_integer(unsigned(dbg_chps_id)));
-- T3 <= TRIG3(to_integer(unsigned(dbg_chps_id)));
-- end generate;
-------------------------------------------------------------------------------
-- WRS Low jitter daughterboard
......
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