Skip to content

W
White Rabbit Switch - Gateware
Commit 7dc9ee34 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
Browse files
Options

Merge branch 'proposed_master' into 'proposed_master' 

Proposed master

See merge request !2
parents c2eb4734 48c57e9d
Pipeline #3199 passed with stage
    in 52 minutes and 33 seconds
    Show whitespace changes
    Inline Side-by-side
    Showing with 102 additions and 17 deletions
    .gitlab-ci.yml 0 → 100644
    View file @ 7dc9ee34
    variables:
    GIT_SUBMODULE_STRATEGY: normal
    stages:
    # - sim
    - syn
    #job_scb_top_sim:
    # stage: sim
    # tags:
    # - modelsim_10.2a
    # script:
    # - /entrypoint.sh
    # - source ~/setup_modelsim.sh
    # - git submodule sync & git submodule update --init
    # - apt-get install -y python
    # - cd top/bare_top
    # - python gen_sdbsyn.py --project wr_switch
    # - cd ../../
    # - cd sim
    # - ln -s ../ip_cores/wr-cores/sim wr-hdl
    # - cd ../testbench/scb_top
    # - cp /opt/compiled_libs_ise14.7/modelsim.ini .
    # - hdlmake makefile
    # - make
    # - vsim -c -do run.do
    job_scb_top_8p_syn:
    stage: syn
    tags:
    - xilinx_ISE_14.7
    script:
    - /entrypoint.sh
    - source ~/setup_ise147.sh
    - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
    - cd top/bare_top
    - python gen_sdbsyn.py --project wr_switch
    - cat synthesis_descriptor.vhd
    - cd ../../syn/scb_8ports
    - hdlmake makefile
    - make
    artifacts:
    name: SCB_TOP_8P_CI_$CI_JOB_ID
    paths:
    - syn/scb_8ports/*.syr
    - syn/scb_8ports/*.mrp
    - syn/scb_8ports/*.bit
    - syn/scb_8ports/*.bin
    - syn/scb_8ports/*.par
    - syn/scb_8ports/*.twr
    #job_scb_top_18p_syn:
    # stage: syn
    # tags:
    # - xilinx_ISE_14.7
    # script:
    # - /entrypoint.sh
    # - source ~/setup_ise147.sh
    # - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
    # - cd top/bare_top
    # - python gen_sdbsyn.py --project wr_switch
    # - cat synthesis_descriptor.vhd
    # - cd ../../syn/scb_18ports
    # - hdlmake makefile
    # - make
    # artifacts:
    # name: SCB_TOP_8P_CI_$CI_JOB_ID
    # paths:
    # - syn/scb_18ports/*.syr
    # - syn/scb_18ports/*.mrp
    # - syn/scb_18ports/*.bit
    # - syn/scb_18ports/*.bin
    # - syn/scb_18ports/*.par
    # - syn/scb_18ports/*.twr
    syn/scb_8ports/Manifest.py
    View file @ 7dc9ee34
    ......@@ -13,4 +13,4 @@ syn_project = "test_scb.xise"
    modules = { "local" : [ "../../top/scb_8ports",
    "../../ip_cores/general-cores",
    "../../ip_cores/wr-cores" ] }
    "../../ip_cores/wr-cores"] }
    testbench/scb_top/Manifest.py
    View file @ 7dc9ee34
    ......@@ -8,11 +8,8 @@ fetchto = "../../ip_cores"
    files = [ "main.sv" ]
    include_dirs = [ "../../sim", "../../sim/wr-hdl"]
    include_dirs = [ "../../sim", "../../sim/wr-hdl", "../../ip-cores/general-cores/modules/wishbone/wb_lm32/src"]
    modules = { "local" : [ "../../top/bare_top",
    "../../ip_cores/general-cores",
    "../../ip_cores/wr-cores"] }
    \ No newline at end of file
    testbench/scb_top_8p/Manifest.py
    View file @ 7dc9ee34
    ......@@ -8,11 +8,20 @@ fetchto = "../../ip_cores"
    files = [ "main.sv" ]
    include_dirs = [ "../../sim", "../../sim/wr-hdl" ]
    include_dirs = [ "../../sim", "../../sim/wr-hdl" , "../../ip_cores/wr-cores/sim",
    "../../ip_cores/wr-cores/testbench",
    "../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic",
    "../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
    "../../ip_cores/general-cores/modules/wishbone/wb_spi",
    "../../modules/wrsw_swcore/Switched-Multiported-RAM"]
    modules = { "local" : ["../../top/bare_top",
    # "../../ip_cores/wr-cores/testbench/wr_streamers/streamers-on-spec_trigger-distribution"]
    modules = { "local" : ["../../",
    "../../top/bare_top",
    "../../ip_cores/general-cores",
    "../../ip_cores/wr-cores"] }
    testbench/scb_top_8p/main.sv
    View file @ 7dc9ee34
    ......@@ -479,7 +479,7 @@ module main;
    pkt = gen.gen();
    if(g_force_payload_size >= 1520) // more than max
    $faltal("wrong g_force_payload_size with wrong opt param");
    $fatal("wrong g_force_payload_size with wrong opt param");
    else if(g_force_payload_size >= 42) // min size of frame is 64,
    pkt.set_size(g_force_payload_size);
    ......
    testbench/scb_top_8p/run.do
    View file @ 7dc9ee34
    make -f Makefile
    #make -f Makefile
    #vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
    vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
    set StdArithNoWarnings 1
    ......
    top/bare_top/Manifest.py
    View file @ 7dc9ee34
    files = [ "scb_top_bare.vhd",
    "wb_cpu_bridge.vhd","wrsw_top_pkg.vhd","scb_top_sim.vhd", "wrs_sdb_pkg.vhd",
    "synthesis_descriptor.vhd" ];
    "wb_cpu_bridge.vhd","wrsw_top_pkg.vhd","scb_top_sim.vhd", "wrs_sdb_pkg.vhd","synthesis_descriptor.vhd" ];
    modules = { "local" : [ "../../" ] };
    modules = { "local" : [ "../../"] };
    top/bare_top/gen_sdbsyn.py
    View file @ 7dc9ee34
    ......@@ -102,7 +102,8 @@ def main():
    ### runtime arguments
    parser = argparse.ArgumentParser(description='Script for generating sdb metadata of HDL projects')
    parser.add_argument('--user', default=git_username(), help='User who makes the synthesis')
    parser.add_argument('--project', default="", required=True, help='Friendly project name')
    # parser.add_argument('--project', default="", required=True, help='Friendly project name')
    parser.add_argument('--project', default="", help='Friendly project name') #added by konstantinos_blantos
    parser.add_argument('--tool', default="ISE", help='Name of the synthesis tool')
    parser.add_argument('--ver', default="14.5", help='Synthesis tool version')
    parser.add_argument('-o', default=".", help='location of output file')
    ......
    top/bare_top/scb_top_sim.vhd
    View file @ 7dc9ee34
    ......@@ -155,6 +155,7 @@ architecture rtl of scb_top_sim is
    signal i2c_sda_out : std_logic_vector(2 downto 0);
    signal i2c_sda_in : std_logic_vector(2 downto 0);
    begin -- rtl
    gen_i2c_tribufs : for i in 0 to 1 generate
    ......@@ -224,7 +225,11 @@ begin -- rtl
    i2c_scl_i => i2c_scl_in,
    i2c_sda_oen_o => i2c_sda_oen,
    i2c_sda_o => i2c_sda_out,
    i2c_sda_i => i2c_sda_in
    i2c_sda_i => i2c_sda_in,
    ljd_loopback_i => '0',
    ljd_osc_freq_i => (others=>'0'),
    ljd_pll_miso_i => '0',
    ljd_pll_locked_i=> '0'
    );
    gen_phys : for i in 0 to g_num_ports-1 generate
    ......
    Markdown is supported
    0% or
    You are about to add 0 people to the discussion. Proceed with caution.
    Finish editing this message first!
    Please register or to comment