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White Rabbit Switch - Gateware
Commits
7dc9ee34
Commit
7dc9ee34
authored
Feb 15, 2022
by
Grzegorz Daniluk
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Merge branch 'proposed_master' into 'proposed_master'
Proposed master See merge request
!2
parents
c2eb4734
48c57e9d
Pipeline
#3199
passed with stage
in 52 minutes and 33 seconds
Changes
10
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1
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10 changed files
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102 additions
and
17 deletions
+102
-17
.gitlab-ci.yml
.gitlab-ci.yml
+74
-0
.gitignore
ip_cores/.gitignore
+1
-1
Manifest.py
syn/scb_8ports/Manifest.py
+1
-1
Manifest.py
testbench/scb_top/Manifest.py
+2
-5
Manifest.py
testbench/scb_top_8p/Manifest.py
+11
-2
main.sv
testbench/scb_top_8p/main.sv
+2
-2
run.do
testbench/scb_top_8p/run.do
+1
-1
Manifest.py
top/bare_top/Manifest.py
+2
-3
gen_sdbsyn.py
top/bare_top/gen_sdbsyn.py
+2
-1
scb_top_sim.vhd
top/bare_top/scb_top_sim.vhd
+6
-1
No files found.
.gitlab-ci.yml
0 → 100644
View file @
7dc9ee34
variables
:
GIT_SUBMODULE_STRATEGY
:
normal
stages
:
# - sim
-
syn
#job_scb_top_sim:
# stage: sim
# tags:
# - modelsim_10.2a
# script:
# - /entrypoint.sh
# - source ~/setup_modelsim.sh
# - git submodule sync & git submodule update --init
# - apt-get install -y python
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - cd ../../
# - cd sim
# - ln -s ../ip_cores/wr-cores/sim wr-hdl
# - cd ../testbench/scb_top
# - cp /opt/compiled_libs_ise14.7/modelsim.ini .
# - hdlmake makefile
# - make
# - vsim -c -do run.do
job_scb_top_8p_syn
:
stage
:
syn
tags
:
-
xilinx_ISE_14.7
script
:
-
/entrypoint.sh
-
source ~/setup_ise147.sh
-
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-
cd top/bare_top
-
python gen_sdbsyn.py --project wr_switch
-
cat synthesis_descriptor.vhd
-
cd ../../syn/scb_8ports
-
hdlmake makefile
-
make
artifacts
:
name
:
SCB_TOP_8P_CI_$CI_JOB_ID
paths
:
-
syn/scb_8ports/*.syr
-
syn/scb_8ports/*.mrp
-
syn/scb_8ports/*.bit
-
syn/scb_8ports/*.bin
-
syn/scb_8ports/*.par
-
syn/scb_8ports/*.twr
#job_scb_top_18p_syn:
# stage: syn
# tags:
# - xilinx_ISE_14.7
# script:
# - /entrypoint.sh
# - source ~/setup_ise147.sh
# - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - cat synthesis_descriptor.vhd
# - cd ../../syn/scb_18ports
# - hdlmake makefile
# - make
# artifacts:
# name: SCB_TOP_8P_CI_$CI_JOB_ID
# paths:
# - syn/scb_18ports/*.syr
# - syn/scb_18ports/*.mrp
# - syn/scb_18ports/*.bit
# - syn/scb_18ports/*.bin
# - syn/scb_18ports/*.par
# - syn/scb_18ports/*.twr
ip_cores/.gitignore
View file @
7dc9ee34
wr-hdl
wr-hdl
general-cores
general-cores
\ No newline at end of file
syn/scb_8ports/Manifest.py
View file @
7dc9ee34
...
@@ -13,4 +13,4 @@ syn_project = "test_scb.xise"
...
@@ -13,4 +13,4 @@ syn_project = "test_scb.xise"
modules
=
{
"local"
:
[
"../../top/scb_8ports"
,
modules
=
{
"local"
:
[
"../../top/scb_8ports"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/wr-cores"
]
}
"../../ip_cores/wr-cores"
]
}
testbench/scb_top/Manifest.py
View file @
7dc9ee34
...
@@ -8,11 +8,8 @@ fetchto = "../../ip_cores"
...
@@ -8,11 +8,8 @@ fetchto = "../../ip_cores"
files
=
[
"main.sv"
]
files
=
[
"main.sv"
]
include_dirs
=
[
"../../sim"
,
"../../sim/wr-hdl"
]
include_dirs
=
[
"../../sim"
,
"../../sim/wr-hdl"
,
"../../ip-cores/general-cores/modules/wishbone/wb_lm32/src"
]
modules
=
{
"local"
:
[
"../../top/bare_top"
,
modules
=
{
"local"
:
[
"../../top/bare_top"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/wr-cores"
]
}
"../../ip_cores/wr-cores"
]
}
\ No newline at end of file
testbench/scb_top_8p/Manifest.py
View file @
7dc9ee34
...
@@ -8,11 +8,20 @@ fetchto = "../../ip_cores"
...
@@ -8,11 +8,20 @@ fetchto = "../../ip_cores"
files
=
[
"main.sv"
]
files
=
[
"main.sv"
]
include_dirs
=
[
"../../sim"
,
"../../sim/wr-hdl"
]
include_dirs
=
[
"../../sim"
,
"../../sim/wr-hdl"
,
"../../ip_cores/wr-cores/sim"
,
"../../ip_cores/wr-cores/testbench"
,
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic"
,
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src"
,
"../../ip_cores/general-cores/modules/wishbone/wb_spi"
,
"../../modules/wrsw_swcore/Switched-Multiported-RAM"
]
# "../../ip_cores/wr-cores/testbench/wr_streamers/streamers-on-spec_trigger-distribution"]
modules
=
{
"local"
:
[
"../../top/bare_top"
,
modules
=
{
"local"
:
[
"../../"
,
"../../top/bare_top"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/general-cores"
,
"../../ip_cores/wr-cores"
]
}
"../../ip_cores/wr-cores"
]
}
testbench/scb_top_8p/main.sv
View file @
7dc9ee34
...
@@ -72,7 +72,7 @@ module main;
...
@@ -72,7 +72,7 @@ module main;
CSimDrv_WDOG
wdog
;
CSimDrv_WDOG
wdog
;
reg
[
g_num_ports
-
1
:
0
]
ep_ctrl
;
reg
[
g_num_ports
-
1
:
0
]
ep_ctrl
;
reg
[
15
:
0
]
ep_failure_type
=
'h00
;
reg
[
15
:
0
]
ep_failure_type
=
'h00
;
/** *************************** basic conf ************************************* **/
/** *************************** basic conf ************************************* **/
integer
g_enable_pck_gaps
=
1
;
// 1=TRUE, 0=FALSE
integer
g_enable_pck_gaps
=
1
;
// 1=TRUE, 0=FALSE
...
@@ -479,7 +479,7 @@ module main;
...
@@ -479,7 +479,7 @@ module main;
pkt
=
gen
.
gen
()
;
pkt
=
gen
.
gen
()
;
if
(
g_force_payload_size
>=
1520
)
// more than max
if
(
g_force_payload_size
>=
1520
)
// more than max
$
fa
l
tal
(
"wrong g_force_payload_size with wrong opt param"
)
;
$
fatal
(
"wrong g_force_payload_size with wrong opt param"
)
;
else
if
(
g_force_payload_size
>=
42
)
// min size of frame is 64,
else
if
(
g_force_payload_size
>=
42
)
// min size of frame is 64,
pkt
.
set_size
(
g_force_payload_size
)
;
pkt
.
set_size
(
g_force_payload_size
)
;
...
...
testbench/scb_top_8p/run.do
View file @
7dc9ee34
make -f Makefile
#
make -f Makefile
#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
#vlog +incdir+../../sim +incdir+../../ip_cores/wr-cores/sim main.sv
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
vsim -L secureip -L unisim -t 10fs work.main -voptargs="+acc" +nowarn8684 +nowarn8683
set StdArithNoWarnings 1
set StdArithNoWarnings 1
...
...
top/bare_top/Manifest.py
View file @
7dc9ee34
files
=
[
"scb_top_bare.vhd"
,
files
=
[
"scb_top_bare.vhd"
,
"wb_cpu_bridge.vhd"
,
"wrsw_top_pkg.vhd"
,
"scb_top_sim.vhd"
,
"wrs_sdb_pkg.vhd"
,
"wb_cpu_bridge.vhd"
,
"wrsw_top_pkg.vhd"
,
"scb_top_sim.vhd"
,
"wrs_sdb_pkg.vhd"
,
"synthesis_descriptor.vhd"
];
"synthesis_descriptor.vhd"
];
modules
=
{
"local"
:
[
"../../"
]
};
modules
=
{
"local"
:
[
"../../"
]
};
top/bare_top/gen_sdbsyn.py
View file @
7dc9ee34
...
@@ -102,7 +102,8 @@ def main():
...
@@ -102,7 +102,8 @@ def main():
### runtime arguments
### runtime arguments
parser
=
argparse
.
ArgumentParser
(
description
=
'Script for generating sdb metadata of HDL projects'
)
parser
=
argparse
.
ArgumentParser
(
description
=
'Script for generating sdb metadata of HDL projects'
)
parser
.
add_argument
(
'--user'
,
default
=
git_username
(),
help
=
'User who makes the synthesis'
)
parser
.
add_argument
(
'--user'
,
default
=
git_username
(),
help
=
'User who makes the synthesis'
)
parser
.
add_argument
(
'--project'
,
default
=
""
,
required
=
True
,
help
=
'Friendly project name'
)
# parser.add_argument('--project', default="", required=True, help='Friendly project name')
parser
.
add_argument
(
'--project'
,
default
=
""
,
help
=
'Friendly project name'
)
#added by konstantinos_blantos
parser
.
add_argument
(
'--tool'
,
default
=
"ISE"
,
help
=
'Name of the synthesis tool'
)
parser
.
add_argument
(
'--tool'
,
default
=
"ISE"
,
help
=
'Name of the synthesis tool'
)
parser
.
add_argument
(
'--ver'
,
default
=
"14.5"
,
help
=
'Synthesis tool version'
)
parser
.
add_argument
(
'--ver'
,
default
=
"14.5"
,
help
=
'Synthesis tool version'
)
parser
.
add_argument
(
'-o'
,
default
=
"."
,
help
=
'location of output file'
)
parser
.
add_argument
(
'-o'
,
default
=
"."
,
help
=
'location of output file'
)
...
...
top/bare_top/scb_top_sim.vhd
View file @
7dc9ee34
...
@@ -154,6 +154,7 @@ architecture rtl of scb_top_sim is
...
@@ -154,6 +154,7 @@ architecture rtl of scb_top_sim is
signal
i2c_sda_oen
:
std_logic_vector
(
2
downto
0
);
signal
i2c_sda_oen
:
std_logic_vector
(
2
downto
0
);
signal
i2c_sda_out
:
std_logic_vector
(
2
downto
0
);
signal
i2c_sda_out
:
std_logic_vector
(
2
downto
0
);
signal
i2c_sda_in
:
std_logic_vector
(
2
downto
0
);
signal
i2c_sda_in
:
std_logic_vector
(
2
downto
0
);
begin
-- rtl
begin
-- rtl
...
@@ -224,7 +225,11 @@ begin -- rtl
...
@@ -224,7 +225,11 @@ begin -- rtl
i2c_scl_i
=>
i2c_scl_in
,
i2c_scl_i
=>
i2c_scl_in
,
i2c_sda_oen_o
=>
i2c_sda_oen
,
i2c_sda_oen_o
=>
i2c_sda_oen
,
i2c_sda_o
=>
i2c_sda_out
,
i2c_sda_o
=>
i2c_sda_out
,
i2c_sda_i
=>
i2c_sda_in
i2c_sda_i
=>
i2c_sda_in
,
ljd_loopback_i
=>
'0'
,
ljd_osc_freq_i
=>
(
others
=>
'0'
),
ljd_pll_miso_i
=>
'0'
,
ljd_pll_locked_i
=>
'0'
);
);
gen_phys
:
for
i
in
0
to
g_num_ports
-1
generate
gen_phys
:
for
i
in
0
to
g_num_ports
-1
generate
...
...
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