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White Rabbit Switch - Gateware
Commits
76eaac7d
Commit
76eaac7d
authored
Aug 19, 2019
by
Grzegorz Daniluk
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ljd: use ad9516 lock signal and reset it with ext_pll_reset bit
parent
90536db3
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8 changed files
with
32 additions
and
11 deletions
+32
-11
wrsw_rt_subsystem.vhd
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
+12
-4
scb_top_bare.vhd
top/bare_top/scb_top_bare.vhd
+2
-0
wrsw_components_pkg.vhd
top/bare_top/wrsw_components_pkg.vhd
+2
-1
wrsw_top_pkg.vhd
top/bare_top/wrsw_top_pkg.vhd
+2
-0
scb_top_synthesis.ucf
top/scb_18ports/scb_top_synthesis.ucf
+1
-0
scb_top_synthesis.vhd
top/scb_18ports/scb_top_synthesis.vhd
+9
-6
scb_top_synthesis.ucf
top/scb_8ports/scb_top_synthesis.ucf
+1
-0
scb_top_synthesis.vhd
top/scb_8ports/scb_top_synthesis.vhd
+3
-0
No files found.
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @
76eaac7d
...
...
@@ -142,6 +142,7 @@ entity wrsw_rt_subsystem is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
-- Debug
spll_dbg_o
:
out
std_logic_vector
(
5
downto
0
)
...
...
@@ -175,6 +176,7 @@ architecture rtl of wrsw_rt_subsystem is
clk_ext_i
:
in
std_logic
;
clk_ext_mul_i
:
in
std_logic_vector
(
g_num_exts
-1
downto
0
);
clk_ext_mul_locked_i
:
in
std_logic
;
clk_ext_rst_o
:
out
std_logic
;
pps_csync_p1_i
:
in
std_logic
;
pps_ext_a_i
:
in
std_logic
;
dac_dmtd_data_o
:
out
std_logic_vector
(
15
downto
0
);
...
...
@@ -270,6 +272,8 @@ architecture rtl of wrsw_rt_subsystem is
end
f_pick
;
signal
ljd_board_detected
:
std_logic
;
signal
ext_pll_locked
:
std_logic
;
signal
ext_pll_reset
:
std_logic
;
begin
-- rtl
...
...
@@ -362,7 +366,8 @@ begin -- rtl
clk_dmtd_i
=>
clk_dmtd_i
,
clk_ext_i
=>
clk_ext_i
,
clk_ext_mul_i
=>
clk_ext_mul_i
,
clk_ext_mul_locked_i
=>
clk_ext_mul_locked_i
,
clk_ext_mul_locked_i
=>
ext_pll_locked
,
clk_ext_rst_o
=>
ext_pll_reset
,
pps_csync_p1_i
=>
pps_csync
,
pps_ext_a_i
=>
pps_ext_i
,
dac_dmtd_data_o
=>
dac_dmtd_data
,
...
...
@@ -495,9 +500,8 @@ begin -- rtl
cpu_reset_n
<=
not
gpio_out
(
2
)
and
rst_sys_n_i
;
rst_n_o
<=
gpio_out
(
3
);
ljd_pll_reset_n_o
<=
gpio_out
(
4
);
gpio_in
(
5
)
<=
ljd_board_detected
;
gpio_in
(
8
downto
6
)
<=
ljd_osc_freq_i
;
gpio_in
(
4
)
<=
ljd_board_detected
;
gpio_in
(
7
downto
5
)
<=
ljd_osc_freq_i
;
U_Main_DAC
:
gc_serial_dac
...
...
@@ -554,6 +558,10 @@ begin -- rtl
board_detected_o
=>
ljd_board_detected
);
ljd_detected_o
<=
ljd_board_detected
;
ext_pll_locked
<=
ljd_pll_locked_i
when
(
ljd_board_detected
=
'1'
)
else
clk_ext_mul_locked_i
;
ljd_pll_reset_n_o
<=
not
ext_pll_reset
when
(
ljd_board_detected
=
'1'
)
else
'1'
;
end
rtl
;
top/bare_top/scb_top_bare.vhd
View file @
76eaac7d
...
...
@@ -152,6 +152,7 @@ entity scb_top_bare is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
-------------------------------------------------------------------------------
-- Misc pins
...
...
@@ -667,6 +668,7 @@ begin
ljd_pll_cs_n_o
=>
ljd_pll_cs_n_o
,
ljd_pll_sync_n_o
=>
ljd_pll_sync_n_o
,
ljd_pll_reset_n_o
=>
ljd_pll_reset_n_o
,
ljd_pll_locked_i
=>
ljd_pll_locked_i
,
spll_dbg_o
=>
spll_dbg_o
);
...
...
top/bare_top/wrsw_components_pkg.vhd
View file @
76eaac7d
...
...
@@ -264,7 +264,8 @@ package wrsw_components_pkg is
ljd_pll_sck_o
:
out
std_logic
;
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
);
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
);
end
component
;
component
chipscope_icon
...
...
top/bare_top/wrsw_top_pkg.vhd
View file @
76eaac7d
...
...
@@ -267,6 +267,7 @@ package wrsw_top_pkg is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
spll_dbg_o
:
out
std_logic_vector
(
5
downto
0
));
end
component
;
...
...
@@ -334,6 +335,7 @@ package wrsw_top_pkg is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
pll_mosi_o
:
out
std_logic
;
pll_miso_i
:
in
std_logic
;
...
...
top/scb_18ports/scb_top_synthesis.ucf
View file @
76eaac7d
...
...
@@ -38,6 +38,7 @@ NET "ljd_clk2_en" LOC = AK31;
NET "ljd_loopback_i" LOC = AM31;
NET "ljd_loopback_o" LOC = AL30;
NET "ljd_pll_locked_i" LOC = AH33;
#EBI BUS
#NET "cpu_clk_i" LOC="";
...
...
top/scb_18ports/scb_top_synthesis.vhd
View file @
76eaac7d
...
...
@@ -145,6 +145,7 @@ entity scb_top_synthesis is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
ljd_dac_main_sync_n_o
:
out
std_logic
;
ljd_dac_main_sclk_o
:
out
std_logic
;
...
...
@@ -384,6 +385,7 @@ architecture Behavioral of scb_top_synthesis is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
pll_mosi_o
:
out
std_logic
;
pll_miso_i
:
in
std_logic
;
...
...
@@ -833,12 +835,13 @@ begin
ljd_clk2_en
=>
ljd_clk2_en
,
ljd_detected_o
=>
ljd_detected
,
ljd_osc_freq_i
=>
ljd_osc_freq_i
,
ljd_pll_mosi_o
=>
ljd_pll_mosi_o
,
ljd_pll_miso_i
=>
ljd_pll_miso_i
,
ljd_pll_sck_o
=>
ljd_pll_sck_o
,
ljd_pll_cs_n_o
=>
ljd_pll_cs_n_o
,
ljd_pll_sync_n_o
=>
ljd_pll_sync_n_o
,
ljd_pll_reset_n_o
=>
ljd_pll_reset_n_o
,
ljd_pll_mosi_o
=>
ljd_pll_mosi_o
,
ljd_pll_miso_i
=>
ljd_pll_miso_i
,
ljd_pll_sck_o
=>
ljd_pll_sck_o
,
ljd_pll_cs_n_o
=>
ljd_pll_cs_n_o
,
ljd_pll_sync_n_o
=>
ljd_pll_sync_n_o
,
ljd_pll_reset_n_o
=>
ljd_pll_reset_n_o
,
ljd_pll_locked_i
=>
ljd_pll_locked_i
,
pll_status_i
=>
clk_10mhz
,
pll_mosi_o
=>
pll_mosi_o
,
...
...
top/scb_8ports/scb_top_synthesis.ucf
View file @
76eaac7d
...
...
@@ -38,6 +38,7 @@ NET "ljd_clk2_en" LOC = AK31;
NET "ljd_loopback_i" LOC = AM31;
NET "ljd_loopback_o" LOC = AL30;
NET "ljd_pll_locked_i" LOC = AH33;
#NET "dbg_clk_ext_o" LOC=AM33;
#NET "spll_dbg_o<0>" LOC=AL33;
...
...
top/scb_8ports/scb_top_synthesis.vhd
View file @
76eaac7d
...
...
@@ -140,6 +140,7 @@ entity scb_top_synthesis is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
ljd_dac_main_sync_n_o
:
out
std_logic
;
ljd_dac_main_sclk_o
:
out
std_logic
;
...
...
@@ -384,6 +385,7 @@ architecture Behavioral of scb_top_synthesis is
ljd_pll_cs_n_o
:
out
std_logic
;
ljd_pll_sync_n_o
:
out
std_logic
;
ljd_pll_reset_n_o
:
out
std_logic
;
ljd_pll_locked_i
:
in
std_logic
;
pll_status_i
:
in
std_logic
;
pll_mosi_o
:
out
std_logic
;
pll_miso_i
:
in
std_logic
;
...
...
@@ -843,6 +845,7 @@ begin
ljd_pll_cs_n_o
=>
ljd_pll_cs_n_o
,
ljd_pll_sync_n_o
=>
ljd_pll_sync_n_o
,
ljd_pll_reset_n_o
=>
ljd_pll_reset_n_o
,
ljd_pll_locked_i
=>
ljd_pll_locked_i
,
pll_status_i
=>
clk_10mhz
,
pll_mosi_o
=>
pll_mosi_o
,
...
...
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