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White Rabbit Switch - Gateware
Commit 5eb9d456 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski Committed by Grzegorz Daniluk
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Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of… 

Migrated the codebase to the November 2018 proposed master of wr-cores. Lot of rework, hopefully it will work...
parent bbe909f5
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modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ 5eb9d456
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-10
-- Last update: 2017-06-22
-- Last update: 2018-11-07
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -153,50 +153,6 @@ end wrsw_rt_subsystem;
architecture rtl of wrsw_rt_subsystem is
component xwr_softpll_ng
generic (
g_tag_bits : integer;
g_num_ref_inputs : integer;
g_num_outputs : integer;
g_num_exts : integer;
g_with_debug_fifo : boolean;
g_divide_input_by_2 : boolean;
g_reverse_dmtds : boolean;
g_ref_clock_rate : integer;
g_ext_clock_rate : integer;
g_use_sampled_ref_clocks : boolean;
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_sys_n_i : in std_logic;
rst_ref_n_i : in std_logic;
rst_ext_n_i : in std_logic;
rst_dmtd_n_i : in std_logic;
clk_ref_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_ref_sampled_i : in std_logic_vector(g_num_ref_inputs-1 downto 0);
clk_fb_i : in std_logic_vector(g_num_outputs-1 downto 0);
clk_dmtd_i : in std_logic;
clk_ext_i : in std_logic;
clk_ext_mul_i : in std_logic_vector(g_num_exts-1 downto 0);
clk_ext_mul_locked_i : in std_logic;
clk_ext_rst_o : out std_logic;
pps_csync_p1_i : in std_logic;
pps_ext_a_i : in std_logic;
dac_dmtd_data_o : out std_logic_vector(15 downto 0);
dac_dmtd_load_o : out std_logic;
dac_out_data_o : out std_logic_vector(15 downto 0);
dac_out_sel_o : out std_logic_vector(3 downto 0);
dac_out_load_o : out std_logic;
out_enable_i : in std_logic_vector(g_num_outputs-1 downto 0);
out_locked_o : out std_logic_vector(g_num_outputs-1 downto 0);
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
debug_o : out std_logic_vector(5 downto 0);
dbg_fifo_irq_o : out std_logic);
end component;
component xwrsw_gen_10mhz
generic (
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
......@@ -347,7 +303,7 @@ begin -- rtl
uart_txd_o => uart_txd_o);
U_SoftPLL : xwr_softpll_ng
U_SoftPLL : entity work.xwr_softpll_ng
generic map (
g_tag_bits => 22,
g_interface_mode => PIPELINED,
......
top/bare_top/scb_top_bare.vhd
View file @ 5eb9d456
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2018-06-16
-- Last update: 2018-11-07
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -336,6 +336,7 @@ architecture rtl of scb_top_bare is
signal rst_periph_ref_n : std_logic;
signal rst_periph_dmtd_n : std_logic;
signal rst_periph_rxclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_periph_txclk_n: std_logic_vector(c_NUM_PORTS-1 downto 0);
signal rst_ref_n : std_logic;
signal rst_ext_n : std_logic;
signal rst_dmtd_n : std_logic;
......@@ -574,6 +575,15 @@ begin
synced_o => rst_periph_dmtd_n);
gen_rst_periph_rxclk : for i in 0 to c_NUM_PORTS-1 generate
U_sync_reset_txclk : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => phys_i(i).ref_clk,
rst_n_i => '1',
data_i => rst_n_periph,
synced_o => rst_periph_txclk_n(i));
U_sync_reset_rxclk: gc_sync_ffs
generic map (
g_sync_edge => "positive")
......@@ -792,7 +802,7 @@ begin
rst_sys_n_i => rst_n_periph,
rst_ref_n_i => rst_periph_ref_n,
rst_dmtd_n_i => rst_periph_dmtd_n,
rst_txclk_n_i => rst_periph_ref_n,
rst_txclk_n_i => rst_periph_txclk_n(i),
rst_rxclk_n_i => rst_periph_rxclk_n(i),
pps_csync_p1_i => pps_csync,
......
top/bare_top/wrsw_top_pkg.vhd
View file @ 5eb9d456
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-02-21
-- Last update: 2018-02-26
-- Last update: 2018-11-07
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -124,6 +124,33 @@ package wrsw_top_pkg is
g_simulation : integer;
g_use_slave_tx_clock : integer;
g_use_bufr : boolean := false);
port (
clk_ref_i : in std_logic;
clk_gtx_i : in std_logic;
tx_data_i : in std_logic_vector(15 downto 0);
tx_k_i : in std_logic_vector(1 downto 0);
tx_disparity_o : out std_logic;
tx_enc_err_o : out std_logic;
rx_rbclk_o : out std_logic;
rx_data_o : out std_logic_vector(15 downto 0);
rx_k_o : out std_logic_vector(1 downto 0);
rx_enc_err_o : out std_logic;
rx_bitslide_o : out std_logic_vector(4 downto 0);
rst_i : in std_logic;
loopen_i : in std_logic;
pad_txn_o : out std_logic;
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic);
end component;
component wr_gtx_phy_virtex6_lp
generic (
g_simulation : integer;
g_use_slave_tx_clock : integer;
g_use_bufr : boolean := false;
g_id : integer);
port (
clk_ref_i : in std_logic;
clk_gtx_i : in std_logic;
......@@ -146,9 +173,7 @@ package wrsw_top_pkg is
pad_txp_o : out std_logic;
pad_rxn_i : in std_logic := '0';
pad_rxp_i : in std_logic := '0';
rdy_o : out std_logic;
tx_sampled_i : in std_logic := '0';
rx_sampled_i : in std_logic := '0'
rdy_o : out std_logic
);
end component;
......@@ -442,7 +467,8 @@ package wrsw_top_pkg is
rtu2tru_o : out t_rtu2tru;
tru_enabled_i: in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
wb_o : out t_wishbone_slave_out;
int_o : out std_logic);
end component;
component xwrsw_rtu_new
generic (
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ 5eb9d456
......@@ -222,13 +222,10 @@ NET "gtx_txn_o[7]" LOC="AP2";
#NET "gtx_rxn_i[9]" LOC="W4";
#NET "gtx_txp_o[9]" LOC="V1";
#NET "gtx_txn_o[9]" LOC="V2";
#NET "gtx_rxp_i[7]" LOC="U3";
#NET "gtx_rxn_i[7]" LOC="U4";
#NET "gtx_txp_o[7]" LOC="T1";
#NET "gtx_txn_o[7]" LOC="T2";
NET "gtx_rxp_i[6]" LOC="R3";
NET "gtx_rxn_i[6]" LOC="R4";
......@@ -411,14 +408,30 @@ PIN "gen_phys[5].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALS
PIN "gen_phys[6].U_PHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_LastPHY/U_GTX_INST/gtxe1_i.TXOUTCLK" CLOCK_DEDICATED_ROUTE = FALSE;
NET "dbg_samp_rx_p_i" LOC="AM33";
NET "dbg_samp_rx_n_i" LOC="AL33";
NET "dbg_samp_tx_p_i" LOC="AE28";
NET "dbg_samp_tx_n_i" LOC="AE29";
NET "dbg_dmtd_tx_clean_o" LOC="AN32";
NET "dbg_dmtd_rx_clean_o" LOC="AM32";
NET "dbg_dmtd_tx_raw_o" LOC="AP32";
NET "dbg_dmtd_rx_raw_o" LOC="AP33";
#NET "dbg_samp_rx_p_i" LOC="AM33";
#NET "dbg_samp_rx_n_i" LOC="AL33";
#NET "dbg_samp_tx_p_i" LOC="AE28";
#NET "dbg_samp_tx_n_i" LOC="AE29";
#NET "dbg_dmtd_tx_clean_o" LOC="AN32";
#NET "dbg_dmtd_rx_clean_o" LOC="AM32";
#NET "dbg_dmtd_tx_raw_o" LOC="AP32";
#NET "dbg_dmtd_rx_raw_o" LOC="AP33";
#Created by Constraints Editor (xc6vlx240t-ff1156-1) - 2018/06/22
#NET "gen_phys[4].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys[4].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys[5].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys[5].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys[6].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys[6].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[0].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[0].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[1].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[1].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[2].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[2].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "gen_phys_bufr[3].U_PHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "gen_phys_bufr[3].U_PHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
#NET "U_LastPHY/U_Sampler_TX/clk_in" MAXDELAY = 0.2 ns;
#NET "U_LastPHY/U_Sampler_TX/clk_in" MAXSKEW = 0.1 ns;
top/scb_8ports/scb_top_synthesis.vhd
View file @ 5eb9d456
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski, Maciej Lipinski, Grzegorz Daniluk
-- Company : CERN BE-CO-HT
-- Created : 2012-03-07
-- Last update: 2018-06-15
-- Last update: 2018-08-09
-- Platform : FPGA-generic
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -213,21 +213,7 @@ entity scb_top_synthesis is
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
dbg_samp_rx_p_i : in std_logic;
dbg_samp_rx_n_i : in std_logic;
dbg_samp_tx_p_i : in std_logic;
dbg_samp_tx_n_i : in std_logic;
-- dbg_dmtd_rx_o : out std_logic;
-- dbg_dmtd_tx_o : out std_logic;
-- dbg_dmtd_tx_mask_o : out std_logic;
-- dbg_dmtd_rx_mask_o : out std_logic;
dbg_dmtd_tx_clean_o : out std_logic;
dbg_dmtd_rx_clean_o : out std_logic;
dbg_dmtd_tx_raw_o : out std_logic;
dbg_dmtd_rx_raw_o : out std_logic
mb_fan2_pwm_o : out std_logic
);
end scb_top_synthesis;
......@@ -274,7 +260,6 @@ architecture Behavioral of scb_top_synthesis is
end f_bool2int;
-------------------------------------------------------------------------------
-- Clocks
-------------------------------------------------------------------------------
......@@ -455,7 +440,6 @@ architecture Behavioral of scb_top_synthesis is
signal phy_rx_clk_vec: std_logic_vector(7 downto 0);
signal dbg_samp_tx, dbg_samp_rx : std_logic;
begin
U_Clk_Buf_GTX0_3 : IBUFDS_GTXE1
......@@ -516,24 +500,6 @@ begin
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_Ref2 : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => dbg_samp_tx,
I => dbg_samp_tx_p_i,
IB => dbg_samp_tx_n_i);
U_Buf_CLK_Ref3 : IBUFGDS
generic map (
DIFF_TERM => true,
IOSTANDARD => "LVDS_25")
port map (
O => dbg_samp_rx,
I => dbg_samp_rx_p_i,
IB => dbg_samp_rx_n_i);
U_Buf_ljd_clk_62mhz : IBUFGDS
generic map (
DIFF_TERM => true,
......@@ -721,11 +687,12 @@ begin
--generate first 4 GTXes with BUFR to reduce the number of global clocks
gen_phys_bufr : for i in 0 to 3 generate
U_PHY : wr_gtx_phy_virtex6
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false)
g_use_bufr => false,
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
......@@ -757,11 +724,12 @@ begin
gen_phys : for i in 4 to c_NUM_PHYS-2 generate
U_PHY : wr_gtx_phy_virtex6
U_PHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => f_bool2int(i /= (i/4)*4),
g_use_bufr => false)
g_use_bufr => false,
g_id => i)
port map (
clk_gtx_i => clk_gtx(i),
clk_ref_i => clk_ref,
......@@ -790,16 +758,16 @@ begin
from_phys(i).ref_clk <= clk_ref;
end generate gen_phys;
U_LastPHY : wr_gtx_phy_virtex6
U_LastPHY : entity work.wr_gtx_phy_virtex6_lp
generic map (
g_simulation => f_bool2int(g_simulation),
g_use_slave_tx_clock => 0,
g_use_bufr => false)
g_use_bufr => false,
g_id => c_NUM_PHYS-1)
port map (
clk_gtx_i => clk_gtx0_3,
clk_ref_i => clk_ref,
clk_dmtd_i => clk_dmtd,
tx_data_i => to_phys(c_NUM_PHYS-1).tx_data,
tx_k_i => to_phys(c_NUM_PHYS-1).tx_k,
tx_disparity_o => from_phys(c_NUM_PHYS-1).tx_disparity,
......@@ -818,9 +786,7 @@ begin
pad_txp_o => gtx_txp_o(7),
pad_rxn_i => gtx_rxn_i(7),
pad_rxp_i => gtx_rxp_i(7),
rdy_o => from_phys(c_NUM_PHYS-1).rdy,
tx_sampled_i => dbg_samp_tx,
rx_sampled_i => dbg_samp_rx
rdy_o => from_phys(c_NUM_PHYS-1).rdy
);
from_phys(c_NUM_PHYS-1).ref_clk <= clk_ref;
......@@ -844,13 +810,13 @@ begin
generic map (
g_num_ports => c_NUM_PORTS,
g_simulation => g_simulation,
g_without_network => true,
g_without_network => false,
g_with_TRU => false,
g_with_TATSU => false,
g_with_HWIU => false,
g_with_PSTATS => false,
g_with_HWIU => true,
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => false,
g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000"
)
port map (
......
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