Commit 4e183daf authored by Maciej Lipinski's avatar Maciej Lipinski

CI: experiment

parent d6d6b4e5
Pipeline #5019 passed with stages
in 59 minutes and 22 seconds
......@@ -2,61 +2,63 @@ variables:
GIT_SUBMODULE_STRATEGY: normal
stages:
# - sim
- sim
- syn
#job_scb_top_sim:
# stage: sim
# tags:
# - modelsim_10.2a
# script:
# - /entrypoint.sh
# - source ~/setup_modelsim.sh
# - git submodule sync & git submodule update --init
# - apt-get install -y python
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - cd ../../modules/wrsw_hwiu
# - python gen_ver.py
# - cd ../../
# - cd sim
# - ln -s ../ip_cores/wr-cores/sim wr-hdl
# - cd ../testbench/scb_top
# - cp /opt/compiled_libs_ise14.7/modelsim.ini .
# - hdlmake makefile
# - make
# - vsim -c -do run.do
job_scb_top_sim:
stage: sim
when: manual
tags:
- modelsim_10.2a
script:
- /entrypoint.sh
- source ~/setup_modelsim.sh
- git submodule sync & git submodule update --init
- apt-get install -y python
- cd top/bare_top
- python gen_sdbsyn.py --project wr_switch
- cd ../../modules/wrsw_hwiu
- python gen_ver.py
- cd ../../
- cd sim
- ln -s ../ip_cores/wr-cores/sim wr-hdl
- cd ../testbench/scb_top
- cp /opt/compiled_libs_ise14.7/modelsim.ini .
- hdlmake makefile
- make
- vsim -c -do run.do
#job_scb_top_8p_syn:
#stage: syn
#tags:
#- xilinx_ISE_14.7
#script:
#- /entrypoint.sh
#- source ~/setup_ise147.sh
#- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
#- cd top/bare_top
#- python gen_sdbsyn.py --project wr_switch
#- cat synthesis_descriptor.vhd
#- cd ../../modules/wrsw_hwiu
#- python gen_ver.py
#- cat gw_ver_pkg.vhd
#- cd ../../syn/scb_8ports
#- hdlmake makefile
#- make
#- bitgen -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
#artifacts:
#name: SCB_TOP_8P_CI_$CI_JOB_ID
#paths:
#- syn/scb_8ports/*.syr
#- syn/scb_8ports/*.mrp
#- syn/scb_8ports/*.bit
#- syn/scb_8ports/*.bin
#- syn/scb_8ports/*.par
#- syn/scb_8ports/*.twr
job_scb_top_8p_syn:
stage: syn
tags:
- xilinx_ISE_14.7
script:
- /entrypoint.sh
- source ~/setup_ise147.sh
- source /opt/Xilinx/14.7/ISE_DS/settings64.sh
- cd top/bare_top
- python gen_sdbsyn.py --project wr_switch
- cat synthesis_descriptor.vhd
- cd ../../modules/wrsw_hwiu
- python gen_ver.py
- cat gw_ver_pkg.vhd
- cd ../../syn/scb_8ports
- hdlmake makefile
- make
- bitgen -b -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
artifacts:
name: SCB_TOP_8P_CI_$CI_JOB_ID
paths:
- syn/scb_8ports/*.syr
- syn/scb_8ports/*.mrp
- syn/scb_8ports/*.bit
- syn/scb_8ports/*.bin
- syn/scb_8ports/*.par
- syn/scb_8ports/*.twr
job_scb_top_18p_syn:
stage: syn
when: manual
tags:
- xilinx_ISE_14.7
# only:
......@@ -77,7 +79,7 @@ job_scb_top_18p_syn:
- cd ../../syn/scb_18ports
- hdlmake makefile
- make
- bitgen -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
- bitgen -b -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd
artifacts:
name: SCB_TOP_8P_CI_$CI_JOB_ID
paths:
......
......@@ -10,6 +10,8 @@ syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
syn_project = "test_scb.xise"
syn_pre_project_cmd="python ../../modules/wrsw_hwiu/gen_ver.py"
syn_post_bitstream_cmd="bitgen -g binary:yes -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd"
modules = { "local" : [ "../../top/scb_18ports",
"../../ip_cores/general-cores",
......
......@@ -10,7 +10,10 @@ syn_grade = "-1"
syn_package = "ff1156"
syn_top = "scb_top_synthesis"
syn_project = "test_scb.xise"
syn_pre_project_cmd="python ../../modules/wrsw_hwiu/gen_ver.py"
syn_post_bitstream_cmd="bitgen -g binary:yes -intstyle ise -f scb_top_synthesis.ut scb_top_synthesis.ncd"
modules = { "local" : [ "../../top/scb_8ports",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores"] }
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