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White Rabbit Switch - Gateware
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White Rabbit Switch - Gateware
Commits
48c57e9d
Commit
48c57e9d
authored
Feb 14, 2022
by
Konstantinos Blantos
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Update .gitlab-ci.yml
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.gitlab-ci.yml
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48c57e9d
...
@@ -2,52 +2,52 @@ variables:
...
@@ -2,52 +2,52 @@ variables:
GIT_SUBMODULE_STRATEGY
:
normal
GIT_SUBMODULE_STRATEGY
:
normal
stages
:
stages
:
-
sim
#
- sim
#
- syn
-
syn
job_scb_top_sim
:
#job_scb_top_sim:
stage
:
sim
# stage: sim
tags
:
-
modelsim_10.2a
script
:
-
/entrypoint.sh
-
source ~/setup_modelsim.sh
-
git submodule sync & git submodule update --init
-
apt-get install -y python
-
cd top/bare_top
-
python gen_sdbsyn.py --project wr_switch
-
cd ../../
-
cd sim
-
ln -s ../ip_cores/wr-cores/sim wr-hdl
-
cd ../testbench/scb_top
-
cp /opt/compiled_libs_ise14.7/modelsim.ini .
-
hdlmake makefile
-
make
-
vsim -c -do run.do
#job_scb_top_8p_syn:
# stage: syn
# tags:
# tags:
# -
xilinx_ISE_14.7
# -
modelsim_10.2a
# script:
# script:
# - /entrypoint.sh
# - /entrypoint.sh
# - source ~/setup_ise147.sh
# - source ~/setup_modelsim.sh
# - source /opt/Xilinx/14.7/ISE_DS/settings64.sh
# - git submodule sync & git submodule update --init
# - apt-get install -y python
# - cd top/bare_top
# - cd top/bare_top
# - python gen_sdbsyn.py --project wr_switch
# - python gen_sdbsyn.py --project wr_switch
# - cat synthesis_descriptor.vhd
# - cd ../../
# - cd ../../syn/scb_8ports
# - cd sim
# - hdlmake makefile
# - ln -s ../ip_cores/wr-cores/sim wr-hdl
# - cd ../testbench/scb_top
# - cp /opt/compiled_libs_ise14.7/modelsim.ini .
# - hdlmake makefile
# - make
# - make
# artifacts:
# - vsim -c -do run.do
# name: SCB_TOP_8P_CI_$CI_JOB_ID
# paths:
job_scb_top_8p_syn
:
# - syn/scb_8ports/*.syr
stage
:
syn
# - syn/scb_8ports/*.mrp
tags
:
# - syn/scb_8ports/*.bit
-
xilinx_ISE_14.7
# - syn/scb_8ports/*.bin
script
:
# - syn/scb_8ports/*.par
-
/entrypoint.sh
# - syn/scb_8ports/*.twr
-
source ~/setup_ise147.sh
-
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
-
cd top/bare_top
-
python gen_sdbsyn.py --project wr_switch
-
cat synthesis_descriptor.vhd
-
cd ../../syn/scb_8ports
-
hdlmake makefile
-
make
artifacts
:
name
:
SCB_TOP_8P_CI_$CI_JOB_ID
paths
:
-
syn/scb_8ports/*.syr
-
syn/scb_8ports/*.mrp
-
syn/scb_8ports/*.bit
-
syn/scb_8ports/*.bin
-
syn/scb_8ports/*.par
-
syn/scb_8ports/*.twr
#job_scb_top_18p_syn:
#job_scb_top_18p_syn:
# stage: syn
# stage: syn
...
...
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